JP2005064768A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem: when huge parameter data large in bit width are simply selected and worked, since a large amount of parameters are accessed and setup data larger in bit amount are compared with count data and a transition time up to data confirmation is made longer, a comparison operating frequency is deteriorated. <P>SOLUTION: In a timing generator 16 for generating a driving pulse changing in time series, a count value of a counter 28 is compared with a parameter value in a comparator 24 in two steps by dividing them into subordinate data and superordinate data by making use of the quality that the count value of the counter 28 sequentially performs increment change. Thus, the number of bit for comparison in the comparator 24 is halved, and the number of circuit gates is suppressed and the comparison operating frequency is improved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device including a timing signal generation circuit that generates a drive signal that changes in time series.

  In recent years, in the camera module such as a digital still camera and a video camera using a solid-state image pickup device such as a CCD (Charge Coupled Device) image sensor as an image pickup device, the development period has been shortened and the price has been reduced. Efforts are being made to increase the pixel size and performance of image sensors. In general, when the solid-state imaging device is improved, compatibility of driving timing is not ensured. Conventionally, the following is known as a timing generator (timing signal generation circuit) for determining the driving timing of the solid-state imaging device.

  First, there is known a timing generator including a decoder for decoding a rising pulse and a decoder for decoding a falling pulse so that the timing pulse can be set programmably by a microcomputer (for example, Patent Documents). 1).

  For the purpose of reducing the memory capacity, a timing generator is known in which a timing pulse that repeats in the horizontal direction and a timing pulse that repeats in the vertical direction are obtained from individual memories (see, for example, Patent Document 2).

  Further, it is known that the amount of data to be stored in a timing generator with a built-in memory for generating timing pulses used for driving a solid-state imaging device is reduced, and a flexible function of the timing generator is realized. (For example, see Patent Document 3).

Japanese Patent Laid-Open No. 10-257398 JP 09-205591 A JP 2002-512270 A

  The number of timing pulses used for driving the solid-state imaging device is large, and the waveform is complicated. Therefore, the conventional technique according to Patent Document 1 has a problem that the amount of data to be programmed is large and the data setting is complicated. Further, in the conventional techniques according to Patent Documents 2 and 3, since a memory for storing data is indispensable, there is a problem that the chip size is increased and the cost is increased. In addition, when timing data is changed by an external setting from a microcomputer, there is a problem that a bus switching transition time increases because a large amount of data is selected at the time of operation transition switching.

  In order to solve the above problems, a solid-state imaging device according to the present invention is a solid-state imaging device including a timing signal generation circuit that generates a drive signal that changes in time series, and the timing signal generation circuit includes the solid-state imaging device. When switching the drive mode of the element, the selection means for selecting parameter data corresponding to the drive mode to be set from the parameter group consisting of a set of parameter data corresponding to various drive modes, and the clock signal with a fixed period Counting means for performing a counting operation, comparing means for comparing the parameter data selected by the selecting means and the count data of the counting means in a plurality of stages in a time-sharing manner, and each stage of the comparing means It has the structure provided with the production | generation means which produces | generates the said drive signal based on every comparison result.

  In the timing signal generation circuit configured as described above, the same comparison is made between the count data of the counting means and the parameter data selected corresponding to the drive mode to be set by utilizing the property that the count value of the counting means is sequentially incremented. By dividing into a plurality of stages by means, the number of bits to be compared by the comparison means can be reduced to 1 / number of stages.

  According to the present invention, when the count data of the counting means and the parameter data selected corresponding to the drive mode to be set are compared, the number of bits to be compared can be reduced to 1 / step number, so that the circuit is correspondingly. Since the number of gates can be suppressed and the transition time until data confirmation can be shortened, the comparison operation frequency can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a configuration diagram showing an outline of the overall configuration of a solid-state imaging device to which the present invention is applied, for example, a CCD image sensor. In FIG. 1, an imaging unit 11 is two-dimensionally arranged in a matrix and photoelectrically converts received light into a signal charge having a charge amount corresponding to the amount of light. The vertical transfer unit 13 includes a CCD that is arranged for each vertical pixel column with respect to the pixel array of the unit 12 and that transfers a signal charge read from the light receiving unit 12 in the vertical direction.

  The signal charges transferred by each of the vertical transfer units 13 are transferred from the imaging unit 11 to the horizontal transfer unit 14 in units of rows (lines). The horizontal transfer unit 14 is composed of a CCD, transfers one row of signal charges transferred from the imaging unit 11 in the horizontal direction, and sequentially supplies them to the charge detection unit 15 provided at the end on the transfer destination side. The charge detection unit 15 is configured by, for example, a floating diffusion amplifier, detects the signal charge sequentially transferred by the horizontal transfer unit 14, converts the signal charge into a signal voltage, and outputs the signal voltage.

  The timing generator 16 drives, for example, four-phase vertical transfer pulses XV1 to XV1 that drive the vertical transfer unit 13 based on a vertical synchronization signal VD, a horizontal synchronization signal HD, and a clock signal CK having a fixed period that is a reference for the operation of the CCD image sensor. Timing signal generation circuit for generating various drive pulses (timing pulses) such as XV4, horizontal transfer pulses XH1 and XH2 for driving the horizontal transfer unit 14 and reset gate pulse XRG for resetting the charge detection unit 15, for example The drive pulses of the solid-state imaging devices that are diversified are controlled parametrically and programmable. The specific configuration and operation of the timing generator 16 will be described later in detail.

  FIG. 2 is a timing chart showing an example of a timing relationship between the vertical synchronization signal VD, the horizontal synchronization signal HD, and the vertical transfer pulses XV1 to XV4. Here, the case where this CCD image sensor is used as an imaging device of a camera is taken as an example. Therefore, the timing chart of FIG. 2 shows normal transfer, high-speed sweep transfer, charge readout transfer, and frame shift transfer within one vertical scanning period in order to realize the electronic zoom function, autofocus function, monitoring function, etc. of the camera. Each control timing is mixed.

  The waveform patterns of the vertical transfer pulses XV1 to XV4 change in time series, but various combinations of waveform pattern change timings can be adopted depending on the drive mode and drive timing of the CCD image sensor. In addition, switching of the waveform pattern of the vertical transfer pulses XV1 to XV4 is performed in the timing generator 16 by using a change in the horizontal synchronization signal HD as a trigger. Hereinafter, a specific configuration and operation of the timing generator 16 will be described.

  FIG. 3 is a block diagram illustrating an example of a specific configuration of the timing generator 16. In FIG. 3, a parameter group including a set of 16-bit parameter data, for example, which differs depending on various drive modes (operation modes) and drive timings of the CCD image sensor is prepared. Then, the timing generator 16 according to this example selects parameter data by matching various timing parameters to the driving mode, compares the selected parameter value with a set value, and generates a pulse based on the comparison result. Is configured to do.

  FIG. 4 is a timing chart showing an enlarged timing relationship in the vicinity of HD where the waveform pattern is switched. The change of the horizontal synchronization signal HD changes the selection parameter, and the mode changes. Here, when a large amount of parameter data with a large bit width is simply selected and processed, a large amount of parameters are accessed, and when setting data with a large bit amount and count data are compared with a comparator, the data until the data is determined. Since the transition time becomes long, the comparison operation frequency is lowered. In addition, when comparing each parameter, the number of gates of the comparator increases, leading to an increase in chip size.

  Therefore, the timing generator 16 according to the present example has a configuration in which data selection, comparison with set values, and pulse generation in accordance with driving modes of various timing parameters can be realized without using a register group or a memory. Adopted. The configuration will be specifically described below.

  In switching the drive mode of the CCD image sensor, the first selector 21 selects a parameter corresponding to the drive mode set from the parameter group in accordance with the change timing of the horizontal synchronization signal HD. The first selector 21 has a counter for counting the number of horizontal lines, and selects a parameter based on the count value of the counter. The selection parameter selected by the first selector 21 is given to the second selector 22.

  The second selector 22 divides the parameter selected by the first selector 21 into a plurality of data, for example, selects upper data and lower data in order. Here, the lower data changes every clock, while the upper data has a low change frequency. For this reason, when the second selector 22 is selected, the state transition circuit 31 performs control so that the lower order data having the higher count change frequency, in this example, the lower order data is selected in order. However, it is also possible to select from higher order data.

  On the other hand, the counter 28 counts a clock signal CK that is a reference for the operation of the CCD image sensor. The count data of the counter 28 is also 16-bit data corresponding to the parameter. The count data of the counter 28 is given to the third selector 29. The third selector 29 divides the count data of the counter 28 into a plurality corresponding to the second selector 22, and in this example, selects the upper data and the lower data in order. Similarly to the second selector 22, the counter 28 is also controlled by the state transition circuit 31 so that reading is performed from the lower side, that is, in the order of the lower bit and the upper bit.

  The parameter upper / lower data selected by the first selector 21 is given to the comparator 24 as one input thereof. The counter upper / lower data selected by the third selector 29 is supplied to the comparator 24 as the other input after passing through the increment circuit 30. First, the comparator 24 compares the parameter lower data given earlier with the counter lower data. The comparison result of the comparator 24 is stored in a flip-flop (F / F) 25. The state of the flip-flop 25 is triggered by the match result (match signal) of the comparator 24, and the bus right is transferred to the upper bus. The output of the flip-flop 25 is given to the flip-flop 26 of the next stage, the second conditional expression circuit 27, and the state transition circuit 31, respectively.

  In the next state, the comparator 24 compares the parameter upper data with the counter upper data. The comparison result is stored in the flip-flop 25. As a result, the comparison result of the lower data compared in the previous state is shifted from the flip-flop 25 to the flip-flop 26 and stored in the flip-flop 26. As a result, the outputs of the flip-flops 25 and 26 are set to the “H” level (logic 1) when both the lower data and the upper data match. The second conditional expression circuit (generating means) 27 receives the outputs of both the “H” level flip-flops 25 and 25 and generates a drive pulse.

  In this way, the parameter and count data are read out in the upper and lower parts, and the comparison processing is performed in the time division by the same comparator 24, so that the number of bits to be compared by the comparator 24 is halved. The gate size can be suppressed and the transition time until the data is determined can be shortened. Further, since only the comparison result of the comparator 24 is stored in the flip-flops 25 and 26, an increase in the number of gates is suppressed as compared with the case where the read lower data and upper data are held in the internal register or memory. can do.

  The count data of the counter 28 to be compared is incremented every cycle by the increment circuit 30. On the other hand, the comparator 24 compares the lower data in one cycle, compares the upper data in the second cycle, and performs a comparison process between the parameter data and the count data in a total of two cycles. As a result, with regard to inconsistency in which the counter upper data is switched, the first conditional expression circuit 23 predicts a carry of the lower data, and increments the count value of the counter 28 to be compared to perform the comparison so that there is no inconsistency. I am doing so.

  Here, the operation of the first conditional expression circuit 23 will be described more specifically. The counter 28 is a 16-bit counter and counts every clock from 0000 to FFFF. For example,..., 11FC, 11FD, 11FE, 11FF, 1200,. When it is desired to make a count comparison with 11FE, FE is first compared with the count lower data. The upper bit is compared with 11 in the next cycle (the count value is 11FF). Since the upper count value has not changed, it can be compared without any problem. However, when compared with 11FF, since it is 1200 in the next cycle, 11 and upper data 12 do not match. In order to prevent this, only when it matches the lower FF (first conditional expression), the upper data is compared by counting +1.

  For pulse generation with critical timing from the switching timing of the drive mode, the upper data is limited. Therefore, when the upper data is prefetched by the second conditional expression circuit 27 and the second conditional expression is satisfied, 2 is satisfied. It is possible to generate a waveform based only on the comparison of the lower data without adopting the comparison result of the upper data in the cycle. That is, the second conditional expression circuit 27 shows the comparison result of the upper data when the condition that the flip-flops 25 and 26 are active (both outputs are logic 1) and the arbitrary mode and any 8 bits match. Make it active without waiting. This condition (second conditional expression) is effective when it is desired to read only specific data quickly.

  As described above, in the timing generator 16 that generates drive pulses that change in time series, the count value of the counter 28 is sequentially incremented and the count value of the counter 28 is compared with the parameter value by the same comparator. Since the number of bits to be compared can be halved by dividing the number of bits into 24 in this example and in two steps in this example, the number of circuit gates can be reduced by that amount, and the transition time until data determination can be shortened, so that the comparison operating frequency Can be improved. In addition, when performing a series of operations in two stages, it uses a register group and memory for storing parameter data by adopting a configuration that stores only the comparison result without storing parameter data. Therefore, it is possible to suppress an increase in the gate scale as compared with the case of storing parameter data.

  Also, as described in the description of the prior art, in order to maintain the compatibility of the driving timing, there is a method of generating a waveform arbitrarily by setting it programmable by an external microcomputer. There is a concern about the increase in the number of gates due to the use of a register or memory (ROM) for saving data and the increase in the chip size associated therewith. On the other hand, in this embodiment, the parameter value is fixed, and the configuration corresponding to the drive mode is selected from the parameter group and read, so that it is not necessary to use a register or a memory. In addition, an increase in the number of gates and a complicated circuit configuration can be prevented.

  In addition, the operating frequency at the time of switching the driving mode is such that the selected parameter data is read out and compared in several times, so that the internal circuit is shared, the bus width is reduced, and the simple processing function Since optimization can be achieved, a compact arithmetic circuit with a high operating frequency can be realized. As for parameters that become a speed bottleneck, by prefetching data, problems such as an increase in gate scale due to programmable parameterization and a speed bottleneck at the time of switching, which were problematic in the prior art, can be solved.

  In the above embodiment, the case where the present invention is applied to a CCD image sensor has been described as an example. However, the present invention is not limited to this application example, and the present invention is a charge transfer type solid-state imaging device other than a CCD image sensor, Can be applied to all solid-state imaging devices including a timing signal generation circuit that generates drive pulses that change in time series, such as an XY address type solid-state imaging device represented by a CMOS image sensor.

  The solid-state imaging device according to the present embodiment described above is suitable for use as an imaging device in a camera module such as a digital still camera or a video camera, or a mobile terminal device equipped with an imaging function represented by a mobile phone. It is.

It is a block diagram which shows the outline of the whole structure of the CCD image sensor to which this invention is applied. 6 is a timing chart showing an example of a timing relationship among a vertical synchronization signal VD, a horizontal synchronization signal HD, and vertical transfer pulses XV1 to XV4. It is a block diagram which shows an example of a specific structure of a timing generator. It is a timing chart which expands and shows the timing relationship of HD vicinity where a waveform pattern switches.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Imaging part, 12 ... Light receiving part, 13 ... Vertical transfer part, 14 ... Horizontal transfer part, 15 ... Charge transfer part, 16 ... Timing generator, 21 ... 1st selector, 22 ... 2nd selector, 23 ... 1st condition Expression circuit, 24 ... Comparator, 25, 26 ... Flip-flop (F / F), 27 ... Second conditional expression circuit, 28 ... Counter, 29 ... Third selector, 30 ... Increment circuit, 31 ... State transition circuit

Claims (4)

A solid-state imaging device including a timing signal generation circuit that generates a drive signal that changes in time series,
The timing signal generation circuit includes:
A first selection means for selecting parameter data corresponding to a driving mode to be set from a parameter group consisting of a set of parameter data corresponding to various driving modes when switching the driving mode of the solid-state imaging device;
Counting means for performing a counting operation in synchronization with a clock signal having a fixed period;
Comparison means for performing time division by comparing the parameter data selected by the first selection means with the count data of the counting means in a plurality of stages;
A solid-state imaging device comprising: generating means for generating the drive signal based on a comparison result for each stage of the comparing means. The comparison means includes
Second selection means for selecting the parameter data selected by the first selection means into a plurality of data and sequentially selecting the data;
A third selection unit that sequentially selects the count data of the counting unit and divides the data into a plurality of data;
The solid-state imaging device according to claim 1, wherein the data selected by the second and third selection means are compared in order. The second selection means selects the parameter data selected by the first selection means in order from the lower side,
The solid-state imaging device according to claim 2, wherein the third selection unit sequentially selects count data of the counting unit from the lower order side. Storage means for storing a comparison result for each stage of the comparison means;
The solid-state imaging device according to claim 1, wherein the generation unit generates the drive signal based on the stored contents of the storage unit.

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