JP2008187232A - Solid-state imaging element drive and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate various drive pulses with a small memory capacity by flexibly designing pulse generation data. <P>SOLUTION: A solid-state imaging element drive comprises memories 46, 47 for storing a CLK_MEM command (2), where status data indicating the initial state of a drive pulse are combined with time designation data, where time from when the drive pulse based on the status data is outputted to, when the drive pulse is changed is designated; a memory 44 for storing inverting timing designation data, where the inverting timing of the drive pulse under output is designated according to the number of times for changing the drive pulse counted, based on the time designation data; and an output control section 49 that outputs the drive pulse, based on the status data to an image pickup device 11; counts the number of times for changing the drive pulse based on the time designation data; and performs control for inverting the drive pulse under output partially, based on the number of change times and the inverting timing designation data. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state image sensor driving apparatus that generates and outputs drive pulses for driving a solid-state image sensor.

  A solid-state image sensor such as a CCD type or a CMOS type used in an image pickup apparatus (hereinafter referred to as a digital camera) such as a digital still camera, a digital video camera, or a camera-equipped mobile phone has a drive pulse generated by the image pickup element drive device. Driven by. For example, in a CCD solid-state imaging device, a vertical charge transfer path (VCCD) is driven by a vertical transfer pulse, and a horizontal charge transfer path (HCCD) is driven by a horizontal transfer pulse.

  Such a drive pulse is generated based on pulse change point data or repetition number (loop number) data stored in a register or memory in advance, but the number of timing pulses for driving the solid-state image sensor is There are many types, and the pulse waveforms are complicated due to differences in drive modes (for example, normal transfer mode and high-speed transfer mode). Therefore, there is a problem that the amount of data for generating the drive pulse is large, and a register and a memory for storing the drive pulse have a large capacity.

  Therefore, in Patent Document 1 below, four memories are prepared, time series data (logic status) is held in the first memory, and the value of the period length from the pulse change point to the next change point is stored in the second memory. By holding the repetition value of the logic change in one cycle in the third memory, holding the repetition value of the cycle itself in the fourth memory, and combining the stored data of these four memories, various drive pulses can be transmitted. Is generated.

JP 2002-512270 A

  In recent years, there has been a high demand for users of digital cameras, and in order to increase their functionality and performance, the drive pulses of solid-state image sensors have become complex in period and pulse waveform, and are required for pulse generation. The amount of data is also increasing. The above-mentioned conventional technique can cope with the drive pulse of the two-mode / two-stage loop, but if the drive pulse of the multi-mode / multi-stage loop becomes necessary, the memory capacity must be increased.

  Also, every time the digital camera design specifications are changed to make it more multifunctional, the drive pulse generation data must also be changed. If the pulse generation flexibility is not high, the cost required for the pulse data design will increase. .

  An object of the present invention is to provide a solid-state imaging device driving apparatus and a digital camera that enable flexible design of pulse generation data and that can generate a wide variety of driving pulses with a small memory capacity.

  The solid-state imaging device driving device of the present invention is a solid-state imaging device driving device that generates and outputs a driving pulse for driving the solid-state imaging device, and an initial state of the driving pulse to be output to the solid-state imaging device is logical. Command data combining initial status data represented by a value and waiting time designation data designating a waiting time from when a driving pulse is output based on the initial status data until the driving pulse is changed is stored. A command data memory, and an inversion timing designation data memory for storing inversion timing designation data that designates the inversion timing of the drive pulse being output according to the number of changes of the drive pulse counted based on the waiting time designation data; When the command data is specified, the driving pulse based on the initial status data Is output to the solid-state imaging device, and thereafter, the number of changes in the drive pulse is counted based on the waiting time designation data, and the number of drive pulses being output is calculated based on the number of changes and the inversion timing designation data. And an output control unit that performs control to invert a part.

  In the solid-state imaging device driving device according to the present invention, the inversion timing designation data memory stores a setting value in association with each output destination of the drive pulse, and the output control unit is based on the waiting time designation data. When there is the set value that matches the number of changes of the drive pulse counted in this way, the drive pulse output to the output destination corresponding to the matched set value is inverted.

  The solid-state imaging device driving device of the present invention includes a status memory in which status data in which a driving pulse to be output to the solid-state imaging device is represented by a logical value for each of a large number of addresses is stored, and the command data memory includes: Address designation command data for sequentially designating the read address of the status memory is stored, and when the address designation command data is designated, the output control unit sets the read address designated sequentially by the address designation command data. Control is performed to output a drive pulse based on the status data to the solid-state imaging device.

  The solid-state imaging device driving device according to the present invention includes a control unit having a serial register that receives and stores a plurality of setting data, and the command data and the address designation command data specified by the output from the serial register. A sequence unit that generates the drive pulse by sequence control based on the sequence unit, the sequence unit being provided independently of the control unit, and the inversion timing designation data memory, the status memory, and the command data memory are included in the sequence Provided in the section.

  In the solid-state imaging device driving device according to the present invention, the solid-state imaging device is a CCD type solid-state imaging device having a vertical charge transfer path and a horizontal charge transfer path, and the command data memory includes a plurality of operation periods. A first memory unit storing data for designating an operation for a horizontal transfer period, and a second memory unit storing either the command data or the address designation command data for each of the plurality of horizontal transfer periods With.

  In the solid-state imaging device driving device according to the present invention, the address designation command data outputs address designation data for designating the read address corresponding to the drive pulse output at the beginning of one horizontal transfer period, and a drive pulse. Wait time until the next drive pulse is changed, wait time / read designation data for designating the read address corresponding to the drive pulse to be output when the wait time has elapsed, and the wait time / read First loop designating command data designating the number of repetition loops of designated data, wherein the command data designates the initial status data, the waiting time data, and the second number of repeating loops of the waiting time data. Loop designation command data, and the second memory unit A clock memory storing data, the waiting time / reading designation data, the initial status data, and the waiting time data, and a loop storing the first loop designation command data and the second loop designation command data And a control memory.

  In the solid-state imaging device driving device according to the present invention, the first memory unit stores a sequence memory storing command data designating a read address of the clock memory, and a read address of the loop control memory at the same timing as the designation. A loop pointer memory in which command data to be specified is stored.

  In the solid-state imaging device driving device according to the present invention, the inversion timing designation data memory, the status memory, the clock memory, and the loop control memory are respectively a first group for vertical transfer pulses and a second group for readout pulses. , And divided into a three-group configuration of a third group for horizontal transfer pulses.

  The imaging device of the present invention includes the solid-state imaging device driving device and the solid-state imaging device.

  According to the present invention, pulse generation data can be designed flexibly, and a wide variety of drive pulses can be generated with a small memory capacity.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a functional block diagram showing main parts of a digital camera according to an embodiment of the present invention. The digital camera shown in the figure captures a CCD solid-state image sensor 11 and analog image data output from the solid-state image sensor 11, and performs correlated double sampling processing, signal amplification processing, black level removal processing, analog digital (AD) conversion processing. An analog front end (AFE) circuit 12 that performs the above, a digital signal processor (DSP) 13 that takes in digital image data output from the AFE circuit 12 and performs a YC conversion process, a compression / decompression process, and the like, and a timing generator described later in detail (TG: drive pulse generation circuit) 14 and drive circuit (V-drv) 15 are provided.

  The timing generator 14 operates based on the master clock signal given from the AFE circuit 12 and the set value data given from the DSP 13, and the horizontal synchronization signal HD, the vertical synchronization signal VD, the horizontal transfer pulses φH1 to 8 and the vertical transfer pulse φV1. ˜8, transfer gate signals (read pulse signals) φTG1˜8, line memory drive pulse φLM, and AFE drive signal for driving the AFE circuit 12 are generated. Hereinafter, φH1-8, φV1-8, φTG1-8, and φLM are collectively referred to as drive pulses.

  The horizontal synchronizing signal HD and the vertical synchronizing signal VD are output from the timing generator 14 to the DSP 13, and the horizontal transfer pulses φH1 to 8H are directly output to the solid-state imaging device 11 because they are low voltages of about 3V, and the vertical transfer pulses φV1 to 8V, The read pulses φTG 1 to 8 and the line memory drive pulse φLM are boosted by the drive circuit 15 and then output to the solid-state imaging device 11.

  FIG. 2 is an explanatory diagram of the solid-state imaging device 11 shown in FIG. The solid-state imaging device 11 includes a number of photodiodes (PD) 21 arranged in a two-dimensional array on the surface of a semiconductor substrate, and a vertical charge transfer path (VCCD) 22 formed along each photodiode row. A horizontal charge transfer path (HCCD) 23 provided on the lower side of the semiconductor substrate, a line memory (LM) 24 provided between the end of each vertical charge transfer path 22 and the horizontal charge transfer path 23, And an output amplifier 25 provided at the output stage of the horizontal charge transfer path 23.

  The line memory 24 temporarily accumulates signal charges transferred by the vertical charge transfer path 23 as described in, for example, Japanese Patent Laid-Open No. 2000-350099, and stores the accumulated charges according to the line memory drive pulse φLM. This is output to the horizontal charge transfer path 23, and the timing is controlled to enable the horizontal addition of signal charges.

  In the solid-state imaging device 11 having such a configuration, when the readout pulses φTG1 to 8 are applied to the electrode that also serves as the readout electrode among the vertical transfer electrodes that constitute the vertical charge transfer path 22, the signal charge of the corresponding photodiode 21 is generated. It is read out in the potential packet formed under the electrode. Then, by applying the vertical transfer pulses φV 1 to 8 to the vertical charge transfer path 22, the signal charge on the vertical charge transfer path 22 is transferred in the direction of the horizontal charge transfer path 23, and each vertical charge transfer path 22 has an end portion. Are transferred to the line memory 24 and temporarily held.

  The signal charges on the line memory 24 are transferred to the horizontal charge transfer path 23 according to the line memory drive pulse φLM, and the signal charges transferred onto the horizontal charge transfer path 23 are output from the output amplifier 25 according to the horizontal transfer pulses φH1-8. Forwarded in the direction. The output amplifier 25 outputs a voltage value signal corresponding to the charge amount of each signal charge transferred to the output stage of the horizontal charge transfer path 23 to the AFE circuit 12 as image data.

  The signal charge for one horizontal line on the vertical charge transfer path 22 is transferred in the direction of the horizontal charge transfer path 23 by one stage according to the vertical transfer pulses φV1 to φ8, and the signal charge for one horizontal line is transferred from the line memory 24 to the horizontal charge transfer path. After the signal charge for one row is transferred in the horizontal direction and output from the output amplifier 25 is finished, the next stage of the signal charge on the vertical charge transfer path 22 in the horizontal charge transfer path 23 direction is completed. The operation of transferring minutes is repeated.

  Although the terms “vertical” and “horizontal” have been described, this means “one direction” along the light receiving surface of the solid-state imaging device and “a direction substantially orthogonal to the one direction”.

  FIG. 3 is a detailed configuration diagram of the timing generator (TG) 14 shown in FIG. The timing generator 14 includes a control unit & trigger pulse generation unit (hereinafter referred to as a control / trigger pulse generation unit) 30 provided conventionally and a sequencer unit 40 provided in the present embodiment. By providing the sequencer unit 40 separately from the control / trigger pulse generation unit 30, the number of registers can be reduced, and the use performance is improved. This is because, in the present embodiment, pulse generation, which has been conventionally performed by register setting of the control / trigger pulse generation unit, is generated by the sequencer unit 40 as will be described later, so that setting registers can be reduced accordingly. It is. In addition, it is more efficient to generate the pulse by the sequence than to generate the pulse by the register, and the data can be reduced.

  The control / trigger pulse generation unit 30 takes in setting value data (data for generating AFE drive control signals, drive pulses φH1 to 8, φTG1 to 8, φLM, φV1 to 8) given as serial data from the DSP 13. The AFE drive signal, the generated horizontal synchronization signal HD, and vertical synchronization signal VD are output.

  The sequencer unit 40 generates and outputs horizontal transfer pulses φH 1 to 8, vertical transfer pulses φV 1 to 8, read pulses φTG 1 to 8, and line memory drive pulse φLM as will be described in detail later.

  The control / trigger pulse generation unit 30 writes the set value data supplied from the DSP 13 to the serial register 31 and the later-described memories 42, 43, 44, 46, 47, 48 of the serial register 31 and the sequencer unit 40. A control unit 32 that performs control, a master counter 33 that is a gray code counter, and a comparator (comparator) 34 are provided.

  The comparator 34 compares the data related to the horizontal synchronization signal HD and the vertical synchronization signal VD among the data written in the serial register 31 with the output value of the master counter 33, and sends the horizontal synchronization signal HD and the vertical synchronization signal VD to the DSP 13. In addition to outputting, the trigger signal is output to the sequencer unit 40. The serial register 31 outputs drive pulse generation data to the sequencer unit 40 as address data.

  The sequencer unit 40 includes a first memory unit 41, a second memory unit 45, a status memory (STS_MEM) 48, an inversion timing designation memory (INV_NUM_MEM) 44, and an output control unit 49.

  The output control unit 49 controls the memories 42, 43, 44, 46, 47, and 48 based on the output from the serial register 31 and outputs drive pulses.

  FIG. 4 is a diagram showing the memory configuration and stored data of the first memory unit 41, the second memory unit 45, the status memory (STS_MEM) 48, and the inversion timing designation memory (INV_NUM_MEM) 44.

  In the status memory (STS_MEM) 48, status data representing drive pulses as logical values is stored with an address. As the status data, a value of “1” or “0” is set for each electrode to which a drive pulse is to be output. For example, if the logical value corresponding to the electrode is “1”, the output control unit 49 A high level pulse is output to the electrode, and if the logical value is “0”, an operation of outputting a low level pulse to the electrode is performed. The status memory 48 has a memory configuration divided into three groups of “for vertical transfer pulse”, “for read pulse and line memory drive pulse”, and “for horizontal transfer pulse”. How to divide the memory configuration is arbitrary by the designer, but in the present embodiment, the most efficient segmentation is realized by adopting the above three-group configuration.

  The first memory unit 41 includes a sequence memory (SEQ_MEM) 42 and a loop pointer memory (LP_MEM) 43.

  In the sequence memory 42, a plurality of horizontal transfer periods (horizontal synchronization signal HD of the horizontal synchronization signal HD) constituting one operation period (a period from the fall of the vertical synchronization signal VD to the next fall of the vertical synchronization signal VD, hereinafter also referred to as 1V). Command data (SEQ_MEM command) designating the operation is stored with an address for each period from the trailing edge to the next falling edge of the horizontal synchronizing signal HD (hereinafter also referred to as 1H).

  In the loop pointer memory 43, command data (LP_MEM command) for specifying a repetitive operation in 1H is stored for each of a plurality of 1H constituting 1V with an address. In the sequence memory 42 and the loop pointer memory 43, the same address is given to the command data for the same horizontal transfer period.

  The second memory unit 45 includes a clock memory (CLK_MEM) 46 and a loop control memory (LC_MEM) 47. Both memories 46 and 47 have a memory configuration divided into three groups of “for vertical transfer pulse”, “for read pulse and line memory drive pulse”, and “for horizontal transfer pulse”. How to divide the memory configuration is arbitrary by the designer, but in the present embodiment, the most efficient segmentation is realized by adopting the above three-group configuration.

  In the clock memory 46, command data (CLK_MEM command) for specifying the operation within 1H in units of clocks is stored with an address. There are two types of CLK_MEM commands: CLK_MEM command (1) and CLK_MEM command (2).

  The CLK_MEM command (1) outputs address designation data (start command) for designating the storage address of the status data corresponding to the drive pulse to be output first in 1H, and the drive pulse after outputting the drive pulse. By a combination of a waiting time to change and a waiting time / read designation data (wait command, wait & call command) for designating a storage address of status data corresponding to a drive pulse to be output when this waiting time has passed Composed.

  The CLK_MEM command (2) outputs the initial status data representing the driving pulse to be output first in 1H as a logical value, the data specifying the address of the inversion timing specifying memory, and the driving pulse after outputting the driving pulse. It is configured by a combination with waiting time designation data (wait command) for designating the waiting time until it is changed.

  In the loop control memory 47, command data (LC_MEM command) designating repetition of either the CLK_MEM command (1) or (2) is stored with an address.

  In the inversion timing designation memory (INV_NUM_MEM) 44, inversion timing designation data that designates the inversion timing of the drive pulse being output according to the number of changes of the drive pulse counted based on the wait command of the CLK_MEM command (2). Stored with an address. The inversion timing designation data is, for example, data in which a predetermined set value is associated with each output destination of the drive pulse, and when this set value matches the number of changes of the drive pulse, the setting that matches the number of changes This command specifies that the drive pulse output to the output destination corresponding to the value is inverted (from high level to low level or from low level to high level). The inversion timing designation memory 44 has a memory configuration divided into three groups of “for vertical transfer pulse”, “for read pulse and line memory drive pulse”, and “for horizontal transfer pulse”. How to divide the memory configuration is arbitrary by the designer, but in the present embodiment, the most efficient segmentation is realized by adopting the above three-group configuration.

  Examples of the SEQ_MEM command include a call command and a loop command. The call command is a command for designating calling of the start address of the CLK_MEM command constituting 1H. The loop command is a command that specifies repetition of the call command.

  An example of the LP_MEM command is a call command. The call command is a command that specifies the start address of the LC_MEM command that specifies repetition of the CLK_MEM command in 1H.

  An example of the LC_MEM command is a loop command. The loop command is a command that specifies repetition of the CLK_MEM command.

  The command data, status data, and inversion timing designation data stored in each of the memories 42, 43, 44, 46, 47, and 48 are output from the DSP 13, supplied from the control unit 32 to the sequencer unit 40, and stored therein.

Next, in order to describe the operation of the output control unit 49, an example of data stored in each memory will be described.
FIG. 5 is a timing chart of drive pulses. This timing chart is a timing chart at the time of high-speed sweep driving performed before outputting a signal from the CCD type solid-state imaging device and signal charge reading from the photodiode continuous to the vertical charge transfer path.

  When starting, first, the drive of the vertical charge transfer path is started with the waveform of the pattern (Pat) 1, and then the sweep drive is performed by looping the pattern 2 of the high-speed pulse waveform 172 times. Thereafter, pattern 4, pattern 3, pattern 4, pattern 3,... Are repeated, and then pattern 5 is driven to perform idle transfer on the vertical charge transfer path. Then, by applying a read pulse signal in pattern 6, signal charge is read from the corresponding photodiode to the vertical charge transfer path, and thereafter, the process proceeds to patterns 7, 8,.

  In order to generate the drive pulses of the patterns 1, 2,... Shown in FIG. 5, the sequencer unit 40 generates pattern 1 at the address “0x000” of the sequence memory 42 as shown in the upper left of FIG. A call command for designating the start address of the CLK_MEM command is stored. The next address “0x001” stores a call command that specifies the start address of the CLK_MEM command of pattern 2, and the next address “0x002” includes a loop command that specifies that pattern 2 is repeated 172 times. The call command for designating the start address of the CLK_MEM command of pattern 4 is stored in the next address “0x003”.

  In FIG. 5, the notation of call (address A, address B, address C) is a command in which call (address A) is “for vertical transfer pulse”, and call (address B) is “for read pulse and line memory drive”. The command for “pulse” and call (address C) indicate that the command is for “horizontal transfer pulse”.

  In the loop pointer memory 43 in which the same address designation as the sequence memory 42 is performed, the call command for designating the start address of the LC_MEM command of the pattern 1 is assigned to the address “0x000” as shown in the upper right part of FIG. The call command for designating the start address of the LC_MEM command of pattern 2 at address “0x001”, no operation (command to do nothing) at the next address “0x002”, and pattern 4 at the next address “0x003” A call command for designating the start address of the LC_MEM command is stored.

  FIG. 6 is an enlarged view of the pattern 1 shown in FIG. In the pattern 1, the timings of the transfer pulses φV2, φV3,..., ΦV7 applied to the vertical transfer electrodes V2, V3,. The transfer pulse φV2 rises after a wait time “76” (counted by the number of clocks of the master clock, the same applies hereinafter) from the start time 0, and the transfer pulse φV3 rises after a wait time “600” with respect to the transfer pulse φV2, and thereafter In order, the transfer pulses φV4, φV5, φV6, and φV7 are designed to rise after the waiting time “600”.

  In order to perform this pulse design, as shown in the upper left part of FIG. 6, a start command which is one of CLK_MEM commands (1) for specifying the start address of the status memory 48 is assigned to the address “0x000” of the clock memory 46. Stored is a wait command that is one of CLK_MEM commands (1) for designating the clock waiting time “76” at the address “0x001”, and CLK_MEM for designating the clock waiting time “600” at the next address “0x002”. A wait command which is one of commands (1) is stored.

  The clock waiting time “600” of the first transfer pulse φV3 is repeated four times as φV4, φV5, φV6, and φV7. When this is sequentially written to the next address of the clock memory 46, the command data is stored. Capacity will increase.

  Therefore, in this embodiment, as shown in the upper right part of FIG. 6, a loop command for designating a loop for repeating the instruction command of the address “0x002” of the clock memory four times to the address “0x000” of the loop control memory 47 is provided. Write it down. As a result, the instruction of the waiting time “600” is repeated four times, and each pulse waveform is generated as described in FIG.

FIG. 7 is a diagram illustrating an example of data stored in the clock memory 46 and the status memory 48 and a timing chart of pattern 1 based on the data example.
The status memory 48 stores status data in which all the electrodes V1, V2,..., V8 are all “0” at the address “0x000”, and only the electrode V2 is “1” at the address “0x001”. Status data is stored, status data with electrodes V2, V3 set to "1" is stored at address "0x002", and status data with electrodes V2, V3, V4 set to "1" at address "0x003". , ..., address data “0x006” stores status data in which the electrodes V2, V3, V4, V5, V6, and V7 are set to “1”.

Next, the operation of the output control unit 49 will be described.
When the address “0x000” is designated by the output data from the serial register 31, the output control unit 49 reads the call command (set to 1) stored in the address “0x000” of the sequence memory 42 and also the loop pointer. A call command (set to 2) stored in the address “0x000” of the memory 43 is read. Next, the output control unit 49 reads the CLK_MEM command specified by the call command 1 and also reads the LC_MEM command specified by the call command 2.

  Next, the output control unit 49 reads the status data of the address “0x000” designated by the start command of the address “0x000” of the read CLK_MEM command, and outputs a drive pulse based on the status data. In this case, the potentials of all the electrodes V1, V2,..., V8 are at a low level.

  Next, the output control unit 49 reads the status data of the next address “0x001” in the status memory 48 after the waiting time “76” specified by the wait command of the next address “0x001” of the CLK_MEM command has passed, and this status data The drive pulse based on is output. As a result, the potential of the electrode V2 rises to a high level after a waiting time “76” from the start time of 1H. As described above, the wait command of CLK_MEM (1) is a command for designating the next address of the address of the status data corresponding to the drive pulse currently being output as the address of the status data corresponding to the drive pulse output after the waiting time has elapsed. From the status memory 48, every time the waiting time specified by the wait command elapses, the read address is incremented by one and the status data is read.

  Although only the example of executing the call command is described here, when the wait & call command is executed, the output control unit 49 responds to the drive pulse currently being output after the waiting time specified by the wait & call command has elapsed. Instead of reading the status data from the next address of the status data address, the status data is read by jumping to the address specified by the wait & call command.

  Next, the output control unit 49 reads the status data of the next address “0x002” of the status memory 48 after the waiting time “600” specified by the wait command of the next address “0x002” of the CLK_MEM command has passed, and this status data The drive pulse based on is output. As a result, the potential of the electrode V3 rises to the high level after a waiting time “600” after the potential of the electrode V2 rises to the high level.

  Note that the wait command at the address “0x002” is designated to loop four times in the loop control memory (FIG. 6). For this reason, the output control unit 49 reads the status data of the next address “0x003” of the status data corresponding to the drive pulse currently being output after the waiting time “600” has elapsed since the potential of the electrode V3 became high level. A drive pulse based on the status data is output. Subsequently, the output control unit 49 reads the status data of the next address “0x004” after the waiting time “600” has elapsed, outputs a drive pulse based on this status data, and after the waiting time “600” has elapsed, the next address “0x005”. The status data of the next address “0x006” is read after the waiting time “600” has elapsed, and the drive pulse based on the status data is output.

  In the above description, the operation when the CLK_MEM command specified in the sequence memory 42 is the CLK_MEM command (1) is taken as an example. However, in the following, the drive pulses as shown in FIGS. The operation when generating according to 2) will be described.

  In this case, as shown in the upper left diagram of FIG. 8, the clock memory 46 has an initial status “00000000” that is one of the CLK_MEM commands (2) and an inversion timing designation at the address “0x000” of the clock memory 46. The address “0x000” of the memory 44 is stored, the wait command which is one of the CLK_MEM commands (2) specifying the clock waiting time “76” is stored in the address “0x001”, and the next address “0x002” waits for the clock A wait command which is one of CLK_MEM commands (2) for designating the time “600” is stored.

  Further, the address “0x000” in the inversion timing designation memory 44 corresponds to the set value “0” for the electrode V1 and the set value “1” for the electrode V2, as shown in the upper right diagram of FIG. The electrode V3 corresponds to the set value “2”, the electrode V4 corresponds to the set value “3”, the electrode V5 corresponds to the set value “4”, and the electrode V6 corresponds to the set value “2”. 5 ”corresponds, the set value“ 6 ”corresponds to the electrode V7, and the set value“ 0 ”corresponds to the electrode V8. Other data stored in the memory is the same as in FIGS.

Next, the operation of the output control unit 49 will be described.
When the address “0x000” is designated by the output data from the serial register 31, the output control unit 49 reads the call command (set to 1) stored in the address “0x000” of the sequence memory 42 and also the loop pointer. A call command (set to 2) stored in the address “0x000” of the memory 43 is read. Next, the output control unit 49 reads the CLK_MEM command (2) specified by the call command 1 and also reads the LC_MEM command specified by the call command 2.

  Next, the output control unit 49 outputs a drive pulse based on the initial status data of the address “0x000” in the read CLK_MEM command (2). As a result, the potentials of all the electrodes V1, V2,..., V8 are at a low level.

  Next, the output control unit 49 increases the number of changes of the drive pulse being output by one when the wait time specified by the wait command of the next address “0x001” of the CLK_MEM command (2) has elapsed, Count the number of drive pulse changes. When the waiting time “76” has elapsed from the output of the drive pulse and the number of changes of the drive pulse becomes “1”, the output control unit 49 performs the inversion specified by the command of the address “0x000” of the CLK_MEM command (2). The set value stored at the address “0x000” of the timing designation memory 44 is compared with the counted number of changes. In this case, since the set value “1” matches the number of changes, the output control unit 49 sets the potential of the electrode V2 corresponding to the set value “1” to a high level.

  Next, when the wait time “600” specified by the wait command of the next address “0x002” of the CLK_MEM command (2) has elapsed and the drive pulse change count becomes “2”, the set value “2” is changed. Therefore, the output control unit 49 sets the potential of the electrode V3 corresponding to the set value “2” to a high level.

  The wait command at the address “0x002” of the CLK_MEM command (2) is designated to loop four times in the loop control memory (FIG. 6). Therefore, the output control unit 49 sets the potential of the electrode V4 corresponding to the set value “3” to the high level after the elapse of the waiting time “600” after the potential of the electrode V3 changes to the high level, and further sets the waiting time “ After the elapse of 600 ", the potential of the electrode V5 corresponding to the set value" 4 "is set to the high level, and after the waiting time" 600 "elapses, the potential of the electrode V6 corresponding to the set value" 5 "is set to the high level. After the elapse of time “600”, the potential of the electrode V7 corresponding to the set value “6” is set to the high level.

  Here, for the sake of explanation, an example in which the same drive pulse is generated by both the CLK_MEM commands (1) and (2) has been described. However, in practice, the CLK_MEM command (1) and ( Data is stored in each memory so that one of 2) is selectively executed. The method of generating the drive pulse based on the CLK_MEM command (2) is effective because the number of changes in the drive pulse is small, and the frequency of the logical value between the status of the drive pulse being output and the status of the next drive pulse is effective. In such a case, the drive pulse is generated based on the CLK_MEM command (2). In other cases, the drive pulse is generated based on the CLK_MEM command (1). Store it.

  As described above, in the digital camera according to the present embodiment, the data for specifying the operation for 1V is stored in the sequence memory 42 and the loop pointer memory 43 in units of 1H, and the operation for 1H is performed in the clock memory 46 by the clock. The loop control memory 47 stores a loop instruction corresponding to 1H, the status memory 48 stores logical value transitions, and a sequencer unit having these memories 42, 43, 46, 47, 48 Since 40 is configured to start the sequence operation at the start address designated by the serial register 31, it is possible to generate complicated and diverse drive pulses by using data stored in a memory having a small capacity.

  In addition, the digital camera according to the present embodiment generates a drive pulse that has a small number of changes and has a high logical frequency overlap between the status corresponding to the drive pulse being output and the status corresponding to the next drive pulse. In this case, a sufficient drive pulse can be generated by the inversion timing designation memory 44 having a data amount smaller than that of the status memory 48. For this reason, the memory capacity can be reduced as a whole by properly using the status memory 48 and the inversion timing designation memory 44 depending on the operation mode.

  Further, data communication within the timing generator 14 of the present embodiment is performed by serial communication. However, if there are no restrictions on the access bits for serial communication, the sequence memory 42 and the loop pointer memory 43 are configured by the same memory. Therefore, the memory can be further reduced in size.

  Furthermore, in the present embodiment, since the clock command and the loop command stored in the second memory unit 45 are stored in different memories 46 and 47 and can be read separately from each other, the loop judgment is delayed at the same time as the clock command. It becomes possible to do without. Thereby, there is no restriction on the read timing by the loop judgment, and it is possible to cope with a wait command for each clock.

  Furthermore, in the present embodiment, the clock memory address that requires the loop is specified by the loop instruction of the loop control memory 47, so that it is possible to deal with multi-stage loops and nested loops without increasing the memory, and the chip size and counters for the multi-stages. If there is no restriction on providing the multi-stage loop, any number of multi-stage loops can be incorporated.

In this case, as a method of indicating the end of the loop during one horizontal transfer period,
(B) A control register for designating the number of loop stages is provided, and a variable stage loop is set by register setting. (C) An end bit is provided for the loop instruction in the loop control memory, and by command setting. There are three possible ways to make the loop variable.

  Furthermore, in this embodiment, command data is used as data to be stored in the memory, and the loop instruction is effectively utilized to realize a multi-stage loop, so that the memory capacity for storing command data can be reduced. it can. In addition, since the status memory 48 is configured to call an address with a call command, the data capacity of the status data can be reduced, and the memory chip can be further reduced in size.

  In this embodiment, since one operation mode is divided in units of horizontal transfer periods, and one horizontal transfer period is divided in units of clocks, the combination can be easily changed and the flexibility of pulse generation can be increased. it can.

  It is also possible to incorporate a loop instruction in the clock memory without using the loop pointer memory 43 or the loop control memory 47. In this case, however, the loop instruction in the clock memory must be determined once and then the instruction at the loop destination must be read. Therefore, one clock is read at the loop determination and one clock is read at the loop destination instruction. It becomes a restriction of. If the system allows this restriction, the memory capacity can be further reduced.

It is a functional block diagram of the principal part of the digital camera which concerns on one Embodiment of this invention. It is a principal block diagram of the solid-state image sensor shown in FIG. It is a detailed block diagram of the timing generator shown in FIG. FIG. 4 is a memory configuration diagram of the timing generator shown in FIG. 3. 5 is a drive pulse timing chart for explaining the relationship between the sequence memory and the loop pointer memory shown in FIG. 4. 6 is an enlarged timing chart of pattern 1 in FIG. 5 for explaining the relationship between the clock memory and the loop control memory shown in FIG. 4. FIG. 7 is the same timing chart as FIG. 6 of drive pulses for explaining the relationship between the clock memory and the status memory shown in FIG. 4. FIG. 7 is the same timing chart as FIG. 6 of drive pulses for explaining the relationship between the clock memory and the inversion timing designation memory shown in FIG. 4.

Explanation of symbols

11 Solid-state image sensor 12 AFE circuit 13 DSP
14 Timing generator (TG)
15 Drive circuit 21 Photo diode 22 Vertical charge transfer path (VCCD)
23 Horizontal charge transfer path (HCCD)
24 Line Memory 30 Control Trigger Pulse Generation Unit 31 Serial Register 32 Setting Value Write Control Unit 33 Master Counter 34 Comparator 40 Sequencer Unit 41 First Memory Unit 42 Sequence Memory (SEQ_MEM)
43 Loop pointer memory (LP_MEM)
44 Inversion timing specification memory (INV_NUM_MEM)
45 Second memory section 46 Clock memory (CLK_MEM)
47 Loop control memory (LC_MEM)
48 Status memory (STS_MEM)
49 Output controller

Claims (9)

A solid-state imaging device driving apparatus that generates and outputs a driving pulse for driving a solid-state imaging device,
Specify the initial status data in which the initial state of the drive pulse to be output to the solid-state image sensor is expressed by a logical value, and the waiting time from when the drive pulse is output based on the initial status data to when the drive pulse is changed Command data memory for storing command data combined with the waiting time designation data,
An inversion timing designation data memory storing inversion timing designation data designating the inversion timing of the drive pulse being output according to the number of changes of the drive pulse counted based on the waiting time designation data;
When the command data is designated, a drive pulse based on the initial status data is output to the solid-state imaging device, and thereafter, the number of changes of the drive pulse is counted based on the waiting time designation data, and the number of changes And an output control unit that performs control to invert a part of the drive pulse being output based on the inversion timing designation data. The solid-state imaging device driving device according to claim 1,
In the inversion timing designation data memory, a set value is stored in association with each output destination of the drive pulse,
The output control unit, when there is the set value that matches the number of changes of the drive pulse counted based on the waiting time designation data, a drive pulse that is output to an output destination corresponding to the matching set value A solid-state imaging device driving device to be reversed. The solid-state image sensor driving device according to claim 1 or 2,
A status memory in which status data in which a drive pulse to be output to the solid-state image sensor for each of a plurality of addresses is represented by a logical value is stored;
The command data memory stores address designation command data for sequentially designating the read address of the status memory,
When the address designation command data is designated, the output control unit controls the output of the drive pulse based on the status data of the read addresses sequentially designated by the address designation command data to the solid-state imaging element. Drive device. The solid-state image sensor driving device according to claim 3,
A control unit having a serial register for receiving and storing a plurality of setting data;
A sequence unit that generates the drive pulse by sequence control based on either the command data specified by the output from the serial register or the address specification command data;
The sequence unit is provided independently of the control unit,
A solid-state image sensor driving device in which the inversion timing designation data memory, the status memory, and the command data memory are provided in the sequence unit. The solid-state image sensor driving device according to claim 4,
The solid-state imaging device is a CCD type solid-state imaging device having a vertical charge transfer path and a horizontal charge transfer path,
The command data memory stores a first memory unit storing data for designating operations for a plurality of horizontal transfer periods constituting one operation period, and the command data and the address for each of the plurality of horizontal transfer periods A solid-state image sensor driving device comprising: a second memory unit storing any one of designated command data. The solid-state imaging device driving device according to claim 5,
The address designation command data is used for designating the read address corresponding to the drive pulse to be output at the beginning of one horizontal transfer period, and from when the drive pulse is output until the next drive pulse is changed. A wait time and read designation data for designating the read address corresponding to the drive pulse to be output when the wait time and the wait time have passed, and the number of repetition loops of the wait time and read designation data are designated. 1 loop designation command data,
The command data includes the initial status data, the wait time data, and second loop designation command data that designates the number of repetition loops of the wait time data,
The second memory unit includes a clock memory storing the address designation data, the waiting time / reading designation data, the initial status data, and the waiting time data, the first loop designation command data, and the second A solid-state image sensor driving device comprising: a loop control memory in which the loop designation command data is stored. It is a solid-state image sensor drive device according to claim 6,
A sequence memory in which command data designating the read address of the clock memory is stored in the first memory unit, and a loop pointer in which command data designating the read address of the loop control memory is stored at the same timing as the designation A solid-state image sensor driving device including a memory. The solid-state image sensor driving device according to claim 6 or 7,
The inversion timing designation data memory, the status memory, the clock memory, and the loop control memory are respectively a first group for vertical transfer pulses, a second group for read pulses, and a third group for horizontal transfer pulses. A solid-state image sensor driving device configured by dividing into three groups.   An imaging device comprising the solid-state imaging device driving device according to claim 1 and the solid-state imaging device.

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