JP4723919B2 - Timing pulse generator and imaging device using the same. - Google Patents

Description

  The present invention relates to a timing pulse generator for generating a pulse (drive pulse) for driving an element such as an image sensor, and an image pickup apparatus using the timing pulse generator.

  When driving a CCD imaging device, an LCD device, or the like, it is necessary to generate a drive pulse by “1” (high level) and “0” (low level) based on the drive specifications of these devices. A desired drive pulse is generated using a counter, a decoder, or the like (see, for example, Patent Document 1).

  FIG. 12 is a block diagram showing a conventional example of a timing pulse generator for generating such drive pulses, in which 30 is a counter, 311,..., 31N are decoders, 32 is a register, and 33 is a multiplexer.

  FIG. 13 is a timing chart showing output pulses D1,..., DN of the decoders 311,.

  12 and 13, the decoder 311 compares the count value of the counter 30 with the value of the register 32, and generates an output pulse D1 when they match. Similarly, the decoders 312,..., 31N also output output pulses D2,. The multiplexer 33 multiplexes the output pulses D1,..., DN of these decoders 311,.

  FIG. 14 is a block diagram showing another conventional example of a timing pulse generator for generating a drive pulse, wherein 40 is an address generating circuit and 41 is a memory.

  FIG. 15 is a timing diagram showing memory output pulses and drive pulses for addresses from the address generation circuit in FIG.

14 and 15, “1” (high level) or “0” (low level) data is written in advance in the memory 41 for each address in correspondence with a desired drive pulse. In the memory 41, addresses “0”, “1”, “2”,... Are sequentially accessed by the address signal generated by the address generation circuit 40, and data “1” or “0” is accessed from the accessed address. It is read out and output as a drive pulse.
Japanese Patent Laid-Open No. 10-257398

  In the conventional technique shown in FIG. 12, the number of change points of the pulse train that can be generated (that is, the switching points of pulse trains having different periods and pulse widths) is determined by the number of decoders, which is greater than the assumed change point. If a number of drive pulses are required, it cannot be handled. When this is used, for example, as a timing pulse generator for a vertical transfer drive pulse of a vertical CCD of a CCD image pickup device, there are various charge transfer methods in the vertical CCD, and this timing is determined according to the transfer method. The circuit configuration of the pulse generator is determined, and it is necessary to create a timing pulse generator having a different circuit configuration for each transfer method employed.

  In the conventional technique shown in FIG. 14, the number of change points is not limited, and a timing pulse generator having the same circuit configuration can be commonly used for CCD image sensors of different vertical transfer methods. Since one address is required for the memory 41 for each step of the drive pulse, for example, even in the case of a drive pulse in which the level “0” state continues for 1000 steps, the address in the memory 41 needs 1000 addresses. The memory usage efficiency will be worse.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a timing pulse generator and an imaging device using the same, which can solve such problems, can cope with the number of drive pulse change points, and can improve the use efficiency of the memory. There is.

In order to achieve the above object, a timing pulse generator according to the present invention comprises an address generating circuit for generating an address, a memory storing setting data and control data corresponding to the address, and driving pulse data, and the memory A first counter that performs a counting operation while generating a clear pulse at a predetermined timing while comparing the count result with the first setting data read from the second setting data, and the second setting data read from the memory The second counter that performs the count operation while comparing the count results with each other and generates an increment pulse at a predetermined timing, and the address generated by the address generation circuit at a timing according to the control data read from the memory in, and an address holding circuit for holding, the address generating circuit, or the first counter The address is incremented for each of the clear pulses, and the address is held in the address holding circuit in accordance with the clear pulse from the first counter and the increment from the second counter. And a drive pulse is output from the memory in accordance with the address.

The timing pulse generator according to the present invention includes an address generation circuit for generating an address, a memory in which setting data and control data corresponding to the address are stored, and first setting data read from the memory, The count operation is performed while comparing the count result, and the first counter that generates a clear pulse at a predetermined timing is compared with the second setting data read from the memory and the count operation is performed. And a second counter for generating an incremental pulse at a predetermined timing, and an address holding circuit for holding an address generated by the address generation circuit at a timing according to the control data read from the memory. , the address generating circuit, ink the address for each said clear pulse from the first counter As well as instruments, the address, in response to the increment from the clear pulse and a second counter from the first counter, to jump to the holding address held in the address holding circuit, from the address generating circuit A predetermined bit of the generated address is used as a drive pulse.

The imaging apparatus according to the present invention is characterized in that any one of the timing pulse generators described above is used as a driving pulse generator for a CCD imaging device.

  According to the present invention, it is possible to cope with an increase in the number of change points of the drive pulse to be generated, and further, it is not necessary to advance the address of the memory during a fixed period of the drive pulse. Becomes higher.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a timing pulse generator according to the present invention, wherein 1 is an address generating circuit, 2 is a memory, 3 is a LEN (length) counter, 4 is a LOOP (loop) counter, 5 Is an AND gate, 6 is an address holding circuit, and 7 is an output terminal.

  In the figure, the storage area of the memory 2 stores data for each data such as the drive pulse DP, LEN (length) data and LOOP (repetition cycle) data as setting data, and RETURN (return) data as control data. The areas are divided, and in each data storage area, data values are sequentially stored for each address. Such an address is designated by an address signal generated from the address generation circuit 1, and in each data storage area, the data value stored therein is read from the address designated by this address signal.

  The address generation circuit 1 resets the address AD to a value “0” by a reset pulse R supplied at a predetermined timing, and also outputs a level “H” (high level) LEN counter output from the LEN counter 3 described later. The address AD is updated at the falling edge of the clear signal or at the falling edge of the level “H” address jump pulse AJ output from the AND gate 5.

  The LEN data output from the memory 2 is set in the LEN counter 3. The LEN counter 3 counts up the clock φ from the initial value “1”, and when this count value becomes equal to the set value of the LEN data, the LEN counter clear pulse of level “H” in the time width of one cycle of the clock φ. And the count value is returned to the initial value “1”.

  The address generation circuit 1 increments the address AD increased by the next value “1” at the falling edge timing of the LEN counter clear pulse from the level “H” to the level “L” (low level). To supply. Therefore, in the memory 2, the next data value is read from the address designated by this address AD in each data storage area. The read LEN data is set in the LEN counter 3, and the LEN counter 3 counts up the clock φ from the initial value “1” as described above.

Further, LOOP data output from the memory 2 in accordance with the address AD from the address generation circuit 1 is set in the LOOP counter 4. This LOOP counter 4 has a level “1” to a level “0 ” of RETURN data “1” (high level) and “0” (low level) output from the memory 3 in response to the address AD from the address generation circuit 1. " LOOP increment pulse" is generated when the RETURN data level is "1" and the count value of the LOOP counter 4 does not match the LOOP data set at that time.

  Here, when the RETURN data is “0”, the address AD at this time is held in the address holding circuit 6 as the holding address HAD.

  The LEN counter clear pulse output from the LEN counter 3 and the LOOP increment pulse output from the LOOP counter 4 are processed by the AND gate 5, and when both the LEN counter clear pulse and the LOOP increment pulse are at level "H". Then, an address jump pulse AJ as a control signal is generated. The address generation circuit 1 normally generates and outputs an address AD that is sequentially incremented at each falling edge of the LEN counter clear pulse from the LEN counter 3. When the address jump pulse AJ is supplied from the AND gate 5, Under control, the address AD is cleared (returned) to the holding address HAD held in the address holding circuit 6. Therefore, the address AD at this time becomes this holding address HAD, and this address AD is held at every falling edge of the LEN counter clear pulse from the LEN counter 3 until the address jump pulse AJ is next supplied from the AND gate 5. Increment sequentially from address HAD.

  In this way, the address generation circuit 1 generates an address AD corresponding to the LEN data, LOOP data, and RETURN data read from the memory 2, and the drive pulse DP is read from the memory 2 by the address AD, and the output terminal 7 to the outside.

  Next, a specific example of the operation of this embodiment will be described.

  Here, it is assumed that data is stored in the memory 2 as shown in FIG. FIG. 2 schematically shows data for each address AD in each data storage area. For example, in the LEN data storage area 2a, the address AD is “0”, “1”, “2”. , “3”, “4”, LEN data of values “2”, “3”, “4”, “2”, “2” are stored, and the address AD is stored in the LOOP data storage area 2b. LOOP data of values “2”, “2”, “1”, “1”, “1” are stored in the order of “0”, “1”, “2”, “3”, “4”, In the RETURN data storage area 2c, the addresses AD are “0”, “1”, “2”, “3”, “4” in the order of levels “0”, “1”, “0”, “0”, “ RETURN data of “0” is stored (however, level “0” is low level and level “1” is high level), and the address AD is “0”, “1” in the drive pulse storage area 2d. , "2", "3", the level "L" in the order of "4", "H", "L", "H", the data of the drive pulse DP of the "L" is stored.

  FIG. 3 is a timing diagram showing the data and signals of each part of FIG. 1 with reference to the timing of each cycle of the clock φ, and the timing of each cycle of the clock φ is represented by φ1, φ2, φ3,. .

  Hereinafter, the operation will be described for each timing (clocks φ1, φ2, φ3,..., Φ18) with reference to FIGS.

A. Regarding the period of clocks φ1 to φ10 (1) Timing of clock φ1:
At this timing, the address generation circuit 1 is reset by the reset pulse R, and the address AD output from the address generation circuit 1 becomes “0”. Thus, at the timing of the clock φ1, the LEN data having the value “2”, the LOOP data having the value “2”, and the RETURN data having “0” are read from the respective data storage areas 2a to 2d of the memory 2. LEN data of “2” is set in the LEN counter 3, and LOOP data of value “2” is set in the LOOP counter 4, respectively. At this time, the count values of the LEN counter 3 and the LOOP counter 4 are reset to the initial value “1” and do not match the respective set values. Therefore, the LEN counter 3 does not output the “H” LEN counter clear pulse, and the LOOP counter 4 does not output the “H” LOOP increment pulse.

  Further, since the RETURN data is “0” at the timing of the clock φ1, the address AD at this time, that is, the address AD of “0” is held in the address holding circuit 6.

  Further, as shown in FIG. 2, at the address AD of “0”, “L” data is stored in the data storage area of the drive pulse in the memory 2, and therefore, this “L” data is read out. Accordingly, the drive pulse DP outputs “L”.

(2) Timing of clock φ2:
At the next clock φ 2 timing, the LEN counter 3 counts up the clock φ and the count value becomes “2”, which is equal to the set value “2” of the LEN counter 3. As a result, the LEN counter 3 outputs an “H” LEN counter clear pulse. However, at this time as well, the address AD from the address generation circuit 1 is held at “0” as it is, so the RETURN data from the memory 2 is “0”, and the LOOP counter 4 does not count up, The value is held as it is at the initial value “1”. Therefore, the LOOP counter 4 does not output a “H” LOOP increment pulse.

  Further, according to FIG. 2, the address AD at this time is “0”, and “L” data is stored in the address “0” of the data storage area of the drive pulse DP of the memory 2. An “L” drive pulse DP is output.

(3) Timing of clock φ3:
At the next clock φ3 timing, when the LEN counter 3 up-counts the clock φ, the LEN counter 3 outputs an “H” LEN counter clear pulse at the timing of the clock φ2, so in advance Since it is known that the LEN counter 3 resets the count value to the initial value “1” at the timing of the next clock φ, that is, the switching timing from the clock φ2 to the clock φ3, the initial value at the falling edge At the same time, the LEN counter clear pulse falls.

  On the other hand, when the LEN counter clear pulse from the LEN counter 3 falls at the timing of the clock φ3, the address generation circuit 1 is incremented at the falling edge, and the address AD becomes “1”.

  As a result, the address “1” is accessed in each data storage area in the memory 2, and the LEN data having the value “3” is read from the memory 2 and set in the LEN counter 3 according to FIG. 2. Further, the LOOP data having the value “2” is read from the memory 2 and set in the LOOP counter 4. This set value is not different from the set value at the timing of the clock φ 1.

  Thus, at the timing of the clock φ3, the address AD is “1”, the LEN counter 3 is set to the value “3”, and the LOOP counter 4 is set to the value “2”.

  On the other hand, according to FIG. 2, when the address AD becomes “1”, the RETURN data output from the memory 2 becomes “1”. However, the LOOP counter 4 does not count up at this rising edge, and the count value remains “ 1 ". However, the count value “1” is different from the set value “2” of the LOOP counter 4 and the RETURN data is “1”. Therefore, the LOOP increment pulse of “H” is output from the LOOP counter 4. Is output.

  2, since “H” data is stored in the address “1” of the data storage area of the drive pulse DP of the memory 2, the “H” drive pulse DP is read from the memory 2 and output. Output from terminal 7.

  Further, since the RETURN data is “1”, the address holding circuit 6 is not rewritten, and the holding address HAD remains “0”.

(4) Timing of clock φ4:
At the timing of the next clock φ4, the LEN counter 3 counts up the clock φ and the count value becomes “2”. However, since this count value does not match the set value “3” of the LEN counter 3, the LEN counter of “H” No counter clear pulse is generated. Therefore, the address AD from the address generation circuit 1 remains “1”. Therefore, the RETURN data from the memory 2 remains “1”, the count value of the LOOP counter 4 remains the initial value “1”, and the output of the “H” LOOP increment pulse continues.

  Note that the drive pulse DP of “H” is continuously read from the memory 2 even at the timing of the clock φ4.

(5) Timing of clock φ5:
At the timing of the next clock φ5, the LEN counter 3 counts up the clock φ and the count value becomes “3”, which is equal to the set value “3” of the LEN counter 3. As a result, the LEN counter 3 starts to output an “H” LEN counter clear pulse. At this time, the count value of the LOOP counter 4 remains the initial value “1” and does not match the set value “2”, and the RETURN data remains “1”. "LOOP increment pulse" continues to be output.

  Thus, at the timing of the clock φ5, since both the LEN counter clear pulse and the LOOP increment pulse are “H”, the AND gate 5 outputs the “H” address jump pulse AJ.

(6) Timing of clock φ6 to timing of clock φ10:
At the timing of the next clock φ6, it is known that the LEN counter 3 is reset to the initial value at the next clock φ in advance, similarly to the switching from the clock φ2 to the clock φ3 . Is reset to the initial value “1”, and at the same time, the LEN counter clear pulse falls. Further, the output level of the AND gate 5 becomes “L”, and the address jump pulse AJ falls. At the falling edge of the address jump pulse AJ, the holding address HAD of “0” of the address holding circuit 6 is taken into the address generation circuit 1 and the address AD is set to a value “0” equal to the holding address HAD. Therefore, the LEN data having the same value “2” as the timing of the clock φ1 is read from the memory 2 and set in the LEN counter 3, and the same value “2” as that at the timing of the clock φ1. The LOOP data is read and set in the LOOP counter 4.

  Since the address AD becomes “0”, the RETURN data from the memory 2 is inverted from “1” to “0” according to FIG. As a result, the LEN counter clear pulse from the LOOP counter 4 is inverted from "1" to "0" and falls. Therefore, the output of the AND gate 5 becomes “L”.

  Further, the level of the RETURN data is inverted from “1” to “0”, so that the address AD at this time, that is, the address AD having the value “0” is held in the address holding circuit 6 as the holding address HAD. .

  In this way, when the value “2” is set in the LEN counter 3 and the LOOP counter 4, the above operations from the timing of the clock φ1 to the clock φ5 are repeated. This period is a period from the timing of the clock φ6 to the timing of the clock φ10. Even during this period, the drive pulse DP of “H” is read from the memory 2 and output from the output terminal 7 while the address value AD is “1”.

  However, the count value of the LOOP counter 4 during this period is “2”, which is equal to the set value of the LOOP counter 4. Therefore, even if the address AD is “1” and the RETURN data is “1”, the LOOP counter 4 does not generate a “H” LOOP increment pulse, and therefore the AND gate 5 generates an address jump pulse AJ. Does not occur.

As described above, the drive pulse DP having a duty ratio of 60% (= 3 × 100/5) is output from the memory 2 twice in the period of the clocks φ1 to φ10 with a period 5T _φ that is five times the clock φ. Become.

B. Regarding the period of clocks φ11 to φ18 (7) Timing of clock φ11:
At the timing of the clock φ10, similarly to the timing of the previous clock φ5, the count value of the LEN counter 3 is “3” which is equal to the set value, and the LEN counter 3 outputs an “H” LEN counter clear pulse. Therefore, since it is known in advance that the LEN counter 3 is reset to the initial value by the clock φ at the timing of the next clock φ11, it is reset to the initial value by the clock φ. At the same time, the LEN counter clear pulse is inverted from "H" to "L" and falls. The address generation circuit 1 increments at the falling edge of the LEN counter clear pulse, and sets the address AD to “2”.

  Therefore, in the memory 2, the address “2” of each data storage area is read, and the LEN data with the value “4” is read and set in the LEN counter 3 according to FIG. LOOP data is read and set in the LOOP counter 4. Further, RETURN data of “0” is read and supplied to the LOOP counter 4 and the address holding circuit 6. Since the return data is “0” and the count value “2” of the LOOP counter 4 at this time coincides with the set value, the count value of the LOOP counter 4 is the initial value “1”. Since the RETURN data is “0”, the address AD of “2” at that time is held as the holding address HAD in the address holding circuit 6.

(8) Timing of clock φ12 to timing of clock φ13:
The LEN counter 3 counts up the clock φ at the timing of the next clock φ12 and the count value becomes “2”, and the LEN counter 3 counts up the clock φ at the timing of the next clock φ13 and the count value thereof. However, since these count values do not coincide with the set value “4”, an LEN counter clear pulse of “H” is not generated from the LEN counter 3.

  At this time, the count value “1” of the LOOP counter 4 matches the set value “1” (even if the RETURN data is “1”), the LOOP counter 4 is also “H”. Does not generate a LOOP increment pulse.

  Therefore, the LEN counter 3 only counts up the clock φ, and the same state is maintained except for this.

(9) Timing of clocks φ14 to φ15:
When the LEN counter 3 up-counts the clock φ at the timing of the next clock φ14 and the count value becomes “4”, this becomes equal to the set value of the LEN counter 3, so that the LEN counter 3 is set to the “H” LEN counter. A clear pulse occurs. However, since the count value “1” matches the set value, the LOOP counter 4 does not generate a “H” LOOP increment pulse.

  Then, at the timing of the next clock φ15, the LEN counter 3 is reset to the initial value, and at the same time, the LEN counter of “H”, similarly to the clocks φ2, φ3, φ5, φ6, φ7, φ8, φ10, φ11, The clear pulse falls from “H” to “L”. At this falling edge, the address generation circuit 1 increments and the address AD becomes “3”.

  When the address AD becomes “3”, the LEN data with the value “2” is read from the memory 2 and set in the LEN counter 3 and the LOOP data with the value “1” is read and set in the LOOP counter 4 according to FIG. Is done. Further, RETURN data “0” is read and supplied to the LOOP counter 4 and the address holding circuit 6. Thereby, the address holding circuit 6 holds the address “3” at that time. However, the LOOP counter 4 does not generate a “H” LOOP increment pulse.

  When the address AD is “3”, the “H” drive pulse DP is read from the memory 2 and output from the output terminal 7.

(10) Timing of clock φ16:
When the LEN counter 3 counts up the clock φ at the timing of the next clock φ16 and the count value becomes “2”, it is equal to the set value of the LEN counter 3, so the LEN counter 3 is cleared from the LEN counter 3. A pulse is output. However, since the count value “1” is equal to the set value, the LOOP counter 4 does not generate a “H” LOOP increment pulse. Also at this time, since the RETURN data is “0”, the address AD of “3” is held in the address holding circuit 6. Further, since the address AD at this time is “3”, the drive pulse DP is generated from the memory 2.

(11) Timing of clock φ17:
At the timing of the next clock φ17, the LEN counter 3 is reset to the initial value, and at the same time, the LEN counter clear pulse falls from “H” to “L”. The address generation circuit 1 is incremented by the falling edge of the LEN counter clear pulse, and the address AD becomes “4”.

  When the address AD becomes “4”, the LEN data having the value “2” is read from the memory 2 and set in the LEN counter 3 and the LOOP data having the value “1” is read and set in the LOOP counter 4 according to FIG. Is done. Further, RETURN data “0” is read and supplied to the LOOP counter 4 and the address holding circuit 6. Thereby, the address holding circuit 6 holds the address AD of “4” at that time. However, the LOOP counter 4 does not generate a “H” LOOP increment pulse.

  When the address AD is “4”, the drive pulse DP output from the memory 2 falls and outputs “L”.

(12) Timing of clock φ18:
When the LEN counter 3 counts up the clock φ at the timing of the next clock φ18 and the count value becomes “2”, it is equal to the set value of the LEN counter 3, so the LEN counter 3 is cleared from the LEN counter 3. A pulse is output. However, since the count value “1” is equal to the set value, the LOOP counter 4 does not generate a “H” LOOP increment pulse. Also at this time, since the RETURN data is “0”, the address AD of “4” is held in the address holding circuit 6 as the holding address HAD. Further, since the address AD at this time is “4”, the drive pulse DP is not generated from the memory 2.

As apparent from the above description of operation, LEN data, the period length of the address AD, a unit length period T _phi clock phi, it prescribes. For example, when the value of the LEN data is “2”, for example, the period length of the address AD of “0” is 2T _φ . From this, the cycle and pulse width of the drive pulse DP are defined according to the LEN data.

  In the above example, the driving pulse is generated in the timing period of the clocks φ3 to φ5 and the timing period of the clocks φ8 to φ10 where the address AD is “1”, and the timing period of the clocks φ15 to φ16 where the address AD is “3”. DP is output from the memory 2.

Here, in the timing period of the clocks φ1 to φ10, the drive pulse DP is generated twice with a period 5T _φ that is five times the cycle of the clock φ. This is made possible by repeating the period in which the addresses AD of “0” and “1” continue twice, and this repetition is determined by the LOOP data. In the example of the above timing period, the value of the LOOP data when the address value AD is “0” and “1” is “2”, so the period when the address value AD is “0” and “1” is 2 However, by setting the LOOP data to a value equal to or greater than “2”, the period in which the address value AD of “0” and “1” continues can be repeated any number of times. An arbitrary number of drive pulses can be generated.

  However, when the address AD of “0” and “1” is repeated in this way, the address AD of “0” is held in the address holding circuit 6 as the holding address HAD, and the passage of the address AD of “1” has elapsed. Thereafter, the holding address HAD of “0” held in the address holding circuit 6 is supplied to the address generation circuit 1 to return the address AD to “0”. This address AD is held in the address holding circuit 6 as a holding address HAD. This operation is repeated as many times as the value of the LOOP data. The holding timing of the address AD to the address holding circuit 6 and the supply timing of the holding address HAD to the address generating circuit 1 are set by “0” and “1” of RETURN data. It prescribes.

  For example, when the value of the LOOP data read from the memory 2 is “3” when the address AD is “0”, “1”, the LOOP counter 4 has an initial value “1” as shown in FIG. To RETURN data is incremented at each falling edge whose level is inverted from “1” to “0”, and the count value is “1”, “2”, “3”, and the address AD is “1”. Thus, the drive pulse DP is generated and the drive pulse DP is generated three times.

  When the value of the LOOP data is “1”, the address AD sequentially incremented from the address generation circuit 1 is generated as in the timing period of the clocks φ11 to φ18 in FIG. By storing “H” data at an appropriate address in the data storage area of the drive pulse DP in the memory 2, the drive pulse DP can be output from the memory 2 at an appropriate timing.

  As described above, in the first embodiment, the LEN data, the LOOP data, and the RETURN data stored in the memory 2 are read according to the address AD from the address generation circuit 1 and read. By controlling the address AD from the address generation circuit 1 according to these data, it is possible to obtain a drive pulse DP having a desired pattern according to the data stored therein from the memory 2.

  When driving pulses DP having a constant cycle are generated continuously, the same address in the memory 2 can be read repeatedly, so that driving pulses having the same pulse pattern, cycle and pulse width are read repeatedly. Thus, such drive pulses can be generated using a small memory capacity, and the use efficiency of the memory is greatly improved.

  Further, according to the first embodiment, even when driving pulses composed of a plurality of types of pulse trains having different pulse patterns are generated, the data of the pulse trains of the respective pulse patterns can be generated only by storing them in the memory 2. In addition, the memory capacity required to store data for generating a pulse train of a pulse pattern is small as described above, and such data can be easily additionally stored. Therefore, the present invention can also be applied to devices using drive pulses having different pulse patterns or drive pulses having different numbers of change points composed of pulse trains of various pulse patterns without changing the circuit configuration. That is, the first embodiment can be applied to a device using a driving pulse having an arbitrary pulse pattern without changing the circuit configuration.

  In the first embodiment, as is apparent from FIG. 2, when the address AD is “1” or “3”, the drive pulse DP of “H” is output from the memory 2. This means that when the least significant bit of the address value AD, which is a digital value, is “1”, a drive pulse DP of “H” is generated.

  FIG. 5 is a block diagram showing a second embodiment of the timing pulse generator according to the present invention, which makes it possible to obtain a drive pulse DP by utilizing this fact, 2 ′ is a memory, and 8 is a signal line. Therefore, portions corresponding to those in FIG.

  FIG. 6 is a timing chart showing data and signals of respective parts in FIG.

  In FIG. 5, the memory 2 ′ is provided with data storage areas for LEN data, LOOP data, and RETURN data. Like the memory 2 in FIG. 1, the LEN data, LOOP data, RETURN data is stored. However, this memory 2 'is not provided with a data storage area for the drive pulse DP.

  Also in the second embodiment, the LEN data, the LOOP data, and the RETURN data corresponding to the address AD from the address generation circuit 1 are read, and according to the data, as shown in FIG. The LOOP counter 4, the AND gate 5, the address holding circuit 6 and the address generation circuit 1 perform the same operations as those in FIG.

  Here, in the second embodiment, when the address AD from the address generation circuit 1 is an odd value, the drive pulse DP of “H” is output. That is, the address AD output from the address generating circuit 1 is parallel digital data composed of a plurality of bits, and the signal line 8 drawn from the least significant bit (LSB) of the signal line of the address AD is the drive pulse DP of “H”. Output line. When the address AD is an odd value, the LSB of the address AD is “1” and is at the “H” level. Therefore, as shown in FIG. 6, when the address AD has the values “1” and “3”, “H” ”Is output through the signal line 8.

  In the second embodiment, the same effects as those of the first embodiment can be obtained. However, substantially, the address generation circuit 1 also serves as a drive pulse DP generation circuit, and the memory 2 ' It is not necessary to store the data of the driving pulse DP, the utilization efficiency of the memory is further improved, and the utilization efficiency of the memory 2 ′ is further improved as compared with the memory 2 in FIG.

  Next, a CCD imaging device will be described as an example of a device using the timing pulse generator according to the present invention.

  FIG. 7 is a block diagram showing the main part of an embodiment of the imaging apparatus according to the present invention using the timing pulse generator according to the present invention, wherein 10 is a CCD imaging device, 11 is a signal processing circuit, and 12 is V (vertical). ) A driver 13 is a timing pulse generator.

In the figure, the timing pulse generator 13 generates a horizontal transfer pulse φ _H and a vertical transfer pulse φ _V. The horizontal transfer pulse φ _H is supplied to the CCD image sensor 10, and the vertical transfer pulse φ _V is amplified by the V driver 12 to a voltage of −9 V to 21 V, for example, and then supplied to the CCD image sensor 10. . In the CCD 10, as is known, pixel charge captured in the vertical transfer CCD (not shown) are vertically transferred by the vertical transfer pulse phi _V, it is sent to the CCD horizontal transfer (not shown) . In this horizontal transfer CCD, the pixel charge sent from the vertical transfer CCD is horizontally transferred by the horizontal transfer pulse φ _{H and} is output from the CCD image sensor 10 as a video signal. This video signal is processed by the signal processing circuit 11.

The timing pulse generator 13 includes a timing pulse generator for generating a vertical transfer pulse φ _V and a timing pulse generator for generating a horizontal transfer pulse φ _H. The timing pulse generator according to the present invention shown as each embodiment is used.

  FIG. 8 is a diagram showing a specific example of each operation period on the imaging screen of the CCD imaging device 10 in FIG.

  In this figure, in this specific example, a part of the imaging screen 14 is an effective area 15 for actually obtaining the imaging screen. This effective area 15 is an aspect 4: 3 screen area. The charges in the effective region 15 are taken in as effective charges, and a signal composed of the effective charges is supplied to the signal processing circuit 11 as an output video signal of the CCD image pickup device 10. Then, the charges in the area other than the effective area 15 on the imaging screen 14 are discarded.

Regarding vertical transfer in the CCD for vertical transfer of the CCD image pickup device 10, normal transfer at normal speed is performed in the vertical effective period T _0,1 for reading charges in the effective area 15. High-speed transfer is performed in the charge sweep periods T _7,8 and T _{3,4 for} sweeping out the charges at. The charge sweep period T ₇ , ₈ is a period during which charge is swept out following the reading of the charge from the sensor (photoelectric conversion element), and the charge sweep period T ₃ , ₄ is the vertical effective period T _{0. , 1} is the period during which charge is swept out.

As for one field, the vertical effective period T _0,1 is a period corresponding to 250 lines (horizontal scanning lines), and the sum of the charge sweep period T _7,8 and the charge sweep period T _3,4 is A period corresponding to a certain number of lines (for example, 100 lines). Thus, the reason why the effective area 15 for obtaining the video signal is made a part of the imaging screen 14 is to enable the effective area 15 to be moved vertically and horizontally within the imaging screen 14. , To prevent shaking the playback screen due to camera shake.

FIG. 9 is a diagram showing a specific example of the vertical transfer pulse φ _V in one field period for vertical transfer for the imaging screen 14 shown in FIG. 8, and is VD (vertical synchronization signal) / HD (horizontal synchronization). Signal) corresponding to the signal timing.

In the figure, a period T _0,1 is a vertical effective period T _0,1 in which the pixels in the effective region 15 in FIG. 8 are vertically transferred, and the vertical transfer pulse φ _{V at} this time is a CCD for horizontal transfer of the pixels. The normal transfer for transferring to is performed. Following this vertical effective period T _0,1 , an “L” period T ₂ is provided, followed by periods T _{3, 4} . This period T ₃ , ₄ is a vertical transfer period for sweeping out charges to the area below the effective area 15 on the imaging screen 14 in FIG. 8, that is, the charge sweep period T ₃ , _4. The vertical transfer pulse φ _{V in the} outgoing period T ₃ , ₄ is used for high-speed pixel transfer.

Periods T _{5 and 6} subsequent to the charge sweep periods T ₃ and ₄ are periods in which charges are transferred from each sensor to the vertical transfer CCD. The next period T _7,8 is a vertical transfer period for sweeping out charges with respect to the area above the effective area 15 on the imaging screen 14 in FIG. 8, that is, the charge sweep period T _7,8. The vertical transfer pulse φ _{V in the} sweep period T _7,8 is for transferring the pixels at high speed. When the charge sweep period T _7,8 ends, the next vertical effective period T _0,1 is entered through the “L” period T ₉ .

(The NTSC system, 262.5 H) or one field is a assignment of the vertical transfer pulse phi _V in the period, the timing pulse generator shown in FIG. 1 or FIG. 5 as a generator of a vertical transfer pulse phi _V Is stored in the memory 2 and 2 ′, the pulse pattern (that is, the period and the pulse width) is obtained every period T _0,1 , T _3,4 , T _5,6 , T _7,8. Vertical transfer pulse φ _V composed of a series of different pulse trains.

10 is a diagram schematically showing data in each data storage area of the memory 2 in the first embodiment shown in FIG. 1 for generating the vertical transfer pulse φ _V shown in FIG.

In the figure, in the vertical effective period T _0,1 , the read address of the memory 2 is “0”, “1”, and when the read address is “1”, the RETURN data is “1” and the LOOP data is the value “ as 250 ", address" 0 ", it is assumed that repeated 250 times with 5T _phi (LEN value data" 2 "and" 3 ") 5 clock cycles to read data" 1 ". When the address is “2”, the drive pulse of “H” is read out, and 250 drive pulses (vertical transfer pulse φ _V ) are generated in the vertical effective period T _0,1 .

In the period T ₂ , the read address of the memory 2 is set to “2”, the RETURN data and the LOOP data are set to the value “1”, and the “L” data (drive pulse) at the address “2” is read once. The period length, since LEN data = "4", which is four clock cycles 4T _phi.

In addition, the total number of horizontal lines of the charge sweep periods T3, ₄ and the charge sweep periods T7, ₈ is set to 100. Of these, n horizontal lines are subjected to charge sweeping during the charge sweep period T7, _8. is, the remaining (100-n) horizontal lines are assumed to sweeping charges is performed in the charge sweeping period T _{3, 4.}

Therefore, in the charge sweep period T ₃ , ₄ , the read address of the memory 2 is set to “3”, “4”. When the read address is “4”, the RETURN data is set to “1” and the LOOP data is set to the value “100”. as -n ", address" 3 ", it is assumed that repeated 4T φ _(100-n) times (LEN data and the value" 2 "," 2 ") 4 clock cycles to read data of" 4 ". Since the drive pulse of “H” is generated at the address “3”, the drive pulse (vertical transfer pulse φ _V ) is generated at high speed (100−n) times in the charge sweep period T ₃ , _4. Will do. In the charge sweep period T ₇ , ₈ , the read address of the memory 2 is “7”, “8”, and when the read address is “8”, the RETURN data is “1”, and the LOOP data is the value “n”. The data reading at the addresses “7” and “8” is repeated n times in 4 clock cycles (LEN data of values “2” and “2”) 4T _φ . Since the drive pulse of “H” is generated at the address “7”, the drive pulse (vertical transfer pulse φ _V ) is generated n times at high speed in this charge sweep period T ₇ , _8. .

In the period T _5,6 , the read address of the memory 2 is “5”, “6”, and when the read address is “6”, the RETURN data is “1”, the LOOP data is “1”, and the address “ Data reading at “5” and “6” is performed once. In this case, when the address is “5”, a drive pulse DP of “H” is generated, and this is used to send charges from the sensor to the vertical transfer CCD.

In the period T ₉ , the read address of the memory 2 is set to “9”, the RETURN data is set to the value “3”, the LOOP data is set to the value “1”, and the “L” data (drive pulse) at the address “9” is set to 1. Read once. The period length, since LEN data = "3", which is a three clock cycles 3T _phi.

As an example of the vertical transfer pulse φ _V generated from the timing pulse generator 13 in FIG. 7 based on the data shown in FIG. 10, the charge sweep from the vertical effective period T _{0,1 is} shown in FIG. The part which moves to period _T3,4 is shown.

In this way, the drive pulse can be obtained according to the data stored in the memory in the timing pulse generator. By storing the desired data in the memory, the vertical transfer pulse φ _A series of desired drive pulses consisting of pulse trains of different pulse patterns, such as _V, can be generated, and pulse trains with periodicity can be generated using only a small memory capacity. It is also possible to generate an additional pulse train of a new pulse pattern by adding data to a memory that already stores data.

1 is a block diagram showing a first embodiment of a timing pulse generator according to the present invention. FIG. It is a figure which shows typically the data in each data storage area of the memory in FIG. FIG. 3 is a timing chart showing data and pulse signals of respective parts in one operation example of the first embodiment shown in FIG. 1. FIG. 6 is a timing chart showing data and pulse signals of each part in another operation example of the first embodiment shown in FIG. 1. It is a block diagram which shows the 2nd Example of the timing pulse generator by this invention. FIG. 6 is a timing chart showing data and pulse signals of respective parts in an operation example of the second embodiment shown in FIG. 5. It is a block diagram which shows the principal part of one Embodiment of the imaging device by this invention. It is a figure which shows one specific example of each operation period on the imaging screen of the CCD imaging device in FIG. FIG. 9 is a diagram illustrating a specific example of a vertical transfer pulse φ _V in one field period for vertical transfer on the imaging screen illustrated in FIG. 8. FIG. 10 is a diagram schematically showing data stored in a memory in the first embodiment shown in FIG. 1 for generating the vertical transfer pulse φ _V shown in FIG. 9. FIG. 11 is a timing chart showing a vertical transfer pulse φ _V when moving from the vertical effective period T _0,1 to the charge sweep period T ₃ , ₄ based on the data shown in FIG. It is a block diagram which shows one prior art example of a timing pulse generator. FIG. 13 is a timing chart showing output pulses of each decoder in FIG. 12 and drive pulses output from a multiplexer. It is a block diagram which shows the other conventional example of a timing pulse generator. FIG. 15 is a timing diagram showing memory output pulses and drive pulses for addresses from the address generation circuit in FIG. 14.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Address generation circuit 2,2 'Memory 3 LEN counter 4 LOOP counter 5 AND gate 6 Address holding circuit 7 Output terminal 8 Signal line 10 CCD image pick-up element 11 Signal processing circuit 12 V (vertical) driver 13 Timing pulse generator

Claims (3)

An address generation circuit for generating an address;
A memory storing setting data, control data, and driving pulse data corresponding to the address;
A first counter that performs a count operation while comparing the count result with the first setting data read from the memory, and generates a clear pulse at a predetermined timing;
A second counter that performs a count operation while comparing the count result with the second setting data read from the memory, and generates an increment pulse at a predetermined timing;
An address holding circuit for holding an address generated by the address generation circuit at a timing according to the control data read from the memory ;
The address generation circuit increments the address for each clear pulse from the first counter and determines the address in response to the clear pulse from the first counter and the increment from a second counter. A timing pulse generator that jumps to a holding address held in the address holding circuit and outputs a drive pulse from the memory in accordance with the address. An address generation circuit for generating an address;
A memory storing setting data and control data corresponding to the address;
A first counter that performs a count operation while comparing the count result with the first setting data read from the memory, and generates a clear pulse at a predetermined timing;
A second counter that performs a count operation while comparing the count result with the second setting data read from the memory, and generates an increment pulse at a predetermined timing;
An address holding circuit for holding an address generated by the address generation circuit at a timing according to the control data read from the memory ;
The address generation circuit increments the address for each clear pulse from the first counter and determines the address in response to the clear pulse from the first counter and the increment from a second counter. The timing pulse generator is characterized by jumping to a holding address held in the address holding circuit and using a predetermined bit of the address generated from the address generation circuit as a drive pulse. 3. A CCD image pickup device, wherein the timing pulse generator according to claim 1 is used as a drive pulse generator for a CCD image pickup device.

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