JP2012084592A - Method of manufacturing optical semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing an optical semiconductor element in which the etching depth for forming mesa portions can be controlled with excellent accuracy.SOLUTION: A method of manufacturing an optical semiconductor element comprises the steps of: growing an etching marker layer 42 above a semi-insulating substrate 20; sequentially forming a lower cladding layer 25, an optical waveguide layer 26, and an upper cladding layer 27 on the etching marker layer 42; and forming mesa portions 22 to 24 extending in a predetermined optical waveguide direction by performing plasma etching to the lower cladding layer 25, the optical waveguide layer 26, and the upper cladding layer 27. The plasma emission intensity of the etching marker layer 42 is larger than that of an n-type contact layer 21 and the lower cladding layer 25 that are in contact with the etching marker layer 42. In etching the mesa portions, the plasma etching is stopped based on variation in the plasma emission intensity.

Description

  The present invention relates to a method for manufacturing an optical semiconductor device mainly used in an optical fiber communication system.

  FIG. 15 is a perspective view showing an internal structure of a conventional optical semiconductor element. As shown in FIG. 15, this optical semiconductor element 100 is provided side by side on a semi-insulating substrate 101, an n-type contact layer 110 provided on the semi-insulating substrate 101, and the n-type contact layer. Three mesa units 102, 103, and 104 are provided. Each mesa part 102-104 is extended along the predetermined | prescribed optical waveguide direction, and is arrange | positioned along with the direction orthogonal to this optical waveguide direction. The mesa portions 102 to 104 have a lower cladding layer 105, an optical waveguide layer 106, and an upper cladding layer 107. The optical waveguide layer 106 includes two types of core layers 106a and 106b arranged in the optical waveguide direction, and has a so-called butt joint structure in which these core layers 106a and 106b are in contact with each other.

  In the central mesa unit 103, light is generated or modulated in the optical waveguide layer 106 by supplying current from an electrode (not shown). In order to form an electrode pattern, both side surfaces of the mesa portion 103 are filled with a resin (not shown). The other mesa portions 102 and 104 are provided to support this resin.

  Such an optical semiconductor element 100 is manufactured as follows, for example. First, an n-type contact layer 110, a lower cladding layer 105, and a semiconductor layer for the core layer 106a are epitaxially grown in this order on the semi-insulating substrate 101. Next, the semiconductor layer for the core layer 106a is divided into two regions arranged in the optical waveguide direction, and one of the regions is removed by etching. Subsequently, a semiconductor layer for the core layer 106b is selectively grown on the lower clad layer 105 while leaving a mask for this etching. Thus, after forming the optical waveguide layer 106 including the core layer 106 a and the core layer 106 b, the upper cladding layer 107 is grown on the optical waveguide layer 106.

  Subsequently, a mask having a shape corresponding to the planar shape of the mesa portions 102 to 104 is formed on the upper cladding layer 107, and the upper cladding layer 107, the optical waveguide layer 106, and the lower cladding layer 105 are etched through this mask. As a result, the mesa portions 102 to 104 are formed. Finally, the n-type contact layer 110 located around the mesa portions 102 to 104 is removed by etching.

JP 2009-071067 A JP 2002-314192 A

  As described above, when an optical semiconductor element is manufactured, etching is performed to form a mesa portion. This etching process may require high accuracy with respect to the etching depth. For example, in the above-described optical semiconductor device 100, if the n-type contact layer 110 is etched, the n-type contact layer 110 may be divided, and current may not be supplied to the mesa portion.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a method of manufacturing an optical semiconductor element capable of accurately controlling the etching depth for forming the mesa portion.

  In order to solve the above-described problems, an optical semiconductor device manufacturing method according to the present invention includes a first etching marker layer growth step of growing a first etching marker layer on a substrate, a first cladding layer, and an optical waveguide. A semiconductor growth step for sequentially growing a layer and a second clad layer on the first etching marker layer, and performing plasma etching on the first clad layer, the optical waveguide layer, and the second clad layer. A mesa etching process for forming a mesa portion extending in the optical waveguide direction, and the plasma emission intensity of the first etching marker layer is larger than the plasma emission intensity of the upper and lower semiconductor layers in contact with the first etching marker layer, The mesa etching process is characterized in that the plasma etching is stopped based on the change in the plasma emission intensity.

  In this method of manufacturing an optical semiconductor element, a first etching marker layer is grown on a substrate before a first cladding layer (corresponding to the lower cladding layer 105 shown in FIG. 15) is grown. Since the plasma emission intensity of the first etching marker layer is higher than the plasma emission intensity of the upper and lower semiconductor layers in contact with the first etching marker layer, the plasma emission intensity in the mesa etching process for forming the mesa portion is the etching intensity. The depth increases when the depth reaches the first etching marker layer, and decreases after the first etching marker layer. Therefore, the etching depth for forming the mesa portion can be accurately controlled by stopping the plasma etching based on the change in the plasma emission intensity.

  In the above manufacturing method, it is preferable that the upper and lower semiconductor layers in contact with the first etching marker layer do not contain Al, and the first etching marker layer contains Al. Thereby, it is possible to suitably realize a configuration in which the plasma emission intensity of the first etching marker layer is larger than the plasma emission intensity of the upper and lower semiconductor layers in contact with the first etching marker layer.

  In the above manufacturing method, the semiconductor growth step includes a first cladding layer growth step for growing the first cladding layer, and a second etching marker for growing the second etching marker layer on the first cladding layer. A layer growth step, a first optical waveguide layer growth step of growing a first semiconductor layer constituting a part of the optical waveguide layer on the second etching marker layer, and a plasma etching of a part of the first semiconductor layer A selective etching step of removing a part of the first clad layer by removing the first clad layer, a second optical waveguide layer growing step of selectively growing the second semiconductor layer in the exposed region of the first clad layer, And a second cladding layer growth step for growing a second cladding layer on the first semiconductor layer and the second semiconductor layer, and the plasma emission intensity of the second etching marker layer is No etch Greater than the plasma emission intensity of the upper and lower semiconductor layer in contact with the Gumaka layer, selective etching process may be characterized in that to stop the plasma etching based on a change in plasma emission intensity.

  In this optical semiconductor device manufacturing method, after the first cladding layer is grown, the first semiconductor layer (corresponding to the semiconductor layer for the core layer 106a shown in FIG. 15) is grown before the first cladding layer is grown. Two etching marker layers are grown on the first cladding layer. Since the plasma emission intensity of the second etching marker layer is larger than the plasma emission intensity of the upper and lower semiconductor layers in contact with the second etching marker layer, the plasma emission intensity in the selective etching step for forming the butt joint structure is When the etching depth reaches the second etching marker layer, the etching depth increases, and after the second etching marker layer, the etching depth decreases. Therefore, the etching depth for forming the butt joint structure can be accurately controlled by stopping the plasma etching based on the change in the plasma emission intensity.

  In this case, in the above manufacturing method, it is preferable that the upper and lower semiconductor layers in contact with the second etching marker layer do not contain Al, and the second etching marker layer contains Al. Thereby, it is possible to suitably realize a configuration in which the plasma emission intensity of the second etching marker layer is larger than the plasma emission intensity of the upper and lower semiconductor layers in contact with the second etching marker layer.

  The manufacturing method also includes a first etching marker layer growth step for growing a third etching marker layer on the substrate and a contact layer growth step for growing a contact layer on the third etching marker layer. The etching marker layer growth step further includes a step of plasma etching a predetermined region of the contact layer after the mesa etching step, and the plasma emission intensity of the third etching marker layer is determined by the third etching marker layer. The contact layer etching step may be characterized in that the plasma etching is stopped based on a change in the plasma emission intensity.

  In this method of manufacturing an optical semiconductor element, the third etching marker layer and the contact layer are grown on the substrate before the first etching marker layer is grown. Since the plasma emission intensity of the third etching marker layer is higher than the plasma emission intensity of the upper and lower semiconductor layers in contact with the third etching marker layer, the contact layer etching step of etching the contact layer to form a wire bonding pad The plasma emission intensity at is increased when the etching depth reaches the third etching marker layer, and is decreased after the third etching marker layer. Therefore, the etching depth with respect to the contact layer can be accurately controlled by stopping the plasma etching based on the change in the plasma emission intensity.

  In this case, in the above manufacturing method, it is preferable that the upper and lower semiconductor layers in contact with the third etching marker layer do not contain Al, and the third etching marker layer contains Al. Thereby, it is possible to suitably realize a configuration in which the plasma emission intensity of the third etching marker layer is larger than the plasma emission intensity of the upper and lower semiconductor layers in contact with the third etching marker layer.

  According to the method for manufacturing an optical semiconductor element according to the present invention, the etching depth for forming the mesa portion can be controlled with high accuracy.

FIG. 1 is a perspective view showing a configuration of an optical semiconductor device according to an embodiment of the present invention. FIG. 2 is a perspective view showing the internal structure of the optical semiconductor element. FIG. 3 is a perspective view showing each step of the manufacturing method according to the present embodiment. FIG. 4 is a perspective view showing each step of the manufacturing method according to the present embodiment. FIG. 5 is a perspective view showing each step of the manufacturing method according to the present embodiment. FIG. 6 is a perspective view showing each step of the manufacturing method according to the present embodiment. FIG. 7 is a perspective view showing each step of the manufacturing method according to the present embodiment. FIG. 8 is a perspective view showing each step of the manufacturing method according to the present embodiment. FIG. 9 is a perspective view showing each step of the manufacturing method according to the present embodiment. FIG. 10 is a perspective view showing each step of the manufacturing method according to the present embodiment. FIG. 11 is a perspective view showing each step of the manufacturing method according to the present embodiment. FIG. 12A is a side sectional view showing a laminated structure grown on a semi-insulating substrate. FIG. 12B shows changes in the plasma emission intensity, where the vertical axis indicates the thickness direction position and the horizontal axis indicates the 850 nm band plasma emission intensity. FIG. 13A is a side sectional view showing a laminated structure grown on a semi-insulating substrate. FIG. 13B shows changes in plasma emission intensity, where the vertical axis indicates the thickness direction position and the horizontal axis indicates the 850 nm band plasma emission intensity. FIG. 14A is a side sectional view showing a laminated structure grown on a semi-insulating substrate. FIG. 14B shows a change in plasma emission intensity, where the vertical axis indicates the thickness direction position and the horizontal axis indicates the 850 nm band plasma emission intensity. FIG. 15 is a perspective view showing an internal structure of a conventional optical semiconductor element.

  Embodiments of an optical semiconductor device manufacturing method according to the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 1 is a perspective view showing a configuration of an optical semiconductor element 10 according to an embodiment of the present invention. FIG. 2 is a perspective view showing the internal structure of the optical semiconductor element 10. As shown in FIGS. 1 and 2, the optical semiconductor element 10 includes a semi-insulating substrate 20, an etching marker layer 41 provided on the semi-insulating substrate 20, and an n provided on the etching marker layer 41. A type contact layer 21 and three mesa portions 22, 23, and 24 provided side by side on the n-type contact layer 21 are provided. The semi-insulating substrate 20 is a substrate made of a semi-insulating semiconductor material such as undoped InP. The n-type contact layer 21 is made of a first-conductivity-type III-V group compound semiconductor material that does not contain Al, for example, an n-type InGaAsP-based semiconductor. The n-type contact layer 21 is provided to supply current to the mesa portion 23. The etching marker layer 41 is a third etching marker layer in the present embodiment, and plasma emission of upper and lower semiconductor layers (in this embodiment, the semi-insulating substrate 20 and the n-type contact layer 21) in contact with the etching marker layer 41. It has a plasma emission intensity greater than the intensity. For example, the etching marker layer 41 is made of a first conductivity type III-V group compound semiconductor material containing Al. In one embodiment, the etching marker layer 41 is made of n-type AlInAs.

  Each of the mesa portions 22 to 24 extends along a predetermined optical waveguide direction A, and is arranged side by side in a direction intersecting with the optical waveguide direction A. As shown in FIG. 2, the mesa portions 22 to 24 each have a lower cladding layer 25, an optical waveguide layer 26, an upper cladding layer 27, and etching marker layers 42 and 43.

  The etching marker layer 42 is a first etching marker layer in the present embodiment. The etching marker layer 42 is provided on the n-type contact layer 21. The etching marker layer 42 has a plasma emission intensity that is greater than the plasma emission intensity of the upper and lower semiconductor layers (in this embodiment, the n-type contact layer 21 and the lower cladding layer 25) in contact with the etching marker layer 42. For example, the etching marker layer 42 is made of a first conductivity type III-V group compound semiconductor material containing Al. In one embodiment, the etching marker layer 42 is made of n-type AlInAs.

  The lower cladding layer 25 is the first cladding layer in the present embodiment. The lower cladding layer 25 is provided on the n-type contact layer 21. The lower cladding layer 25 is made of a first conductive type III-V group compound semiconductor material that does not contain Al, for example, n-type InP.

  The etching marker layer 43 is a second etching marker layer in the present embodiment. The etching marker layer 43 is provided on one of the two regions arranged along the optical waveguide direction A on the lower cladding layer 25. The etching marker layer 43 has a plasma emission intensity larger than that of the upper and lower semiconductor layers (in this embodiment, the lower cladding layer 25 and the core layer 26a (described later) of the optical waveguide layer 26) in contact with the etching marker layer 43. . For example, the etching marker layer 43 is made of a first conductivity type III-V group compound semiconductor material containing Al. In one embodiment, the etching marker layer 43 is made of n-type AlInAs.

  The optical waveguide layer 26 includes two types of core layers 26 a and 26 b arranged along the optical waveguide direction A. The core layers 26a and 26b have a so-called butt joint structure in which their end faces are in contact with each other. The core layer 26a is the first semiconductor layer in the present embodiment, and is provided on the etching marker layer 43 in one of the two regions on the lower cladding layer 25 aligned along the optical waveguide direction A. A part of the optical waveguide layer 26 is formed. The core layer 26a is made of an undoped III-V compound semiconductor material that does not contain Al, for example, InGaAsP. The core layer 26b is the second semiconductor layer in the present embodiment, and is provided on the lower cladding layer 25 in the other region of the two regions on the lower cladding layer 25 arranged along the optical waveguide direction A. The other part of the optical waveguide layer 26 is formed. The core layer 26b is made of an undoped III-V compound semiconductor material having a composition different from that of the core layer 26a, for example, AlGaInAs.

  The upper clad layer 27 is the second clad layer in the present embodiment, and is provided on the optical waveguide layer 26. The upper cladding layer 27 includes a second conductivity type III-V group compound semiconductor material and is made of, for example, p-type InP. A p-type contact layer (not shown) is provided on the upper cladding layer 27. This p-type contact layer is made of a second conductivity type III-V group compound semiconductor material, for example, a p-type InGaAsP-based semiconductor.

  As shown in FIG. 1, the optical semiconductor element 10 further includes embedded regions 27a and 27b made of resin. The embedded region 27 a is provided between the mesa unit 22 and the mesa unit 23 and embeds one side surface of the mesa unit 23. The embedded region 27 b is provided between the mesa portion 23 and the mesa portion 24 and embeds the other side surface of the mesa portion 23. The upper surfaces of the buried regions 27 a and 27 b and the upper surfaces of the mesa portions 22 to 24 are flush with each other, and constitute a flat upper surface of the optical semiconductor element 10. The buried regions 27a and 27b can be made of various resins (polymers) such as BCB, AL polymer, and polyimide. These buried regions 27a and 27b are provided for the purpose of avoiding the formation of wiring on the side surface of the mesa portion 23 in order to suppress scattering and absorption of propagating light.

  The optical semiconductor element 10 further includes two anode electrodes 32 and 33, a cathode electrode 34, wirings 35a, 35b and 35c, and wire bonding pads 36a, 36b and 36c. The anode electrode 32 is an electrode for supplying a current to the core layer 26 a and is provided on the mesa portion 23 at a position on the core layer 26 a. The anode electrode 33 is an electrode for supplying a current to the core layer 26b, and is provided on the mesa portion 23 at a position on the core layer 26b. The anode electrodes 32 and 33 are made of a metal such as an Au / Zn alloy, and form an ohmic contact with the p-type contact layer of the mesa portion 23.

  The cathode electrode 34 is an electrode for supplying current to both the core layers 26 a and 26 b, and is provided on the n-type contact layer 21 on the side of the mesa portion 22. The cathode electrode 34 is made of a metal such as an Au / Ge alloy and forms an ohmic junction with the n-type contact layer 21.

  Bonding wires (not shown) for electrically connecting the anode electrodes 32 and 33 and the cathode electrode 34 to the external circuit of the optical semiconductor element 10 are attached to the wire bonding pads 36a, 36b and 36c, respectively. It is done. The wire bonding pads 36a, 36b, and 36c are disposed on a predetermined region of the semi-insulating substrate 20, and the etching marker layer 41 and the n-type contact layer 21 are removed from the region. The wire bonding pads 36a, 36b and 36c are formed by, for example, Au plating.

  The wiring 35a connects the anode electrode 32 and the wire bonding pad 36a to each other. Similarly, the wiring 35b connects the anode electrode 33 and the wire bonding pad 36b to each other. The wirings 35a and 35b are made of, for example, a metal such as Ti / Pt / Au, and pass through the flat upper surface of the embedded region 27b from the upper surface of the mesa portion 23, through the upper surface and side surfaces of the mesa portion 24, and wire bonding pads 36a, 36b Are arranged respectively. As shown in FIG. 1, the side surfaces of the mesa portions 22 to 24 may be covered with the semi-insulating InP region 37 in order to protect the side surfaces of the core layer 26 a of the mesa portions 22 to 24. In this case, the wiring 35 a is preferably disposed on the side surface of the semi-insulating InP region 37. The wiring 35c connects the cathode electrode 34 and the wire bonding pad 36c to each other. The wiring 35c is made of a metal such as Ti / Pt / Au, for example, and is disposed from the region on the n-type contact layer 21 where the cathode electrode 34 is provided to the wire bonding pad 36c.

  Then, the manufacturing method of the optical semiconductor element 10 of this embodiment provided with the said structure is demonstrated. 3 to 11 are perspective views showing each step of the manufacturing method according to the present embodiment.

  First, as shown in FIG. 3A, an etching marker layer 41 is grown on the semi-insulating substrate 20 (third etching marker growth step). Next, the contact layer 21 is grown on the etching marker layer 41 (contact layer growth step).

  Subsequently, the etching marker layer 42 is grown on the semi-insulating substrate 20 (first etching marker layer growth step). In the present embodiment, the etching marker layer 42 is grown on the contact layer 21. Then, the lower cladding layer 25 is grown on the etching marker layer 42 (first cladding layer growth step).

  Subsequently, after the etching marker layer 43 is grown on the lower cladding layer 25 (second etching marker layer growth step), the core layer 26a is grown on the etching marker layer 43 (first optical waveguide layer growth step). ). Thereafter, as shown in FIG. 3B, an etching mask M1 is formed on one of the two regions on the cladding layer 25 aligned along the predetermined optical waveguide direction A. The etching mask M1 is made of a dielectric insulating film such as silicon oxide or silicon nitride. Then, as shown in FIG. 4A, by performing plasma etching on the portion of the core layer 26a that is not covered with the etching mask M1, the portion of the core layer 26a grown on the one region is removed. This is removed to expose a part of the lower cladding layer 25 (selective etching process). In this step, due to the difference in plasma emission intensity between the core layer 26a and the lower cladding layer 25 and the etching marker layer 43, the plasma emission intensity increases when the etching depth reaches the etching marker layer 43, and the etching marker layer After 43, the lower cladding layer 25 is reached. While observing the change in the plasma emission intensity, the plasma etching is stopped at the changed timing (preferably at the timing when the plasma emission intensity is reduced).

  Subsequently, as shown in FIG. 4B, the core layer 26b is selectively grown on the one region (exposed region) of the lower cladding layer 25 (second optical waveguide layer growing step). . Thus, the optical waveguide layer 26 including the core layers 26a and 26b forming the butt joint structure is formed. Thereafter, as shown in FIG. 5A, an upper clad layer 27 and a p-type contact layer (not shown) are grown on the optical waveguide layer 26 (second clad layer growth step).

  Subsequently, as shown in FIG. 5B, an etching mask M2 having a pattern corresponding to the planar shape of the mesa portions 22 to 24 is formed on the p-type contact layer. The etching mask M2 is made of a dielectric insulating film such as silicon oxide or silicon nitride. Then, as shown in FIG. 6A, by performing plasma etching on the upper cladding layer 27, the optical waveguide layer 26, and the lower cladding layer 25 that are not covered with the etching mask M2, the mesa portions 22 to 24 are performed. Is formed (mesa etching step). In this step, due to the difference in plasma emission intensity between the lower clad layer 25 and the n-type contact layer 21 and the etching marker layer 42, when the etching depth reaches the etching marker layer 42, the plasma emission intensity increases, and etching is performed. When the marker layer 42 is passed and the n-type contact layer 21 is reached, the plasma emission intensity decreases. While observing the change in the plasma emission intensity, the plasma etching is stopped at the changed timing (preferably at the timing when the plasma emission intensity is reduced).

  Subsequently, as illustrated in FIG. 6B, an etching mask M <b> 3 is formed to cover the top and side surfaces of the mesa portions 22 to 24 and the exposed surface of the n-type contact layer 21. The etching mask M3 removes a portion of the n-type contact layer 21 on the region in order to secure the region for forming the wire bonding pads 36a to 36c shown in FIG. 1 on the semi-insulating substrate 20. Formed for the purpose of. The etching mask M3 is made of a dielectric insulating film such as silicon oxide or silicon nitride. When forming the etching mask M3, it is not necessary to remove the etching mask M2 that has already been formed. Then, as shown in FIG. 7A, by performing plasma etching on the portion of the n-type contact layer 21 that is not covered with the etching mask M3, the portion of the n-type contact layer 21 grown in the region. Is removed (contact layer etching step). In this step, due to the difference in plasma emission intensity between the n-type contact layer 21 and the semi-insulating substrate 20 and the etching marker layer 41, the plasma emission intensity increases when the etching depth reaches the etching marker layer 41, When the etching marker layer 41 is passed and the semi-insulating substrate 20 is reached, the plasma emission intensity decreases. While observing the change in the plasma emission intensity, the plasma etching is stopped at the changed timing (preferably at the timing when the plasma emission intensity is reduced). Thereafter, as shown in FIG. 7B, the etching mask M3 is removed. The etching mask M2 remains and is used again in a later process.

  Subsequently, as shown in FIG. 8A, a mask M4 for forming a semi-insulating InP region 37 (see FIG. 1) is formed. This mask M4 is formed on the entire surface of the semi-insulating substrate 20 except the region where the semi-insulating InP region 37 is formed. Then, as shown in FIG. 8B, a semi-insulating InP region 37 is selectively grown. Thereafter, as shown in FIG. 9A, the mask M4 is removed.

Subsequently, as shown in FIG. 9B, an insulating film 38 as a protective film is formed on the entire surface of the semi-insulating substrate 20 (upper and side surfaces of the mesa portions 22 to 24 and the surface of the n-type contact layer 21). ) To form. The insulating film 38 can be made of, for example, SiN or SiO ₂ . Then, as shown in FIG. 10A, resin-embedded regions 27a and 27b are formed in the region between the mesa unit 22 and the mesa unit 23 and the region between the mesa unit 23 and the mesa unit 24. Form. The buried regions 27a and 27b are preferably formed by, for example, applying a resin layer on the semi-insulating substrate 20, forming a mask on the resin layer, and then partially curing the resin layer through the mask. It is formed.

  Subsequently, as shown in FIG. 10B, openings (contact holes) are formed in the portions of the insulating film 38 located on the core layer 26a and the core layer 26b of the mesa portion 23, and the openings are embedded. Thus, anode electrodes 32 and 33 are formed. Further, as shown in FIG. 11A, an opening (contact hole) is formed in a part of the insulating film 38 located on the n-type contact layer 21, and the cathode electrode 34 is formed so as to fill the opening. Finally, as shown in FIG. 11B, bonding pads 36a to 36c and wirings 35a to 35c are formed. Through the above steps, the optical semiconductor element 10 according to this embodiment is completed.

  The effect by the manufacturing method of the optical semiconductor element 10 according to the present embodiment will be described. In the manufacturing method of the present embodiment, after the lower cladding layer 25 is grown, the etching marker layer 43 is grown on the lower cladding layer 25 before the core layer 26a is grown. The etching marker layer 43 has a plasma emission intensity larger than that of the core layer 26 a and the lower cladding layer 25. Therefore, in the selective etching process (FIG. 4A) for forming the butt joint structure, when the etching depth reaches the etching marker layer 43 from the core layer 26a, the plasma emission intensity increases, and the etching marker layer 43 is passed. When reaching the lower cladding layer 25, the plasma emission intensity decreases.

  Here, the change in the plasma emission intensity will be described in detail with reference to FIG. FIG. 12A shows a laminated structure comprising an etching marker layer 41, an n-type contact layer 21, an etching marker layer 42, a lower cladding layer 25, an etching marker layer 43, and a core layer 26a grown on the semi-insulating substrate 20. FIG. FIG. 12B shows changes in plasma emission intensity, where the vertical axis indicates the thickness direction position and the horizontal axis indicates the 850 nm band plasma emission intensity. In the III-V group compound semiconductor, the plasma emission intensity of Al is the highest, the plasma emission intensity of Ga is lower than that of Al, and the plasma emission intensity of In is lower than Ga. Therefore, as shown in FIG. 12, when the plasma emission intensity when etching the core layer 26a made of InGaAsP-based semiconductor is P1, the plasma emission intensity when etching the etching marker layer 43 made of AlInAs is etched. P2 is larger than P1. That is, at the moment when the etching depth exceeds the thickness of the core layer 26a and reaches the etching marker layer 43, the plasma emission intensity increases. Further, if the plasma emission intensity when the lower cladding layer 25 made of n-type InP is etched is P3, P3 is smaller than P2. That is, the plasma emission intensity decreases at the moment when the etching depth passes through the etching marker layer 43 and reaches the lower cladding layer 25. According to the manufacturing method of this embodiment, the etching depth with respect to the core layer 26a can be accurately controlled by stopping the plasma etching based on such a change in the plasma emission intensity.

  When etching the core layer 26a, if the etching depth exceeds a predetermined depth, the etching proceeds to the lower cladding layer 25, and the height positions of the core layer 26b and the core layer 26a grown thereafter are aligned. I will not do it. For this reason, high etching accuracy is required when etching the core layer 26a. As described above, according to the manufacturing method of this embodiment, the etching depth for the core layer 26a can be accurately controlled.

  In the present embodiment, the core layer 26a and the lower cladding layer 25 do not contain Al in the composition, and the etching marker layer 43 contains Al in the composition. As described above, since the plasma emission intensity of Al is the highest in the group III-V compound semiconductor, the etching marker having a plasma emission intensity larger than that of the core layer 26a and the lower cladding layer 25 is obtained by such a configuration. The layer 43 can be suitably realized.

  In the manufacturing method of this embodiment, after the n-type contact layer 21 is grown, the etching marker layer 42 is grown on the n-type contact layer 21 before the lower cladding layer 25 is grown. The plasma emission intensity of the etching marker layer 42 is higher than the plasma emission intensity of the lower cladding layer 25 and the n-type contact layer 21. Therefore, in the mesa etching process for forming the mesa portions 22 to 24 (FIG. 6A), when the etching depth reaches the etching marker layer 42 from the lower cladding layer 25, the plasma emission intensity increases, and further, the n-type. When the contact layer 21 is reached, the plasma emission intensity decreases.

  FIG. 13A shows an etching marker layer 41, an n-type contact layer 21, an etching marker layer 42, a lower cladding layer 25, an etching marker layer 43, a core layer 26a, and an upper cladding layer 27 grown on the semi-insulating substrate 20. 2 is a side sectional view showing a laminated structure including a p-type contact layer 29 and FIG. FIG. 13B shows changes in plasma emission intensity, where the vertical axis indicates the thickness direction position and the horizontal axis indicates the 850 nm band plasma emission intensity. As described above, in the III-V group compound semiconductor, the plasma emission intensity of Al is the highest, the plasma emission intensity of Ga is lower than that of Al, and the plasma emission intensity of In is lower than Ga. Therefore, as shown in FIG. 13, when the plasma emission intensity when etching the lower cladding layer 25 made of n-type InP is P3, the plasma emission when the etching marker layer 42 made of AlInAs is etched. The intensity P4 (= P2) is larger than P3. That is, the plasma emission intensity increases at the moment when the etching depth exceeds the thickness of the lower cladding layer 25 and reaches the etching marker layer 42. Further, when the plasma emission intensity when etching the n-type contact layer 21 made of an InGaAsP-based semiconductor is P1, P1 is smaller than P4. That is, the plasma emission intensity decreases at the moment when the etching depth passes through the etching marker layer 42 and reaches the n-type contact layer 21. According to the manufacturing method of this embodiment, the etching depth for forming the mesa portions 22 to 24 can be accurately controlled by stopping the plasma etching based on such a change in the plasma emission intensity.

  When the mesa portions 22 to 24 are formed, if the etching depth exceeds a predetermined depth, the etching proceeds to the n-type contact layer 21, the n-type contact layer 21 is divided, and the mesa portion 23 and the cathode electrode 34. There is a risk that the electrical connection to may be lost. For this reason, when forming the mesa portions 22 to 24, high etching accuracy is required. As described above, according to the manufacturing method of this embodiment, the etching depth when forming the mesa portions 22 to 24 can be accurately controlled.

  In the present embodiment, the lower cladding layer 25 and the n-type contact layer 21 do not contain Al in the composition, and the etching marker layer 42 contains Al in the composition. As described above, since the plasma emission intensity of Al is the highest in the group III-V compound semiconductor, the structure has a plasma emission intensity greater than that of the lower cladding layer 25 and the n-type contact layer 21. The etching marker layer 42 can be suitably realized.

  In the manufacturing method of the present embodiment, the etching marker layer 41 is grown on the semi-insulating substrate 20 before the n-type contact layer 21 is grown. The plasma emission intensity of the etching marker layer 41 is higher than the plasma emission intensity of the n-type contact layer 21 and the semi-insulating substrate 20. Therefore, the etching depth is etched from the n-type contact layer 21 in the step of etching the portion of the n-type contact layer 21 in order to secure a region for forming the wire bonding pads 36a to 36c (FIG. 7A). When reaching the marker layer 41, the plasma emission intensity increases, and when reaching the semi-insulating substrate 20, the plasma emission intensity decreases.

  FIG. 14A is a cross-sectional view showing a stacked structure similar to FIG. FIG. 14B shows changes in plasma emission intensity, where the vertical axis indicates the thickness direction position and the horizontal axis indicates the 850 nm band plasma emission intensity. As described above, in the III-V group compound semiconductor, the plasma emission intensity of Al is the highest, the plasma emission intensity of Ga is smaller than Al, and the plasma emission intensity of In is smaller than Ga. Therefore, as shown in FIG. 14, when the plasma emission intensity when etching the n-type contact layer 21 made of InGaAsP-based semiconductor is P5, the plasma when etching the etching marker layer 41 made of AlInAs is etched. The emission intensity P6 (= P2) is greater than P5. That is, the plasma emission intensity increases at the moment when the etching depth exceeds the thickness of the n-type contact layer 21 and reaches the etching marker layer 41. If the plasma emission intensity when etching the semi-insulating substrate 20 made of InP is P3, P3 is smaller than P6. That is, the plasma emission intensity decreases at the moment when the etching depth passes through the etching marker layer 41 and reaches the semi-insulating substrate 20. According to the manufacturing method of this embodiment, the etching depth with respect to the n-type contact layer 21 can be accurately controlled by stopping the plasma etching based on such a change in the plasma emission intensity.

  When the n-type contact layer 21 is etched, if the etching depth exceeds a predetermined depth, the etching proceeds to the semi-insulating substrate 20, and the surface on which the wire bonding pads 36a to 36c are formed and the n-type contact layer Since the level difference with the surface of 21 becomes large, formation of wiring 35a-35c will become difficult. For this reason, high etching accuracy is required when the n-type contact layer 21 is etched. As described above, according to the manufacturing method of the present embodiment, the etching depth with respect to the n-type contact layer 21 can be accurately controlled.

  In the present embodiment, the n-type contact layer 21 and the semi-insulating substrate 20 do not contain Al in the composition, and the etching marker layer 41 contains Al in the composition. As described above, since the plasma emission intensity of Al is the highest in the group III-V compound semiconductor, the plasma emission intensity larger than the plasma emission intensity of the n-type contact layer 21 and the semi-insulating substrate 20 is obtained by such a configuration. The etching marker layer 41 having it can be suitably realized.

  In the present embodiment, the semi-insulating substrate 20 is exemplified as the substrate. If an unnecessary conductive layer is present in the optical semiconductor element, depending on the element structure, this conductive layer may promote the formation of stray capacitance, which may degrade the high-frequency characteristics of the optical semiconductor element. Therefore, the substrate in the optical semiconductor element is desirably semi-insulating.

  In the present embodiment, plasma etching is performed in each of the mesa etching process, the selective etching process, and the contact layer etching process. In an optical semiconductor device having an optical waveguide, in order to obtain good light propagation characteristics, dry etching that provides a highly perpendicular shape and a smooth surface is preferable, and plasma etching (particularly for etching an InP-based semiconductor). For example, inductively coupled plasma etching) is preferable.

  Further, according to the manufacturing method according to the present embodiment, when employing a large-diameter wafer process (for example, φ4 inch process) advantageous for mass production of butt-joint integrated waveguide type optical semiconductor elements and reduction of manufacturing cost, An easy mesa formation process independent of the wafer size can be provided without sacrificing other processes and device characteristics. Therefore, it can contribute to an increase in the diameter of the wafer process.

  The method for manufacturing an optical semiconductor device according to the present invention is not limited to the above-described embodiment, and various other modifications are possible. For example, in the above embodiment, the optical waveguide layer includes two core layers, and the so-called butt joint structure in which these core layers are arranged in the optical waveguide direction is exemplified, but the present invention is not limited to such a configuration, The present invention can also be applied to an optical semiconductor element having an optical waveguide layer composed of layers. In that case, the second etching marker layer is unnecessary.

  In the above embodiment, a semi-insulating substrate is exemplified as the substrate. However, the substrate in the present invention may be a conductive substrate made of an n-type or p-type semiconductor. In that case, the n-type contact layer and the third etching marker layer are unnecessary.

In the above embodiment, silicon oxide (SiO ₂ ) or silicon nitride (SiN) is used as the dielectric insulating film, but the material of the dielectric insulating film is not limited to these. The dielectric insulating film may be a fluoride, oxide, or nitride such as silicon, aluminum, and titanium.

  In the above embodiment, an example in which an n-type semiconductor is disposed between the substrate and the optical waveguide layer and a p-type semiconductor is disposed on the optical waveguide layer has been described. A p-type semiconductor may be disposed between them, and an n-type semiconductor may be disposed on the optical waveguide layer.

  In addition to the devices according to the above-described embodiments, other optical devices and electronic devices (for example, photodiodes and heterojunction bipolar transistors), capacitors, resistors, and the like are formed on the semi-insulating substrate, and photoelectric conversion is performed. A circuit may be formed.

  DESCRIPTION OF SYMBOLS 10 ... Optical semiconductor element, 20 ... Semi-insulating substrate, 21 ... N-type contact layer, 22-24 ... Mesa part, 25 ... Lower clad layer, 25 ... Cladding layer, 25 ... Lower clad layer, 26 ... Optical waveguide layer, 26a ... core layer (first semiconductor layer), 26b ... core layer (second semiconductor layer), 27 ... upper clad layer, 27a, 27b ... buried region, 29 ... p-type contact layer, 32 ... anode electrode, 33 ... Anode electrode, 34 ... Cathode electrode, 35a-35c ... Wiring, 36a-36c ... Wire bonding pad, 38 ... Insulating film, 41-43 ... Etching marker layer, A ... Optical waveguide direction, M1-M3 ... Etching mask.

Claims (6)

A first etching marker layer growth step of growing a first etching marker layer on the substrate;
A semiconductor growth step of sequentially growing a first cladding layer, an optical waveguide layer, and a second cladding layer on the first etching marker layer;
A mesa etching step of forming a mesa portion extending in a predetermined optical waveguide direction by performing plasma etching on the first cladding layer, the optical waveguide layer, and the second cladding layer,
The plasma emission intensity of the first etching marker layer is greater than the plasma emission intensity of the upper and lower semiconductor layers in contact with the first etching marker layer,
The method for manufacturing an optical semiconductor device, wherein the mesa etching step stops the plasma etching based on a change in the plasma emission intensity.   2. The method of manufacturing an optical semiconductor device according to claim 1, wherein upper and lower semiconductor layers in contact with the first etching marker layer do not contain Al, and the first etching marker layer contains Al. 3. The semiconductor growth step
A first cladding layer growth step for growing the first cladding layer;
A second etching marker layer growth step of growing a second etching marker layer on the first cladding layer;
A first optical waveguide layer growth step for growing a first semiconductor layer constituting a part of the optical waveguide layer on the second etching marker layer;
A selective etching step of removing a part of the first semiconductor layer by plasma etching and exposing a part of the first cladding layer;
A second optical waveguide layer growth step of selectively growing a second semiconductor layer in the exposed region of the first cladding layer;
And a second cladding layer growth step for growing the second cladding layer on the first semiconductor layer and the second semiconductor layer,
The plasma emission intensity of the second etching marker layer is greater than the plasma emission intensity of the upper and lower semiconductor layers in contact with the second etching marker layer,
The method of manufacturing an optical semiconductor element according to claim 1, wherein the selective etching step stops the plasma etching based on a change in plasma emission intensity.   4. The method of manufacturing an optical semiconductor element according to claim 3, wherein upper and lower semiconductor layers in contact with the second etching marker layer do not contain Al, and the second etching marker layer contains Al. 5. The manufacturing method includes a third etching marker layer growth step for growing a third etching marker layer on the substrate, and a contact layer growth step for growing a contact layer on the third etching marker layer. A step of plasma-etching a predetermined region of the contact layer before the etching marker layer growth step is further provided after the mesa etching step;
The plasma emission intensity of the third etching marker layer is greater than the plasma emission intensity of the upper and lower semiconductor layers in contact with the third etching marker layer,
5. The method of manufacturing an optical semiconductor element according to claim 1, wherein the contact layer etching step stops the plasma etching based on a change in plasma emission intensity.   6. The method of manufacturing an optical semiconductor element according to claim 5, wherein the upper and lower semiconductor layers in contact with the third etching marker layer do not contain Al, and the third etching marker layer contains Al.

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