JP2012074613A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2012074613A
JP2012074613A JP2010219570A JP2010219570A JP2012074613A JP 2012074613 A JP2012074613 A JP 2012074613A JP 2010219570 A JP2010219570 A JP 2010219570A JP 2010219570 A JP2010219570 A JP 2010219570A JP 2012074613 A JP2012074613 A JP 2012074613A
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sealing
substrate
epoxy resin
semiconductor device
resin composition
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Keiichi Sakumichi
慶一 作道
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Sumitomo Bakelite Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of both reducing thickness and achieving high reliability in an area mounting type semiconductor device such as BGA.SOLUTION: There is provided a manufacturing method of a semiconductor device comprising a sealant resin cured body 6 for sealing a substrate 1, a semiconductor element 4, and a connection member and satisfying the following requirements of (1) to (3) and (a), (b). (1) A size of the semiconductor device is 20 mm×20 mm or less. (2) A thickness of the substrate is 300 μm or less. (3) A maximum thickness of the sealant resin cured body from a semiconductor element mounting surface of the substrate is 600 μm or less. (a) A sealant resin composition includes an inorganic filler and an inorganic filler content in the composition is 74 mass% or more and 86 mass% or less. (b) In the case that the inorganic filler content in the sealant resin composition is defined as x (mass%) and a mold shrinkage rate when the sealant resin composition is post cured at 175°C for 4 hours after being molded at 175°C for 90 seconds is defined as y (%), a value of 0.032x+y-2.965 is 0.000 to 0.300.

Description

本発明は、半導体装置の製造方法及び半導体装置に関する。   The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

近年、電子機器の小型化、軽量化、高機能化の市場動向において、半導体装置の高集積化、薄型化が年々進み、また、半導体装置の表面実装化が促進されるなかで、従来用いてきたリードフレームの代わりに、有機基板やセラミック基板等の基板に半導体素子を搭載し、基板と半導体素子とを接続部材で電気的に接続した後、半導体素子と接続部材とをモールド材により成形封止して得られるエリア実装型半導体装置への移行が進んでいる。エリア実装型半導体装置としては、BGA(ボール・グリッド・アレイ)又は更に小型化を追求したCSP(チップスケールパッケージ)等が代表的なものとして挙げられる。また、エリア実装型半導体装置の製造においては、部材コストの低減と生産性の向上等を目的として、基板に複数の半導体装置に対応する半導体素子を搭載し、半導体素子と接続部材とをモールド材により一括で成形封止した後、切り離しを行って半導体装置とするMAP(モールド・アレイ・パッケージ)成形方式が確立され、成形方式の主流になりつつある。   In recent years, in the trend of downsizing, weight reduction, and higher functionality of electronic devices, semiconductor devices have been used in the past, as integration and thinning of semiconductor devices have progressed year by year, and surface mounting of semiconductor devices has been promoted. Instead of a lead frame, a semiconductor element is mounted on a substrate such as an organic substrate or a ceramic substrate, and the substrate and the semiconductor element are electrically connected by a connecting member, and then the semiconductor element and the connecting member are molded and sealed with a molding material. The shift to area-mounted semiconductor devices that can be obtained without stopping is progressing. Typical examples of the area mounting type semiconductor device include BGA (ball grid array) or CSP (chip scale package) pursuing further miniaturization. In the manufacture of area-mounted semiconductor devices, for the purpose of reducing member costs and improving productivity, semiconductor elements corresponding to a plurality of semiconductor devices are mounted on a substrate, and the semiconductor elements and connection members are molded. MAP (Mold Array Package) molding method has been established to form a semiconductor device by performing molding and sealing at once, and is becoming the mainstream of the molding method.

さらに、高機能化の要求に対しては、IO端子の増加及び高速動作に対応するため、基板と半導体素子との電気的接続を、フェイスアップで搭載された半導体素子上の電極と基板上の電極とをボンディングワイヤを介して行うワイヤーボンディングから、フェイスダウンで搭載された半導体素子上の電極と基板上の電極とを半田バンプを介して行うフリップチップボンディングへの移行が進んできている。フリップチップボンディングした半導体装置の封止には、これまでキャピラリーアンダーフィル材の毛細管現象を利用した充填により、半田バンプ等の接続部材周辺を含む基板と半導体素子との間隙部分を封止した後、実装歩留まりや信頼性の向上等の必要に応じて、モールド材を用いたトランスファー成形により、半導体素子をカバーするオーバーモールドが施されてきた。特に半導体装置の薄型化のために300μm以下の薄型の基板を用いる半導体装置においては、基板自体の剛性不足により半導体装置の反りが大きくなり、実装歩留まりや信頼性の低下を抑えるためにオーバーモールドを施すことが不可欠である。しかしながら、上記生産方式では、封止とオーバーモールドとを別の工程で行う必要があり、生産性が劣るため、モールドアンダーフィル材を用いたトランスファーモールド法により一工程で封止とオーバーモールドとを行う方法又はコンプレッションモールド法により一工程で封止とオーバーモールドとを行う方法が広まっている。この生産方式は、半田バンプ等の接続部材周辺を含む半導体素子と基板との間隙部分の封止とオーバーモールドとを同時に実施できるので、工程の簡略化による大きな生産性の向上が達成できる。   Furthermore, in response to the demand for higher functionality, the electrical connection between the substrate and the semiconductor element is made in a face-up manner in order to cope with the increase in IO terminals and high-speed operation. There has been a shift from wire bonding in which electrodes are connected via bonding wires to flip chip bonding in which electrodes on a semiconductor element mounted face down and electrodes on a substrate are connected via solder bumps. For sealing a flip-chip bonded semiconductor device, the gap between the substrate and the semiconductor element including the periphery of the connecting member such as a solder bump is sealed by filling the capillary underfill material using the capillary phenomenon. Overmolding that covers semiconductor elements has been performed by transfer molding using a molding material as required for improving the mounting yield and reliability. In particular, in a semiconductor device using a thin substrate of 300 μm or less in order to reduce the thickness of the semiconductor device, warping of the semiconductor device increases due to insufficient rigidity of the substrate itself, and overmolding is performed in order to suppress a reduction in mounting yield and reliability. It is essential to apply. However, in the above production method, it is necessary to perform sealing and overmolding in separate steps, and the productivity is inferior. Therefore, sealing and overmolding are performed in one step by a transfer molding method using a mold underfill material. A method of performing sealing and overmolding in one step by a method of performing or a compression molding method has been widespread. Since this production method can simultaneously perform sealing and overmolding of the gap between the semiconductor element including the periphery of the connecting member such as a solder bump and the substrate, a great improvement in productivity can be achieved by simplifying the process.

一方、小型化、軽量化の要求に対しては、半導体装置の薄型化の進展が目覚しく、特に携帯電話向けの半導体装置では多機能かつ省スペースである薄型BGAの開発が活発になっている。しかしながら、薄型BGAにおいては、パッケージ反りによる半導体素子への応力及び実装後の温度サイクル性の低下、あるいは、MAP成形方式で製造した際のパネル反りによる生産性の低下等、新たな問題が顕在化してきている。   On the other hand, in response to demands for miniaturization and weight reduction, the progress of thinning of semiconductor devices is remarkable, and development of a thin BGA that is multifunctional and space-saving is particularly active in semiconductor devices for mobile phones. However, in thin BGA, new problems such as stress on semiconductor elements due to package warpage and deterioration of temperature cycle after mounting, or reduction in productivity due to panel warpage when manufactured by the MAP molding method are manifested. Have been doing.

これまでのBGAパッケージでは、基板の半導体素子搭載面からの封止樹脂硬化体の厚みが1mm前後と厚く、成形時の封止樹脂の収縮が大きいことによるSmile反り(封止面を上にした場合下に凸の反り)の低減が課題であった。このような課題に対しては、フリップチップ実装用のアンダーフィル材として好適な充填性を維持しながら、封止後の基板反り(MAP成形方式で製造した際のパネル反り)及びパッケージ反り(パッケージ
単位に切り離し後の反り)を低減されることを目的として、エポキシ樹脂成形材料のガラス転移温度、曲げ弾性率及び成形収縮率を特定範囲とすることが提案されている(例えば、「特許文献1」参照。)。
In conventional BGA packages, the thickness of the cured sealing resin from the semiconductor element mounting surface of the substrate is as thick as about 1 mm, and the small warpage (with the sealing surface up) due to large shrinkage of the sealing resin during molding. In some cases, the reduction of the downward convex warping was a problem. For such problems, substrate warpage after sealing (panel warpage when manufactured by the MAP molding method) and package warpage (package) while maintaining a suitable filling property as an underfill material for flip chip mounting. For the purpose of reducing the warpage after being separated into units, it has been proposed to set the glass transition temperature, bending elastic modulus, and molding shrinkage ratio of the epoxy resin molding material within specific ranges (for example, “Patent Document 1”). "reference.).

しかしながら、BAGにおけるパッケージ反り及びパネル反りの方向は、主な構成要素である基板、半導体装置及び封止樹脂硬化体の厚み、平面上での面積、各要素の諸物性により変わり、基板の厚みが300μm以下であり、かつ基板の半導体素子搭載面からの封止樹脂硬化体の厚みが600μm以下となる薄型BGAにおいては、パッケージ反りの方向が逆になり、Cry反り(封止面を上にした場合上に凸の反り)の低減が課題となってくるため、上述のような従来技術では対応できないものとなっている。このため対応する封止用エポキシ樹脂組成物には、従来のSmile反り対応とは逆の方策となる高収縮化が必要となってくるが、単純に樹脂成分の配合量を増やすのみの方策では、耐湿性等の信頼性の低下を伴う弊害が発生することとなる。特に封止樹脂硬化体の厚みが200μm以上、400μm以下となる極薄型のBGAでは上記弊害が顕著であり、反りと信頼性とを両立できる技術が必要になってきている。   However, the direction of package warpage and panel warpage in the BAG varies depending on the thickness of the substrate, the semiconductor device and the encapsulated resin cured body, the area on the plane, and various physical properties of each element, which are the main components. In a thin BGA having a thickness of 300 μm or less and the thickness of the cured resin body from the semiconductor element mounting surface of the substrate being 600 μm or less, the direction of the package warp is reversed, and the Cry warp (with the sealing surface up) In this case, since the reduction of the convex warpage is an issue, the conventional technology as described above cannot cope with it. For this reason, the corresponding epoxy resin composition for sealing needs to have a high shrinkage, which is the opposite of the conventional countermeasure against Smile warping. However, it is not possible to simply increase the amount of the resin component. In addition, adverse effects accompanied by a decrease in reliability such as moisture resistance will occur. In particular, in the ultra-thin BGA in which the thickness of the encapsulated resin cured body is 200 μm or more and 400 μm or less, the above-described adverse effect is remarkable, and a technique capable of achieving both warpage and reliability is required.

特開2004−307647号公報JP 2004-307647 A

本発明の目的は、BGA等のエリア実装型半導体装置において、薄型化と高い信頼性の両立できる半導体装置を提供することにある。   An object of the present invention is to provide a semiconductor device capable of achieving both a reduction in thickness and high reliability in an area mounting type semiconductor device such as a BGA.

本発明の半導体装置の製造方法は、基板と、前記基板上に搭載された1個以上の半導体素子と、前記基板と前記半導体素子とを電気的に接続する接続部材と、前記半導体素子と前記接続部材とを封止する封止樹脂硬化体とを備え、かつ下記1)〜3)の要件を満たす半導体装置の製造方法であって、前記封止樹脂硬化体が、下記a)、b)の要件を満たす封止用エポキシ樹脂組成物をトランスファーモールド法、コンプレッションモールド法又はインジェクションモールド法で成形することにより得られることを特徴とする半導体装置の製造方法。
1)半導体装置のサイズが20mm×20mm以下である。
2)基板の厚みが300μm以下である。
3)基板の半導体素子搭載面からの封止樹脂硬化体の最大厚みが600μm以下である。a)封止用エポキシ樹脂組成物が無機充填材を含むものであり、前記組成物中における無機充填材含有量が74質量%以上、86質量%以下である。
b)封止用エポキシ樹脂組成物における無機充填材含有量をx(質量%)とし、封止用エポキシ樹脂組成物を175℃、120秒で成形した際の成形収縮率をy(%)としたとき、0.032x+y−2.965の値が0.000〜0.300である。
The method for manufacturing a semiconductor device of the present invention includes a substrate, one or more semiconductor elements mounted on the substrate, a connection member that electrically connects the substrate and the semiconductor element, the semiconductor element, and the semiconductor element. A method for manufacturing a semiconductor device comprising: a cured sealing resin that seals a connection member, and satisfying the following requirements 1) to 3), wherein the cured cured resin is a) and b): A method for producing a semiconductor device, which is obtained by molding a sealing epoxy resin composition satisfying the above requirements by a transfer molding method, a compression molding method or an injection molding method.
1) The size of the semiconductor device is 20 mm × 20 mm or less.
2) The thickness of the substrate is 300 μm or less.
3) The maximum thickness of the cured resin body from the semiconductor element mounting surface of the substrate is 600 μm or less. a) The epoxy resin composition for sealing contains an inorganic filler, and the inorganic filler content in the composition is 74% by mass or more and 86% by mass or less.
b) The content of the inorganic filler in the epoxy resin composition for sealing is x (mass%), and the molding shrinkage rate when the epoxy resin composition for sealing is molded at 175 ° C. for 120 seconds is y (%). The value of 0.032x + y-2.965 is 0.000 to 0.300.

本発明の半導体装置の製造方法は、前記封止用エポキシ樹脂組成物が下記一般式(1):

Figure 2012074613
(ただし、上記一般式(1)において、Arは炭素数6〜20の芳香族基であり、互いに同じであっても異なっていてもよい。R1は炭素数1〜6の炭化水素基であり、互いに同じであっても異なっていてもよい。R2は炭素数1〜4の炭化水素基で、W1は酸素原子又は硫黄原子である。R3は水素、炭素数1〜4の炭化水素基又は炭素数6〜20の芳香族基であり、互いに同じであっても異なっていてもよい。aは0〜10の整数、bは1〜3の整数である。m、nはモル比を表し、0≦m<1、0<n≦1で、m+n=1、かつ、m/nの平均値は1/10〜1/1である。)
で表される構造を有するエポキシ樹脂を含むものとすることができる。 In the method for producing a semiconductor device of the present invention, the sealing epoxy resin composition has the following general formula (1):
Figure 2012074613
(In the above general formula (1), Ar is an aromatic group having 6 to 20 carbon atoms, and may be the same or different from each other. R1 is a hydrocarbon group having 1 to 6 carbon atoms. And R2 is a hydrocarbon group having 1 to 4 carbon atoms, W1 is an oxygen atom or a sulfur atom, R3 is hydrogen, a hydrocarbon group having 1 to 4 carbon atoms, or An aromatic group having 6 to 20 carbon atoms, which may be the same or different from each other, a is an integer of 0 to 10, b is an integer of 1 to 3, and m and n represent molar ratios. 0 ≦ m <1, 0 <n ≦ 1, m + n = 1, and the average value of m / n is 1/10 to 1/1.)
The epoxy resin which has a structure represented by this shall be included.

本発明の半導体装置の製造方法は、前記封止用エポキシ樹脂組成物が硬化剤としてビフェニレン骨格含有フェノールアラルキル樹脂を含むものとすることができる。   In the method for producing a semiconductor device of the present invention, the sealing epoxy resin composition may contain a biphenylene skeleton-containing phenol aralkyl resin as a curing agent.

本発明の半導体装置の製造方法は、前記封止用エポキシ樹脂組成物が平均粒径1〜20μmの無機充填材を含むものとすることができる。   In the method for manufacturing a semiconductor device of the present invention, the sealing epoxy resin composition may include an inorganic filler having an average particle diameter of 1 to 20 μm.

本発明の半導体装置の製造方法は、前記接続部材が半田バンプであり、前記半田バンプが形成された前記半導体素子をフェイスダウンで前記基板上に搭載し、前記半田バンプと前記基板上の電極とを電気的に接続するものとすることができる。   In the method of manufacturing a semiconductor device of the present invention, the connection member is a solder bump, the semiconductor element on which the solder bump is formed is mounted on the substrate face down, and the solder bump, the electrode on the substrate, Can be electrically connected.

本発明の半導体装置の製造方法は、前記基板に複数の半導体装置に対応する前記半導体素子を搭載し、前記半導体素子と前期接続部材とを前記封止樹脂硬化体により一括で封止した後、前記半導体装置単位に切り離しを行うことで得られるものとすることができる。   In the method for manufacturing a semiconductor device of the present invention, the semiconductor element corresponding to a plurality of semiconductor devices is mounted on the substrate, the semiconductor element and the previous connection member are collectively sealed by the sealing resin cured body, It can be obtained by separating the semiconductor device unit.

本発明の半導体装置は、上述の半導体装置の製造方法により得られることを特徴とする。   The semiconductor device of the present invention is obtained by the above-described method for manufacturing a semiconductor device.

本発明によれば、BGA等のエリア実装型半導体装置において、薄型化と高い信頼性の両立ができる半導体装置が提供される。   According to the present invention, there is provided a semiconductor device capable of achieving both a reduction in thickness and high reliability in an area mounting type semiconductor device such as a BGA.

実施の形態に係る半導体装置の一例について、断面構造を模式的に示した図である。It is the figure which showed typically the cross-sectional structure about an example of the semiconductor device which concerns on embodiment. 実施の形態に係る半導体装置の一例について、断面構造を模式的に示した図である。It is the figure which showed typically the cross-sectional structure about an example of the semiconductor device which concerns on embodiment. 実施の形態に係る半導体装置の一例について、断面構造を模式的に示した図である。It is the figure which showed typically the cross-sectional structure about an example of the semiconductor device which concerns on embodiment.

以下、本発明の実施の形態について、図面を用いて説明する。尚、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

以下、本発明の半導体装置の製造方法について、好適な実施形態に基づいて説明する。本発明の半導体装置の製造方法は、基板と、基板上に搭載された1個以上の半導体素子と、基板と半導体素子とを電気的に接続する接続部材と、半導体素子と接続部材とを封止する封止樹脂硬化体とを備え、かつ下記1)〜3)の要件を満たす半導体装置の製造方法であって、封止樹脂硬化体が、下記a)、b)の要件を満たす封止用エポキシ樹脂組成物をトランスファーモールド法、コンプレッションモールド法又はインジェクションモールド法で成形することにより得られることを特徴とする。
1)半導体装置のサイズが20mm×20mm以下である。
2)基板の厚みが300μm以下である。
3)基板の半導体素子搭載面からの封止樹脂硬化体の最大厚みが600μm以下である。a)封止用エポキシ樹脂組成物が無機充填材を含むものであり、組成物中における無機充填材含有量が74質量%以上、86質量%以下である。
b)封止用エポキシ樹脂組成物における無機充填材含有量をx(質量%)とし、封止用エポキシ樹脂組成物を175℃、120秒で成形した際の成形収縮率をy(%)としたとき、0.032x+y−2.965の値が0.000〜0.300である。
Hereinafter, a method for manufacturing a semiconductor device of the present invention will be described based on a preferred embodiment. A method of manufacturing a semiconductor device according to the present invention includes a substrate, one or more semiconductor elements mounted on the substrate, a connection member that electrically connects the substrate and the semiconductor element, and the semiconductor element and the connection member. And a sealing resin cured body satisfying the following requirements 1) to 3), wherein the cured sealing resin satisfies the following requirements a) and b): It is obtained by forming the epoxy resin composition for use by a transfer molding method, a compression molding method or an injection molding method.
1) The size of the semiconductor device is 20 mm × 20 mm or less.
2) The thickness of the substrate is 300 μm or less.
3) The maximum thickness of the cured resin body from the semiconductor element mounting surface of the substrate is 600 μm or less. a) The epoxy resin composition for sealing contains an inorganic filler, and the inorganic filler content in the composition is 74 mass% or more and 86 mass% or less.
b) The content of the inorganic filler in the epoxy resin composition for sealing is x (mass%), and the molding shrinkage rate when the epoxy resin composition for sealing is molded at 175 ° C. for 120 seconds is y (%). The value of 0.032x + y-2.965 is 0.000 to 0.300.

ここで、要件b)は、無機充填材含有量xとの関係において、成形収縮率yの範囲を規定したものである。封止用エポキシ樹脂組成物の成形収縮率yは、無機充填材含有量xにより変化するため、本パラメータでは無機充填材含有量xを式中に取り込んだうえで、封止用エポキシ樹脂組成物の成形収縮率yの範囲が特定範囲となるように規定を行っている。これにより、エポキシ樹脂−硬化剤の組合せの寄与がより明確に判断でき、反りと信頼性の両立を達成する樹脂系の選択を容易にすることができる。その値は0.000〜0.3000であり、より好ましくは0.059〜0.159である。この値が上記範囲内であれば、信頼性と反りのバランスが高いレベルで保たれ、反り改良に伴う信頼性の低下を最小限に抑えることができる。この値が上記下限値以上であれば、反りと信頼性の両立を図ることができ、上記上限値以下であれば、樹脂が柔らかくなることによるパッケージ強度の低下を生ずる恐れが少ない。   Here, the requirement b) defines the range of the molding shrinkage y in relation to the inorganic filler content x. Since the molding shrinkage y of the epoxy resin composition for sealing changes depending on the inorganic filler content x, in this parameter, after incorporating the inorganic filler content x into the formula, the epoxy resin composition for sealing The range of the molding shrinkage ratio y is defined to be a specific range. Thereby, the contribution of the combination of the epoxy resin and the curing agent can be judged more clearly, and selection of a resin system that achieves both warpage and reliability can be facilitated. The value is 0.000-0.3,000, More preferably, it is 0.059-0.159. If this value is within the above range, the balance between reliability and warpage can be maintained at a high level, and a decrease in reliability due to improvement in warpage can be minimized. If this value is not less than the above lower limit value, it is possible to achieve both warpage and reliability, and if it is not more than the above upper limit value, there is little possibility of causing a decrease in package strength due to softening of the resin.

a)、b)の要件を満たす封止用エポキシ樹脂組成物をトランスファーモールド法、コンプレッションモールド法又はインジェクションモールド法で成形して封止樹脂硬化体を得ることにより、半田バンプ等の接続部材周辺を含む基板と半導体素子との間隙部分の封止と、半導体素子をカバーするオーバーモールドとを一工程で行うことができる。また、半導体装置のサイズが20mm×20mm以下であり、基板の厚みが300μm以下であり、かつ基板の半導体素子搭載面からの封止樹脂硬化体の厚みが600μm以下となる薄型BGAにおいて、耐湿性等の信頼性の低下を来たすことなく、パッケージ反りや、MAP成形方式で製造した際のパネル反りを低減することができ、BGA等のエリア実装型半導体装置における薄型化と高い信頼性との両立を図ることができる。尚、封止用エポキシ樹脂組成物がb)の要件を満たすためには、封止用エポキシ樹脂組成物の構成成分であるエポキシ樹脂の種類や配合量、硬化剤の種類や配合量、硬化促進剤の種類や配合量、無機充填材の種類や配合量、ならびに、それらの配合比率を調整すること等によって達成することができる。   A sealing epoxy resin composition that satisfies the requirements of a) and b) is molded by a transfer molding method, a compression molding method, or an injection molding method to obtain a cured sealing resin, whereby the periphery of a connecting member such as a solder bump is obtained. Sealing of the gap portion between the substrate and the semiconductor element and the overmold covering the semiconductor element can be performed in one step. Further, in a thin BGA in which the size of the semiconductor device is 20 mm × 20 mm or less, the thickness of the substrate is 300 μm or less, and the thickness of the cured resin body from the semiconductor element mounting surface of the substrate is 600 μm or less, moisture resistance The package warp and panel warp when manufactured by the MAP molding method can be reduced without causing a decrease in reliability such as BGA, etc., and both thinning and high reliability in area mounted semiconductor devices such as BGA Can be achieved. In order for the sealing epoxy resin composition to satisfy the requirements of b), the type and amount of epoxy resin, the type and amount of curing agent, and curing acceleration, which are constituent components of the sealing epoxy resin composition This can be achieved by adjusting the type and blending amount of the agent, the type and blending amount of the inorganic filler, and the blending ratio thereof.

尚、封止用エポキシ樹脂組成物の成形収縮率は、JIS K 6911に準じて求めることができ、より具体的には下記のようにして求めることができる。トランスファー成形機を用いて、金型温度175℃、成形圧力9.8MPa、硬化時間120秒の条件下で、直径90mm、厚み5mmの円盤状で、直径80mm部にリブ(高さ3mm、幅2mm)
をもつ試験片を成形し、20℃での金型キャビティのリブ部内径寸法と、20℃での円盤状試験片のリブ部外径寸法とを測定し、下記式で算出する。
The molding shrinkage of the sealing epoxy resin composition can be determined according to JIS K 6911, and more specifically can be determined as follows. Using a transfer molding machine, under the conditions of a mold temperature of 175 ° C., a molding pressure of 9.8 MPa, and a curing time of 120 seconds, the disk is 90 mm in diameter and 5 mm in thickness, and the rib is 80 mm in diameter (height 3 mm, width 2 mm). )
, The inner diameter dimension of the rib part of the mold cavity at 20 ° C. and the outer diameter dimension of the rib part of the disc-shaped test piece at 20 ° C. are measured and calculated by the following formula.

成形収縮率(%)={(20℃での金型キャビティのリブ部内径寸法)−(20℃での円盤状試験片のリブ部外径寸法)}/(20℃での金型キャビティのリブ部内径寸法)×100(%)
以下、封止用エポキシ樹脂組成物について詳細に説明する。本発明では、封止用エポキシ樹脂組成物が充填材として、無機充填材を用いる。無機充填材としては、一般に封止用エポキシ樹脂組成物に用いられているものを使用することができ、例えば、溶融シリカ、球状シリカ、結晶シリカ、アルミナ、窒化珪素、窒化アルミ等が挙げられる。無機充填材の平均粒径としては、1μm以上、20μm以下であることが好ましい。平均粒径が上記上限値以下であれば、半田バンプ等の接続部材周辺を含む半導体素子と基板との間隙部分への充填性が低下する恐れが少ない。また、平均粒径が上記下限値以上であれば、増粘によって充填性が低下する恐れが少ない。
Mold Shrinkage Ratio (%) = {(Inner Diameter of Rib Part of Mold Cavity at 20 ° C.) − (Outer Diameter of Rib Part of Disc Specimen at 20 ° C.)} / (Die Cavity of Mold Cavity at 20 ° C. Rib inner diameter) x 100 (%)
Hereinafter, the epoxy resin composition for sealing will be described in detail. In the present invention, the sealing epoxy resin composition uses an inorganic filler as the filler. As an inorganic filler, what is generally used for the epoxy resin composition for sealing can be used, and examples thereof include fused silica, spherical silica, crystalline silica, alumina, silicon nitride, and aluminum nitride. The average particle size of the inorganic filler is preferably 1 μm or more and 20 μm or less. If the average particle size is less than or equal to the above upper limit value, there is little possibility that the filling property in the gap portion between the semiconductor element including the periphery of the connection member such as a solder bump and the substrate will be lowered. Moreover, if an average particle diameter is more than the said lower limit, there is little possibility that a filling property will fall by thickening.

また、無機充填材の含有量としては、封止用エポキシ樹脂組成物全体の74質量%以上、86質量%以下が好ましく、より好ましくは74質量%以上、82質量%以下である。無機充填材の含有量の下限値が上記範囲内であると、封止用エポキシ樹脂組成物の硬化物の吸水量が増加して強度が低下することによる耐半田性の低下を引き起こす恐れが少ない。また、無機充填材の含有量の上限値が上記範囲内であると、半導体装置の反り特性が損なわれる不具合の恐れが少ない。   Moreover, as content of an inorganic filler, 74 mass% or more and 86 mass% or less of the whole epoxy resin composition for sealing are preferable, More preferably, they are 74 mass% or more and 82 mass% or less. When the lower limit value of the content of the inorganic filler is within the above range, the amount of water absorption of the cured product of the epoxy resin composition for sealing increases, and there is little possibility of causing a decrease in solder resistance due to a decrease in strength. . Further, when the upper limit value of the content of the inorganic filler is within the above range, there is little fear of a problem that the warp characteristics of the semiconductor device are impaired.

本発明では、封止用エポキシ樹脂組成物の樹脂成分として、エポキシ樹脂を用いることができる。本発明における封止用エポキシ樹脂組成物で用いることができるエポキシ樹脂としては、封止用エポキシ樹脂組成物がa)の要件を満たしつつb)の要件をも満たすように調整できるものであれば、特に制限されるものではなく、例えば、ビフェニル型エポキシ樹脂、ビスフェノールA型エポキシ樹脂、ビスフェノールF型エポキシ樹脂、スチルベン型エポキシ樹脂、ハイドロキノン型エポキシ樹脂等の結晶性エポキシ樹脂;クレゾールノボラック型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、ナフトールノボラック型エポキシ樹脂等のノボラック型エポキシ樹脂;フェニレン骨格含有フェノールアラルキル型エポキシ樹脂、ビフェニレン骨格含有フェノールアラルキル型エポキシ樹脂、フェニレン骨格含有ナフトールアラルキル型エポキシ樹脂等のフェノールアラルキル型エポキシ樹脂;トリフェノールメタン型エポキシ樹脂、アルキル変性トリフェノールメタン型エポキシ樹脂等の3官能型エポキシ樹脂;ジシクロペンタジエン変性フェノール型エポキシ樹脂、テルペン変性フェノール型エポキシ樹脂等の変性フェノール型エポキシ樹脂;トリアジン核含有エポキシ樹脂等の複素環含有エポキシ樹脂等が挙げられる。これらのエポキシ樹脂は、1種類を単独で用いても2種類以上を組み合わせて用いてもよい。   In this invention, an epoxy resin can be used as a resin component of the epoxy resin composition for sealing. As an epoxy resin that can be used in the epoxy resin composition for sealing in the present invention, as long as the epoxy resin composition for sealing can be adjusted so as to satisfy the requirements of b) while satisfying the requirements of a). There are no particular restrictions, for example, crystalline epoxy resins such as biphenyl type epoxy resins, bisphenol A type epoxy resins, bisphenol F type epoxy resins, stilbene type epoxy resins, hydroquinone type epoxy resins; cresol novolac type epoxy resins, Novolak type epoxy resins such as phenol novolac type epoxy resin and naphthol novolak type epoxy resin; phenylene skeleton containing phenol aralkyl type epoxy resin, biphenylene skeleton containing phenol aralkyl type epoxy resin, phenylene skeleton containing naphthol aralkyl Phenol aralkyl type epoxy resins such as epoxy resins; Trifunctional methane type epoxy resins, trifunctional epoxy resins such as alkyl modified triphenol methane type epoxy resins; Dicyclopentadiene modified phenol type epoxy resins, terpene modified phenol type epoxy resins, etc. Modified phenol type epoxy resins; heterocyclic ring-containing epoxy resins such as triazine nucleus-containing epoxy resins. These epoxy resins may be used alone or in combination of two or more.

これらのなかでも、封止用エポキシ樹脂組成物がa)の要件を満たしつつb)の要件をも容易に満たすことができるとの観点からは、下記一般式(1)で表される構造を有するエポキシ樹脂、ビフェニル型エポキシ樹脂、ビスフェノールA型エポキシ樹脂、ビスフェノールF型エポキシ樹脂、ビフェニレン骨格含有フェノールアラルキル型エポキシ樹脂を用いることが好ましく、特に下記一般式(1)で表される構造を有するエポキシ樹脂を用いることが好ましい。これらのエポキシ樹脂は、樹脂自体の収縮が大きく、無機充填材の配合量を過度に減じることなしに封止用エポキシ樹脂組成物の収縮率を大きくすることができる。よって、薄型BGAにおいてBGAの信頼性を保ちつつCry反りへの対応が容易になる。   Among these, from the viewpoint that the epoxy resin composition for sealing can easily satisfy the requirements of b) while satisfying the requirements of a), the structure represented by the following general formula (1) is used. It is preferable to use an epoxy resin, a biphenyl type epoxy resin, a bisphenol A type epoxy resin, a bisphenol F type epoxy resin, a biphenylene skeleton-containing phenol aralkyl type epoxy resin, and particularly an epoxy having a structure represented by the following general formula (1) It is preferable to use a resin. These epoxy resins have large shrinkage of the resin itself, and can increase the shrinkage rate of the sealing epoxy resin composition without excessively reducing the blending amount of the inorganic filler. Therefore, it becomes easy to cope with the Cry warp while maintaining the reliability of the BGA in the thin BGA.

Figure 2012074613
(ただし、上記一般式(1)において、Arは炭素数6〜20の芳香族基であり、互いに同じであっても異なっていてもよい。R1は炭素数1〜6の炭化水素基であり、互いに同じであっても異なっていてもよい。R2は炭素数1〜4の炭化水素基で、W1は酸素原子又は硫黄原子である。R3は水素、炭素数1〜4の炭化水素基又は炭素数6〜20の芳香族基であり、互いに同じであっても異なっていてもよい。aは0〜10の整数、bは1〜3の整数である。m、nはモル比を表し、0≦m<1、0<n≦1で、m+n=1、かつ、m/nの平均値は1/10〜1/1である。)
Figure 2012074613
(In the above general formula (1), Ar is an aromatic group having 6 to 20 carbon atoms, and may be the same or different from each other. R1 is a hydrocarbon group having 1 to 6 carbon atoms. And R2 is a hydrocarbon group having 1 to 4 carbon atoms, W1 is an oxygen atom or a sulfur atom, R3 is hydrogen, a hydrocarbon group having 1 to 4 carbon atoms, or An aromatic group having 6 to 20 carbon atoms, which may be the same or different from each other, a is an integer of 0 to 10, b is an integer of 1 to 3, and m and n represent molar ratios. 0 ≦ m <1, 0 <n ≦ 1, m + n = 1, and the average value of m / n is 1/10 to 1/1.)

複数のエポキシ樹脂を併用する場合、上記5種の好ましいエポキシ樹脂の配合割合の下限値としては、全エポキシ樹脂に対して、30質量%以上であることが好ましく、50質量%以上であることがより好ましく、70質量%以上であることが特に好ましい。配合割合の下限値が上記範囲内であると、無機充填材の配合量を過度に減じることなしに封止用エポキシ樹脂組成物の収縮率を大きくする効果を得ることができる。   When a plurality of epoxy resins are used in combination, the lower limit of the blending ratio of the above five kinds of preferable epoxy resins is preferably 30% by mass or more, and more preferably 50% by mass or more based on the total epoxy resin. More preferably, it is particularly preferably 70% by mass or more. When the lower limit value of the blending ratio is within the above range, an effect of increasing the shrinkage rate of the sealing epoxy resin composition can be obtained without excessively reducing the blending amount of the inorganic filler.

エポキシ樹脂全体の配合割合の下限値は、封止用エポキシ樹脂組成物の全量に対して、好ましくは3質量%以上であり、より好ましくは5質量%以上である。下限値が上記範囲内であると、得られる樹脂組成物は良好な流動性を有する。また、エポキシ樹脂全体の配合量の上限値は、封止用エポキシ樹脂組成物の全量に対して、好ましくは15質量%以下であり、より好ましくは13質量%以下である。上限値が上記範囲内であると、得られる樹脂組成物は良好な耐半田性を有する。   The lower limit of the blending ratio of the entire epoxy resin is preferably 3% by mass or more, more preferably 5% by mass or more with respect to the total amount of the epoxy resin composition for sealing. When the lower limit is within the above range, the resulting resin composition has good fluidity. Moreover, the upper limit of the compounding quantity of the whole epoxy resin becomes like this. Preferably it is 15 mass% or less with respect to the whole quantity of the epoxy resin composition for sealing, More preferably, it is 13 mass% or less. When the upper limit is within the above range, the resulting resin composition has good solder resistance.

本発明では、封止用エポキシ樹脂組成物のエポキシ樹脂を硬化させる成分として、硬化剤を用いることができる。本発明における封止用エポキシ樹脂組成物で用いることができる硬化剤としては、封止用エポキシ樹脂組成物がa)の要件を満たしつつb)の要件をも満たすように調整できるものであれば特に制限されるものではなく、例えば、エチレンジアミン、トリメチレンジアミン、テトラメチレンジアミン、ヘキサメチレンジアミン等の炭素数2〜20の直鎖脂肪族ジアミン、メタフェニレンジアミン、パラフェニレンジアミン、パラキシレンジアミン、4,4’−ジアミノジフェニルメタン、4,4’−ジアミノジフェニルプロパン、4,4’−ジアミノジフェニルエーテル、4,4’−ジアミノジフェニルスルホン、4,4’−ジアミノジシクロヘキサン、ビス(4−アミノフェニル)フェニルメタン、1,5−ジアミノナフタレン、メタキシレンジアミン、パラキシレンジアミン、1,1−ビス(4−アミノフェニル)シクロヘキサン、ジシアノジアミド等のアミノ類;アニリン変性レゾール樹脂やジメチルエーテルレゾール樹脂等のレゾール型フェノール樹脂;フェノールノボラック樹脂、クレゾールノボラック樹脂、tert−ブチルフェノールノボラック樹脂、ノニルフェノールノボラック樹脂等のノボラック型フェノール樹脂;フェニレン骨格含有フェノールアラルキル樹脂、ビフェニレン骨格含有フェノールアラルキル樹脂等のフェノールアラルキル樹脂;ナフタレン骨格やアントラセン骨格のような縮合多環構造を有するフェノール樹脂;ポリパラオキシスチレン等のポリオキシスチ
レン;ヘキサヒドロ無水フタル酸(HHPA)、メチルテトラヒドロ無水フタル酸(MTHPA)などの脂環族酸無水物、無水トリメリット酸(TMA)、無水ピロメリット酸(PMDA)、ベンゾフェノンテトラカルボン酸(BTDA)などの芳香族酸無水物などを含む酸無水物等;ポリサルファイド、チオエステル、チオエーテルなどのポリメルカプタン化合物;イソシアネートプレポリマー、ブロック化イソシアネートなどのイソシアネート化合物;カルボン酸含有ポリエステル樹脂などの有機酸類が例示される。これらは1種類を単独で用いても2種類以上を組み合わせて用いてもよい。また、これらのうち、耐湿性、信頼性等の点から、1分子内に少なくとも2個のフェノール性水酸基を有する化合物が好ましく、フェノールノボラック樹脂、クレゾールノボラック樹脂、tert−ブチルフェノールノボラック樹脂、ノニルフェノールノボラック樹脂等のノボラック型フェノール樹脂;レゾール型フェノール樹脂;ポリパラオキシスチレン等のポリオキシスチレン;フェニレン骨格含有フェノールアラルキル樹脂、ビフェニレン骨格含有フェノールアラルキル樹脂等が例示される。
In the present invention, a curing agent can be used as a component for curing the epoxy resin of the epoxy resin composition for sealing. As a hardening | curing agent which can be used with the epoxy resin composition for sealing in this invention, if the epoxy resin composition for sealing can adjust so that the requirements of b) may be satisfy | filled while satisfy | filling the requirements of a). It is not particularly limited, and examples thereof include linear aliphatic diamines having 2 to 20 carbon atoms such as ethylenediamine, trimethylenediamine, tetramethylenediamine, hexamethylenediamine, metaphenylenediamine, paraphenylenediamine, paraxylenediamine, 4 , 4'-diaminodiphenylmethane, 4,4'-diaminodiphenylpropane, 4,4'-diaminodiphenyl ether, 4,4'-diaminodiphenyl sulfone, 4,4'-diaminodicyclohexane, bis (4-aminophenyl) phenyl Methane, 1,5-diaminonaphthalene, metaxylene di Aminos such as amine, paraxylenediamine, 1,1-bis (4-aminophenyl) cyclohexane and dicyanodiamide; resol type phenol resins such as aniline-modified resole resin and dimethyl ether resole resin; phenol novolac resin, cresol novolac resin, tert -Novolak type phenol resins such as butylphenol novolak resin and nonylphenol novolak resin; phenol aralkyl resins such as phenylene skeleton-containing phenol aralkyl resin and biphenylene skeleton-containing phenol aralkyl resin; Polyoxystyrene such as polyparaoxystyrene; hexahydrophthalic anhydride (HHPA), methyltetrahydrophthalic anhydride (MTHP) A) and other alicyclic acid anhydrides, trimellitic anhydride (TMA), pyromellitic anhydride (PMDA), acid anhydrides including aromatic acid anhydrides such as benzophenone tetracarboxylic acid (BTDA), etc .; polysulfide Examples thereof include polymercaptan compounds such as thioesters and thioethers; isocyanate compounds such as isocyanate prepolymers and blocked isocyanates; and organic acids such as carboxylic acid-containing polyester resins. These may be used alone or in combination of two or more. Of these, compounds having at least two phenolic hydroxyl groups in one molecule are preferable from the viewpoint of moisture resistance, reliability, etc., and phenol novolak resin, cresol novolak resin, tert-butylphenol novolak resin, nonylphenol novolak resin Examples include novolak-type phenol resins such as resol-type phenol resins; polyoxystyrenes such as polyparaoxystyrene; phenylene skeleton-containing phenol aralkyl resins and biphenylene skeleton-containing phenol aralkyl resins.

さらにこれらのなかでも、封止用エポキシ樹脂組成物がa)の要件を満たしつつb)の要件をも容易に満たすことができるとの観点からは、ビフェニレン骨格含有フェノールアラルキル樹脂、フェニレン骨格含有アラルキル樹脂を用いることが好ましく、特にビフェニレン骨格含有フェノールアラルキル樹脂を用いることが好ましい。これらの硬化剤を一般式(1)で表される構造を有するエポキシ樹脂と組み合わせることにより、BGAの信頼性を保ちつつ薄型化への対応が容易となる。   Furthermore, among these, from the viewpoint that the epoxy resin composition for sealing can easily satisfy the requirements of b) while satisfying the requirements of a), a biphenylene skeleton-containing phenol aralkyl resin, a phenylene skeleton-containing aralkyl It is preferable to use a resin, and it is particularly preferable to use a phenol aralkyl resin containing a biphenylene skeleton. Combining these curing agents with an epoxy resin having a structure represented by the general formula (1) makes it easy to cope with the reduction in thickness while maintaining the reliability of the BGA.

複数の硬化剤を併用する場合、上記2種の好ましい硬化剤の配合割合の下限値としては、全硬化剤に対して、30質量%以上であることが好ましく、50質量%以上であることがより好ましく、70質量%以上であることが特に好ましい。配合割合の下限値が上記範囲内であると、無機充填材の配合量を過度に減じることなしに封止用エポキシ樹脂組成物の収縮率を大きくする効果を得ることができる。   In the case where a plurality of curing agents are used in combination, the lower limit of the blending ratio of the above two preferred curing agents is preferably 30% by mass or more and 50% by mass or more with respect to the total curing agent. More preferably, it is particularly preferably 70% by mass or more. When the lower limit value of the blending ratio is within the above range, an effect of increasing the shrinkage rate of the sealing epoxy resin composition can be obtained without excessively reducing the blending amount of the inorganic filler.

硬化剤全体の配合割合の下限値については、特に限定されないが、全樹脂組成物中に、1.5質量%以上であることが好ましく3質量%以上であることがより好ましい。配合割合の下限値が上記範囲内であると、充分な流動性を得ることができる。また、硬化剤全体の配合割合の上限値についても、特に限定されないが、全樹脂組成物中に、12質量%以下であることが好ましく、10質量%以下であることがより好ましい。配合割合の上限値が上記範囲内であると、良好な耐半田性を得ることができる。   Although it does not specifically limit about the lower limit of the mixture ratio of the whole hardening | curing agent, It is preferable that it is 1.5 mass% or more in all the resin compositions, and it is more preferable that it is 3 mass% or more. When the lower limit value of the blending ratio is within the above range, sufficient fluidity can be obtained. Further, the upper limit of the blending ratio of the entire curing agent is not particularly limited, but is preferably 12% by mass or less, and more preferably 10% by mass or less in the entire resin composition. When the upper limit of the blending ratio is within the above range, good solder resistance can be obtained.

なお、硬化剤としてフェノール樹脂系硬化剤のみを用いる場合におけるフェノール樹脂系硬化剤とエポキシ樹脂とは、全エポキシ樹脂のエポキシ基数(EP)と、全フェノール樹脂系硬化剤のフェノール性水酸基数(OH)との当量比(EP)/(OH)が、0.5以上、1.5以下となるように配合することが好ましい。当量比が上記範囲内であると、得られる樹脂組成物を成形する際、十分な硬化特性を得ることができる。さらにこれらのなかでも、封止用エポキシ樹脂組成物がa)の要件を満たしつつb)の要件をも容易に満たすことができるとの観点からは、当量比(EP)/(OH)が1.0以上、1.3以下となるように配合することが好ましい。これにより、耐湿性等の信頼性の低下を来たすことが少なく、収縮率を大きくすることが可能となる。   In addition, in the case of using only a phenol resin curing agent as the curing agent, the phenol resin curing agent and the epoxy resin are the number of epoxy groups (EP) of all epoxy resins and the number of phenolic hydroxyl groups (OH) of all phenol resin curing agents. The equivalent ratio (EP) / (OH) is preferably 0.5 or more and 1.5 or less. When the equivalent ratio is within the above range, sufficient curing characteristics can be obtained when the resulting resin composition is molded. Among these, from the viewpoint that the epoxy resin composition for sealing can easily satisfy the requirement of b) while satisfying the requirement of a), the equivalent ratio (EP) / (OH) is 1. It is preferable to mix | blend so that it may become 0.0 or more and 1.3 or less. As a result, reliability such as moisture resistance is hardly lowered, and the shrinkage rate can be increased.

本発明では、封止用エポキシ樹脂組成物に、更に硬化促進剤を用いることができる。硬化促進剤は、エポキシ樹脂と硬化剤との架橋反応を促進する作用を有するものであればよく、一般の封止用エポキシ樹脂組成物に使用されているものを利用することができる。具体例としては、有機ホスフィン、テトラ置換ホスホニウム化合物、ホスホベタイン化合物、ホスフィン化合物とキノン化合物との付加物、ホスホニウム化合物とシラン化合物との付加物等のリン原子含有化合物;1,8−ジアザビシクロ(5,4,0)ウンデセン−7
、ベンジルジメチルアミン、2−メチルイミダゾール等の窒素原子含有化合物等が挙げられる。これらのうち、リン原子含有化合物が好ましく、特に封止用エポキシ樹脂組成物の粘度を低くすることにより流動性を向上させることができること、さらに硬化立ち上がり速度という点を考慮するとテトラ置換ホスホニウム化合物が好ましく、また封止用エポキシ樹脂組成物の硬化物の熱時低弾性率という点を考慮するとホスホベタイン化合物、ホスフィン化合物とキノン化合物との付加物が好ましく、また潜伏的硬化性という点を考慮すると、ホスホニウム化合物とシラン化合物との付加物が好ましい。また、封止用エポキシ樹脂組成物がa)の要件を満たしつつb)の要件をも容易に満たすことができるとの観点からは、ホスホニウム化合物とシラン化合物との付加物、1,8−ジアザビシクロ(5,4,0)ウンデセン−7、ポスフィン化合物とキノン化合物の付加物、有機ホスフィンを用いることが好ましく、特にホスホニウム化合物とシラン化合物との付加物を用いることが好ましい。
In the present invention, a curing accelerator can be further used in the epoxy resin composition for sealing. Any curing accelerator may be used as long as it has a function of promoting a crosslinking reaction between the epoxy resin and the curing agent, and those used in general sealing epoxy resin compositions can be used. Specific examples include phosphorus-containing compounds such as organic phosphines, tetra-substituted phosphonium compounds, phosphobetaine compounds, adducts of phosphine compounds and quinone compounds, adducts of phosphonium compounds and silane compounds; 1,8-diazabicyclo (5 , 4, 0) Undecene-7
And nitrogen atom-containing compounds such as benzyldimethylamine and 2-methylimidazole. Among these, a phosphorus atom-containing compound is preferable, and in particular, a tetra-substituted phosphonium compound is preferable in view of the fact that fluidity can be improved by lowering the viscosity of the epoxy resin composition for sealing, and in addition, in view of the cure startup speed. In addition, phosphobetaine compounds, adducts of phosphine compounds and quinone compounds are preferable in consideration of the low thermal modulus of the cured epoxy resin composition, and in view of latent curability, Adducts of phosphonium compounds and silane compounds are preferred. Moreover, from the viewpoint that the epoxy resin composition for sealing can easily satisfy the requirements of b) while satisfying the requirements of a), an adduct of a phosphonium compound and a silane compound, 1,8-diazabicyclo (5, 4, 0) undecene-7, an adduct of a phosphine compound and a quinone compound, and an organic phosphine are preferably used, and an adduct of a phosphonium compound and a silane compound is particularly preferably used.

ホスホニウム化合物とシラン化合物との付加物としては、下記一般式(2)で表される化合物等が挙げられる。   Examples of the adduct of the phosphonium compound and the silane compound include compounds represented by the following general formula (2).

Figure 2012074613
(ただし、上記一般式(2)において、A1は窒素原子又はリン原子である。Siは珪素原子である。R4、R5、R6及びR7は、それぞれ、芳香環もしくは複素環を有する有機基、又は脂肪族基であり、互いに同一であっても異なっていてもよい。X1は、Y1及びY2と結合する有機基である。X2は、Y3及びY4と結合する有機基である。Y1及びY2は、プロトン供与性置換基がプロトンを放出してなる基であり、それらは互いに同一であっても異なっていてもよく、同一分子内のY1及びY2が珪素原子と結合してキレート構造を形成するものである。Y3及びY4は、プロトン供与性置換基がプロトンを放出してなる基であり、同一分子内のY3及びY4が珪素原子と結合してキレート構造を形成するものである。X1及びX2は互いに同一であっても異なっていてもよく、Y1、Y2、Y3及びY4は互いに同一であっても異なっていてもよい。Z1は芳香環又は複素環を有する有機基或いは脂肪族基である。)
Figure 2012074613
(In the above general formula (2), A1 is a nitrogen atom or a phosphorus atom. Si is a silicon atom. R4, R5, R6 and R7 are each an organic group having an aromatic ring or a heterocyclic ring, or X1 is an organic group bonded to Y1 and Y2, X2 is an organic group bonded to Y3 and Y4, and Y1 and Y2 are aliphatic groups that may be the same or different from each other. The proton-donating substituent is a group formed by releasing a proton, and they may be the same or different from each other, and Y1 and Y2 in the same molecule bind to a silicon atom to form a chelate structure. Y3 and Y4 are groups formed by proton-donating substituents releasing protons, and Y3 and Y4 in the same molecule are combined with a silicon atom to form a chelate structure. 2 may be the same as or different from each other, and Y1, Y2, Y3, and Y4 may be the same as or different from each other, and Z1 represents an organic group or an aliphatic group having an aromatic ring or a heterocyclic ring. is there.)

一般式(2)において、R4、R5、R6及びR7としては、例えば、フェニル基、メチルフェニル基、メトキシフェニル基、ヒドロキシフェニル基、ナフチル基、ヒドロキシナフチル基、ベンジル基、メチル基、エチル基、n−ブチル基、n−オクチル基及びシクロヘキシル基等が挙げられ、これらの中でも、フェニル基、メチルフェニル基、メトキシフェニル基、ヒドロキシフェニル基、ヒドロキシナフチル基等の置換基を有する芳香族基もしくは無置換の芳香族基がより好ましい。
また、一般式(2)において、X1は、Y1及びY2と結合する有機基である。同様に、X2は、Y3及びY4と結合する有機基である。Y1及びY2はプロトン供与性置換基がプロトンを放出してなる基であり、同一分子内のY1及びY2が珪素原子と結合してキレート構造を形成するものである。同様にY3及びY4はプロトン供与性置換基がプロトンを放出してなる基であり、同一分子内のY3及びY4が珪素原子と結合してキレート構造を形成するものである。X1及びX2は互いに同一でも異なっていてもよく、Y1、Y
2、Y3及びY4は互いに同一であっても異なっていてもよい。
In the general formula (2), as R4, R5, R6 and R7, for example, phenyl group, methylphenyl group, methoxyphenyl group, hydroxyphenyl group, naphthyl group, hydroxynaphthyl group, benzyl group, methyl group, ethyl group, n-butyl group, n-octyl group, cyclohexyl group, and the like. Among these, an aromatic group having a substituent such as phenyl group, methylphenyl group, methoxyphenyl group, hydroxyphenyl group, hydroxynaphthyl group, or the like. A substituted aromatic group is more preferred.
Moreover, in General formula (2), X1 is an organic group couple | bonded with Y1 and Y2. Similarly, X2 is an organic group that binds to Y3 and Y4. Y1 and Y2 are groups formed by proton-donating substituents releasing protons, and Y1 and Y2 in the same molecule are combined with a silicon atom to form a chelate structure. Similarly, Y3 and Y4 are groups formed by proton-donating substituents releasing protons, and Y3 and Y4 in the same molecule are combined with a silicon atom to form a chelate structure. X1 and X2 may be the same or different from each other, and Y1, Y
2, Y3 and Y4 may be the same or different from each other.

このような一般式(2)中の−Y1−X1−Y2−及び−Y3−X2−Y4−で表される基は、プロトン供与体が、プロトンを2個放出してなる基で構成されるものであり、プロトン供与体としては、例えば、カテコール、ピロガロール、1,2−ジヒドロキシナフタレン、2,3−ジヒドロキシナフタレン、2,2’−ビフェノール、1,1’−ビ−2−ナフトール、サリチル酸、1−ヒドロキシ−2−ナフトエ酸、3−ヒドロキシ−2−ナフトエ酸、クロラニル酸、タンニン酸、2−ヒドロキシベンジルアルコール、1,2−シクロヘキサンジオール、1,2−プロパンジオール及びグリセリン等が挙げられるが、これらの中でも、カテコール、1,2−ジヒドロキシナフタレン、2,3−ジヒドロキシナフタレンがより好ましい。   The groups represented by -Y1-X1-Y2- and -Y3-X2-Y4- in general formula (2) are composed of groups in which a proton donor releases two protons. Examples of proton donors include catechol, pyrogallol, 1,2-dihydroxynaphthalene, 2,3-dihydroxynaphthalene, 2,2′-biphenol, 1,1′-bi-2-naphthol, salicylic acid, Examples include 1-hydroxy-2-naphthoic acid, 3-hydroxy-2-naphthoic acid, chloranilic acid, tannic acid, 2-hydroxybenzyl alcohol, 1,2-cyclohexanediol, 1,2-propanediol, and glycerin. Of these, catechol, 1,2-dihydroxynaphthalene, and 2,3-dihydroxynaphthalene are more preferable.

また、一般式(2)中のZ1は、芳香環又は複素環を有する有機基又は脂肪族基を表し、これらの具体的な例としては、メチル基、エチル基、プロピル基、ブチル基、ヘキシル基及びオクチル基等の脂肪族基;フェニル基、ベンジル基、ナフチル基及びビフェニル基等の芳香族基;グリシジルオキシプロピル基、メルカプトプロピル基、アミノプロピル基及びビニル基等の反応性置換基を有する有機基などが挙げられるが、これらの中でも、メチル基、エチル基、フェニル基、ナフチル基及びビフェニル基が熱安定性の面からより好ましい。   Z1 in the general formula (2) represents an organic group or an aliphatic group having an aromatic ring or a heterocyclic ring. Specific examples thereof include a methyl group, an ethyl group, a propyl group, a butyl group, and a hexyl group. Group and aliphatic groups such as octyl group; aromatic groups such as phenyl group, benzyl group, naphthyl group and biphenyl group; having reactive substituents such as glycidyloxypropyl group, mercaptopropyl group, aminopropyl group and vinyl group An organic group and the like can be mentioned, and among these, a methyl group, an ethyl group, a phenyl group, a naphthyl group, and a biphenyl group are more preferable from the viewpoint of thermal stability.

ホスホニウム化合物とシラン化合物との付加物の製造方法としては、メタノールを入れたフラスコに、フェニルトリメトキシシラン等のシラン化合物、2,3−ジヒドロキシナフタレン等のプロトン供与体を加えて溶かし、次に室温攪拌下ナトリウムメトキシド−メタノール溶液を滴下する。さらにそこへ予め用意したテトラフェニルホスホニウムブロマイド等のテトラ置換ホスホニウムハライドをメタノールに溶かした溶液を室温攪拌下滴下すると結晶が析出する。析出した結晶を濾過、水洗、真空乾燥すると、ホスホニウム化合物とシラン化合物との付加物が得られる。しかし、これに限定されるものではない。   As a method for producing an adduct of a phosphonium compound and a silane compound, a silane compound such as phenyltrimethoxysilane and a proton donor such as 2,3-dihydroxynaphthalene are added to a flask containing methanol and dissolved, and then room temperature. Sodium methoxide-methanol solution is added dropwise with stirring. Furthermore, when a solution prepared by dissolving a tetra-substituted phosphonium halide such as tetraphenylphosphonium bromide in methanol in methanol is added dropwise with stirring at room temperature, crystals are precipitated. The precipitated crystals are filtered, washed with water, and vacuum dried to obtain an adduct of a phosphonium compound and a silane compound. However, it is not limited to this.

本発明に用いることができる硬化促進剤の配合量は、全封止用エポキシ樹脂組成物中0.1質量%以上、1質量%以下が好ましい。硬化促進剤の配合量の下限値が上記範囲内であると、硬化性の低下を引き起こす恐れが少ない。また、硬化促進剤の配合量の上限値が上記範囲内であると、流動性の低下を引き起こす恐れが少ない。   The blending amount of the curing accelerator that can be used in the present invention is preferably 0.1% by mass or more and 1% by mass or less in the total sealing epoxy resin composition. When the lower limit of the blending amount of the curing accelerator is within the above range, there is little possibility of causing a decrease in curability. Moreover, there is little possibility of causing the fall of fluidity | liquidity that the upper limit of the compounding quantity of a hardening accelerator is in the said range.

本発明では、封止用エポキシ樹脂組成物に、更にシランカップリング剤を用いることができる。シランカップリング剤は、エポキシシラン、アミノシラン、ウレイドシラン、メルカプトシラン等が好ましいが、特にこれらに限定されず、エポキシ樹脂と無機充填材との間で反応し、エポキシ樹脂と無機充填材の界面強度を向上させるものであればよい。エポキシシランとしては、例えば、γ−グリシドキシプロピルトリエトキシシラン、γ−グリシドキシプロピルトリメトキシシラン、γ−グリシドキシプロピルメチルジメトキシシラン、β−(3,4エポキシシクロヘキシル)エチルトリメトキシシラン等が挙げられ、アミノシランとしては、例えば、γ−アミノプロピルトリエトキシシラン、γ−アミノプロピルトリメトキシシラン、N−β(アミノエチル)γ−アミノプロピルトリメトキシシラン、N−β(アミノエチル)γ−アミノプロピルメチルジメトキシシラン、N−フェニルγ−アミノプロピルトリエトキシシラン、N−フェニルγ−アミノプロピルトリメトキシシラン、N−β(アミノエチル)γ−アミノプロピルトリエトキシシラン、N−6−(アミノヘキシル)3−アミノプロピルトリメトキシシラン、N−(3−(トリメトキシシリルプロピル)−1,3−ベンゼンジメタナン等が挙げられ、ウレイドシランとしては、例えば、γ−ウレイドプロピルトリエトキシシラン、ヘキサメチルジシラザン等が挙げられ、メルカプトシランとしては、例えば、γ−メルカプトプロピルトリメトキシシラン等が挙げられる。これらのシランカップリング剤は1種類を単独で用いても2種類以上を併
用してもよい。
In the present invention, a silane coupling agent can be further used in the epoxy resin composition for sealing. The silane coupling agent is preferably an epoxy silane, amino silane, ureido silane, mercapto silane, etc., but is not particularly limited, and reacts between the epoxy resin and the inorganic filler, and the interfacial strength between the epoxy resin and the inorganic filler. What is necessary is just to improve. Examples of the epoxy silane include γ-glycidoxypropyltriethoxysilane, γ-glycidoxypropyltrimethoxysilane, γ-glycidoxypropylmethyldimethoxysilane, β- (3,4 epoxycyclohexyl) ethyltrimethoxysilane. Examples of aminosilanes include γ-aminopropyltriethoxysilane, γ-aminopropyltrimethoxysilane, N-β (aminoethyl) γ-aminopropyltrimethoxysilane, and N-β (aminoethyl) γ. -Aminopropylmethyldimethoxysilane, N-phenylγ-aminopropyltriethoxysilane, N-phenylγ-aminopropyltrimethoxysilane, N-β (aminoethyl) γ-aminopropyltriethoxysilane, N-6- (amino (Hexyl) 3-aminopropyl Examples include trimethoxysilane and N- (3- (trimethoxysilylpropyl) -1,3-benzenedimethanane. Examples of ureidosilane include γ-ureidopropyltriethoxysilane and hexamethyldisilazane. Examples of the mercaptosilane include γ-mercaptopropyltrimethoxysilane, etc. These silane coupling agents may be used alone or in combination of two or more.

本発明に用いることができるシランカップリング剤の配合量は、全封止用エポキシ樹脂組成物中0.01質量%以上、1質量%以下が好ましく、より好ましくは0.05質量%以上、0.8質量%以下、特に好ましくは0.1質量%以上、0.6質量%以下である。シランカップリング剤の配合量の下限値が上記範囲内であれば、エポキシ樹脂と無機充填材との界面強度が低下することによる半導体装置における耐半田性の低下を引き起こす恐れが少ない。また、シランカップリング剤の配合量の上限値が上記範囲内であれば、封止用エポキシ樹脂組成物の硬化物の吸水性が増大することによる耐半田性の低下も引き起こす恐れが少ない。   The blending amount of the silane coupling agent that can be used in the present invention is preferably 0.01% by mass or more and 1% by mass or less, more preferably 0.05% by mass or more, 0 in the total epoxy resin composition for sealing. 0.8 mass% or less, particularly preferably 0.1 mass% or more and 0.6 mass% or less. When the lower limit of the amount of the silane coupling agent is within the above range, there is little possibility of causing a decrease in solder resistance in the semiconductor device due to a decrease in the interface strength between the epoxy resin and the inorganic filler. Moreover, if the upper limit of the compounding quantity of a silane coupling agent exists in the said range, there is little possibility of causing the fall of solder resistance by the water absorption of the hardened | cured material of the epoxy resin composition for sealing increasing.

本発明では、封止用エポキシ樹脂組成物に、上述の各成分を用いることができるが、更にこれ以外に必要に応じて、カルナバワックス等の天然ワックス、ポリエチレンワックス等の合成ワックス、ステアリン酸やステアリン酸亜鉛等の高級脂肪酸及びその金属塩類若しくはパラフィン等の離型剤;カーボンブラック、ベンガラ等の着色剤;シリコーンオイル、シリコーンゴム等の低応力添加剤;ハイドロタルサイト、酸化ビスマス水和物等の無機イオン交換体;水酸化アルミニウム、水酸化マグネシウム等の金属水酸化物、硼酸亜鉛、モリブデン酸亜鉛、フォスファゼン等の難燃剤等の添加剤を適宜配合してもよい。   In the present invention, the above-described components can be used for the epoxy resin composition for sealing. In addition to these, natural wax such as carnauba wax, synthetic wax such as polyethylene wax, stearic acid, Release agents such as higher fatty acids such as zinc stearate and its metal salts or paraffin; Colorants such as carbon black and bengara; Low stress additives such as silicone oil and silicone rubber; Hydrotalcite, bismuth oxide hydrate, etc. Inorganic ion exchangers such as: metal hydroxides such as aluminum hydroxide and magnesium hydroxide, and additives such as flame retardants such as zinc borate, zinc molybdate, and phosphazene may be appropriately blended.

本発明では、封止用エポキシ樹脂組成物は、上述の各成分及びその他の添加剤等を、例えば、ミキサー等を用いて常温で均一に混合したもの、更にその後、加熱ロール、ニーダー又は押出機等の混練機を用いて溶融混練し、続いて冷却、粉砕したものなど、必要に応じて適宜分散度や流動性等を調整したものを用いることができる。   In the present invention, the epoxy resin composition for sealing is obtained by uniformly mixing the above-described components and other additives at room temperature using, for example, a mixer, and then heating roll, kneader or extruder. It is possible to use a material which is appropriately adjusted in degree of dispersion, fluidity, etc., if necessary, such as melt kneaded using a kneader such as the above, followed by cooling and pulverization.

本発明では、半導体素子を搭載する基板の厚みが300μm以下のものを対象とする。本発明で用いられる基板は、その厚みが300μm以下のものであれば特に限定されるものではなく、例えば、有機基板やセラミック基板等を用いることができる。有機基板としては、例えば、BT樹脂/銅箔回路基板(ビスマレイミド・トリアジン樹脂/ガラスクロス基板)に代表される硬質回路基板、あるいは、ポリイミド樹脂フィルム/銅箔回路基板に代表されるフレキシブル回路基板等が挙げられる。基板の厚みの上限値については、半導体装置の薄型化という観点から、250μm以下であることがより好ましく、200μm以下であることが特に好ましい。また、基板の厚みの下限値については、基板自体の反りによるチップ実装の歩留まりという観点から、50μm以上であることが好ましく、100μm以上であることがより好ましい。   In the present invention, a substrate on which a semiconductor element is mounted has a thickness of 300 μm or less. The board | substrate used by this invention will not be specifically limited if the thickness is 300 micrometers or less, For example, an organic substrate, a ceramic substrate, etc. can be used. As an organic substrate, for example, a hard circuit board represented by BT resin / copper foil circuit board (bismaleimide / triazine resin / glass cloth board), or a flexible circuit board represented by polyimide resin film / copper foil circuit board Etc. The upper limit value of the thickness of the substrate is more preferably 250 μm or less, and particularly preferably 200 μm or less, from the viewpoint of reducing the thickness of the semiconductor device. Further, the lower limit value of the substrate thickness is preferably 50 μm or more, and more preferably 100 μm or more, from the viewpoint of yield of chip mounting due to warpage of the substrate itself.

本発明で基板に搭載される半導体素子としては、例えば、集積回路、大規模集積回路、トランジスタ、サイリスタ、ダイオード、固体撮像素子等が挙げられるが、これらに限定されるものではない。   Examples of the semiconductor element mounted on the substrate in the present invention include, but are not limited to, an integrated circuit, a large-scale integrated circuit, a transistor, a thyristor, a diode, and a solid-state imaging element.

本発明における半導体装置の形態としては、例えば、ボール・グリッド・アレイ(BGA)、チップ・サイズ・パッケージ(CSP)、マトリクス・アレイ・パッケージ・ボール・グリッド・アレイ(MAPBGA)、チップ・スタックド・チップ・サイズ・パッケージ等が挙げられるが、これらに限定されるものではない。   Examples of the semiconductor device according to the present invention include a ball grid array (BGA), a chip size package (CSP), a matrix array package ball grid array (MAPBGA), and a chip stacked chip. -Size, package, etc. are mentioned, but it is not limited to these.

封止用エポキシ樹脂組成物をトランスファーモールド法、コンプレッションモールド法又はインジェクションモールド法で成形して封止樹脂硬化体とし、半導体素子と接続部材とを封止した半導体装置は、そのまま、あるいは必要に応じて、80℃から200℃程度の温度で、10分から10時間程度の時間をかけて封止樹脂硬化体の硬化度を更に高めた後に、電子機器などに搭載される。   A semiconductor device in which an epoxy resin composition for sealing is molded by a transfer molding method, a compression molding method or an injection molding method to form a cured sealing resin, and the semiconductor element and the connection member are sealed is used as it is or as necessary. Then, after further increasing the degree of curing of the cured sealing resin at a temperature of about 80 ° C. to 200 ° C. over a period of about 10 minutes to 10 hours, it is mounted on an electronic device or the like.

図1は、実施の形態に係る片面封止型の半導体装置の一例であるBGAパッケージについて、断面構造を模式的に示した図である。基板1の表面に、ソルダーレジスト2の層が形成された積層体のソルダーレジスト2上に、ダイボンド材硬化体3を介して半導体素子4がフェイスアップで固定されている。半導体素子4の電極パッドと基板1上の電極パッドとの間はボンディングワイヤ5によって電気的に接続されている。図示していないが、導通をとるため、基板1の電極パッドが露出するよう、電極パッド上のソルダーレジスト2は現像法により除去されている。封止用エポキシ樹脂組成物を成形することで形成される封止樹脂硬化体6によって、半導体素子4とボンディングワイヤ5とを含む、基板1の半導体素子4が搭載された片面側のみが封止されている。基板1上の電極パッドは基板1上の非封止面側の半田ボール7と内部で電気的に接続されている。図1では、半導体装置において、基板1上に半導体素子4が1個搭載されたものを示したが、2個以上が並列又は積層されて搭載されていてもよい。かかる半導体装置は、1)〜3)の要件を満たすものであり、かつ、a)、b)の要件を満たす封止用エポキシ樹脂組成物を成形することにより得られる封止樹脂硬化体6により、半導体素子4とボンディングワイヤ5とが封止されているため、耐湿性等の信頼性の低下を来たすことなく、パッケージ反りを低減することができ、薄型化と高い信頼性の両立ができる半導体装置を経済的に得ることができる。   FIG. 1 is a diagram schematically showing a cross-sectional structure of a BGA package which is an example of a single-side sealed semiconductor device according to an embodiment. The semiconductor element 4 is fixed face-up on the solder resist 2 of the laminated body in which the layer of the solder resist 2 is formed on the surface of the substrate 1 through the die bond material cured body 3. The electrode pads of the semiconductor element 4 and the electrode pads on the substrate 1 are electrically connected by bonding wires 5. Although not shown, the solder resist 2 on the electrode pad is removed by a developing method so that the electrode pad of the substrate 1 is exposed for electrical conduction. Only one side of the substrate 1 including the semiconductor element 4 and the bonding wire 5 on which the semiconductor element 4 is mounted is sealed by the sealing resin cured body 6 formed by molding the sealing epoxy resin composition. Has been. The electrode pads on the substrate 1 are electrically connected internally to the solder balls 7 on the non-sealing surface side on the substrate 1. Although FIG. 1 shows a semiconductor device in which one semiconductor element 4 is mounted on a substrate 1, two or more semiconductor elements 4 may be mounted in parallel or stacked. Such a semiconductor device satisfies the requirements of 1) to 3) and is obtained by the encapsulated resin cured body 6 obtained by molding an epoxy resin composition for encapsulation that satisfies the requirements of a) and b). Since the semiconductor element 4 and the bonding wire 5 are sealed, the package warpage can be reduced without causing deterioration in reliability such as moisture resistance, and a semiconductor capable of achieving both thinning and high reliability. The device can be obtained economically.

図2は、実施の形態に係る片面封止型の半導体装置の一例であるFC(フリップチップ)−BGAパッケージについて、断面構造を模式的に示した図である。基板1の表面に、ソルダーレジスト2の層が形成された積層体のソルダーレジスト2上に、半田バンプ8を介して半導体素子4がフェイスダウンで搭載されている。半導体素子4の電極パッドと基板1上の電極パッドとの間は半田バンプ8によって電気的に接続されている。図示していないが、導通をとるため、基板1の電極パッドが露出するよう、電極パッド上のソルダーレジスト2は現像法により除去されている。封止用エポキシ樹脂組成物を成形することで形成される封止樹脂硬化体6によって、半田バンプ周辺を含む基板と半導体素子との間隙部分と、半導体素子4の周辺部分とを含む、基板1の半導体素子4が搭載された片面側のみが封止されている。基板1上の電極パッドは基板1上の非封止面側の半田ボール7と内部で電気的に接続されている。図2では、半導体装置において、基板1上に半導体素子4が1個搭載されたものを示したが、2個以上が並列又は積層されて搭載されていてもよい。かかる半導体装置は、1)〜3)の要件を満たすものであり、かつ、a)、b)の要件を満たす封止用エポキシ樹脂組成物を成形することにより得られる封止樹脂硬化体6により、半田バンプ周辺を含む基板と半導体素子との間隙部分の封止と、半導体素子4のオーバーモールドが形成されているため、耐湿性等の信頼性の低下を来たすことなく、パッケージ反りを低減することができ、薄型化と高い信頼性の両立ができる半導体装置を経済的に得ることができる。   FIG. 2 is a diagram schematically showing a cross-sectional structure of an FC (flip chip) -BGA package which is an example of a single-side sealed semiconductor device according to the embodiment. The semiconductor element 4 is mounted face-down on the surface of the substrate 1 via the solder bumps 8 on the solder resist 2 of the laminate in which the layer of the solder resist 2 is formed. The electrode pads of the semiconductor element 4 and the electrode pads on the substrate 1 are electrically connected by solder bumps 8. Although not shown, the solder resist 2 on the electrode pad is removed by a developing method so that the electrode pad of the substrate 1 is exposed for electrical conduction. Substrate 1 including a gap portion between the substrate including the solder bump periphery and the semiconductor element and a peripheral portion of the semiconductor element 4 by the cured sealing resin body 6 formed by molding the epoxy resin composition for sealing. Only one side on which the semiconductor element 4 is mounted is sealed. The electrode pads on the substrate 1 are electrically connected internally to the solder balls 7 on the non-sealing surface side on the substrate 1. Although FIG. 2 shows the semiconductor device in which one semiconductor element 4 is mounted on the substrate 1, two or more semiconductor elements 4 may be mounted in parallel or stacked. Such a semiconductor device satisfies the requirements of 1) to 3) and is obtained by the encapsulated resin cured body 6 obtained by molding an epoxy resin composition for encapsulation that satisfies the requirements of a) and b). Since the gap between the substrate including the periphery of the solder bump and the semiconductor element is sealed and the overmolding of the semiconductor element 4 is formed, the package warpage is reduced without deteriorating reliability such as moisture resistance. Therefore, it is possible to economically obtain a semiconductor device that can achieve both thinning and high reliability.

図3は、実施の形態に係る片面封止型の半導体装置の一例であるMAP−BGAパッケージについて、一括封止成形後(個片化前)のパネルの断面構造を模式的に示した図である。基板1の表面に、ソルダーレジスト2の層が形成された積層体のソルダーレジスト2上に、半田バンプ8を介して半導体素子4が複数個(例えば、3×3=9個)、フェイスダウンで搭載されている。半導体素子4の電極パッドと基板1上の電極パッドとの間は半田バンプ8によって電気的に接続されている。図示していないが、導通をとるため、基板1の電極パッドが露出するよう、電極パッド上のソルダーレジスト2は現像法により除去されている。封止用エポキシ樹脂組成物を成形することで形成される封止樹脂硬化体6によって、半田バンプ周辺を含む基板と半導体素子との間隙部分と、半導体素子4の周辺部分とを含む、基板1の半導体素子4が搭載された片面側のみが封止されている。尚、ダイシングライン9に沿ってダイシングすることで、それぞれの半導体装置に個片化される。個片化後、基板1上の非封止面側に半田ボール7を接合する。これにより、基板1上の電極パッドは基板1上の非封止面側の半田ボール7と内部で電気的に接続される。図3では、個片化された後の半導体装置において、基板1上に半導体素子4が1個搭載された形態
のものを示したが、2個以上が並列又は積層されて搭載された形態のものであってもよい。かかる半導体装置は、1)〜3)の要件を満たすものであり、かつ、a)、b)の要件を満たす封止用エポキシ樹脂組成物を成形することにより得られる封止樹脂硬化体6により、半田バンプ周辺を含む基板と半導体素子との間隙部分の封止と、半導体素子4のオーバーモールドが形成されているため、耐湿性等の信頼性の低下を来たすことなく、パネル反りやパッケージ反りを低減することができ、薄型化と高い信頼性の両立ができる半導体装置を経済的に得ることができる。
FIG. 3 is a diagram schematically showing a cross-sectional structure of a panel after collective sealing molding (before singulation) for a MAP-BGA package which is an example of a single-side sealed semiconductor device according to an embodiment. is there. A plurality of semiconductor elements 4 (for example, 3 × 3 = 9) are disposed face down on the solder resist 2 of the laminated body in which the layer of the solder resist 2 is formed on the surface of the substrate 1 via the solder bumps 8. It is installed. The electrode pads of the semiconductor element 4 and the electrode pads on the substrate 1 are electrically connected by solder bumps 8. Although not shown, the solder resist 2 on the electrode pad is removed by a developing method so that the electrode pad of the substrate 1 is exposed for electrical conduction. Substrate 1 including a gap portion between the substrate including the solder bump periphery and the semiconductor element and a peripheral portion of the semiconductor element 4 by the cured sealing resin body 6 formed by molding the epoxy resin composition for sealing. Only one side on which the semiconductor element 4 is mounted is sealed. In addition, by dicing along the dicing line 9, it is separated into individual semiconductor devices. After the separation, the solder balls 7 are joined to the non-sealing surface side on the substrate 1. As a result, the electrode pads on the substrate 1 are electrically connected internally to the solder balls 7 on the non-sealing surface side on the substrate 1. FIG. 3 shows a semiconductor device in which one semiconductor element 4 is mounted on the substrate 1 in the semiconductor device after being singulated, but two or more are mounted in parallel or stacked. It may be a thing. Such a semiconductor device satisfies the requirements of 1) to 3) and is obtained by the encapsulated resin cured body 6 obtained by molding an epoxy resin composition for encapsulation that satisfies the requirements of a) and b). Since the gap between the substrate including the periphery of the solder bump and the semiconductor element is sealed and the overmolding of the semiconductor element 4 is formed, panel warpage and package warpage are brought about without deteriorating reliability such as moisture resistance. Thus, a semiconductor device that can achieve both thinning and high reliability can be obtained economically.

以下、本発明を実験例にて具体的に説明するが、本発明はこれらの実験例によりなんら限定されるものではない。配合割合は質量部とする。   EXAMPLES Hereinafter, although this invention is demonstrated concretely by an experiment example, this invention is not limited at all by these experiment examples. The blending ratio is part by mass.

実験例で用いた封止用エポキシ樹脂組成物の構成成分を以下に示す。
(無機充填材)
無機充填材1:溶融球状シリカ((株)龍森製、MUF−6。篩により24μm以上の粒子を除去したもの。平均粒径6μm、比表面積3.4m/g。)
The constituent components of the sealing epoxy resin composition used in the experimental examples are shown below.
(Inorganic filler)
Inorganic filler 1: fused spherical silica (manufactured by Tatsumori Co., Ltd., MUF-6. Particles of 24 μm or more removed by a sieve. Average particle diameter 6 μm, specific surface area 3.4 m 2 / g)

(エポキシ樹脂)
エポキシ樹脂1:下記式(3)で表される構造を有するエポキシ樹脂(大日本インキ(株)製、EXA−7320。o−クレゾールとホルムアルデヒドと2−メトキシナフタレンを共縮合して得られたフェノール樹脂をエピクロルヒドリンでグリシジルエーテル化したエポキシ樹脂。エポキシ当量251g/eq、軟化点58℃。下記式(3)において、m、nはモル比を表し、m/nの平均値は1/4。)

Figure 2012074613
(Epoxy resin)
Epoxy resin 1: Epoxy resin having a structure represented by the following formula (3) (Dainippon Ink Co., Ltd., EXA-7320. Phenol obtained by co-condensation of o-cresol, formaldehyde and 2-methoxynaphthalene. (Epoxy resin obtained by glycidyl etherification of resin with epichlorohydrin. Epoxy equivalent 251 g / eq, softening point 58 ° C. In the following formula (3), m and n represent molar ratios, and the average value of m / n is 1/4.)
Figure 2012074613

エポキシ樹脂2:テトラメチルビフェニル型エポキシ樹脂(三菱化学(株)製、YX4000H。エポキシ当量185g/eq、融点107℃。)
エポキシ樹脂3:トリス(ヒドロキシフェニル)メタン型エポキシ樹脂(三菱化学(株)製、1032H60。エポキシ当量170g/eq、軟化点60℃。)
Epoxy resin 2: Tetramethylbiphenyl type epoxy resin (Mitsubishi Chemical Corporation, YX4000H. Epoxy equivalent 185 g / eq, melting point 107 ° C.)
Epoxy resin 3: Tris (hydroxyphenyl) methane type epoxy resin (manufactured by Mitsubishi Chemical Corporation, 1032H60. Epoxy equivalent 170 g / eq, softening point 60 ° C.)

(硬化剤)
硬化剤1:ビフェニレン骨格含有フェノールアラルキル樹脂(日本化薬(株)製、GPH−65、水酸基当量196g/eq、軟化点65℃。)
硬化剤2:フェニレン骨格含有フェノールアラルキル樹脂(三井化学(株)製、XLC−4L。水酸基当量165g/eq、軟化点65℃。)
硬化剤3:フェノールノボラック樹脂(住友ベークライト(株)製、PR−HF−3。水酸基当量104g/eq、軟化点80℃。)
(Curing agent)
Curing agent 1: Biphenylene skeleton-containing phenol aralkyl resin (manufactured by Nippon Kayaku Co., Ltd., GPH-65, hydroxyl group equivalent 196 g / eq, softening point 65 ° C.)
Curing agent 2: Phenol aralkyl resin containing a phenylene skeleton (Mitsui Chemicals, XLC-4L. Hydroxyl equivalent 165 g / eq, softening point 65 ° C.)
Curing agent 3: Phenol novolak resin (manufactured by Sumitomo Bakelite Co., Ltd., PR-HF-3. Hydroxyl equivalent weight 104 g / eq, softening point 80 ° C.)

(硬化促進剤)
硬化促進剤1:下記式(4)で表される硬化促進剤

Figure 2012074613
(Curing accelerator)
Curing accelerator 1: Curing accelerator represented by the following formula (4)
Figure 2012074613

(シランカップリング剤)
シランカップリング剤1:N−フェニル−γ−アミノプロピルトリメトキシシラン(東レ・ダウコーニング(株)製、商品名CF−4083)
(Silane coupling agent)
Silane coupling agent 1: N-phenyl-γ-aminopropyltrimethoxysilane (made by Toray Dow Corning Co., Ltd., trade name CF-4083)

(その他の添加剤)
離型剤1:カルナバワックス(日興リカ(株)製、ニッコウカルナバ)
着色剤1:カーボンブラック(三菱化学(株)製、MA600)
(Other additives)
Mold release agent 1: Carnauba wax (Nikko Rica Co., Ltd., Nikko Carnauba)
Colorant 1: Carbon black (manufactured by Mitsubishi Chemical Corporation, MA600)

(エポキシ樹脂組成物の製造)
表1及び表2の配合に従い、各原料をミキサーで混合した後、表面温度が90℃と45℃の2本ロールを用いて混練し、冷却後粉砕してエポキシ樹脂組成物を得た。得られたエポキシ樹脂組成物を以下の方法で評価した。結果を表1及び表2に示した。
(Manufacture of epoxy resin composition)
According to the composition of Table 1 and Table 2, after mixing each raw material with a mixer, it was kneaded using two rolls having surface temperatures of 90 ° C. and 45 ° C., cooled and pulverized to obtain an epoxy resin composition. The obtained epoxy resin composition was evaluated by the following methods. The results are shown in Tables 1 and 2.

評価方法
スパイラルフロー:低圧トランスファー成形機(コータキ精機(株)製、KTS−15)を用いて、ANSI/ASTM D 3123−72に準じたスパイラルフロー測定用金型に、金型温度175℃、注入圧力6.9MPa、保圧時間120秒の条件でエポキシ
樹脂組成物を注入し、流動長を測定した。単位はcm。スパイラルフローは、流動性のパラメータであり、数値が大きい方が良好な流動性を示す。判定基準は100cm未満を不合格、100cm以上を合格とした。
Evaluation Method Spiral Flow: Using a low-pressure transfer molding machine (KTS-15, manufactured by Kotaki Seiki Co., Ltd.), a mold temperature of 175 ° C. was injected into a spiral flow measurement mold according to ANSI / ASTM D 3123-72. The epoxy resin composition was injected under the conditions of a pressure of 6.9 MPa and a holding time of 120 seconds, and the flow length was measured. The unit is cm. Spiral flow is a parameter of fluidity, and a larger value indicates better fluidity. The criteria for determination were less than 100 cm as unacceptable and 100 cm or more as acceptable.

成形収縮率:低圧トランスファー成形機(コータキ精機(株)製、KTS−15)を用いて、金型温度175℃、成形圧力9.8MPa、硬化時間120秒の条件下で、直径90mm、厚み5mmの円盤状で、直径80mm部にリブ(高さ3mm、幅2mm)をもつ試験片を成形し、20℃での金型キャビティのリブ部内径寸法と、20℃での円盤状試験片のリブ部外径寸法とを測定し、下記式で算出した。
成形収縮率(%)={(20℃での金型キャビティのリブ部内径寸法)−(20℃での円盤状試験片のリブ部外径寸法)}/(20℃での金型キャビティのリブ部内径寸法)×100(%)
Molding shrinkage ratio: 90 mm in diameter and 5 mm in thickness using a low pressure transfer molding machine (KTS-15, manufactured by Kotaki Seiki Co., Ltd.) under conditions of a mold temperature of 175 ° C., a molding pressure of 9.8 MPa, and a curing time of 120 seconds. A test piece having a diameter of 80 mm and a rib (height 3 mm, width 2 mm) was molded, and the inner diameter dimension of the rib part of the mold cavity at 20 ° C. and the rib of the disk-shaped test piece at 20 ° C. The part outer diameter was measured and calculated by the following formula.
Mold Shrinkage Ratio (%) = {(Inner Diameter of Rib Part of Mold Cavity at 20 ° C.) − (Outer Diameter of Rib Part of Disc Specimen at 20 ° C.)} / (Die Cavity of Mold Cavity at 20 ° C. Rib inner diameter) x 100 (%)

パネル反り量(A PKG):低圧トランスファー成形機(TOWA(株)製、Yseries)を用いて、金型温度175℃、注入圧力6.9MPa、硬化時間90秒、注入
時間15秒の条件で脱気成形(17torr)にて50mm×55mm×350μm厚(基板の半導体素子搭載面からの封止樹脂硬化体の最大厚み)のサイズのパネルを成形した。成形に用いた基板(コア:三菱瓦斯化学(株)製、CCL−HL832HS、100μm厚。Cu:12μ厚。レジスト:太陽インキ製造(株)製、PSR−AUS308、12μ厚。)のサイズは55mm×62mmで、あらかじめ10mm×10mm×150μm厚(半田バンプを除く)のフリップチップ(SIN表面、搭載半田バンプ:φ100μmの鉛フリー半田、200μmピッチのフルグリッド)を3×3=9個搭載してある。成
形後、ポストキュアとして175℃で4時間加熱処理し、個片化前のパネルについて、シャドーモアレ方式の反り測定装置(Acrometrix社製、PS−200)を用いて高さ方向の変位を測定し、変位差の最も大きい値をパネル反り量とした。測定温度は25℃。判定基準は、1.2mm以上を不合格、1.2mm未満を合格とした。
パネル反り量(B PKG):基板の半導体素子搭載面からの封止樹脂硬化体の最大厚みを上記パネル反り量(A PKG)より100μm薄くして250μmとした以外は、上記パネル反り量(A PKG)と同様の処理、測定を行った。判定基準は、1.2mm以上を不合格、1.2mm未満を合格とした。
Panel warpage (A PKG): Using a low pressure transfer molding machine (manufactured by TOWA Co., Ltd., Yserials), removal was performed under conditions of a mold temperature of 175 ° C., an injection pressure of 6.9 MPa, a curing time of 90 seconds, and an injection time of 15 seconds. A panel having a size of 50 mm × 55 mm × 350 μm thickness (maximum thickness of the cured sealing resin body from the semiconductor element mounting surface of the substrate) was molded by air molding (17 torr). The size of the substrate (core: manufactured by Mitsubishi Gas Chemical Co., Ltd., CCL-HL832HS, 100 μm thick, Cu: 12 μm thick, resist: manufactured by Taiyo Ink Manufacturing Co., Ltd., PSR-AUS308, 12 μm thick) used for molding was 55 mm. 3 × 3 = 9 flip chips (SIN surface, mounted solder bump: lead-free solder of φ100 μm, full grid of 200 μm pitch) of 10 mm × 10 mm × 150 μm (excluding solder bumps) in advance of × 62 mm is there. After molding, heat treatment was performed at 175 ° C. for 4 hours as post-cure, and the displacement in the height direction of the panel before singulation was measured using a shadow moire type warpage measuring device (manufactured by Acrometrix, PS-200). The largest displacement difference was defined as the amount of panel warpage. The measurement temperature is 25 ° C. The judgment criteria were 1.2 mm or more as unacceptable and less than 1.2 mm as acceptable.
Panel warpage amount (B PKG): The panel warpage amount (A) except that the maximum thickness of the cured resin body from the semiconductor element mounting surface of the substrate is 250 μm, which is 100 μm thinner than the panel warpage amount (A PKG). The same treatment and measurement as in PKG) were performed. The judgment criteria were 1.2 mm or more as unacceptable and less than 1.2 mm as acceptable.

パッケージ反り量(A PKG):低圧トランスファー成形機(TOWA(株)製、Yseries)を用いて、金型温度175℃、注入圧力6.9MPa、硬化時間90秒、
注入時間15秒の条件で脱気成形(17torr)にて50mm×55mm×350μm厚(基板の半導体素子搭載面からの封止樹脂硬化体の最大厚み)のサイズのパネルを成形した。成形に用いた基板(コア:三菱瓦斯化学(株)製、CCL−HL832HS、100μm厚。Cu:12μ厚。レジスト:太陽インキ製造(株)製、PSR−AUS308、12μ厚。)のサイズは55mm×62mmで、あらかじめ10mm×10mm×150μm厚(半田バンプを除く)のフリップチップ(SIN表面、搭載半田バンプ:φ100μmの鉛フリー半田、200μmピッチのフルグリッド)を3×3=9個搭載してある。成形後、ポストキュアとして175℃で4時間加熱処理し、14×14mmのサイズに9個切り出し、テスト用のBGAパッケージを得た。得られたパッケージ9個について、シャドーモアレ方式の反り測定装置(Acrometrix社製、PS−200)を用いて高さ方向の変位を測定し、変位差の最も大きい値をパッケージ反り量とした。測定温度は25℃。判定基準は、50μm以上を不合格、50μm未満を合格とした。
パッケージ反り量(B PKG):基板の半導体素子搭載面からの封止樹脂硬化体の最大厚みを上記パッケージ反り量(A PKG)より100μm薄くして250μmとした以外は、上記パッケージ反り量(A PKG)と同様の処理、測定を行った。判定基準は、同様に、50μm以上を不合格、50μm未満を合格とした。
Package warpage (A PKG): Using a low-pressure transfer molding machine (manufactured by TOWA Co., Ltd., Yseries), mold temperature 175 ° C., injection pressure 6.9 MPa, curing time 90 seconds,
A panel having a size of 50 mm × 55 mm × 350 μm thickness (maximum thickness of the cured sealing resin from the semiconductor element mounting surface of the substrate) was molded by degassing molding (17 torr) under the condition of an injection time of 15 seconds. The size of the substrate (core: manufactured by Mitsubishi Gas Chemical Co., Ltd., CCL-HL832HS, 100 μm thick, Cu: 12 μm thick, resist: manufactured by Taiyo Ink Manufacturing Co., Ltd., PSR-AUS308, 12 μm thick) used for molding was 55 mm. 3 × 3 = 9 flip chips (SIN surface, mounted solder bump: lead-free solder of φ100 μm, full grid of 200 μm pitch) of 10 mm × 10 mm × 150 μm (excluding solder bumps) in advance of × 62 mm is there. After molding, heat treatment was performed at 175 ° C. for 4 hours as post-cure, and 9 pieces were cut into a size of 14 × 14 mm to obtain a test BGA package. With respect to nine obtained packages, the displacement in the height direction was measured using a shadow moire type warpage measuring apparatus (manufactured by Acrometrics, PS-200), and the largest value of the displacement difference was taken as the amount of package warpage. The measurement temperature is 25 ° C. As the judgment criteria, 50 μm or more was rejected, and less than 50 μm was accepted.
Package warpage amount (B PKG): The package warpage amount (A) except that the maximum thickness of the cured resin body from the semiconductor element mounting surface of the substrate is 250 μm less than the package warpage amount (A PKG) by 100 μm. The same treatment and measurement as in PKG) were performed. Similarly, the determination criteria were 50 μm or more as unacceptable and less than 50 μm as acceptable.

耐半田リフロー性(A PKG、B PKG):上記パッケージ反り量の評価において作製した、ポストキュア、切断後の14×14mmBGA(A PKG、B PKG)を、処理条件85℃、相対湿度60%で168時間加湿処理した後、IRリフロー処理(260℃、JEDEC・Le1el2条件に従う)を行った。処理後のパッケージ各6個について、内部の剥離及びクラックの有無を超音波探傷機(日立建機ファインテック(株)製、mi−scope10)で観察し、剥離発生率[(剥離発生パッケージ数)/(全パッケージ数)×100]を算出した。単位は%。耐半田性の判断基準は、剥離が発生しなかったものを◎、剥離発生率が20%未満のものを○、剥離発生率が20%以上、40%未満のものを△、剥離発生率が40%以上のものを×とした。   Solder reflow resistance (A PKG, B PKG): 14 × 14 mm BGA (A PKG, B PKG) after the post-cure and cutting produced in the evaluation of the amount of warping of the package described above at a processing condition of 85 ° C. and a relative humidity of 60%. After humidification treatment for 168 hours, IR reflow treatment (in accordance with JEDEC / Le1el2 conditions at 260 ° C.) was performed. For each of the 6 packages after treatment, the presence or absence of internal peeling and cracks was observed with an ultrasonic flaw detector (manufactured by Hitachi Construction Machinery Finetech Co., Ltd., mi-scope 10), and the rate of peeling occurrence [(number of peeling occurrence packages) / (Total number of packages) × 100]. Units%. The criteria for determining the soldering resistance are: ◎ if no peeling occurred, ○ if the peeling occurrence rate was less than 20%, Δ if the peeling occurrence rate was 20% or more and less than 40%, and the peeling occurrence rate was Those with 40% or more were marked with x.

Figure 2012074613
Figure 2012074613

Figure 2012074613
Figure 2012074613

実施例1〜6は、要件a)(無機充填材含有量が74質量%以上、86質量%以下)、及び要件b)(無機充填材含有量xと成形収縮率yとの関係が特定範囲)をともに満たすものであり、エポキシ樹脂の種類、硬化剤の種類、全エポキシ樹脂のエポキシ基数と全フェノール樹脂系硬化剤のフェノール性水酸基数との当量比、ならびに、無機充填材の含有量等を変えたものを含むものであるが、いずれにおいても、薄型のBGAパッケージ及びパネルにおける低反り性と耐半田リフロー性がともに優れる結果が得られた。   In Examples 1 to 6, requirement a) (inorganic filler content is 74% by mass or more and 86% by mass or less), and requirement b) (relationship between inorganic filler content x and molding shrinkage y is a specific range. ), The epoxy resin type, the type of curing agent, the equivalent ratio of the number of epoxy groups of all epoxy resins to the number of phenolic hydroxyl groups of all phenolic resin-based curing agents, the content of inorganic fillers, etc. However, in both cases, the low warpage property and the solder reflow resistance were excellent in thin BGA packages and panels.

一方、比較例1〜7は、要件a)は満たすものの、要件b)を満たさないものであり、薄型のBGAパッケージ及びパネルにおける低反り性及び耐半田リフロー性のいずれか、又は両方において劣る結果となった。   On the other hand, Comparative Examples 1 to 7 satisfy the requirement a) but do not satisfy the requirement b), and are inferior in either or both of low warpage and solder reflow resistance in thin BGA packages and panels. It became.

本発明に従うと、BGA等のエリア実装型半導体装置において、薄型化と高い信頼性の両立ができるので、基板の厚みが300μm以下、基板の半導体素子搭載面からの封止樹脂硬化体の最大厚みが600μm以下の半導体装置、とりわけ、封止樹脂硬化体の厚みが200μm以上、400μm以下となる極薄型のBGAパッケージに好適である。   According to the present invention, in an area-mounted semiconductor device such as a BGA, both thinning and high reliability can be achieved. Therefore, the thickness of the substrate is 300 μm or less, and the maximum thickness of the cured resin cured body from the semiconductor element mounting surface of the substrate Is suitable for a semiconductor device having a thickness of 600 μm or less, in particular, an extremely thin BGA package in which the thickness of the cured encapsulating resin is 200 μm or more and 400 μm or less.

1 基板
2 ソルダーレジスト
3 ダイボンド材硬化体
4 半導体素子
5 ボンディングワイヤ
6 封止樹脂硬化体
7 半田ボール
8 半田バンプ
9 ダイシングライン
DESCRIPTION OF SYMBOLS 1 Board | substrate 2 Solder resist 3 Die-bond material hardening body 4 Semiconductor element 5 Bonding wire 6 Sealing resin hardening body 7 Solder ball 8 Solder bump 9 Dicing line

Claims (7)

基板と、前記基板上に搭載された1個以上の半導体素子と、前記基板と前記半導体素子とを電気的に接続する接続部材と、前記半導体素子と前記接続部材とを封止する封止樹脂硬化体とを備え、かつ下記1)〜3)の要件を満たす半導体装置の製造方法であって、前記封止樹脂硬化体が、下記a)、b)の要件を満たす封止用エポキシ樹脂組成物をトランスファーモールド法、コンプレッションモールド法又はインジェクションモールド法で成形することにより得られることを特徴とする半導体装置の製造方法。
1)半導体装置のサイズが20mm×20mm以下である。
2)基板の厚みが300μm以下である。
3)基板の半導体素子搭載面からの封止樹脂硬化体の最大厚みが600μm以下である。a)封止用エポキシ樹脂組成物が無機充填材を含むものであり、前記組成物中における無機充填材含有量が74質量%以上、86質量%以下である。
b)封止用エポキシ樹脂組成物における無機充填材含有量をx(質量%)とし、封止用エポキシ樹脂組成物を175℃、120秒で成形した際の成形収縮率をy(%)としたとき、0.032x+y−2.965の値が0.000〜0.300である。
A substrate, one or more semiconductor elements mounted on the substrate, a connection member that electrically connects the substrate and the semiconductor element, and a sealing resin that seals the semiconductor element and the connection member An epoxy resin composition for sealing comprising a cured body and satisfying the following requirements 1) to 3), wherein the cured sealing resin satisfies the following requirements a) and b): A method for producing a semiconductor device, characterized in that the product is obtained by molding a product by a transfer molding method, a compression molding method or an injection molding method.
1) The size of the semiconductor device is 20 mm × 20 mm or less.
2) The thickness of the substrate is 300 μm or less.
3) The maximum thickness of the cured resin body from the semiconductor element mounting surface of the substrate is 600 μm or less. a) The epoxy resin composition for sealing contains an inorganic filler, and the inorganic filler content in the composition is 74% by mass or more and 86% by mass or less.
b) The content of the inorganic filler in the epoxy resin composition for sealing is x (mass%), and the molding shrinkage rate when the epoxy resin composition for sealing is molded at 175 ° C. for 120 seconds is y (%). The value of 0.032x + y-2.965 is 0.000 to 0.300.
前記封止用エポキシ樹脂組成物が下記一般式(1):
Figure 2012074613
(ただし、上記一般式(1)において、Arは炭素数6〜20の芳香族基であり、互いに同じであっても異なっていてもよい。R1は炭素数1〜6の炭化水素基であり、互いに同じであっても異なっていてもよい。R2は炭素数1〜4の炭化水素基で、W1は酸素原子又は硫黄原子である。R3は水素、炭素数1〜4の炭化水素基又は炭素数6〜20の芳香族基であり、互いに同じであっても異なっていてもよい。aは0〜10の整数、bは1〜3の整数である。m、nはモル比を表し、0≦m<1、0<n≦1で、m+n=1、かつ、m/nの平均値は1/10〜1/1である。)
で表される構造を有するエポキシ樹脂を含むことを特徴とする請求項1記載の半導体装置の製造方法。
The sealing epoxy resin composition has the following general formula (1):
Figure 2012074613
(In the above general formula (1), Ar is an aromatic group having 6 to 20 carbon atoms, and may be the same or different from each other. R1 is a hydrocarbon group having 1 to 6 carbon atoms. And R2 is a hydrocarbon group having 1 to 4 carbon atoms, W1 is an oxygen atom or a sulfur atom, R3 is hydrogen, a hydrocarbon group having 1 to 4 carbon atoms, or An aromatic group having 6 to 20 carbon atoms, which may be the same or different from each other, a is an integer of 0 to 10, b is an integer of 1 to 3, and m and n represent molar ratios. 0 ≦ m <1, 0 <n ≦ 1, m + n = 1, and the average value of m / n is 1/10 to 1/1.)
The method for manufacturing a semiconductor device according to claim 1, further comprising an epoxy resin having a structure represented by:
前記封止用エポキシ樹脂組成物が硬化剤としてビフェニレン骨格含有フェノールアラルキル樹脂を含むことを特徴とする請求項1又は2に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the sealing epoxy resin composition contains a phenol aralkyl resin containing a biphenylene skeleton as a curing agent. 前記封止用エポキシ樹脂組成物が平均粒径1〜20μmの無機充填材を含むことを特徴とする請求項1ないし3のいずれか1項に記載された半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the sealing epoxy resin composition includes an inorganic filler having an average particle diameter of 1 to 20 μm. 前記接続部材が半田バンプであり、前記半田バンプが形成された前記半導体素子をフェイスダウンで前記基板上に搭載し、前記半田バンプと前記基板上の電極とを電気的に接続することを特徴とする請求項1ないし4のいずれか1項に記載の半導体装置の製造方法。   The connection member is a solder bump, the semiconductor element on which the solder bump is formed is mounted on the substrate face down, and the solder bump and an electrode on the substrate are electrically connected. A method for manufacturing a semiconductor device according to claim 1. 前記基板に複数の半導体装置に対応する前記半導体素子を搭載し、前記半導体素子と前期接続部材とを前記封止樹脂硬化体により一括で封止した後、前記半導体装置単位に切り離しを行うことで得られることを特徴とする請求項1ないし5のいずれか1項に記載の半導体装置の製造方法。   By mounting the semiconductor elements corresponding to a plurality of semiconductor devices on the substrate, sealing the semiconductor elements and the previous connection member together with the sealing resin cured body, and then separating the semiconductor devices into units. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the method is obtained. 請求項1ないし6のいずれか1項に記載の半導体装置の製造方法により得られることを特徴とする半導体装置。   A semiconductor device obtained by the method for manufacturing a semiconductor device according to claim 1.
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014152302A (en) * 2013-02-13 2014-08-25 Sumitomo Bakelite Co Ltd Epoxy resin composition for sealing semiconductor, method for manufacturing semiconductor device, and semiconductor device
JP2015196628A (en) * 2014-04-02 2015-11-09 株式会社アドマテックス Alumina particle and production method thereof, and resin composition
JP2015213101A (en) * 2014-05-01 2015-11-26 住友ベークライト株式会社 Resin composition for seal, semiconductor device, and structure
KR20160059964A (en) 2014-11-19 2016-05-27 신에쓰 가가꾸 고교 가부시끼가이샤 Producing method of semiconductor device and semiconductor device
WO2016151717A1 (en) * 2015-03-23 2016-09-29 住友ベークライト株式会社 Mold underfill material for compression molding, semiconductor package, structure, and process for producing semiconductor package
JP2016213391A (en) * 2015-05-13 2016-12-15 日東電工株式会社 Sealing resin sheet
WO2018221681A1 (en) 2017-05-31 2018-12-06 日立化成株式会社 Liquid resin composition for sealing and electronic component device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09181226A (en) * 1995-10-27 1997-07-11 Sumitomo Bakelite Co Ltd Resin composition for ball-grid-array
JP2002110718A (en) * 2000-09-29 2002-04-12 Hitachi Ltd Manufacturing method of semiconductor device
JP2002194058A (en) * 2000-12-22 2002-07-10 Sumitomo Bakelite Co Ltd Semiconductor device
JP2004165381A (en) * 2002-11-12 2004-06-10 Nitto Denko Corp Semiconductor device
JP2004307647A (en) * 2003-04-07 2004-11-04 Hitachi Chem Co Ltd Epoxy resin molding material for sealing use and semiconductor device
JP2004307650A (en) * 2003-04-07 2004-11-04 Hitachi Chem Co Ltd Epoxy resin molding material for sealing and semiconductor device
JP2009130221A (en) * 2007-11-26 2009-06-11 Sumitomo Bakelite Co Ltd Semiconductor apparatus and sealing resin composition

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09181226A (en) * 1995-10-27 1997-07-11 Sumitomo Bakelite Co Ltd Resin composition for ball-grid-array
JP2002110718A (en) * 2000-09-29 2002-04-12 Hitachi Ltd Manufacturing method of semiconductor device
JP2002194058A (en) * 2000-12-22 2002-07-10 Sumitomo Bakelite Co Ltd Semiconductor device
JP2004165381A (en) * 2002-11-12 2004-06-10 Nitto Denko Corp Semiconductor device
JP2004307647A (en) * 2003-04-07 2004-11-04 Hitachi Chem Co Ltd Epoxy resin molding material for sealing use and semiconductor device
JP2004307650A (en) * 2003-04-07 2004-11-04 Hitachi Chem Co Ltd Epoxy resin molding material for sealing and semiconductor device
JP2009130221A (en) * 2007-11-26 2009-06-11 Sumitomo Bakelite Co Ltd Semiconductor apparatus and sealing resin composition

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014152302A (en) * 2013-02-13 2014-08-25 Sumitomo Bakelite Co Ltd Epoxy resin composition for sealing semiconductor, method for manufacturing semiconductor device, and semiconductor device
JP2015196628A (en) * 2014-04-02 2015-11-09 株式会社アドマテックス Alumina particle and production method thereof, and resin composition
JP2015213101A (en) * 2014-05-01 2015-11-26 住友ベークライト株式会社 Resin composition for seal, semiconductor device, and structure
KR20160059964A (en) 2014-11-19 2016-05-27 신에쓰 가가꾸 고교 가부시끼가이샤 Producing method of semiconductor device and semiconductor device
WO2016151717A1 (en) * 2015-03-23 2016-09-29 住友ベークライト株式会社 Mold underfill material for compression molding, semiconductor package, structure, and process for producing semiconductor package
JP2016213391A (en) * 2015-05-13 2016-12-15 日東電工株式会社 Sealing resin sheet
WO2018221681A1 (en) 2017-05-31 2018-12-06 日立化成株式会社 Liquid resin composition for sealing and electronic component device
EP3620481B1 (en) * 2017-05-31 2024-03-27 Resonac Corporation Liquid resin composition for sealing and electronic component apparatus

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