JP2012060591A - Solid-state image pickup device and image pickup apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device that suppresses the variation of a noise amount included in an image pickup signal, and an image pickup apparatus.SOLUTION: A controller 700 provides a first suspension period with at least one of initiation timing and cancellation timing of resetting a photoelectric conversion device as a reference to suspend reading of reset signals during a first period for sequentially reading the reset signals row by row, and provides a second suspension period for suspending reading of optical signals of pixels of the row in which the reading of the reset signals is suspended during a second period for sequentially reading the optical signals row by row.

Description

  The present invention relates to a solid-state imaging device and an imaging device in which a plurality of pixels are arranged, and more particularly to a solid-state imaging device and an imaging device having a global shutter function.

  Conventionally, as a MOS type solid-state imaging device, a global shutter system is known in which the exposure start time and the exposure end time of all pixels are the same, that is, the exposure period of all pixels is the same (for example, see Patent Document 1). FIG. 4 shows a pixel configuration of a global shutter type MOS solid-state imaging device. In FIG. 4, a single pixel 100 includes a photodiode 101, a transfer transistor 102, a charge holding unit (FD) 103, an FD reset transistor 104, an amplification transistor 105, a selection transistor 106, and a PD reset transistor 107.

  The photodiode 101 is a photoelectric conversion element that converts incident light into signal charges and accumulates them. The transfer transistor 102 is a transistor for transferring the signal charge accumulated in the photodiode 101 to the charge holding unit 103. The charge holding unit 103 holds the signal charge transferred from the photodiode 101 by the transfer transistor 102. The FD reset transistor 104 is a transistor for resetting signal charges in the charge holding unit 103. The amplification transistor 105 is a transistor for amplifying the voltage level of the charge holding unit 103 and outputting it as a pixel signal. The selection transistor 106 is a transistor for outputting a pixel signal to the vertical signal line 114 when the pixel 100 is selected as a pixel from which signal charges are read. The PD reset transistor 107 is a transistor for resetting the signal charge in the photodiode 101. Here, light is shielded except for the photodiode 101.

  In addition to the vertical signal line 114, a pixel power line 110, an FD reset line 111, a transfer line 112, a selection line 113, and a PD reset line 115 are arranged in the pixel 100. The pixel power supply line 110 is a signal line for applying the power supply voltage VDD, and is electrically connected to the drain side of the amplification transistor 105, the drain side of the PD reset transistor 107, and the drain side of the FD reset transistor 104. . The FD reset line 111 is a signal line for applying an FD reset pulse φRMi (i = 1 to m, m is the number of rows) for resetting the charge holding unit 103 for one row. The reset transistor 104 is connected to the gate.

  The transfer line 112 is a signal line for applying a row transfer pulse φTRi (i = 1 to m) for transferring the signal charges of pixels for one row to the charge holding unit 103 of each pixel. The pixel is electrically connected to the gate of the transfer transistor 102 of the pixel. The selection line 113 is a signal line for applying a row selection pulse φSEi (i = 1 to m) for selecting pixels for one row from which pixel signals are read out. It is electrically connected to the gate. Thus, a photoelectric conversion function, a reset function, an amplification read function, a temporary memory function, and a selection function are realized by a pixel configuration using five transistors.

  FIG. 5 shows the configuration of the MOS type solid-state imaging device. 5 includes a pixel unit 200, a vertical scanning circuit 300, a horizontal signal readout circuit 400, a current source 150, a column processing circuit 350, an ADC (AD (Analog to Digital) converter) 500, and a noise suppression circuit 600. It has.

  The pixel unit 200 has a structure in which the pixels 100 shown in FIG. 4 are arranged in a 3 × 3 two-dimensional shape. The pixel 100 in the pixel unit 200 constitutes a reading target area. The vertical scanning circuit 300 performs drive control of the pixel unit 200 in units of rows. In order to perform this drive control, the vertical scanning circuit 300 includes unit circuits 301-1, 301-2, and 301-3 as many as the number of rows. Each unit circuit includes control units 302-i, 303-i, 304-i, and 305-i (i = 1, 2, 3).

  The control unit 302-i independently controls the FD reset pulse φRMi (i = 1, 2, 3) for resetting the charge holding unit 103 for one row for each row. The control unit 303-i independently generates a row transfer pulse φTRi (i = 1, 2, 3) for transferring the signal charges of the pixels 100 for one row to the charge holding unit 103 of each pixel 100 for each row. Control. The control unit 304-i controls the PD reset pulse φRPDi (i = 1, 2, 3) for resetting the photodiodes 101 for one row independently for each row. The control unit 305-i independently controls the row selection pulse φSEi (i = 1, 2, 3) for selecting the pixels 100 for one row from which signals are read out for each row. The signal of the pixel 100 in the row selected by the row selection pulse φSEi is output to the vertical signal line 114 provided for each column.

  The current source 150 is connected to the vertical signal line 114, and forms a source follower circuit with the amplification transistor 105 in the pixel 100. The column processing circuit 350 is a circuit that performs a clamp operation and an amplification operation on the pixel signal output to the vertical signal line 114. The horizontal signal readout circuit 400 outputs the pixel signals of the pixels 100 for one row, which are output to the vertical signal line 114 and processed by the column processing circuit 350, from the output terminal 410 in time series in the horizontal order. The ADC 500 performs A / D conversion on the signal output from the output terminal 410.

  The noise suppression circuit 600 suppresses noise of the signal output from the ADC 500. The noise suppression circuit 600 includes a frame memory 610 and a subtracter 620. The frame memory 610 stores the signal that has been A / D converted by the ADC 500. The subtracter 620 subtracts the signal stored in the frame memory 610 from the signal A / D converted by the ADC 500 to generate an imaging signal.

  In FIG. 5, the FD reset line 111, the transfer line 112, the selection line 113, the vertical signal line 114, and the PD reset line 115 are illustrated, but the pixel power supply line 110 that supplies the power supply voltage VDD is not illustrated.

  Next, a global shutter read operation when the solid-state imaging device shown in FIG. 5 is applied to a digital camera or the like and a still image is taken will be described with reference to a timing chart shown in FIG. When the solid-state imaging device receives an imaging start signal, first, PD reset pulse φRPDi of all rows is “H” level, FD reset pulse φRMi is “L” level, row transfer pulse φTRi is “L” level, row selection pulse When φSEi becomes “L” level and the PD reset transistor 107 is turned on, the photodiodes 101 of all the pixels are reset. The PD reset pulse φRPDi, the FD reset pulse φRMi, the row transfer pulse φTRi, and the row selection pulse φSEi are output from the vertical scanning circuit 300.

  Subsequently, the FD reset pulse φRM1 in the first row becomes “H” level, and the FD reset transistor 104 in the first row is turned on, so that the charge holding unit 103 in the first row is reset. Then, after the FD reset pulse φRM1 in the first row becomes “L” level and the FD reset transistor 104 in the first row turns off, the row selection pulse φSE1 in the first row becomes “H” level. When the selection transistor 106 is turned on, the reset level of the charge holding unit 103 in the first row is output to the horizontal signal readout circuit 400 via the column processing circuit 350, and the reset signal corresponding to the reset level is output to the horizontal signal. The signals are output in time series from the output terminal 410 of the reading circuit 400 in the order of horizontal arrangement. The output reset signal in the first row is A / D converted by the ADC 500 and held in the frame memory 610. After the reset signal is read, the row selection pulse φSE1 in the first row becomes “L” level, and the selection transistor 106 in the first row is turned off.

  Subsequently, the same operation as the first row is performed for the second and third rows, and the reset signals of all the pixels are read out.

  Subsequently, the PD reset pulse φRPDi of all rows becomes “L” level and the PD reset transistor 107 is turned off, whereby the photodiode 101 starts accumulation. When the desired accumulation time has elapsed, the row transfer pulse φTRi for all rows becomes “H” level, and the transfer transistors 102 for all the pixels are turned on, so that the signal charges accumulated in the photodiodes 101 for all the pixels are retained. Transferred to the unit 103. The period from the start of accumulation of the photodiode 101 to the end of transfer of the signal charge to the charge holding unit 103 is an exposure period. Immediately after the signal charge transfer operation is completed, the row transfer pulse φTRi of all rows becomes “L” level, the transfer transistors 102 of all pixels are turned off, and the PD reset pulse φRPDi of all rows is “H”. The photodiode 101 of all pixels is reset.

  Subsequently, the row selection pulse φSE1 of the first row becomes “H” level, and the optical signal level corresponding to the signal charge is output from the pixels of the first row to the horizontal signal readout circuit 400 via the column processing circuit 350, Optical signals are output in time series from the output terminal 410 of the horizontal signal readout circuit 400 in the order of horizontal arrangement. The output optical signal in the first row is A / D converted by the ADC 500 and input to the subtractor 620. The subtractor 620 calculates the difference between the optical signal of the first row and the reset signal of the charge holding unit 103 of the first row held in the frame memory 610, and is stored in the photodiode 101 during the exposure period. Only the optical signal component corresponding to the received signal charge is extracted. In this operation, the reset noise of the charge holding unit 103 can be removed, so that a high S / N signal can be obtained. After the optical signal is read, the row selection pulse φSE1 of the first row becomes “L” level.

  Subsequently, the same operation as the first row is performed for the second and third rows, the optical signals of all pixels are read out, and the difference from the reset signal is taken to obtain a high S / N optical signal component. Only is taken out. An imaging signal composed of an optical signal component is input to an image processing circuit (not shown) and processed, and a final still image can be obtained. As described above, according to the solid-state imaging device shown in FIG. 5, it is possible to realize a global shutter operation in which the start and end timings of signal accumulation in all rows are the same.

  In such a global shutter type MOS solid-state imaging device, the reset signal is read as shown in FIG. 7 in order to shorten the time from reading the reset signal to reading the optical signal (FD accumulation time). A driving method has been proposed in which the PD reset pulse φRPDi of all the pixels is simultaneously set to the “L” level and exposure is started for all the pixels at the same time (for example, see Patent Document 2). In FIG. 7, the PD reset pulse φRPDi of all the pixels simultaneously becomes “L” level from when the reset signal of the first row is read to when the reset signal of the second row is read, and batch reset is performed. Then, the reset signal for the second row and the reset signal for the third row are read during the exposure period.

  By using this driving method, reading of the optical signal can be started immediately after reading of the reset signal, and the FD accumulation time can be shortened. Further, in Patent Document 2, when this driving method is used, the PD reset pulse φRPDi for batch reset is set so that fluctuations in the ground and pixel power generated when resetting all the pixels at once are not affected by the reset signal. There has been a proposal to temporarily stop the reading operation during the changing period.

  Hereinafter, a description will be given with reference to FIG. In FIG. 8, VD is a vertical synchronizing signal, and HD is a horizontal synchronizing signal. Further, VDD is a pixel power supply voltage, and GND is a ground level. In the operation shown in FIG. 8, all the pixels are reset at once while the reset signal is read out, but in order to prevent the ground level variation caused by the batch reset from affecting the reset signal, the batch reset is performed. During the period when the PD reset pulse φRPDi is changing, the reset signal reading operation is not performed. In FIG. 8, the PD reset pulse φRPDi of all the pixels simultaneously becomes “L” level after the reset signal of the first row is read until the reset signal of the second row is read out, and the batch reset is performed. The operation of reading the reset signal in the second row is stopped during a predetermined period (a temporary suspension period in FIG. 8) after the operation is performed. Thereby, the influence of the fluctuation | variation of the ground level which arises in the case of a batch reset can be suppressed.

JP 2005-65184 A JP 2008-131127 A

  However, in the prior art, the FD accumulation time from when the reset signal is read to when the optical signal is read is different between the row where the reset signal read operation is temporarily stopped and the previous row. In FIG. 8, the FD accumulation time Tfd1 in the first row is different from the FD accumulation time Tfd2 in the second row (= the FD accumulation time Tfd3 in the third row). When the FD accumulation time is different, the amount of FD noise such as FD dark current superimposed on the optical signal is different. Therefore, as shown in FIG. 9, in the output image based on the imaging signal, the reset signal readout operation is temporarily stopped. There was a problem that noise with steps was visible above and below.

  The present invention has been made in view of the above-described problems, and an object thereof is to provide a solid-state imaging device and an imaging device that can suppress variation in the amount of noise included in an imaging signal.

  The present invention has been made to solve the above-described problem, and includes a photoelectric conversion element, a charge holding unit that holds signal charges accumulated in the photoelectric conversion element, and a signal charge accumulated in the photoelectric conversion element. A transfer unit for transferring the charge to the charge holding unit, a first reset unit for resetting the signal charge held in the charge holding unit, and a second reset unit for resetting the signal charge accumulated in the photoelectric conversion element And a pixel unit including a readout unit that reads out a signal based on the signal charge held in the charge holding unit in a two-dimensional manner, and the charge holding unit of all pixels in the readout target region 1 is reset all at once, and immediately after resetting the charge holding unit, the readout unit sequentially reads out reset signals row by row, and the light of all pixels in the readout target region is read out. The conversion elements are collectively reset by the second reset unit, and after a predetermined time has elapsed from the resetting of the photoelectric conversion elements, all the pixels in the read target region are batched from the photoelectric conversion elements to the charge holding unit. A first control unit configured to transfer a signal charge by the transfer unit, and perform a control of sequentially reading the optical signal for each row by the reading unit after the signal charge is transferred from the photoelectric conversion element to the charge holding unit; In a first period in which the reset signal is sequentially read out for each row by the reading unit, a first stop period based on at least one of timing of start or release of resetting of the photoelectric conversion element by the second reset unit Is provided so as to temporarily stop reading of the reset signal by the reading unit, and by the reading unit In the second period of sequentially reading out the recording signal for each row, the reading out of the optical signal by the reading unit related to the pixel in the row where the reading of the reset signal by the reading unit is temporarily stopped is second stopped. And a second control unit that performs control to provide a stop period.

  In the solid-state imaging device of the present invention, the second control unit further performs control so that the lengths of the first stop period and the second stop period are the same.

  In the solid-state imaging device according to the aspect of the invention, the second control unit may further include a length of a period from the reading of the reset signal by the reading unit to the reading of the optical signal by the reading unit within the reading target region. Control is performed so as to be the same for all pixels.

  Moreover, this invention is an imaging device which has said solid-state imaging device.

  According to the present invention, in the second period in which the readout unit sequentially reads out the optical signal for each row, readout of the optical signal by the readout unit related to the pixel in the row in which readout of the reset signal by the readout unit is temporarily stopped is temporarily stopped. By providing the second stop period, the variation in the amount of noise included in the imaging signal can be suppressed.

It is a block diagram which shows the structure of the solid-state imaging device by one Embodiment of this invention. 6 is a timing chart illustrating an operation of the solid-state imaging device according to the embodiment of the present invention. It is a block diagram which shows the structure of the imaging device to which the solid-state imaging device by one Embodiment of this invention is applied. It is a circuit diagram which shows the structure of the pixel which a solid-state imaging device has. It is a block diagram which shows the structure of the conventional solid-state imaging device. It is a timing chart which shows operation | movement of the conventional solid-state imaging device. It is a timing chart which shows operation | movement of the conventional solid-state imaging device. It is a timing chart which shows operation | movement of the conventional solid-state imaging device. It is a reference figure for demonstrating the noise in an output image.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of a solid-state imaging device according to an embodiment of the present invention. The solid-state imaging device shown in FIG. 1 includes a pixel unit 200, a vertical scanning circuit 300, a horizontal signal readout circuit 400, a current source 150, a column processing circuit 350, an ADC 500, a noise suppression circuit 600, and a controller 700. The configuration of the solid-state imaging device shown in FIG. 1 is the same as that of the solid-state imaging device shown in FIG. 5 except that a controller 700 is added. The controller 700 performs control related to a period during which the operation of reading out the pixel signal from the pixel 100 is stopped. In particular, the controller 700 performs control so that the length of the period from the reset signal readout to the optical signal readout is the same for all pixels. The configuration of the pixel 100 included in the pixel unit 200 is the same as the configuration illustrated in FIG.

  Next, the operation of the solid-state imaging device shown in FIG. 1 will be described with reference to the timing chart shown in FIG. In FIG. 2, VD is a vertical synchronizing signal, and HD is a horizontal synchronizing signal. Further, VDD is a pixel power supply voltage, and GND is a ground level. A plurality of operation periods based on the horizontal synchronization signal HD are provided, and the reset signal and the optical signal of each row are read out within the operation period corresponding to each row. In FIG. 2, the breaks between the operation periods A to K are indicated by broken lines.

  When the solid-state imaging device receives an imaging start signal, first, PD reset pulse φRPDi of all rows is “H” level, FD reset pulse φRMi is “L” level, row transfer pulse φTRi is “L” level, row selection pulse When φSEi becomes “L” level and the PD reset transistor 107 is turned on, the photodiodes 101 of all the pixels are reset (start of reset).

  Subsequently, in the operation period C, the reset signal in the first row is read. That is, the FD reset pulse φRM1 in the first row becomes “H” level and the FD reset transistor 104 in the first row is turned on, so that the charge holding unit 103 in the first row is reset. Then, after the FD reset pulse φRM1 in the first row becomes “L” level and the FD reset transistor 104 in the first row turns off, the row selection pulse φSE1 in the first row becomes “H” level. When the selection transistor 106 is turned on, the reset level of the charge holding unit 103 in the first row is output to the horizontal signal readout circuit 400 via the column processing circuit 350, and the reset signal corresponding to the reset level is output to the horizontal signal. The signals are output in time series from the output terminal 410 of the reading circuit 400 in the order of horizontal arrangement. The output reset signal in the first row is A / D converted by the ADC 500 and held in the frame memory 610. After the reset signal is read, the row selection pulse φSE1 in the first row becomes “L” level, and the selection transistor 106 in the first row is turned off.

  At the end of the operation period C, the PD reset pulse φRPDi of all rows becomes “L” level, and the PD reset transistor 107 is turned off, so that the photodiode 101 starts accumulation (reset release). In the operation period D (first stop period) immediately after the PD reset pulse φRPDi becomes “L” level, the read operation of the reset signal in the second row is stopped under the control of the controller 700. Subsequently, the reset signal in the second row is read in the operation period E, and the reset signal in the third row is read in the operation period F.

  At the end of the operation period F, the row transfer pulse φTRi of all rows becomes “H” level, and the transfer transistors 102 of all the pixels are turned on, so that the signal charges accumulated in the photodiodes 101 of all the pixels are charged. Forwarded to The period from the start of accumulation of the photodiode 101 to the end of transfer of the signal charge to the charge holding unit 103 is an exposure period. Immediately after the signal charge transfer operation is completed, the row transfer pulse φTRi of all rows becomes “L” level, the transfer transistors 102 of all pixels are turned off, and the PD reset pulse φRPDi of all rows is “H”. The photodiode 101 of all pixels is reset.

  Subsequently, the optical signals in each row are read in order from the first row. In the operation period G immediately after the PD reset pulse φRPDi becomes “H” level, the optical signal reading operation in the first row is controlled by the controller 700. Is stopped. Subsequently, in the operation period H, the optical signal in the first row is read out. That is, the row selection pulse φSE1 in the first row becomes “H” level, and the optical signal level corresponding to the signal charge is output from the pixels in the first row to the horizontal signal readout circuit 400 via the column processing circuit 350, Signals are output from the output terminal 410 of the horizontal signal readout circuit 400 in time series in the order of horizontal alignment. The output optical signal in the first row is A / D converted by the ADC 500 and input to the subtractor 620. The subtractor 620 calculates the difference between the optical signal of the first row and the reset signal of the charge holding unit 103 of the first row held in the frame memory 610, and is stored in the photodiode 101 during the exposure period. Only the optical signal component corresponding to the received signal charge is extracted. In this operation, the reset noise of the charge holding unit 103 can be removed, so that a high S / N signal can be obtained. After the optical signal is read, the row selection pulse φSE1 of the first row becomes “L” level.

  In the operation period I following the operation period H, the optical signal in the second row is read out. However, in the present embodiment, since the temporary stop period (operation period D) related to reading of the reset signal in the second row is provided, in the operation period I (second stop period) corresponding to the temporary stop period, the controller Under the control of 700, the optical signal reading operation in the second row is stopped. Subsequently, the optical signal of the second row is read out during the operation period J, and the optical signal of the third row is read out during the operation period K. By stopping the reading operation of the optical signal in the second row in the operation period I, the FD accumulation time Tfd1 in the first row and the FD accumulation time Tfd2 in the second row become the same. Further, since the FD accumulation time Tfd2 in the second row and the FD accumulation time Tfd3 in the third row are the same, the FD accumulation times in all rows are the same.

  As described above, the optical signals of all the pixels are read out, and only the high S / N optical signal components are extracted by taking the difference from the reset signal. An imaging signal composed of an optical signal component is input to an image processing circuit (not shown) and processed, and a final still image can be obtained.

  In the present embodiment, when all the pixels are collectively reset, the PD reset pulse φRPDi of all the pixels simultaneously becomes “H” level or “L” level. In the operation period D immediately after the PD reset pulse φRPDi changes in the reset signal reading period, the reset signal reading operation is stopped under the control of the controller 700. Thereby, it is possible to suppress the reset signal from being affected by the change in the ground level accompanying the collective reset of all the pixels. In addition, since the optical signal reading operation is stopped even in the operation period G immediately after the PD reset pulse φRPDi is changed, it is possible to suppress the optical signal from being affected by the change in the ground level due to the collective reset of all the pixels. it can.

  Further, in the optical signal readout period, the controller 700 stops the optical signal readout operation in the same row as the row in which the reset signal readout operation is temporarily stopped for the same period as the period in which the reset signal readout operation is stopped. To control. With the operation as described above, the FD accumulation time from reading the reset signal to reading the optical signal is the same for all rows. For this reason, variation in the amount of noise included in the image pickup signal can be suppressed, and a step due to noise is less noticeable in the output image.

  Furthermore, by setting the length of the period in which reading of the reset signal and the optical signal is temporarily stopped to an integral multiple of the period of the horizontal synchronization signal HD (1 in the above example), the imaging signal output from the solid-state imaging device Signal processing is simplified. In the present embodiment, the case where the pixels are arranged in 3 rows and 3 columns has been described in a simple manner. However, the present invention is not limited to this, and can be changed without departing from the purpose.

  The configuration when the solid-state imaging device according to the present embodiment is applied to a digital camera (imaging device) will be described below with reference to FIG. A digital camera 10 shown in FIG. 3 includes a lens unit 1, a lens control device 2, a solid-state imaging device 3, a drive circuit 4, a memory 5, a signal processing circuit 6, a recording device 7, a control device 8, and a display device 9.

  The lens unit 1 includes a zoom lens and a focus lens, and forms light from the subject as a subject image on the light receiving surface of the solid-state imaging device 3. The lens control device 2 controls zoom, focus, aperture, and the like of the lens unit 1. The light taken in via the lens unit 1 is imaged on the light receiving surface of the solid-state imaging device 3. The solid-state imaging device 3 converts the subject image formed on the light receiving surface into an image signal and outputs the image signal. On the light receiving surface of the solid-state imaging device 3, a plurality of pixels are two-dimensionally arranged in the row direction and the column direction.

  The drive circuit 4 drives the solid-state imaging device 3 and controls its operation. The memory 5 temporarily stores image data. The signal processing circuit 6 performs a predetermined process on the image signal output from the solid-state imaging device 3. The processing performed by the signal processing circuit 6 includes amplification of an image signal, various corrections of image data, compression of image data, and the like.

  The recording device 7 includes a semiconductor memory for recording or reading image data, and is built in the digital camera 10 in a detachable state. The display device 9 displays a moving image (live view image), displays a still image, displays a moving image and a still image recorded in the recording device 7, displays a state of the digital camera 10, and the like.

  The control device 8 controls the entire digital camera 10. The operation of the control device 8 is defined by a program stored in a ROM built in the digital camera 10. The control device 8 reads this program and performs various controls according to the contents defined by the program.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention. .

  DESCRIPTION OF SYMBOLS 1 ... Lens part, 2 ... Lens control apparatus, 3 ... Solid-state imaging device, 4 ... Drive circuit, 5 ... Memory, 6 ... Signal processing circuit, 7 ... Recording device , 8 ... Control device, 9 ... Display device, 10 ... Digital camera, 100 ... Pixel, 101 ... Photodiode (photoelectric conversion element), 102 ... Transfer transistor (transfer unit) , 103 ... Charge holding unit, 104 ... FD reset transistor (first reset unit), 105 ... Amplifying transistor, 106 ... Selection transistor (reading unit), 107 ... PD reset transistor ( (Second reset unit), 150 ... current source, 200 ... pixel unit, 300 ... vertical scanning circuit (first control unit), 350 ... column processing circuit, 400 ... horizontal signal Readout circuit, 500 ... ADC, 600 ... Noise suppression circuit, 610 ... Frame memory, 620 ... Subtractor, 700 Controller (second controller)

Claims (4)

A photoelectric conversion element, a charge holding unit that holds signal charges accumulated in the photoelectric conversion element, a transfer unit that transfers signal charges accumulated in the photoelectric conversion element to the charge holding unit, and a charge holding unit A first reset unit that resets the held signal charge, a second reset unit that resets the signal charge accumulated in the photoelectric conversion element, and a signal based on the signal charge held in the charge holding unit are read out A pixel unit in which pixels including a readout unit are arranged in a two-dimensional manner;
The charge holding units of all the pixels in the reading target region are collectively reset by the first reset unit, and immediately after the charge holding unit is reset, a reset signal is sequentially read out row by row by the reading unit. The photoelectric conversion elements of all the pixels in the target area are collectively reset by the second reset unit, and after a predetermined time has elapsed from the reset of the photoelectric conversion elements, the photoelectric conversion elements are collectively set in all the pixels in the reading target area. Control for transferring the signal charge from the photoelectric conversion element to the charge holding unit by the transfer unit, and sequentially reading the optical signal for each row by the reading unit after the signal charge is transferred from the photoelectric conversion element to the charge holding unit. A first control unit for performing
In a first period in which the reset signal is sequentially read out for each row by the reading unit, a first stop period based on at least one of timing of start or release of resetting of the photoelectric conversion element by the second reset unit And reading the reset signal by the reading unit in a second period in which the reading unit sequentially reads the optical signal for each row. A second control unit that performs control to provide a second stop period in which reading of the optical signal by the reading unit related to the pixels in the stopped row is temporarily stopped;
A solid-state imaging device.   The solid-state imaging device according to claim 1, wherein the second control unit further performs control so that the lengths of the first stop period and the second stop period are the same.   The second control unit further controls the length of the period from the reading of the reset signal by the reading unit to the reading of the optical signal by the reading unit to be the same for all the pixels in the reading target region. The solid-state imaging device according to claim 1, wherein:   The imaging device which has a solid-state imaging device as described in any one of Claims 1-3.

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