JP2012175259A - Solid state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image pickup device capable of reducing the influence of noise due to leakage of a signal charge to a charge holding unit.SOLUTION: A photoelectric conversion unit PD forms a signal charge based on incident light, where a global shutter operation exposes all pixels in a predetermined region at the same time. A charge holding unit FD holds the signal charge formed in the photoelectric conversion unit PD. A transfer transistor Mt transfers the signal charge from the photoelectric conversion unit PD to the charge holding unit FD. A correction dummy DM holds a noise charge generated corresponding to light quantity incident on the photoelectric conversion unit PD. An amplifier transistor Ma amplifies a signal based on the signal charge held by the charge holding unit FD and outputs the signal as an optical signal, and amplifies a signal based on the noise charge held by the correction dummy DM and outputs the signal as a noise signal. The optical signal and the noise signal are used to perform an operation for removing the noise signal from the optical signal.

Description

  The present invention relates to a solid-state imaging device capable of a global shutter operation in which exposure is performed simultaneously on all pixels in a predetermined region.

  An imaging device (solid-state imaging device) that converts an optical image into an electrical signal is mounted on an imaging device such as a digital camera or a digital video camera. In recent years, the market share of this image sensor is shifting from CCD to CMOS. A general MOS type image pickup device such as a CMOS mounted on an image pickup apparatus sequentially reads out charges accumulated in a plurality of pixels arranged two-dimensionally on the image pickup surface. Then, the exposure start time and the exposure end time are different for each pixel (or for each line), and the image is distorted.

  Therefore, there is provided a MOS type image pickup device that is configured so that the exposure start time of all the pixels can be made the same and the exposure end time of all the pixels can be made the same (that is, control by a global shutter is possible). is there. This MOS type imaging device includes a photoelectric conversion unit such as a photodiode that generates charges according to the exposure amount, and also includes a charge holding unit that temporarily holds signal charges generated in the photoelectric conversion unit, transfer of charges, A transistor or the like that functions as a switch when resetting is provided.

  FIG. 10 shows an example of a pixel configuration of such an image sensor. As shown in FIG. 10, five transistors (Mf, Mt, Mr, Ma, Ms) are provided in one pixel. For example, MOS transistors are used as these transistors.

  The photoelectric conversion unit PD is, for example, a photodiode, and generates a signal charge based on incident light. The charge holding unit FD temporarily holds the signal charge generated by the photoelectric conversion unit PD. The transfer transistor Mt transfers the signal charge generated by the photoelectric conversion unit PD to the charge holding unit FD based on a transfer pulse TX given from a vertical control circuit (not shown). The amplification transistor Ma amplifies a signal based on the signal charge held in the charge holding unit FD, and outputs the amplified signal to the vertical signal line ReadBus via the selection transistor Ms. Here, an example of a source follower circuit including a current source (not shown) and an amplification transistor Ma connected to the vertical signal line ReadBus is shown. The charge holding unit FD is connected to the input unit of the amplification transistor Ma.

  The selection transistor Ms outputs a signal from the amplification transistor Ma to the vertical signal line ReadBus based on the selection pulse SEL given from the vertical control circuit. By turning on the selection transistor Ms with the selection pulse SEL, it is possible to select each pixel and read a signal from each pixel. The reset transistor Mr is connected to a voltage source that supplies a reference voltage VAA_PIX, and resets the potential of the charge holding unit FD based on a reset pulse RST supplied from the vertical control circuit. The PD reset transistor Mf is connected to a voltage source that supplies the reference voltage VAA_GS, and resets the potential of the photoelectric conversion unit PD based on a PD reset pulse FT supplied from the vertical control circuit.

With the configuration shown in FIG. 10, control by a global shutter is possible using the charge holding unit FD as an in-pixel memory. For example, Patent Document 1 discloses a technique for driving an image sensor and its peripheral circuits in the following sequence to suppress KTC noise (reset noise) when the image sensor is used in a digital camera. .
(1) The signal charge accumulated in the charge holding unit FD is reset, and the reset signal is sequentially scanned and read for each line and stored.
(2) The signal charges generated in the photoelectric conversion units PD of all the pixels are collectively reset, and after a predetermined exposure time has elapsed, the signal charges of the photoelectric conversion units PD are collectively transferred to the charge holding unit FD.
(3) The optical signal based on the signal charge transferred to the charge holding unit FD is sequentially scanned and read for each line, and the reset signal stored in (1) is subtracted from the optical signal (the optical signal and the reset signal Take the difference).

JP 2005-65184 A

  When the imaging device is driven in the sequence as described above, the charge holding unit FD is used for at least one frame period from immediately after reading a reset signal for removing fixed pattern noise and reset noise until reading an optical signal. Becomes a state in which the signal charge is held. Therefore, when strong light is irradiated onto the photoelectric conversion unit PD during that period, signal charges due to stray light corresponding to the amount of incident light or signal charges overflowing from the photoelectric conversion unit PD leak into the charge holding unit FD. In some cases, the noise charge is superimposed on the signal charge, and the image quality deteriorates.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a solid-state imaging device capable of reducing the influence of noise due to leakage of signal charges into the charge holding unit.

  The present invention has been made to solve the above-described problem, and includes a photoelectric conversion unit that generates a signal charge based on incident light, a charge holding unit that holds a signal charge generated by the photoelectric conversion unit, A transfer unit that transfers signal charges from the photoelectric conversion unit to the charge holding unit, a noise holding unit that holds noise charges generated according to the amount of light incident on the photoelectric conversion unit, and held by the charge holding unit A pixel including an amplification unit that amplifies a signal based on the signal charge and outputs it as an optical signal, amplifies the signal based on the noise charge held in the noise holding unit and outputs the signal as a noise signal, and arranged in a two-dimensional manner A pixel unit, a control unit that controls exposure in the pixel so as to perform a global shutter operation that simultaneously performs exposure in all the pixels in a predetermined region, and the optical signal and the noise signal. There are a solid-state imaging apparatus characterized by comprising a, a calculation section that performs calculation for removing the noise signal from the optical signal.

  In the solid-state imaging device of the present invention, the arithmetic unit subtracts a signal obtained by multiplying the noise signal by a predetermined coefficient from the optical signal.

  In the solid-state imaging device of the present invention, the coefficient is a coefficient corresponding to the position of the pixel arranged in a two-dimensional manner.

  The solid-state imaging device of the present invention includes a first switch that connects the charge holding unit, the transfer unit, and the input unit of the amplification unit, the noise holding unit, the transfer unit, and the input unit of the amplification unit. And a second switch for connecting the two to each other.

  In the solid-state imaging device of the present invention, the control unit turns on the first switch and the second switch to reset the charge holding unit and the noise holding unit, A second step of turning off the second switch and outputting a reset signal from the pixel; a third step of collectively resetting the photoelectric conversion unit in all pixels in the predetermined region; and an exposure period After the elapse of time, a fourth step of transferring the signal charge from the photoelectric conversion unit to the charge holding unit via the transfer unit collectively in all the pixels, and a step of outputting the optical signal from the pixel. And a sixth step of turning off the first switch and turning on the second switch to output the noise signal from the pixel. And wherein the door.

  The solid-state imaging device of the present invention further includes a second transfer unit that transfers signal charges from the charge holding unit to the noise holding unit, and the noise holding unit is connected to an input side of the amplification unit. It is characterized by a capacity.

  In the solid-state imaging device according to the aspect of the invention, the control unit may collectively reset the photoelectric conversion unit for all the pixels in the predetermined region, and the charge for all the pixels. A second step of resetting the holding unit and the noise holding unit; and after the exposure period has elapsed, the signal charge is transferred from the photoelectric conversion unit to the charge holding unit via the transfer unit in a batch at all the pixels. A third step of outputting the noise signal, a fourth step of outputting the noise signal from the pixel, a fifth step of resetting the noise holding unit and outputting a reset signal from the pixel, and the charge holding unit And a sixth step of transferring the signal charge from the pixel to the noise holding unit via the second transfer unit and outputting the optical signal from the pixel. Using the signal and the noise signal and the reset signal, and performs the operation for removing the noise signal from the optical signal.

  In the solid-state imaging device of the present invention, the planar arrangement of the photoelectric conversion unit, the charge holding unit, and the noise holding unit in the pixel is an axis with respect to an optical axis of a lens that allows light to enter the pixel unit. It is symmetric.

  According to the present invention, the signal charge to the charge holding unit is obtained by performing an operation of removing the noise signal based on the noise charge held in the noise holding unit from the optical signal based on the signal charge held in the charge holding unit. It is possible to reduce the influence of noise due to leakage.

It is a block diagram which shows the structure of the imaging device by each embodiment of this invention. It is a block diagram which shows the structure of the imaging part in the 1st Embodiment of this invention. FIG. 2 is a circuit diagram illustrating a configuration of a pixel in the first embodiment of the present invention. It is a timing chart which shows the global shutter operation | movement in the 1st Embodiment of this invention. 3 is a timing chart showing pixel drive timing in the first embodiment of the present invention. It is a block diagram which shows the structure of the imaging part in the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the pixel in the 2nd Embodiment of this invention. 6 is a timing chart illustrating pixel drive timings according to a second embodiment of the present invention. It is a reference diagram showing a layout of a pixel in the third embodiment of the present invention. It is a circuit diagram which shows the structure of the conventional pixel.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of an imaging apparatus used for the description of each embodiment below. An imaging apparatus shown in FIG. 1 includes a lens 1, an imaging unit 2, an image processing unit 3, a display unit 4, a drive control unit 5, a lens control unit 6, a camera control unit 7, and a camera operation unit 8. And. Although the memory card 9 is also shown in FIG. 1, the memory card 9 may be configured not to be unique to the imaging apparatus by configuring the memory card 9 to be detachable from the imaging apparatus.

  The lens 1 is a photographic lens for forming an optical image of a subject on an imaging surface of an imaging unit 2 constituting an imaging element (solid-state imaging device). The imaging unit 2 converts the optical image of the subject formed by the lens 1 into a digital image signal by photoelectric conversion and outputs the digital image signal. The image processing unit 3 performs various digital image processing on the image signal output from the imaging unit 2. The image processing unit 3 includes a first image processing unit 3a that processes an image signal for recording, and a second image processing unit 3b that processes the image signal for display.

  The display unit 4 displays an image based on the image signal subjected to image processing for display by the second image processing unit 3b of the image processing unit 3. The display unit 4 can reproduce and display a still image, and can perform a moving image (live view) display that displays an image in a captured range in real time. The drive control unit 5 controls the operation of the imaging unit 2 based on an instruction from the camera control unit 7. The lens control unit 6 controls the aperture and focal position of the lens 1 based on an instruction from the camera control unit 7.

  The camera control unit 7 controls the entire imaging apparatus. The camera operation unit 8 includes various members for operation for the user to perform various operation inputs to the imaging apparatus, and outputs a signal based on the result of the operation input to the camera control unit 7. As a specific example of the camera operation unit 8, a power switch for turning on and off the imaging apparatus, a release button for instructing still image shooting, and a still image shooting mode are switched between a single shooting mode and a continuous shooting mode. For example, a still image shooting mode switch. The memory card 9 is a recording medium for storing the image signal processed for recording by the first image processing unit 3a.

(First embodiment)
First, a first embodiment of the present invention will be described. FIG. 2 shows a configuration of the imaging unit 2 in the first embodiment. The imaging unit 2 includes an imaging device 21 that is a MOS solid-state imaging device, an AD conversion unit 22, and a noise removal unit 23.

  The image sensor 21 includes a pixel unit 24, a column processing circuit unit 25, a vertical control circuit 26 (control unit), and a horizontal scanning circuit 27. The column processing circuit unit 25 includes a noise calculation unit 25a (calculation unit). ). The image sensor 21 can operate in a global shutter mode in which the pixel accumulation operation (exposure operation) is controlled collectively for all pixels. Note that the image sensor 21 may be able to operate in a rolling shutter mode in which pixel accumulation operation is controlled for each row.

  The pixel unit 24 is configured by two-dimensionally arranging a plurality of pixels 28 in the row direction and the column direction. The vertical control circuit 26 applies a signal for controlling the operation of the pixel in units of rows to the pixels 28 of the pixel unit 24 to control the reset operation, the accumulation operation, the signal readout operation, and the like of the pixels 28. Pixel signals are output from the pixels 28 in the row selected by the vertical control circuit 26 to the vertical signal line ReadBus (see FIG. 3) provided for each column.

  The column processing circuit unit 25 processes the pixel signal output to the vertical signal line ReadBus for each column. For example, the column processing circuit unit 25 performs an amplification operation and removes noise when the image pickup device 21 is operated as a rolling shutter. CDS processing is performed. The horizontal scanning circuit 27 outputs the pixel signals output from the column processing circuit unit 25 as image signals in time series in the order of arrangement in the horizontal direction.

  The AD conversion unit 22 performs AD conversion for converting an analog image signal output from the image sensor 21 into a digital image signal. When the column processing circuit unit 25 has an AD conversion circuit, the AD conversion unit 22 is not necessary. The noise removal unit 23 performs noise removal processing on the digital image signal output from the AD conversion unit 22 when the image sensor 21 performs a global shutter operation. The noise removing unit 23 includes a memory for storing an image signal.

  FIG. 3 shows the configuration of the pixel 28 in the first embodiment. The photoelectric conversion unit PD is, for example, a photodiode, and generates a signal charge based on incident light. The charge holding unit FD temporarily holds the signal charge generated by the photoelectric conversion unit PD. The correction dummy DM (noise holding unit) holds a noise charge equivalent to the noise component superimposed on the signal charge of the charge holding unit FD according to the amount of incident light. The charge holding unit FD is connected to the transfer transistor Mt (transfer unit) and the input unit (gate terminal) of the amplification transistor Ma via the switch SW1 (first switch), and the correction dummy DM is connected to the switch SW2 (second switch). To the input section (gate terminal) of the transfer transistor Mt and the amplification transistor Ma.

  The transfer transistor Mt transfers the signal charge generated by the photoelectric conversion unit PD to the charge holding unit FD based on the transfer pulse TX supplied from the vertical control circuit 26. The amplification transistor Ma amplifies a signal based on the signal charge held in the charge holding unit FD, and outputs a reset signal or an optical signal to the vertical signal line ReadBus via the selection transistor Ms. The amplification transistor Ma amplifies a signal based on the signal charge held in the correction dummy DM, and outputs a noise signal to the vertical signal line ReadBus via the selection transistor Ms. Here, an example of a source follower circuit including a current source (not shown) and an amplification transistor Ma connected to the vertical signal line ReadBus is shown.

  The selection transistor Ms outputs a signal from the amplification transistor Ma to the vertical signal line ReadBus based on the selection pulse SEL provided from the vertical control circuit 26. By turning on the selection transistor Ms with the selection pulse SEL, it is possible to select each pixel 28 and read a signal from each pixel 28. The reset transistor Mr is connected to a voltage source that supplies the reference voltage VAA_PIX, and resets the potential of the charge holding unit FD based on the reset pulse RST supplied from the vertical control circuit 26. The PD reset transistor Mf is connected to a voltage source that supplies the reference voltage VAA_GS, and resets the potential of the photoelectric conversion unit PD based on the PD reset pulse FT supplied from the vertical control circuit 26.

  The switch SW1 is controlled to be turned on / off based on a control pulse P1 given from the vertical control circuit 26. The switch SW2 is controlled to be turned on / off based on a control pulse P2 provided from the vertical control circuit 26. For example, MOS transistors are used as the switches SW1 and SW2.

  In the present embodiment, an area including all the pixels 28 included in the image sensor 21 is a pixel signal readout target area. However, a part of an area including all the pixels 28 included in the image sensor 21 is defined as a readout target area. The pixel signal described in (1) may be read out.

  Next, the operation of the imaging unit 2 will be described. The imaging device 21 can perform a global shutter operation, and the operation of the imaging unit 2 when the imaging device 21 performs the global shutter operation will be described.

  FIG. 4 shows the global shutter operation. The horizontal axis in FIG. 4 indicates time. A broken line DL1 and a solid line SL1 indicate pixel signal readout timing for each row. FIG. 4 shows the timing at which all the pixels are simultaneously applied to the transfer pulse TX and the PD reset pulse FT. FIG. 4 also shows an output signal of the horizontal scanning circuit 27.

  First, in the reset signal readout period, reset signals are read out in units of rows in order from the pixels 28. When the reset signal is read out from the pixel 28 in the first row and the reset signal is read out from the pixel 28 in the n-th row which is the last row, the reset signal readout period ends. Subsequently, exposure (optical signal accumulation) is simultaneously started in all the pixels 28, and after a predetermined exposure period has elapsed, exposure (optical signal accumulation) is simultaneously completed in all the pixels 28. In the optical signal readout period after the exposure (optical signal accumulation) is completed, the optical signals are read out in units of rows in order from the pixels 28. When the readout of the optical signal is started from the pixel 28 in the first row and the optical signal is read out from the pixel 28 in the n-th row which is the final row, the optical signal readout period ends.

  FIG. 5 shows the drive timing of the pixels 28 in the first row as an example. FIG. 5 shows each signal output from the vertical control circuit 26 and the signal level V_ReadBus of the vertical signal line ReadBus. In the reset signal readout period before exposure (optical signal accumulation) by the global shutter operation, readout of the reset level of the charge holding unit FD and reset operation of the correction dummy DM are performed. Hereinafter, the reset signal readout period will be divided into periods T1, T2, and T3, and the operation of the pixels 28 in the first row will be mainly described.

  In the period T1 (first step), the reset pulse RST is applied to the reset transistor Mr, and the control pulse P1 and the control pulse P2 are applied to the switch SW1 and the switch SW2, respectively. As a result, the reset transistor Mr, the switch SW1, and the switch SW2 are turned on, the charge holding unit FD is reset via the reset transistor Mr and the switch SW1, and the correction dummy DM is reset via the reset transistor Mr and the switch SW2. Reset. Further, the selection pulse SEL is applied to the selection transistor Ms, and the selection transistor Ms is turned on.

  In the period T2 (second step), the application of the control pulse P2 to the switch SW2 is canceled and the switch SW2 is turned off. Since the switch SW1 and the selection transistor Ms are on, a reset signal based on the reset potential of the charge holding unit FD is output to the vertical signal line ReadBus. The reset signal output to the vertical signal line ReadBus is output to the noise removal unit 23 via the column processing circuit unit 25, the horizontal scanning circuit 27, and the AD conversion unit 22, and is stored in the noise removal unit 23.

  After the reading of the reset signal is completed, the application of the selection pulse SEL to the selection transistor Ms is released, and the selection transistor Ms is turned off. Such an operation is performed from the first row to the n-th row (final row) of the pixel unit 24.

  In the period T3 (third step), the PD reset pulse FT is simultaneously applied to the PD reset transistors Mf of all the pixels 28, and the PD reset transistors Mf are simultaneously turned on. Thereby, the photoelectric conversion parts PD of all the pixels 28 are collectively reset. Thereafter, the application of the PD reset pulse FT to the PD reset transistors Mf of all the pixels 28 is simultaneously canceled and the PD reset transistors Mf are simultaneously turned off, so that exposure (accumulation) is started in all the pixels 28 at once. Is done.

  In the following description, the optical signal readout period after the end of the exposure period is divided into periods T5, T6, and T7, and the operation of the pixels 28 in the first row will be mainly described. After an arbitrary exposure period (period T4) has elapsed since the start of exposure, in period T5 (fourth step), the transfer pulse TX is simultaneously applied to the transfer transistors Mt of all the pixels 28, and the transfer transistors Mt are turned on. It turns on at the same time. Further, the switch SW1 remains on. Thereby, the signal charges accumulated in the photoelectric conversion unit PD during the exposure period are collectively transferred to the charge holding unit FD. That is, the exposure of all the pixels 28 is completed simultaneously.

  In the period T6 (fifth step), the selection pulse SEL is applied to the selection transistor Ms, and the selection transistor Ms is turned on. Since the switch SW1 and the selection transistor Ms are on, an optical signal based on the potential of the charge holding unit FD after the signal charge is transferred from the photoelectric conversion unit PD is output to the vertical signal line ReadBus, and the column processing circuit unit 25 It is sampled and stored as signal V1.

  In the period T7 (sixth step), the application of the control pulse P1 to the switch SW1 is canceled and the switch SW1 is turned off, while the control pulse P2 is applied to the switch SW2 and the switch SW2 is turned on. As a result, a noise signal based on the potential of the correction dummy DM is output to the vertical signal line ReadBus, and is sampled and stored as the signal V2 by the column processing circuit unit 25.

  Here, the signal V1 stored in the column processing circuit unit 25 corresponds to the sum of the signal component ΔVs and the noise component ΔVn1 due to the signal charge leaking into the charge holding unit FD. The signal V2 corresponds to a noise component ΔVn2 due to noise charges accumulated in the correction dummy DM. Therefore, assuming that the noise charge accumulated in the charge holding unit is equal to the noise charge accumulated in the correction dummy DM, ΔVn1 = ΔVn2, and the charge holding unit FD is calculated by calculating the difference between the signal V2 and the signal V1. Thus, an optical signal from which noise due to the signal charge leaking into the light is removed is detected.

  The noise calculation unit 25a of the column processing circuit unit 25 performs the above calculation and outputs an optical signal after the calculation. Note that reset noise is superimposed on this optical signal. The optical signal output from the column processing circuit unit 25 is output to the noise removal unit 23 via the horizontal scanning circuit 27 and the AD conversion unit 22. The noise removal unit 23 generates an image signal from which the reset noise is removed by taking a difference between the stored reset signal and the optical signal processed by the noise calculation unit 25a of the column processing circuit unit 25. The image signal processed by the noise removing unit 23 is output from the imaging unit 2 to the image processing unit 3.

  After the reading of the optical signal is completed, the application of the control pulse P2 to the switch SW2 is released and the switch SW2 is turned off. Further, the application of the selection pulse SEL to the selection transistor Ms is released, and the selection transistor Ms is turned off. Such an operation is performed from the first row to the n-th row (final row) of the pixel portion 24 as in the reset readout.

  In this embodiment, ΔVn1 = ΔVn2 is set. However, due to circuit layout restrictions, the charge holding unit FD and the correction dummy DM may have different capacities, or the charge holding unit FD and the correction dummy DM may vary due to fluctuations in manufacturing conditions. There may be a case where variations in capacitance occur. For this reason, it is necessary to multiply the noise component ΔVn2 by a predetermined coefficient in order to correct the gain. In this case, in the noise calculation unit 25a of the column processing circuit unit 25, the noise due to the signal charge leaking into the charge holding unit FD is removed by taking the difference between αΔVn2 obtained by multiplying the noise component ΔVn2 by the coefficient α and the signal V1. An optical signal can be obtained.

  Further, since the incident angle of light increases as the pixel position moves away from the optical axis of the lens 1 due to the aberration of the lens 1, the amount of stray light that causes noise increases. As a result, as the distance from the optical axis increases, it is necessary to increase the noise coefficient α of each pixel 28 in proportion to the distance from the optical axis. The layout is not limited to this.

  As described above, according to the present embodiment, by performing an operation of removing the noise signal based on the noise charge held in the correction dummy DM from the optical signal based on the signal charge held in the charge holding unit FD. In addition, it is possible to reduce the influence of noise due to leakage of signal charges into the charge holding portion FD. Therefore, even when shooting a subject with strong light, it is possible to eliminate noise due to light leakage, and to shoot high-quality images without distortion using a global shutter type MOS solid-state imaging device. Can be done.

  Further, by multiplying the noise signal by a predetermined coefficient α and then subtracting it from the optical signal, the noise component superimposed on the optical signal and the noise component included in the noise signal are converted into the charge holding unit FD and the correction dummy. Even in the case where it differs depending on the capacity ratio with DM, the noise signal can be accurately removed from the optical signal, and a high-quality optical signal can be detected.

  Further, by setting the predetermined coefficient α to a coefficient corresponding to the pixel position, it is possible to accurately remove the noise signal from the optical signal regardless of the pixel position, and to detect a high-quality optical signal.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 6 shows a configuration of the imaging unit 2 in the second embodiment. The configuration of the imaging unit 2 in the second embodiment is a configuration obtained by removing the noise removing unit 23 from the configuration of the imaging unit 2 (FIG. 2) shown in the first embodiment. Omitted.

  FIG. 7 shows a configuration of the pixel 28 in the second embodiment. When the configuration of the pixel 28 in the second embodiment is compared with the configuration of the pixel 28 in the first embodiment, a charge holding unit FD1 is provided instead of the correction dummy DM. Further, a transfer transistor Mt1 (second transfer unit) connected to the input portions of the transfer transistor Mt and the amplification transistor Ma is provided. The charge holding unit FD is directly connected to the transfer transistor Mt and the transfer transistor Mt1, and the charge holding unit FD1 is directly connected to the transfer transistor Mt1 and the amplification transistor Ma.

  The image sensor 21 in the present embodiment can also perform a global shutter operation, and the operation will be described with reference to FIG. FIG. 8 shows the drive timing of the pixel 28 in this embodiment. FIG. 8 shows each signal output from the vertical control circuit 26, the potential Vfd of the charge holding unit FD, and the potential Vfd1 of the charge holding unit FD1.

  As in the first embodiment, the application of the PD reset pulse FT and the transfer pulse TX is performed at once for all the pixels 28. The PD reset pulse FT applied collectively at all the pixels 28 is expressed as FT (1... N), and the transfer pulse TX applied collectively at all the pixels 28 is TX (1... N). It expresses. Note that a reset pulse RST, a transfer pulse TX1, and a selection pulse SEL applied to an arbitrary m-th row of pixels 28 are represented as RST (m), TX1 (m), and SEL (m), respectively, and an arbitrary m + 1-th row. The reset pulse RST, transfer pulse TX1, and selection pulse SEL applied to the pixel 28 are represented as RST (m + 1), TX1 (m + 1), and SEL (m + 1), respectively.

  In the period T1 (first step) before the exposure period, the PD reset pulse FT is simultaneously applied to the PD reset transistors Mf of all the pixels 28, and the PD reset transistors Mf are simultaneously turned on. Thereby, the photoelectric conversion parts PD of all the pixels 28 are collectively reset. Thereafter, the application of the PD reset pulse FT to the PD reset transistors Mf of all the pixels 28 is simultaneously canceled and the PD reset transistors Mf are simultaneously turned off, so that exposure (accumulation) is started in all the pixels 28 at once. Is done.

  Hereinafter, the operation of the pixel 28 will be described by dividing the exposure period into periods T2, T3, and T4. In a period T2 (second step) after the elapse of a predetermined period from the start of exposure, the reset pulse RST is applied to the reset transistors Mr of all the pixels 28 and the transfer pulse TX1 is applied to the transfer transistors Mt1. Is done. Accordingly, the reset transistor Mr and the transfer transistor Mt1 are turned on, the charge holding unit FD1 is reset via the reset transistor Mr, and the charge holding unit FD is reset via the reset transistor Mr and the transfer transistor Mt1.

  In the subsequent period T3, the application of all the pixels 28 to the transfer transistors Mt1 is released and the transfer transistors Mt1 are turned off. In the period T4, the application of the reset pulse RST to the reset transistors Mr of all the pixels 28 is released and reset. The transistor Mr is turned off.

  Hereinafter, the operation of the pixel 28 will be described by dividing the optical signal readout period after the exposure period into periods T5, T6, T7, and T8. In the period T5 (third step), the transfer pulse TX is simultaneously applied to the transfer transistors Mt of all the pixels 28, and the transfer transistors Mt are simultaneously turned on. Thereby, the signal charges accumulated in the photoelectric conversion unit PD during the exposure period are collectively transferred to the charge holding unit FD. That is, the exposure of all the pixels 28 is completed simultaneously.

  In a period T6 (fourth step) after a period T5 corresponding to the row position has elapsed after the exposure period ends, the selection pulse SEL is applied to the selection transistor Ms of the pixel 28 in the m-th row, and the selection transistor Ms is turned on. Thus, a noise signal based on the potential of the charge holding unit FD1 of the pixel 28 in the m-th row is output to the vertical signal line ReadBus, and is sampled and stored as the signal V1 by the column processing circuit unit 25.

  In a period T7 (fifth step), a reset pulse is applied to the reset transistor Mr of the pixel 28 in the m-th row, and the reset transistor Mr is turned on. As a result, the charge holding unit FD1 of the pixel 28 in the m-th row is reset, a reset signal based on the reset potential of the charge holding unit FD1 is output to the vertical signal line ReadBus, and is sampled as the signal V2 by the column processing circuit unit 25. And memorized. Subsequently, the application of the reset pulse RST to the reset transistor Mr of the pixel 28 in the m-th row is released, and the reset transistor RST is turned off.

  In the period T8 (sixth step), the transfer pulse TX1 is applied to the transfer transistor Mt1 of the pixel 28 in the m-th row, and the transfer transistor Mt1 is turned on. As a result, the signal charge held in the charge holding unit FD is transferred to the charge holding unit FD1. Since the selection transistor Ms is on, an optical signal based on the potential of the charge holding unit FD1 is output to the vertical signal line ReadBus, and is sampled and stored as the signal V3 by the column processing circuit unit 25.

  Subsequently, the same operation as described above in the periods T6, T7, and T8 is performed on the pixels 28 in the (m + 1) th row. That is, in the periods T6, T7, and T8, the signals V1, V2, and V3 are sequentially read from the pixel 28 in the first row to the pixel 28 in the n-th row (final row).

Next, signal processing related to noise removal performed by the noise calculation unit 25a of the column processing circuit unit 25 in the present embodiment will be described. In the column processing circuit unit 25 of the present embodiment, sampling of the pixel signal is performed three times for the signal V1 (noise signal), the signal V2 (reset signal), and the signal V3 (optical signal). The calculation formula is shown below.
(V2-V3) -α (V2-V1) (A)
α: Ratio of noise components accumulated in the charge holding unit FD and the charge holding unit FD

  Noise components generated until a signal based on the signal charge of the charge holding unit FD is read out are accumulated in both the charge holding unit FD and the charge holding unit FD1. If the noise component accumulated in the charge holding unit FD is ΔVn1 and the noise component accumulated in the charge holding unit FD1 is ΔV2, ΔVn1 = αΔVn2.

  (V2−V3) in the equation (A) corresponds to the sum of the noise component ΔVn1 accumulated in the charge holding unit FD and the signal charge generated by the photoelectric conversion unit PD, and (V2−V3) in the equation (A). V1) corresponds to the noise component ΔVn2 accumulated in the charge holding unit FD1. Therefore, the optical signal from which the noise component is removed is obtained by the equation (A). When the noise components accumulated in the charge holding unit FD and the charge holding unit FD1 are equal, α = 1, and the expression (A) is simplified to V1-V3.

  The noise calculation unit 25a performs calculation according to the equation (A) and outputs the calculated optical signal. The optical signal output from the column processing circuit unit 25 is output to the image processing unit 3 as an image signal via the horizontal scanning circuit 27 and the AD conversion unit 22.

  As described above, according to the present embodiment, from the optical signal based on the signal charge held in the charge holding unit FD and then held in the charge holding unit FD1, based on the noise charge held in the charge holding unit FD1. By performing the calculation for removing the noise signal, it is possible to reduce the influence of noise due to leakage of the signal charge into the charge holding unit FD. Therefore, even when shooting a subject with strong light, it is possible to eliminate noise due to light leakage, and to shoot high-quality images without distortion using a global shutter type MOS solid-state imaging device. Can be done.

  In addition, although seven transistors are used in the pixel 28 in the first embodiment, six transistors are used in the pixel 28 in the second embodiment. For example, the circuit scale can be reduced as compared with the pixel 28 in the first embodiment.

(Third embodiment)
Next, a third embodiment of the present invention will be described. In the conventional image sensor, the layout of the pixel portion is the same regardless of the position. In the present embodiment, a method of using the pixels 28 of the first embodiment and optimizing the layout of the four pixels 28 located at the ends of the pixel unit 24 according to the respective positions will be described.

  FIG. 9 shows an outline of a planar layout of the pixel 28 in the present embodiment. Here, as an example, (a) the upper left pixel, (b) the lower left pixel, (c) the upper right pixel, and (d) the lower right pixel of the pixel unit 24 in which the pixels 28 are arranged in a 4 × 4 matrix. The layout is extracted and shown.

  (A) The correction dummy DM in the upper left pixel is arranged on the left side of the charge holding unit FD arranged under the photoelectric conversion unit PD. (B) The correction dummy DM in the lower left pixel is arranged on the left side of the charge holding unit FD arranged on the photoelectric conversion unit PD. (C) The correction dummy DM in the upper right end pixel is arranged on the right side of the charge holding unit FD arranged under the photoelectric conversion unit PD. (D) The correction dummy DM in the lower right pixel is arranged on the right side of the charge holding unit FD arranged on the photoelectric conversion unit PD. The arrangement of each component in the pixel 28 at each of the four end portions is an axis object with respect to the optical axis L of the lens 1 that causes light to enter the pixel portion 24. The optical axis L is assumed to be parallel to the direction perpendicular to the paper surface in FIG. 9 (that is, the direction perpendicular to the imaging surface on which the pixels 28 are arranged).

  Depending on the aberration of the lens 1, the incident angle of light incident on the pixel 28 varies depending on the distance from the optical axis L, and the amount of light varies depending on the incident angle of light. When the coefficient α described in the first embodiment is set to a coefficient corresponding to the distance of the pixel 28 from the optical axis L, the layout arrangement of the pixel 28 is set to the layout arrangement of the present embodiment, so that The distances of the photoelectric conversion units PD from the optical axis L are equal, the distances of the charge holding units FD from the optical axis L are equal, and the correction dummy DM from the optical axis L is between the pixels 28 having the same distance. The distances are equal. Therefore, even when the same coefficient α is set between the plurality of pixels 28 having the same distance from the optical axis L, it is possible to reduce the influence of different incident light depending on the pixel position.

  In the present embodiment, the pixel at the end of the pixel unit 24 is shown as an example. However, in actuality, the layout is changed gradually according to the distance of each pixel 28 from the optical axis L, or the pixel unit 24 is changed. It may be divided into a plurality of blocks, and the layout may be changed in units of blocks according to the distance from the optical axis L of each block. In the present embodiment, the application to the pixel 28 of the first embodiment has been described. However, the application to the pixel 28 of the second embodiment may be similarly performed.

  As described above, according to the present embodiment, the positional relationship among the photoelectric conversion unit PD that receives light, the charge holding unit FD that stores optical signals, and the correction dummy DM that stores noise components is optimized. As a result, it is possible to reduce the influence of different incident light depending on the position of the pixel 28 in the pixel portion 24. For this reason, it is possible to reduce the calculation in the noise calculation unit 25a, and as a result, it is possible to provide comfortable shooting for the user as the entire camera system.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention. .

  DESCRIPTION OF SYMBOLS 1 ... Lens, 2 ... Imaging part, 3 ... Image processing part, 3a ... 1st image processing part, 3b ... 2nd image processing part, 4 ... Display part, 5. ..Drive control unit, 6 ... Lens control unit, 7 ... Camera control unit, 8 ... Camera operation unit, 21 ... Image sensor, 22 ... AD conversion unit, 23 ... Noise Removal unit, 24 ... pixel unit, 25 ... column processing circuit unit, 25a ... noise calculation unit, 26 ... vertical control circuit, 27 ... horizontal scanning circuit, PD ... photoelectric conversion unit , FD, FD1 ... charge holding unit, DM ... correction dummy, Mf ... PD reset transistor, Mt, Mt1 ... transfer transistor, Mr ... reset transistor, Ma ... amplification transistor, Ms ... selection transistor, SW1, SW2 ... switch

Claims (8)

A photoelectric conversion unit that generates a signal charge based on incident light; and
A charge holding unit for holding the signal charge generated by the photoelectric conversion unit;
A transfer unit that transfers signal charges from the photoelectric conversion unit to the charge holding unit;
A noise holding unit for holding noise charges generated according to the amount of light incident on the photoelectric conversion unit;
An amplification unit that amplifies a signal based on the signal charge held in the charge holding unit and outputs it as an optical signal, amplifies a signal based on the noise charge held in the noise holding unit, and outputs the amplified signal
A pixel portion in which pixels including are two-dimensionally arranged;
A control unit that controls exposure in the pixels so as to perform a global shutter operation that simultaneously performs exposure in all the pixels in a predetermined region;
An arithmetic unit that performs an operation of removing the noise signal from the optical signal using the optical signal and the noise signal;
A solid-state imaging device comprising:   The solid-state imaging device according to claim 1, wherein the arithmetic unit subtracts a signal obtained by multiplying the noise signal by a predetermined coefficient from the optical signal.   The solid-state imaging device according to claim 2, wherein the coefficient is a coefficient corresponding to a position of the pixel arranged two-dimensionally. A first switch connecting the charge holding unit, the transfer unit, and the input unit of the amplification unit;
A second switch connecting the noise holding unit, the transfer unit, and the input unit of the amplification unit;
The solid-state imaging device according to claim 1, further comprising: The controller is
A first step of turning on the first switch and the second switch to reset the charge holding unit and the noise holding unit;
A second step of turning off the second switch and outputting a reset signal from the pixel;
A third step of collectively resetting the photoelectric conversion unit in all the pixels in the predetermined region;
A fourth step of transferring signal charges from the photoelectric conversion unit to the charge holding unit via the transfer unit in a lump for all the pixels after the exposure period has passed;
A fifth step of outputting the optical signal from the pixel;
A sixth step of turning off the first switch and turning on the second switch to output the noise signal from the pixel;
The solid-state imaging device according to claim 4, wherein control is performed. A second transfer unit that transfers a signal charge from the charge holding unit to the noise holding unit;
The solid-state imaging device according to claim 1, wherein the noise holding unit is a capacitor connected to an input side of the amplification unit. The controller is
A first step of collectively resetting the photoelectric conversion unit in all pixels in the predetermined region;
A second step of collectively resetting the charge holding unit and the noise holding unit in all the pixels;
A third step of transferring signal charges from the photoelectric conversion unit to the charge holding unit via the transfer unit in a lump in all the pixels after the exposure period has elapsed;
A fourth step of outputting the noise signal from the pixel;
A fifth step of resetting the noise holding unit and outputting a reset signal from the pixel;
A sixth step of transferring a signal charge from the charge holding unit to the noise holding unit via the second transfer unit and outputting the optical signal from the pixel;
Control with
The solid-state imaging device according to claim 6, wherein the arithmetic unit performs an operation of removing the noise signal from the optical signal using the optical signal, the noise signal, and the reset signal.   The planar arrangement of the photoelectric conversion unit, the charge holding unit, and the noise holding unit in the pixel is axially symmetric with respect to an optical axis of a lens that allows light to enter the pixel unit. The solid-state imaging device according to claim 1 or 2.

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