JP2012058514A - Semiconductor integrated circuit, and operation method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To save storage capacity of a built-in memory used for an image drawing process and an image display process.SOLUTION: First and second display units 2A and 2B of a semiconductor integrated circuit output first and second mutually independent display data 6A and 6B, respectively. First, second, and third storage sections 4A, 4B, and 4C of a built-in memory 4 store respectively first, second, and third image data 5A, 5B, and 5C which are mutually independent. First and second selectors 3A and 3B includes first, second, and third input terminals and first, second, and third output terminals. The first input terminals of the selectors 3A and 3B are connected to an output of the first storage section 4A, the second input terminals of the selectors 3A and 3B are connected to an output of the second storage section 4B, the third input terminals of the selectors 3A and 3B are connected to an output of the third storage section 4C, and output terminals of the selectors 3A and 3B are connected to an input of the display units 2A and 2B.

Description

  The present invention relates to a semiconductor integrated circuit having an image processing function and an operation method thereof, and more particularly to a technique effective for enabling saving of a storage capacity of an internal memory used for image drawing processing and display processing. is there.

  Conventionally, in order to display an image on a display screen of an LCD (liquid crystal display) device, a CRT (cathode ray tube) display device, or the like, a drawing process of buffering image data to be displayed in a buffer memory called a frame memory has been performed. Executed. When the drawing process is completed, the image data stored in the frame memory is sequentially read out and transferred to the display device, and the display process is executed.

  The prior art of Patent Document 1 below describes that two frame buffers are prepared and these frame buffers are alternately allocated to a display buffer and an update buffer (drawing buffer) (memory interleaving). Further, in the embodiment of the following Patent Document 1, three frames of frame buffers are prepared, and these are alternately assigned as a display buffer, a next display buffer, and an update buffer, thereby increasing the efficiency of display data update storage processing. It is described that graphics are displayed on a display screen at high speed.

JP-A-5-333830

  Prior to the present invention, the inventors engaged in the development of a semiconductor integrated circuit incorporating a high-performance central processing unit (CPU) core and a large-capacity SRAM and mounting a graphics display function and a display controller function. did. A 1-Mbyte large-capacity SRAM is used not only as a program area and work area for a central processing unit (CPU), but also as a frame buffer for images and moving images. 16-bit gradation digital RGB display output is possible with the size of (Wide Quarter Video Graphics Array). Note that SRAM is an abbreviation for static random access memory.

  Applications of this semiconductor integrated circuit were assumed to be in-vehicle digital audio devices, automobile dashboards, graphics applications for in-vehicle devices, in-vehicle information devices that display camera images on the side and back of the vehicle body, and the like. Therefore, the graphic display and display controller function of a semiconductor integrated circuit requires a multi-window display and an alpha blend (α blend) function that combines a plurality of images into one frame image with a predetermined transmittance. It was done.

  This multi-window display or alpha blend display operation requires drawing processing and display processing of a plurality of frames, and therefore the present invention has a problem that the memory usage of the built-in SRAM of the semiconductor integrated circuit increases. It was clarified in advance by examination by the present inventors.

  FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit 1 equipped with a display function studied by the present inventors prior to the present invention.

  The semiconductor integrated circuit 1 studied by the inventors prior to the present invention shown in FIG. 1 includes a display unit 2, a selection unit 3, and a built-in SRAM 4.

  The display unit 2 includes a first display unit 2A and a second display unit 2B in order to realize multi-window display and alpha blending functions.

  The built-in SRAM 4 that can be used as a frame buffer for a plurality of images or moving images includes a first SRAM array 4A, a second SRAM array 4B, a third SRAM array 4C, and a fourth SRAM array 4D.

  The selection unit 3 selects the image data stored in the four SRAM arrays 4A to 4D of the built-in SRAM 4 and supplies them to the first display unit 2A and the second display unit 2B. 3A and a second selector 3B are included. That is, the first input terminal and the second input terminal of the first selector 3A, the first input terminal and the second input terminal of the second selector 3B are the first SRAM array 4A, the second SRAM array 4B, and the second input terminal. 3 SRAM array 4C and 4th SRAM array 4D, respectively. The output terminal of the first selector 3A and the output terminal of the second selector 3B are the first display unit 2A and the second display unit 2B. Are connected to each.

  FIG. 1 shows that the first image data 5A stored in the first SRAM array 4A is selected by the first selector 3A and displayed as the first display data 6A by the first display unit 2A. It also shows how the second image data 5B stored in the array 4D is selected by the second select 3B and displayed as the second display data 6B by the second display unit 2B.

  In addition, the semiconductor integrated circuit 1 shown in FIG. 1 switches the selection operation of the first selector 3A and the selection operation of the second selector 3B of the selection unit 3 to switch the first display unit 2A of the display unit 2 It is possible to sequentially switch the display screen displayed by the second display unit 2B. Before the new display screen is displayed, it is naturally necessary to draw a new display screen.

  FIG. 2 is a diagram showing a process in which the third image data 5C is drawn on the second SRAM array 4B which is not selected by the first selector 3A after the display process of FIG. Also during the drawing process shown in FIG. 2, the first image data 5A stored in the first SRAM array 4A is selected by the first selector 3A, and the first display data is displayed by the first display unit 2A. Displayed as 6A.

  In FIG. 3, after the drawing process of the third image data 5C shown in FIG. 2, the third image data 5C drawn and stored in the second SRAM array 4B is selected by the first selector 3A and is displayed in the first display. The second image data 5B displayed as the first display data 6A by the unit 2A and stored in the fourth SRAM array 4D is selected by the second select 3B, and the second display data 2B is displayed by the second display unit 2B. It is a figure which shows a mode that it displays as 6B. Also during the display process of the third image data 5C shown in FIG. 3, the fourth image data 5D is drawn on the third SRAM array 4C which is not selected by the second selector 3B. .

  In FIG. 4, after the display process and the drawing process of FIG. 3, the third image data 5C stored in the second SRAM array 4B is selected by the first selector 3A and the first display unit 2A performs the first display. The fourth image data 5D displayed as data 6A and drawn and stored in the third SRAM array 4C is selected by the second select 3B and displayed as the second display data 6B by the second display unit 2B. FIG.

  As described above, by using the semiconductor integrated circuit 1 shown in FIG. 1 constituted by the display unit 2, the selection unit 3, and the built-in SRAM 4 of the four SRAM arrays 4A to 4D, a multi-window display or It is possible to realize an alpha blend display operation. However, the semiconductor integrated circuit 1 shown in FIG. 1 has a problem that the memory usage of the built-in SRAM 4 is large.

  For example, if each display size of the first display data 6A and the second display data 6B is a WQVGA size of 480 pixels × 240 pixels and one pixel is a 16-bit gradation digital RGB display, four SRAMs are displayed. The storage capacity of each SRAM array in the arrays 4A to 4D is 230.4 KB (kilobytes), and the total storage capacity of the four SRAM arrays 4A to 4D is 921.6 KB.

  Therefore, even if the built-in SRAM 4 having a large capacity of 1 MB (8 Mbit) is integrated in the semiconductor integrated circuit 1 shown in FIG. 1, the remaining storage capacity is about 78.4 KB, and the program area of the central processing unit (CPU) It is insufficient for use as a work area.

  The present invention has been made as a result of the examination by the present inventors prior to the present invention as described above.

  Accordingly, an object of the present invention is to make it possible to save the storage capacity of a built-in memory used for image drawing processing and display processing in a semiconductor integrated circuit incorporating an image processing function.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical one of the inventions disclosed in the present application will be briefly described as follows.

  That is, the semiconductor integrated circuit (1) according to the representative embodiment of the present invention includes a first display unit (2A) and a second display unit (2B), a first selector (3A), and a second display unit. A built-in memory (4) having a selector (3B), a first storage unit (4A), a second storage unit (4B), and a third storage unit (4C) is provided.

  The output of the first display unit (2A) and the output of the second display unit (2B) are the first display data (6A) and the second display data (6B) which are independent from each other. Output is possible.

  The first storage unit (4A), the second storage unit (4B), and the third storage unit (4C) include first image data (5A) and second image data that are independent of each other. (5B) and third image data (5C) can be stored.

  Each selector of the first selector (3A) and the second selector (3B) has at least a first input terminal, a second input terminal, a third input terminal, and an output terminal.

  The first input terminal of the first selector (3A) and the first input terminal of the second selector (3B) are connected to the output of the first storage unit (4A), and the first input terminal The second input terminal of the selector (3A) and the second input terminal of the second selector (3B) are connected to the output of the second storage unit (4B), and the first selector (3A) The third input terminal and the third input terminal of the second selector (3B) are connected to the output of the third storage unit (4C).

  The output terminal of the first selector (3A) and the output terminal of the second selector (3B) are connected to the input of the first display unit (2A) and the second display unit (2B). It is characterized by being connected to the input (see FIG. 5).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, it is possible to save the storage capacity of the built-in memory used for image drawing processing and display processing.

FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit 1 equipped with a display function studied by the present inventors prior to the present invention, and the first image data 5A stored in the first SRAM array 4A. Is selected by the first selector 3A and displayed as the first display data 6A by the first display unit 2A, and the second image data 5B stored in the fourth SRAM array 4D is selected by the second selector 3B. It is also a diagram showing how the second display unit 2B displays the second display data 6B. FIG. 2 is a diagram showing a process in which the third image data 5C is drawn on the second SRAM array 4B which is not selected by the first selector 3A after the display process of FIG. In FIG. 3, after the drawing process of the third image data 5C shown in FIG. 2, the third image data 5C drawn and stored in the second SRAM array 4B is selected by the first selector 3A and is displayed in the first display. The second image data 5B displayed as the first display data 6A by the unit 2A and stored in the fourth SRAM array 4D is selected by the second select 3B, and the second display data 2B is displayed by the second display unit 2B. It is a figure which shows a mode that it displays as 6B. In FIG. 4, after the display process and the drawing process of FIG. 3, the third image data 5C stored in the second SRAM array 4B is selected by the first selector 3A and the first display unit 2A performs the first display. The fourth image data 5D displayed as data 6A and drawn and stored in the third SRAM array 4C is selected by the second select 3B and displayed as the second display data 6B by the second display unit 2B. FIG. FIG. 5 is a diagram showing a configuration of the semiconductor integrated circuit 1 according to the first embodiment of the present invention having a display function, and the first image data 5A stored in the first SRAM array 4A is the first selector. The second image data 5B selected by 3A and displayed as the first display data 6A by the first display unit 2A and stored in the third SRAM array 4C is selected by the second select 3B and the second display. It is a figure which also shows a mode that it displays as 2nd display data 6B by the unit 2B. In FIG. 6, the third image data 5C drawn and stored in the second SRAM array 4B by the drawing process of the third image data 5C shown in FIG. 5 is selected by the first selector 3A and the first display unit 2A. Is displayed as the first display data 6A, and the second image data 5B stored in the third SRAM array 4C is selected by the second select 3B and is used as the second display data 6B by the second display unit 2B. It is a figure which shows a mode that it displays. FIG. 7 shows the first SRAM that is not selected by the first selector 3A and the second selector 3B during the display processing of the second image data 5B and the third image data 5C shown in FIG. It is a figure which shows a mode that the 4th image data 5D is drawn on the array 4A. In FIG. 8, after the display process and the drawing process of FIG. 7, the third image data 5C stored in the second SRAM array 4B is selected by the first selector 3A and the first display unit 2A performs the first display. The fourth image data 5D displayed as data 6A and drawn and stored in the first SRAM array 4A is selected by the second select 3B and displayed as the second display data 6B by the second display unit 2B. FIG. FIG. 9 is a diagram showing a more specific configuration of the semiconductor integrated circuit 1 according to the second embodiment of the present invention in which the display function is mounted. FIG. 10 is a diagram for explaining an alpha blending operation realized by using the built-in SRAM 4 and the video display controller VDC built in the specific semiconductor integrated circuit 1 according to the second embodiment of the present invention shown in FIG. It is. FIG. 11 is a diagram showing a configuration of a semiconductor integrated circuit 1 according to another embodiment of the present invention equipped with a display function. First image data 5A stored in the first SRAM array 4A of the display buffer is shown in FIG. The second display data 2B is displayed by the second display unit 2B on the second image data 5B which is displayed as the first display data 6A by the first display unit 2A and stored in the third SRAM array 4C of the display buffer. In addition, a process of drawing the third image data 5C in the second SRAM array 4B of the drawing buffer is executed between the display processes of the first image data 5A and the second image data 5B. It also shows how it works. In FIG. 12, the third image data 5C drawn and stored in the second SRAM array 4B of the drawing buffer by the drawing process of the third image data 5C shown in FIG. 11 is copied to the display buffer 4A and displayed. The copy image data of the third image data 5C stored in the first SRAM array 4A in the buffer is displayed as the first display data 6A by the first display unit 2A, and is displayed in the third SRAM array 4C in the display buffer. It is a figure which shows a mode that the stored 2nd image data 5B is displayed as the 2nd display data 6B by the 2nd display unit 2B. FIG. 13 shows a state in which the fourth image data 5D is drawn in the second SRAM array 4B of the drawing buffer during the display processing of the second image data 5B and the third image data 5C shown in FIG. FIG. In FIG. 14, the fourth image data 5D drawn and stored in the second SRAM array 4B of the drawing buffer by the drawing process of the fourth image data 5D shown in FIG. 13 is copied to the display buffer 4C and displayed. The copy image data of the fourth image data 5D stored in the third SRAM array 4C of the buffer is displayed as the second display data 6B by the second display unit 2B, and is displayed in the first SRAM array 4A of the display buffer. It is a figure which shows a mode that the stored 3rd image data 5C is displayed as 1st display data 6A by the 1st display unit 2A.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor integrated circuit (1) according to a typical embodiment of the present invention includes a first display unit (2A), a second display unit (2B), a first selector (3A), and a second display unit. And a built-in memory (4) having a first storage unit (4A), a second storage unit (4B), and a third storage unit (4C).

  The output of the first display unit (2A) and the output of the second display unit (2B) are the first display data (6A) and the second display data (6B) which are independent from each other. Output is possible.

  The first storage unit (4A), the second storage unit (4B), and the third storage unit (4C) include first image data (5A) and second image data that are independent of each other. (5B) and third image data (5C) can be stored.

  Each selector of the first selector (3A) and the second selector (3B) has at least a first input terminal, a second input terminal, a third input terminal, and an output terminal.

  The first input terminal of the first selector (3A) and the first input terminal of the second selector (3B) are connected to the output of the first storage unit (4A), and the first input terminal The second input terminal of the selector (3A) and the second input terminal of the second selector (3B) are connected to the output of the second storage unit (4B), and the first selector (3A) The third input terminal and the third input terminal of the second selector (3B) are connected to the output of the third storage unit (4C).

  The output terminal of the first selector (3A) and the output terminal of the second selector (3B) are connected to the input of the first display unit (2A) and the second display unit (2B). It is characterized by being connected to the input (see FIG. 5).

  According to the embodiment, it is possible to save the storage capacity of the built-in memory used for image drawing processing and display processing.

  In a preferred embodiment, the first selector (3A) and the second selector (3B) are the first storage unit (4A) and the second storage unit of the built-in memory (4). (4B), the first image data (5A), the second image data (5B), and the third image data (5C) stored in the third storage unit (4C). By selecting data (5A, 5B), the first display data (6A) and the second display data (6B) as the input of the first display unit (2A) and the second display unit ( 2B) can be supplied to the input (see FIG. 5).

  In another preferred embodiment, the first display is responsive to the two data (5A, 5B) selected by the first selector (3A) and the second selector (3B). The output of the unit (2A) and the output of the second display unit (2B) output the first display data (6A) and the second display data (6B), respectively. (See FIG. 5).

  In still another preferred embodiment, in response to the two data selected by the first and second selectors, the first and second display units output the first and second outputs from the first and second display units. After the second display data is output, the remaining one piece of data that is not selected by the first selector (3A) and the second selector (3B) when the two pieces of data are selected. (5C) is selected (see FIG. 6).

  In a more preferred embodiment, the remaining one data (5C) is selected by one selector (3A) of the first selector (3A) and the second selector (3B), and the one of the one data (5C) is selected. One display unit (2A) of the first display unit (2A) and the second display unit (2B) in response to the remaining one data (5C) selected by the selector (3A) Thus, one display data (6A) of the first display data (6A) and the second display data (6B) is output (see FIG. 6).

  In another more preferred embodiment, the first display data (6A) output from the output of the first display unit (2A) and the output of the second display unit (2B), respectively. The second display data (6B) is used for any of multi-window display, alpha blend display, and multi-display display.

  The semiconductor integrated circuit (1) according to still another more preferred embodiment includes a third selector (3C) having at least a first input terminal, a second input terminal, a third input terminal, and an output terminal, and a third selector. And a third display unit (2C) capable of outputting the display data from the output.

  The first input terminal of the third selector (3C) is connected to the first input terminal of the first selector (3A) and the first input terminal of the second selector (3B). The second input terminal of the third selector (3C) is connected to the second input terminal of the first selector (3A) and the second input terminal of the second selector (3B), and the third input terminal The third input terminal of the selector (3C) is connected to the third input terminal of the first selector (3A) and the third input terminal of the second selector (3B).

  The output terminal of the third selector (3C) is connected to the input of the third display unit (2C) (see FIG. 9).

  A semiconductor integrated circuit (1) according to another more preferred embodiment includes a processor unit (10, 11), a processor bus (12), an intermediate layer bus (17A-17F), a peripheral bus (22), A first bus bridge (13 to 16), a second bus bridge (18, 19), and peripheral devices (23 to 28) are further provided.

  The processor unit is connected to the processor bus, the processor bus is connected to the intermediate layer bus via the first bus bridge, and the intermediate layer bus is connected to the intermediate bus via the second bus bridge (18, 19). The peripheral bus is connected to the peripheral device.

  The built-in memory (4) is a random access memory (RAM) connected to the intermediate layer bus, and the first storage unit (4A), the second storage unit (4B), and the third storage unit. (4C) is a first memory array, a second memory array, and a third memory array of the random access memory (RAM) of the built-in memory (4), respectively.

  The first display unit (2A), the second display unit (2B), the third display unit (2C), the first selector (3A), the second selector (3B), and the The third selector (3C) constitutes a video display controller (VDC) connected to the intermediate layer bus.

  The random access memory can store an operation program for the processor unit, and further, the first image data, the second image data, and the third image data for the video display controller, Can be stored (see FIG. 9).

  In still another more preferred embodiment, the intermediate layer bus includes a first image internal bus (17C), a second image internal bus (17D), a third image internal bus (17E), and a fourth image internal bus ( 17F).

  The video display controller (VDC) has an image input unit (7) for supplying image information to the first image internal bus by connecting an output to the first image internal bus, and an input is connected to the second image internal bus. A first image direct memory access controller (9A) connected to the bus; a second image direct memory access controller (9B) whose input is connected to the third image internal bus; and an input Includes a third image direct memory access controller (9C) connected to the fourth image internal bus.

  The first image internal bus is connected to the input terminal of the first memory array, the input terminal of the second memory array, and the input terminal of the third memory array to the first image internal bus. The image information can be stored in the first memory array, the second memory array, and the third memory array.

  A first output terminal of the first memory array, a first output terminal of the second memory array, and a first output terminal of the third memory array are connected to the second image internal bus; A second output terminal of the first memory array, a second output terminal of the second memory array, and a second output terminal of the third memory array are connected to the image internal bus, and the fourth image internal bus is connected. And a third output terminal of the first memory array, a third output terminal of the second memory array, and a third output terminal of the third memory array.

  The output of the first image direct memory access controller is the first input terminal of the first selector, the first input terminal of the second selector, and the first input terminal of the third selector. And the output of the second image direct memory access controller is connected to the second input terminal of the first selector, the second input terminal of the second selector, and the third selector. And the output of the third image direct memory access controller is connected to the second input terminal of the first selector and the third input terminal of the second selector. And the third input terminal of the third selector (see FIG. 9).

  In a specific embodiment, the first, second, and third image information respectively stored in the first, second, and third memory arrays are the second, the third, and the third, respectively. Via the fourth image internal bus, the first, second, and third image direct memory access controllers and the first, second, and third selectors, It is possible to supply in parallel to the inputs of the second and third display units (see FIG. 9).

  In the most specific embodiment, the processor unit includes a central processing unit (10), and the built-in memory (4) is a static random access memory (SRAM) connected to the intermediate layer bus, and the static random The access memory can store the operation program for the central processing unit (see FIG. 9).

  [2] A typical embodiment of another aspect of the present invention includes a first display unit (2A) and a second display unit (2B), a first selector (3A) and a second selector ( 3B), the operation of the semiconductor integrated circuit (1) including the built-in memory (4) having the first storage unit (4A), the second storage unit (4B), and the third storage unit (4C). Is the method.

  The output of the first display unit (2A) and the output of the second display unit (2B) are the first display data (6A) and the second display data (6B) which are independent from each other. Output is possible.

  The first storage unit (4A), the second storage unit (4B), and the third storage unit (4C) include first image data (5A) and second image data that are independent of each other. (5B) and third image data (5C) can be stored.

  Each selector of the first selector (3A) and the second selector (3B) has at least a first input terminal, a second input terminal, a third input terminal, and an output terminal.

  The first input terminal of the first selector (3A) and the first input terminal of the second selector (3B) are connected to the output of the first storage unit (4A), and the first input terminal The second input terminal of the selector (3A) and the second input terminal of the second selector (3B) are connected to the output of the second storage unit (4B), and the first selector (3A) The third input terminal and the third input terminal of the second selector (3B) are connected to the output of the third storage unit (4C).

  The output terminal of the first selector (3A) and the output terminal of the second selector (3B) are connected to the input of the first display unit (2A) and the second display unit (2B). Each is connected to the input (see FIG. 5).

  The first selector (3A) and the second selector (3B) are the first storage unit (4A), the second storage unit (4B) and the third storage unit of the built-in memory (4). Two data (5A, 5B) from the first image data (5A), the second image data (5B), and the third image data (5C) stored in the storage unit (4C) Select and supply the first display data (6A) and the second display data (6B) to the input of the first display unit (2A) and the input of the second display unit (2B). This is characterized by being made possible (see FIG. 5).

  According to the embodiment, it is possible to save the storage capacity of the built-in memory used for image drawing processing and display processing.

2. Details of Embodiment Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, components having the same functions as those in the above-mentioned drawings are denoted by the same reference numerals, and repeated description thereof is omitted.

[Embodiment 1]
<Configuration of semiconductor integrated circuit>
FIG. 5 is a diagram showing a configuration of the semiconductor integrated circuit 1 according to the first embodiment of the present invention that is equipped with a display function.

  The semiconductor integrated circuit 1 according to the first embodiment of the present invention shown in FIG. 5 is different from the semiconductor integrated circuit 1 examined by the inventors prior to the present invention shown in FIG. is there.

  First, in the semiconductor integrated circuit 1 according to the first embodiment of the present invention shown in FIG. 5, the built-in SRAM 4 that can be used as a frame buffer for a plurality of images or moving images includes the first SRAM array 4A and the second SRAM array. 4B and a third SRAM array 4C.

  Next, the first selector 3A and the second selector 3B of the selection unit 3 are composed of selectors having three input terminals.

  Further, the first selector 3A and the second selector 3B of the selection unit 3 select the image data stored in the three SRAM arrays 4A, 4B, 4C of the built-in SRAM 4 and select the first display unit 2A. And the second display unit 2B. That is, the first input terminal of the first selector 3A and the first input terminal of the second selector 3B are connected to the first SRAM array 4A, and the second input terminal of the first selector 3A and the second selector are connected. The 3B second input terminal is connected to the second SRAM array 4B. Finally, the third input terminal of the first selector 3A and the third input terminal of the second selector 3B are the third SRAM array 4C. It is connected. The output terminal of the first selector 3A and the output terminal of the second selector 3B are connected to the first display unit 2A and the second display unit 2B, respectively.

<< Display operation of semiconductor integrated circuit >>
FIG. 5 shows that the first image data 5A stored in the first SRAM array 4A is selected by the first selector 3A and displayed as the first display data 6A by the first display unit 2A. It also shows how the second image data 5B stored in the array 4C is selected by the second select 3B and displayed as the second display data 6B by the second display unit 2B.

  Further, the semiconductor integrated circuit 1 shown in FIG. 5 switches between the selection operation of the first selector 3A and the selection operation of the second select 3B of the selection unit 3, just like the semiconductor integrated circuit 1 shown in FIG. Thus, the display screen displayed by the first display unit 2A and the second display unit 2B of the display unit 2 can be sequentially switched. In addition, before displaying a new display screen, it is naturally necessary to draw a new display screen.

  In addition, during the display processing of the first image data 5A and the second image data 5B shown in FIG. 5, the second SRAM array 4B that is not selected by the first selector 3A and the second selector 3B. In addition, a process of drawing the third image data 5C is executed.

  In FIG. 6, the third image data 5C drawn and stored in the second SRAM array 4B by the drawing process of the third image data 5C shown in FIG. 5 is selected by the first selector 3A and the first display unit 2A. Is displayed as the first display data 6A, and the second image data 5B stored in the third SRAM array 4C is selected by the second select 3B and is used as the second display data 6B by the second display unit 2B. It is a figure which shows a mode that it displays.

  FIG. 7 shows the first SRAM that is not selected by the first selector 3A and the second selector 3B during the display processing of the second image data 5B and the third image data 5C shown in FIG. It is a figure which shows a mode that the 4th image data 5D is drawn on the array 4A.

  In FIG. 8, after the display process and the drawing process of FIG. 7, the third image data 5C stored in the second SRAM array 4B is selected by the first selector 3A and the first display unit 2A performs the first display. The fourth image data 5D displayed as data 6A and drawn and stored in the first SRAM array 4A is selected by the second select 3B and displayed as the second display data 6B by the second display unit 2B. FIG.

  Further, the third SRAM array 4C that is not selected by the first selector 3A and the second selector 3B during the display processing of the third image data 5C and the fourth image data 5D shown in FIG. A process for drawing the first image data 5A is executed.

<< Effects of Embodiment 1 >>
As described above, the display unit 2 constituted by the first and second display units 2A and 2B, the selection unit 3 constituted by the first and second selectors 3A and 3B having three input terminals, and 3 By using the semiconductor integrated circuit 1 shown in FIG. 5 configured by the SRAM arrays 4A, 4B, and 4C, it is possible to realize multi-window display and alpha blend display operation. However, according to the semiconductor integrated circuit 1 shown in FIG. 5, the memory usage of the built-in SRAM 4 can be saved.

  For example, if each display size of the first display data 6A and the second display data 6B is a WQVGA size of 480 pixels × 240 pixels and one pixel is a 16-bit gradation digital RGB display, three SRAMs are displayed. The storage capacity of each of the SRAM arrays 4A, 4B, and 4C is 230.4 KB (kilobytes), and the total storage capacity of the three SRAM arrays 4A, 4B, and 4C is 691.2 KB.

  Accordingly, when the built-in SRAM 4 having a large capacity of 1 MB is integrated in the semiconductor integrated circuit 1 shown in FIG. 5, the remaining storage capacity is about 308.8 KB, and the program area and work area of the central processing unit (CPU). It is enough to use as.

[Embodiment 2]
<< More specific configuration of semiconductor integrated circuit >>
FIG. 9 is a diagram showing a more specific configuration of the semiconductor integrated circuit 1 according to the second embodiment of the present invention in which the display function is mounted.

  A specific semiconductor integrated circuit 1 according to the second embodiment of the present invention shown in FIG. 9 is similar to the semiconductor integrated circuit 1 according to the first embodiment of the present invention shown in FIG. It includes not only the SRAM 4 but also other functional blocks.

  That is, the semiconductor integrated circuit 1 according to the second embodiment of the present invention shown in FIG. 9 first includes a central processing unit (CPU) 10 and a floating point arithmetic unit (FPU) 11. The central processing unit 11 and the floating point arithmetic unit 11 are connected to a cache controller (Cache Cnt) 13, an instruction cache memory (Int Cache) 14, an operand cache memory (Operand Cache) 15, via a CPU bus 12. A high-speed SRAM (HS RAM) 16 is connected.

  A peripheral controller (Peri Cnt) 19 and a built-in SRAM 4 are connected to the cache controller 13, the instruction cache memory 14, and the operand cache memory 15 via an internal CPU bus (Int CPU bus) 17A.

  A direct memory access controller (DMA Cnt) 18 and a built-in SRAM 4 are connected to the high-speed SRAM 16 via an internal DMA bus 17B.

  Also, six SRAM arrays 4A to 4F inside the built-in SRAM 4 are connected to the internal CPU bus 17A and the internal DMA bus 17B.

  A general-purpose input / output port (General I / O port) 23 and an SD type flash memory card can be connected to the direct memory access controller 18 and the peripheral controller 19 via a peripheral bus (Peri bus) 22. SD host interface (SD host I / F) 24, NAND type flash memory controller (NAND flash memory Cnt) 25 to which a NAND type flash memory card can be connected, analog / digital converter (ADC) 26, serial input / output port ( Serial I / O port) 2 7 and other peripheral ports 28 are connected. For example, a digital audio signal can be generated from the other peripheral port 28. The digital audio signal is converted into an analog audio signal by an external digital / analog converter and then supplied to an audio amplifier and a speaker.

  Although not shown in FIG. 9, the peripheral bus 22 is connected to a USB port to which an external USB (Universal Serial Bus) device can be connected and an SDRAM port to which an external synchronous DRAM (SDRAM) device can be connected. ing.

<Display function>
The semiconductor integrated circuit 1 shown in FIG. 9 includes an image input port (Video in port) 20 through which image data can be supplied from the outside.

  Image data supplied from the outside to the image input port 20 is supplied to a first internal image bus (IV1-bus) 17C via an image input unit (Video in) 7 in the video display controller VDC. Since the six internal terminals of the six SRAM arrays 4A to 4F in the internal SRAM 4 are connected to the first internal image bus 17C, the image data in the first internal image bus 17C is the six SRAMs in the internal SRAM 4. The data can be stored in any of the arrays 4A to 4F. The total storage capacity of the built-in SRAM 4 is set to 1 MB (exactly, 1,024 KB), and each of the six SRAM arrays 4A to 4F is set to an appropriate storage capacity size.

  The six first output terminals of the six SRAM arrays 4A to 4F in the built-in SRAM 4 are connected to the first direct memory access of the video display controller VDC via the second internal image bus (IV2-bus) 17D. It is connected to a controller (DMA Cnt) 9A. Six second output terminals of the six SRAM arrays 4A to 4F in the built-in SRAM 4 are connected to the second direct memory access of the video display controller VDC via a third internal image bus (IV3-bus) 17E. It is connected to the controller (DMA Cnt) 9B. Six third output terminals of the six SRAM arrays 4A to 4F in the built-in SRAM 4 are connected to the third direct memory access of the video display controller VDC via a fourth internal image bus (IV4-bus) 17F. It is connected to a controller (DMA Cnt) 9C.

  Therefore, image data generated from any of the six SRAM arrays 4A to 4F of the built-in SRAM 4 is one of the second internal image bus 17D, the third internal image bus 17E, and the fourth internal image bus 17F. Via the internal bus, it can be supplied to the input terminal of one of the first, second, and third direct memory access controllers 9A, 9B, 9C. The image data from the output terminals of any one of the first, second and third direct memory access controllers 9A, 9B and 9C is a first input which is composed of a selector of three input terminals inside the selection unit 3. Any of the first, second, and third line buffer memories (Line Buff) 8A, 8B, 8C of the line buffer memory 8 via any one of the selector 3A, the second selector 3B, and the third selector 3C. It can be supplied to the input terminal of the controller.

  Three output terminals of the first, second, and third line buffer memories 8A, 8B, and 8C of the line buffer memory 8 are connected to the first, second, and third display units 2A, 2B, and 2C of the display unit 2, respectively. The three output terminals of the first, second, and third display units 2A, 2B, and 2C are connected to the three input terminals of an image processing unit (Video Processing Unit) 21. The Further, the output terminal of the image processing unit 21 of the video display controller VDC is connected to the image input terminal of the liquid crystal display device LCD outside the semiconductor integrated circuit 1.

  Therefore, by using the built-in SRAM 4 and the video display controller VDC built in the specific semiconductor integrated circuit 1 according to the second embodiment of the present invention shown in FIG. 9, the six SRAM arrays 4A to 4F of the built-in SRAM 4 are used. Three image data generated from any three arrays of the first, second, and third images via the second internal image bus 17D, the third internal image bus 17E, and the fourth internal image bus 17F. The direct memory access controllers 9A, 9B and 9C can be supplied simultaneously and in parallel. As a result, the three image data generated from the three output terminals of the first, second and third direct memory access controllers 9A, 9B and 9C are converted into the first selector 3A of the selection unit 3. The first, second, and third line buffer memories 8A, 8B, and 8C of the line buffer memory 8 and the first of the display unit 2 through the second selector 3B and the third selector 3C. In addition, it can be supplied to the three input terminals of the second and third display units 2A, 2B and 2C simultaneously and in parallel.

  As a result, the image processing unit 21 of the video display controller VDC has three frames generated from the three output terminals of the first, second and third line buffer memories 8A, 8B and 8C of the line buffer memory 8. It is possible to execute an alpha blending operation in which each pixel of an image is synthesized into one frame image with a predetermined transmittance. At that time, in the line buffer memory 8, the frame image generated from the output terminal of the first line buffer memory 8A, the frame image generated from the output terminal of the second line buffer memory 8B, and the third line buffer memory 8C. The frame image generated from the output terminal corresponds to, for example, the lowermost layer, the intermediate layer, and the uppermost layer of the alpha blend composite frame image.

《Alpha blend operation》
FIG. 10 is a diagram for explaining an alpha blending operation realized by using the built-in SRAM 4 and the video display controller VDC built in the specific semiconductor integrated circuit 1 according to the second embodiment of the present invention shown in FIG. It is.

  As shown in FIG. 10, in the line buffer memory 8, the lowest layer 100 before composition is generated by the frame image generated from the output terminal of the first line buffer memory 8A, and the second line buffer memory 8B The intermediate layer 101 before synthesis is generated by the frame image generated from the output terminal, and the uppermost layer 102 before synthesis is generated by the frame image generated from the output terminal of the third line buffer memory 8C. As a result, the image processing unit 21 of the video display controller VDC executes an alpha blend operation 103 in which the pixels of the lowermost layer 100, the pixels of the intermediate layer 101, and the pixels of the uppermost layer 102 are respectively combined with a predetermined transmittance. By executing the alpha blend operation 103, one alpha blend composite frame image 104 is generated.

《Other operation modes》
Furthermore, it is possible to realize multi-window display or picture-in-picture display by changing the operation mode of the semiconductor integrated circuit 1 to another operation mode. At this time, the three image data generated simultaneously and in parallel from the three output terminals of the first, second and third line buffer memories 8A, 8B and 8C of the line buffer memory 8 are displayed in a multi-window display. This is used for drawing processing of three different display areas such as a screen and a picture-in-picture display screen.

<< Effects of Embodiment 2 >>
As described above, the display unit 2 constituted by the first, second, and third display units 2A, 2B, and 2C, and the first, second, and third selectors 3A, 3B, and 3C having three input terminals. By using the configured selection unit 3 and the built-in SRAM 4 composed of the six SRAM arrays 4A to 4F, it is possible to realize multi-window display and alpha blend display operation, and further use the memory of the built-in SRAM 4. The amount can be saved.

  For example, in FIG. 10, the display size of the image frame of the lowermost layer 100, the image frame of the intermediate layer 101, and the image frame of the uppermost layer 102 is WQVGA size of 480 pixels × 240 pixels, and one pixel is a 16-bit gradation digital. In the case of RGB display, the used storage capacity of the built-in SRAM 4 is 691.2 KB.

  Therefore, when the 1 MB large-capacity built-in SRAM 4 is integrated in the semiconductor integrated circuit 1 shown in FIG. 9, the remaining storage capacity is about 308.8 KB, and the operation program of the central processing unit (CPU) 10 is stored. This is sufficient for use as a program area or work area. Further, when realizing the alpha blend display operation as shown in FIG. 10, it is not necessary to use an external memory device such as an external SDRAM, so that a display operation with high speed and low power consumption can be achieved. Become.

  Various image processing functions built in the specific semiconductor integrated circuit 1 according to the second embodiment of the present invention shown in FIG. 9 shown in FIG. 9 described above, a high-performance central processing unit 11, a floating point arithmetic unit 11, and a large capacity built-in. By using the SRAM 4, the semiconductor integrated circuit 1 is applied to an in-vehicle digital audio device, an automobile dashboard, a graphics application for an in-vehicle device, an in-vehicle information device that displays a camera image of the side and back of the vehicle body, and the like. In this case, it is possible to realize a high-performance image processing function.

  As mentioned above, the invention made by the present inventor has been specifically described based on various embodiments. However, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, by applying a DRAM logic mixed semiconductor manufacturing process to the semiconductor integrated circuit 1, the large-capacity built-in SRAM 4 built in the semiconductor integrated circuit 1 can be replaced with a large-capacity built-in DRAM having a small semiconductor chip occupation area. It becomes.

  Furthermore, in the semiconductor integrated circuit 1 according to the second embodiment of the present invention shown in FIG. 9, three image data generated in parallel from the three output terminals of the three line buffer memories 8A, 8B, 8C of the line buffer memory 8. Can be used for a multi-display operation in which a plurality of display devices are connected to a personal computer, a workstation or the like for display.

  Further, in the semiconductor integrated circuit 1 according to the second embodiment of the present invention shown in FIG. 9, for example, a nonvolatile memory such as a flash memory or a read only memory (ROM) is connected to the peripheral bus 22, and the central processing unit is connected to the nonvolatile memory. Eleven operation programs can be stored. Further, in this non-volatile memory, three image data generated from the three output terminals of the first, second and third display units 2A, 2B and 2C of the display unit 2 of the video display controller VDC are stored. It is also possible to store a part of pixel data.

[Other embodiments]
Further, as shown in FIGS. 11, 12, 13, and 14, two built-in SRAM arrays 4A, 4C, three built-in SRAM arrays 4A, 4B, and 4C are used as display buffers, and the remaining one. The built-in SRAM 4B array can be used as a drawing buffer for creating data. It is also possible to execute double buffering by capturing image data by drawing processing in the data creation buffer 4B and copying the data to one of the two display buffers 4A and 4C. Is possible.

  FIG. 11 is a diagram showing a configuration of a semiconductor integrated circuit 1 according to another embodiment of the present invention equipped with a display function. First image data 5A stored in the first SRAM array 4A of the display buffer is shown in FIG. The second display data 2B is displayed by the second display unit 2B on the second image data 5B which is displayed as the first display data 6A by the first display unit 2A and stored in the third SRAM array 4C of the display buffer. It also shows how it is displayed as.

  In addition, during the display process of the first image data 5A and the second image data 5B shown in FIG. 11, a process of drawing the third image data 5C in the second SRAM array 4B of the drawing buffer is executed. It is.

  In FIG. 12, the third image data 5C drawn and stored in the second SRAM array 4B of the drawing buffer by the drawing process of the third image data 5C shown in FIG. 11 is copied to the display buffer 4A and displayed. The copy image data of the third image data 5C stored in the first SRAM array 4A in the buffer is displayed as the first display data 6A by the first display unit 2A, and is displayed in the third SRAM array 4C in the display buffer. It is a figure which shows a mode that the stored 2nd image data 5B is displayed as the 2nd display data 6B by the 2nd display unit 2B.

  FIG. 13 shows a state in which the fourth image data 5D is drawn in the second SRAM array 4B of the drawing buffer during the display processing of the second image data 5B and the third image data 5C shown in FIG. FIG.

  In FIG. 14, the fourth image data 5D drawn and stored in the second SRAM array 4B of the drawing buffer by the drawing process of the fourth image data 5D shown in FIG. 13 is copied to the display buffer 4C and displayed. The copy image data of the fourth image data 5D stored in the third SRAM array 4C of the buffer is displayed as the second display data 6B by the second display unit 2B, and is displayed in the first SRAM array 4A of the display buffer. It is a figure which shows a mode that the stored 3rd image data 5C is displayed as 1st display data 6A by the 1st display unit 2A.

  Further, during the display processing of the third image data 5C and the fourth image data 5D shown in FIG. 14, it is also possible to draw other image data 5D in the second SRAM array 4B of the drawing buffer. .

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit 2, 2A-2C ... Display unit 3 ... Selection unit 3A-3C ... Selector 4 ... Built-in SRAM
4A to 4F ... SRAM array 5A to 5D ... Image data 6A to 6D ... Display data 7 ... Image input unit (Video in)
8, 8A-8C ... Line buffer memory (Line Buff)
9A to 9C: Direct memory access controller (DMA Cnt)
10: Central processing unit (CPU)
11: Floating point arithmetic unit (FPU)
12 ... CPU bus
13 ... Cache controller (Cache Cnt)
14: Instruction cache memory (Int Cache)
15 ... Operand Cache
16 ... High-speed SRAM (HS RAM)
17A ... Internal CPU bus
17B ... Int DMA bus
17C ... First internal image bus (IV1-bus)
17D ... Second internal image bus (IV2-bus)
17E ... Third internal image bus (IV3-bus)
17F ... 4th internal image bus (IV4-bus)
18 ... Direct memory access controller (DMA Cnt)
19 ... Peripheral controller (Peri Cnt)
20. Image input port (Video in port)
21 ... Video Processing Unit
22 ... Peri bus
23 ... General I / O port
24 ... SD host interface (SD host I / F)
25 ... NAND flash memory controller (NAND flash memory Cnt)
26 ... Analog / digital converter (ADC)
27: Serial I / O port
28 ... Other peripheral ports LCD ... External liquid crystal display device

Claims (20)

A semiconductor integrated circuit includes a first display unit, a second display unit, a first selector, a second selector, a first storage unit, a second storage unit, and a third storage unit. A memory,
The output of the first display unit and the output of the second display unit can output first display data and second display data independent of each other, respectively.
The first storage unit, the second storage unit, and the third storage unit are capable of storing the first image data, the second image data, and the third image data that are independent from each other.
Each selector of the first selector and the second selector has at least a first input terminal, a second input terminal, a third input terminal, and an output terminal,
The first input terminal of the first selector and the first input terminal of the second selector are connected to an output of the first storage unit, and the second input terminal of the first selector and the first input terminal The second input terminal of the second selector is connected to the output of the second storage unit, and the third input terminal of the first selector and the third input terminal of the second selector are the Connected to the output of the third storage unit,
The output terminal of the first selector and the output terminal of the second selector are respectively connected to an input of the first display unit and an input of the second display unit. Semiconductor integrated circuit. In claim 1,
The first selector and the second selector include the first image data stored in the first storage unit, the second storage unit, and the third storage unit of the internal memory, and the Two pieces of data are selected from the second image data and the third image data, and the input and the second display of the first display unit are used as the first display data and the second display data. A semiconductor integrated circuit which can be supplied to the input of a unit. In claim 2,
The output of the first display unit and the output of the second display unit are responsive to the two data selected by the first selector and the second selector. Display data and said 2nd display data are output, respectively, The semiconductor integrated circuit characterized by the above-mentioned. In claim 3,
In response to the two data selected by the first and second selectors, the first and second display data are output from the outputs of the first and second display units. Thereafter, when the two pieces of data are selected, the remaining one piece of data that has not been selected by the first selector and the second selector is selected. In claim 4,
The remaining one data is selected by one of the first selector and the second selector, and in response to the remaining one data selected by the one selector, the first data One display data of the first display data and the second display data is output by one display unit of the second display unit and the second display unit. In claim 5,
The first display data and the second display data respectively output from the output of the first display unit and the output of the second display unit are a multi-window display, an alpha blend display, and a multi-display. A semiconductor integrated circuit used for either display display. In claim 5,
The semiconductor integrated circuit includes a third selector having at least a first input terminal, a second input terminal, a third input terminal, and an output terminal, and a third display unit capable of outputting third display data from an output. Further comprising
The first input terminal of the third selector is connected to the first input terminal of the first selector and the first input terminal of the second selector, and the second input terminal of the third selector. Is connected to the second input terminal of the first selector and the second input terminal of the second selector, and the third input terminal of the third selector is the third input of the first selector. A terminal and the third input terminal of the second selector;
The semiconductor integrated circuit, wherein the output terminal of the third selector is connected to an input of the third display unit. In claim 7,
The semiconductor integrated circuit further comprises a processor unit, a processor bus, an intermediate layer bus, a peripheral bus, a first bus bridge, a second bus bridge, and a peripheral device,
The processor unit is connected to the processor bus, the processor bus is connected to the intermediate layer bus via the first bus bridge, and the intermediate layer bus is connected to the peripheral bus via the second bus bridge. The peripheral bus is connected to the peripheral device;
The internal memory is a random access memory connected to the intermediate layer bus, and the first storage unit, the second storage unit, and the third storage unit are respectively the random access memory of the internal memory. A first memory array, a second memory array, and a third memory array;
The first display unit, the second display unit, the third display unit, the first selector, the second selector, and the third selector are connected to the intermediate layer bus. It constitutes a video display controller,
The random access memory can store an operation program for the processor unit, and further, the first image data, the second image data, and the third image data for the video display controller, A semiconductor integrated circuit characterized in that can be stored. In claim 8,
The intermediate layer bus includes a first image internal bus, a second image internal bus, a third image internal bus, and a fourth image internal bus,
The video display controller has an image input unit for supplying image information to the first image internal bus by connecting an output to the first image internal bus, and an input connected to the second image internal bus. One image direct memory access controller, a second image direct memory access controller whose input is connected to the third image internal bus, and a second one whose input is connected to the fourth image internal bus. 3 image direct memory access controllers,
The first image internal bus is connected to the input terminal of the first memory array, the input terminal of the second memory array, and the input terminal of the third memory array to the first image internal bus. The image information can be stored in the first memory array, the second memory array, and the third memory array,
A first output terminal of the first memory array, a first output terminal of the second memory array, and a first output terminal of the third memory array are connected to the second image internal bus; A second output terminal of the first memory array, a second output terminal of the second memory array, and a second output terminal of the third memory array are connected to the image internal bus, and the fourth image internal bus is connected. A third output terminal of the first memory array, a third output terminal of the second memory array, and a third output terminal of the third memory array;
The output of the first image direct memory access controller is the first input terminal of the first selector, the first input terminal of the second selector, and the first input terminal of the third selector. And the output of the second image direct memory access controller is connected to the second input terminal of the first selector, the second input terminal of the second selector, and the third selector. And the output of the third image direct memory access controller is connected to the second input terminal of the first selector and the third input terminal of the second selector. And a third input terminal of the third selector. In claim 9,
The first, second, and third image information stored in the first, second, and third memory arrays, respectively, are the second, third, and fourth image internal buses, and The first, second, and third image direct memory access controllers and the first, second, and third selectors through the first, second, and third selectors. A semiconductor integrated circuit characterized in that it can be supplied in parallel to the input of the display unit. In claim 10,
The processor unit includes a central processing unit, and the internal memory is a static random access memory connected to the intermediate layer bus, and the operation program for the central processing unit can be stored in the static random access memory A semiconductor integrated circuit characterized by the above. A first display unit; a second display unit; a first selector; a second selector; and a built-in memory having a first storage unit, a second storage unit, and a third storage unit. A method for operating a semiconductor integrated circuit, comprising:
The output of the first display unit and the output of the second display unit can output first display data and second display data independent of each other, respectively.
The first storage unit, the second storage unit, and the third storage unit are capable of storing the first image data, the second image data, and the third image data that are independent from each other.
Each selector of the first selector and the second selector has at least a first input terminal, a second input terminal, a third input terminal, and an output terminal,
The first input terminal of the first selector and the first input terminal of the second selector are connected to an output of the first storage unit, and the second input terminal of the first selector and the first input terminal The second input terminal of the second selector is connected to the output of the second storage unit, and the third input terminal of the first selector and the third input terminal of the second selector are the Connected to the output of the third storage unit,
The output terminal of the first selector and the output terminal of the second selector are respectively connected to an input of the first display unit and an input of the second display unit;
The first selector and the second selector include the first image data stored in the first storage unit, the second storage unit, and the third storage unit of the internal memory, and the Two pieces of data are selected from the second image data and the third image data, and the input and the second display of the first display unit are used as the first display data and the second display data. A method of operating a semiconductor integrated circuit, characterized in that it can be supplied to the input of a unit. In claim 12,
The output of the first display unit and the output of the second display unit are responsive to the two data selected by the first selector and the second selector. A method of operating a semiconductor integrated circuit, wherein display data and the second display data are respectively output. In claim 13,
In response to the two data selected by the first and second selectors, the first and second display data are output from the outputs of the first and second display units. Thereafter, when the two pieces of data are selected, the remaining one piece of data that has not been selected by the first selector and the second selector is selected. In claim 14,
The remaining one data is selected by one of the first selector and the second selector, and in response to the remaining one data selected by the one selector, the first data One of the first display data and the second display data is output from one display unit of the display unit and the second display unit. A method for operating a semiconductor integrated circuit, wherein: In claim 15,
The first display data and the second display data respectively output from the output of the first display unit and the output of the second display unit are a multi-window display, an alpha blend display, and a multi-display. A method for operating a semiconductor integrated circuit, which is used for display display. In claim 15,
The semiconductor integrated circuit includes a third selector having at least a first input terminal, a second input terminal, a third input terminal, and an output terminal, and a third display unit capable of outputting third display data from an output. Further comprising
The first input terminal of the third selector is connected to the first input terminal of the first selector and the first input terminal of the second selector, and the second input terminal of the third selector. Is connected to the second input terminal of the first selector and the second input terminal of the second selector, and the third input terminal of the third selector is the third input of the first selector. A terminal and the third input terminal of the second selector;
The method of operating a semiconductor integrated circuit, wherein the output terminal of the third selector is connected to an input of the third display unit. In claim 17,
The semiconductor integrated circuit further comprises a processor unit, a processor bus, an intermediate layer bus, a peripheral bus, a first bus bridge, a second bus bridge, and a peripheral device,
The processor unit is connected to the processor bus, the processor bus is connected to the intermediate layer bus via the first bus bridge, and the intermediate layer bus is connected to the peripheral bus via the second bus bridge. The peripheral bus is connected to the peripheral device;
The internal memory is a random access memory connected to the intermediate layer bus, and the first storage unit, the second storage unit, and the third storage unit are respectively the random access memory of the internal memory. A first memory array, a second memory array, and a third memory array;
The first display unit, the second display unit, the third display unit, the first selector, the second selector, and the third selector are connected to the intermediate layer bus. It constitutes a video display controller,
The random access memory can store an operation program for the processor unit, and further, the first image data, the second image data, and the third image data for the video display controller, A method for operating a semiconductor integrated circuit, wherein: In claim 18,
The intermediate layer bus includes a first image internal bus, a second image internal bus, a third image internal bus, and a fourth image internal bus,
The video display controller has an image input unit for supplying image information to the first image internal bus by connecting an output to the first image internal bus, and an input connected to the second image internal bus. One image direct memory access controller, a second image direct memory access controller whose input is connected to the third image internal bus, and a second one whose input is connected to the fourth image internal bus. 3 image direct memory access controllers,
The first image internal bus is connected to the input terminal of the first memory array, the input terminal of the second memory array, and the input terminal of the third memory array to the first image internal bus. The image information can be stored in the first memory array, the second memory array, and the third memory array,
A first output terminal of the first memory array, a first output terminal of the second memory array, and a first output terminal of the third memory array are connected to the second image internal bus; A second output terminal of the first memory array, a second output terminal of the second memory array, and a second output terminal of the third memory array are connected to the image internal bus, and the fourth image internal bus is connected. A third output terminal of the first memory array, a third output terminal of the second memory array, and a third output terminal of the third memory array;
The output of the first image direct memory access controller is the first input terminal of the first selector, the first input terminal of the second selector, and the first input terminal of the third selector. And the output of the second image direct memory access controller is connected to the second input terminal of the first selector, the second input terminal of the second selector, and the third selector. And the output of the third image direct memory access controller is connected to the second input terminal of the first selector and the third input terminal of the second selector. And the third input terminal of the third selector,
The first, second, and third image information stored in the first, second, and third memory arrays, respectively, are the second, third, and fourth image internal buses, and The first, second, and third image direct memory access controllers and the first, second, and third selectors through the first, second, and third selectors. A method of operating a semiconductor integrated circuit, characterized in that it can be supplied in parallel to the input of a display unit. In claim 19,
The processor unit includes a central processing unit, and the internal memory is a static random access memory connected to the intermediate layer bus, and the operation program for the central processing unit can be stored in the static random access memory A method of operating a semiconductor integrated circuit, wherein

Images