JP2001024180A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable high-speed processing without loading even in the case of processing using repeatedly the same image data. SOLUTION: With regard to the semiconductor integrated circuit device, a frame buffer memory 11, a pixel processing unit 13, a comparing unit 14, and a register file 12 which is connected to the frame buffer memory 11 through a global bus 17 and stores image data supplied from the frame buffer memory 11 or stores the calculation results of the image processing unit 13 and the like, are at least formed on the same semiconductor substrate. An off-screen memory 20 for storing a part of image information stored in the frame buffer memory 11, a bus 21 connecting between the frame buffer memory 11 and the off-screen memory 20, and a control unit 16 for controlling the data transmission between the frame buffer memory 11 and the off-screen memory 20 through the bus 21, are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit device used as a frame buffer having an image processing function, which is used in a work station or a personal computer.

[0002]

2. Description of the Related Art In recent years, for example, (1280 × 1024)
A high-resolution display device having pixels is frequently used, and a DRAM (dynamic random access memory) having a low cost per bit and a large storage capacity is used as a frame buffer. In this high-resolution display device, for example, 60 screens are displayed in one second, so that DRA is performed on the order of 10 nsec.
M needs to be accessed. However, the access time of a commercially available DRAM is, for example, about 200 nsec. Therefore, a plurality of DRAMs are accessed in parallel to read a plurality of data at a time, and the read data is multiplexed and processed one data at a time. Like that.

When such a plurality of DRAMs are used as a frame buffer memory, the number of wirings on the board on which the frame buffer memory is mounted increases, and the board size increases. As a result, the parasitic capacitance of the wiring for the frame buffer memory is charged and discharged,
Power consumption increases. On the other hand, in the graphics processing, it is necessary to perform a logical operation between pixel data such as a raster operation which is frequently used, and this logical operation requires, for example, a parallel operation for each pixel of RGB in order to reduce time. Therefore, there is a problem in that the number of wirings increases, and it takes more time than simple data transfer time due to the existence of the parasitic capacitance due to the wirings.

Therefore, for example, Japanese Patent Application Laid-Open No. 7-249116 discloses
In the semiconductor integrated circuit device described in Japanese Patent Application Laid-Open Publication No. H10-209, the above-described frame buffer memory and the function of performing a logical operation between pixel data are integrated on one semiconductor substrate, and the parasitic capacitance on the wiring is reduced as much as possible. A three-dimensional frame buffer memory that enables high-speed graphics processing is realized.

FIG. 10 is a block diagram showing the overall configuration of a conventional semiconductor integrated circuit device having at least such a three-dimensional frame buffer memory and a function of performing a logical operation. 10, this semiconductor integrated circuit device includes a frame buffer memory 111 composed of a DRAM and a register file 112 composed of an SRAM (static random access memory).
, Data supplied from the register file 112 and data DQ0 supplied from the external input / output data terminal 125.
To DQ31, a comparison unit 114 for comparing them, and the image data stored in the frame buffer memory 111, and the video output data V0 via a video output data terminal 128 of a display device (not shown). A serial access memory (SAM) 115 for outputting and a control unit 116 for controlling these are configured on at least one semiconductor substrate.

The frame buffer memory 111 is composed of four banks, each of which is (512 × 640 ×
8) It has memory cells and can store 2.6 Mbits of data. Therefore, the frame buffer memory 111 as a whole has a storage capacity of 10.5 megabits, and can store 1/4 frame image data on the display screen of the display device connected to the video output data terminal 128. On the other hand, the register file 112 includes eight memory blocks, and each memory block can store 256-bit data. Therefore, the register file 112 can store 2 kilobits of data.

[0007] The frame buffer memory 111 and the register file 112 are connected by a 256-bit global bus 117.
Register file 1 from frame buffer memory 111
While performing data transfer in 256-bit units to 12,
From the register file 112 to the frame buffer memory 1
11, data is transferred in units of 256 bits. One memory block in the register file 112 is rewritten by the 256-bit data transferred from the frame buffer memory 111, and when data is transferred from the register file 112 to the frame buffer memory 111, one of the memory blocks in the register file 112 is rewritten. The data of one memory block is transferred collectively.

[0008] The pixel processing unit 113 receives the data from the register file 112 via the data bus 118.
Bit data and external input / output data terminals DQ0 to DQ
Based on the 32-bit data provided through the interface 31, predetermined arithmetic processing is performed. The 32-bit data resulting from this operation is written back to the register file 112 via the data bus 119. The comparison unit 114
The 32-bit data supplied from the register file 112 via the data bus 118 is compared with the 32-bit external input / output data DQ0 to DQ31 supplied via the external input / output data terminal 125, and the comparison result is obtained. It is output as a flag signal FLAGOUT, and based on the comparison result, is input to the register file 112 as a flag signal FLAGIN indicating whether or not to write the data of the operation result by the pixel processing unit 113 to the register file 112.

The serial access memory 115 reads data from the frame buffer memory 111 every 640 bits, responds to the video clock signal on the display device side, and outputs the read data via the video output data terminal 128 every 16 bits. To output video output data V0 to the display device. Further, the control unit 116 includes a control signal CONT and a clock signal CLK supplied from outside.
, A control signal for controlling the frame buffer memory 111, the register file 112, the serial access memory 115, the pixel processing unit 113, and the comparison unit 114 is generated. For example, the pixel processing unit 113 operates in response to the control signal CNT1, and the comparison unit 114 operates in response to the control signal CNT2. The external input / output data DQ0 to DQ31 can transfer the data of the register file 112 to the outside via the data bus 119.

[0010]

When displaying image data on a display device using a frame buffer memory, an application that uses the same image data many times may be used. In this case, it generally takes time to rewrite the image data displayed on the display device. Therefore, high-speed processing can be realized by increasing the capacity of the frame buffer memory and using the remaining memory area as a save area for image data to be repeatedly displayed. Since a large number of memory chips are used by adding DRAMs, the number of wirings on the board increases, and the problem based on the parasitic capacitance of the wirings becomes more serious.

On the other hand, the conventional semiconductor integrated circuit device described above can solve the problem of an increase in the parasitic capacitance due to an increase in the number of wirings. region,
That is, a process of writing back to the save area is required, and there is a problem that the processing load is increased by performing the process of writing back, and high-speed processing is hindered.

In the three-dimensional graphic processing, there is a case where the image data once drawn is pasted as a texture on the object again. In such a case, in the conventional semiconductor integrated circuit device, the frame buffer memory 1 is used.
The image data is read out via the global bus 117 for the image data 11 and processed by the image processing unit 113 and the like. However, the reading out of the image data and the writing into the frame buffer memory 111 are performed by the same global bus 117. Also, there is a problem that the processing speed is reduced.

The present invention has been made in view of the above,
It is an object of the present invention to provide a semiconductor integrated circuit device as a frame buffer memory having an arithmetic processing function capable of performing high-speed processing without imposing a load even when performing processing using the same image data repeatedly.

[0014]

In order to achieve the above object, a semiconductor integrated circuit device according to the present invention comprises a frame buffer memory, an image information held in the frame buffer memory, and an externally input image information. Computing means for performing image processing computation on image information to be output to the display means from the frame buffer memory, and an image which is connected to the frame buffer memory via a first bus and is a processing target of the computation means In a semiconductor integrated circuit device in which information or a first storage means for storing image processing operation results is formed at least on the same semiconductor substrate, part of image information in the image information stored in the frame buffer memory is stored. A second storage means for connecting the frame buffer memory and the second storage means, A transfer for controlling to mutually transfer a part of the image information in the image information stored in the frame buffer memory and a part of the image information stored in the second storage means via a second bus; And control means.

According to the present invention, the transfer control means controls the transfer of the image data to the frame buffer memory independently of the transfer of the image information between the frame buffer memory and the first storage means via the first bus. Via a second bus connecting the second storage means, a part of the image information in the image information stored in the frame buffer memory is transferred to the second storage means, or the second storage means A part of the image information stored in the means is transferred to the frame buffer memory so that the part of the image information can be transferred separately from the image calculation processing by the calculation means.

According to another aspect of the present invention, there is provided a semiconductor integrated circuit device, comprising: a frame buffer memory; and outputting from the frame buffer memory to display means based on image information held in the frame buffer memory and image information input externally. Calculating means for performing an image processing operation on image information to be processed; and a first means connected to the frame buffer memory via a first bus and storing image information or an image processing operation result to be processed by the calculating means. In a semiconductor integrated circuit device in which a storage unit is formed at least on the same semiconductor substrate, a second storage unit that stores a part of image information stored in the first storage unit, and the first storage unit And a third bus connecting the second storage means,
Transfer control for performing control for mutually transferring a part of the image information stored in the first storage means and a part of the image information stored in the second storage means via the third bus; Means.

According to the present invention, when the transfer control means transfers the image information between the frame buffer memory and the first storage means via the first bus, the first storage means and the second storage means Via a third bus connecting the storage means, a part of the image information in the image information stored in the first storage means is transferred to the second storage means, or the second storage Control is performed to transfer a part of the image information stored in the means to the first storage means.

According to another aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a frame buffer memory; an image output from the frame buffer memory to display means based on image information held in the frame buffer memory and image information input externally; Calculating means for performing an image processing operation on image information to be processed; and a first means connected to the frame buffer memory via a first bus and storing image information or an image processing operation result to be processed by the calculating means. In a semiconductor integrated circuit device in which a storage unit is formed at least on the same semiconductor substrate, a part of image information in the image information stored in the frame buffer memory or a part of the image information stored in the first storage unit. A second storage unit for storing image information; and a second storage unit for connecting the frame buffer memory and the second storage unit. Bus, a third bus connecting the first storage means and the second storage means, and a part of the image information stored in the frame buffer memory via the second bus. Control to mutually transfer the image information and a part of the image information stored in the second storage means, and a part of the image information stored in the first storage means via the third bus. And a transfer control means for selectively performing control for mutually transferring a part of the image information stored in the second storage means.

According to the present invention, the transfer control means controls the transfer of the image data between the frame buffer memory and the first storage means independently of the transfer of the image information between the frame buffer memory and the first storage means via the first bus. Via a second bus connecting the second storage means, a part of the image information in the image information stored in the frame buffer memory is transferred to the second storage means, or the second storage means Means for transferring part of the image information stored in the means to the frame buffer memory so that the part of the image information can be transferred separately from the image calculation processing by the calculation means, or the transfer control means When transferring image information between the frame buffer memory and the first storage means via a bus, the first storage means and the first storage means are connected via a third bus connecting the second storage means. Memory hand Transfer part of the image information in the image information stored in the second storage means, or transfer part of the image information stored in the second storage means to the first storage means Transfer control is selectively performed.

The semiconductor integrated circuit device according to the next invention is the semiconductor integrated circuit device according to the above invention, further comprising an area designating means for designating a storage area for the partial image information, corresponding to the image information displayed on the display means. It is characterized by having.

According to this invention, the area designating means designates a storage area of the partial image information, for example, a rectangular area, corresponding to the image information displayed on the display means,
By specifying the storage area, the transfer source area or the transfer destination area of the frame buffer memory, the first storage means, or the second storage means is collectively specified and transferred.

The semiconductor integrated circuit device according to the next invention is the semiconductor integrated circuit device according to the above invention, wherein: an external output terminal; a fourth bus connecting the second storage means and the external output terminal; Transfer output control means for transferring and outputting a part of the image information stored in the means via the external output terminal.

According to the present invention, the second storage means is connected to the external output terminal via the fourth bus, and transfers a part of the image information stored in the second storage means by the transfer output control means. Output to

The semiconductor integrated circuit device according to the next invention is provided between the second storage means and the external output terminal in the above-mentioned invention, and transfers the data from the frame buffer memory to the second storage means. The image processing apparatus further includes scaling processing means for scaling the selected part of the image information or the part of the image information transferred from the second storage means to the frame buffer memory.

According to the present invention, the enlargement / reduction processing means:
Part of the image information stored in the second storage means is subjected to enlargement / reduction processing, and the image information subjected to the enlargement / reduction processing is transferred to an external output terminal or a frame buffer memory or the like.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor integrated circuit device according to the present invention will be described below in detail with reference to the accompanying drawings.

Embodiment 1 First, a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 1 of the present invention. In FIG. 1, the semiconductor integrated circuit device is the same as that shown in FIG.
0, as in the conventional semiconductor integrated circuit device shown in FIG.
A frame buffer memory 11 constituted by M
A register file 12 constituted by an SRAM;
Data supplied from the register file 12 and external input / output data DQ supplied from the external input / output data terminal 25
0 to DQ31, a comparison unit 14 for comparing these, and the image data stored in the frame buffer memory 11 and the video output data V0 via a video output data terminal 28 of a display device (not shown). Serial access memory (SA
M) 15 and a control unit 16 for performing these controls are formed on at least one semiconductor substrate, and perform high-speed graphic processing while minimizing parasitic capacitance on wiring.

In the first embodiment, the SRAM
And has at least a bus 21 connecting the frame buffer memory 11 and the off-screen memory 20 as a save area for repeatedly used image data.

First, the frame buffer memory 11 is composed of four banks (not shown).
It has 2 × 640 × 8) memory cells and can store 2.6 Mbits of data. Therefore, the frame buffer memory 11 as a whole has a storage capacity of 10.5 megabits, and can store 1/4 frame image data on the display screen of the display device connected to the video output data terminal V0. On the other hand, the register file 12 is composed of eight memory blocks,
Each memory block can store 256 bits of data. Therefore, the register file 12
2 kilobits of data can be stored.

Between the frame buffer memory 11 and the register file 12, a 256-bit global bus 1
7 and the global bus 17 transfers 256 bytes from the frame buffer memory 11 to the register file 12.
Data is transferred in units of bits, and data is transferred from the register file 12 to the frame buffer memory 11 in units of 256 bits. Frame buffer memory 1
If one memory block in the register file 12 is rewritten by the 256-bit data transferred from the register file 12 and data is transferred from the register file 12 to the frame buffer memory 11, one memory block in the register file 12 Will be transferred collectively.

The pixel processing unit 13 converts the 32-bit old data supplied from the register file 12 via the data bus 18 and the new 32-bit data DQ0 to DQ31 supplied via the external input / output data terminal 25. Based on this, predetermined arithmetic processing is performed. Pixel processing unit 1
In No. 3, an α-blend process, which is the basis of the three-dimensional graphics process, and a logical operation process between pixel data called a raster operation are selectively performed. The α-blend process is performed to represent the sense of transparency when three-dimensional graphics are displayed on a display screen, and adjusts the color component output value of each pixel. The 32-bit data, which is the operation result of the pixel processing unit 13, is written back to the register file 12 via the data bus 19.

The comparison unit 14 stores the register file 1
2 and the 32-bit data DQ0 to DQ31 supplied through the external input / output data terminal 25, and outputs the comparison result as a flag signal FLAGOUT. And
Based on this comparison result, the data of the operation result by the pixel processing unit 13 is input to the register file 12 as a flag signal FLGIN indicating whether or not to write the data to the register file 12. Whether to write to the register file 12 is realized by a mask process.

In general, when displaying three-dimensional graphics, each pixel has five data of R, G, B, α, and Z. Here, R, G, and B indicate color data, α indicates a mixing ratio in the above-described α-blend processing, that is, how much old data is mixed with new data, and Z indicates depth information. The larger the value, the farther from the person watching the screen, and the smaller the value, the closer to the person watching the screen. That is, in the comparison unit 14, these R, G,
The data of B, α, and Z will be compared.

The serial access memory 15 reads the data from the frame buffer memory 11 every 640 bits, responds to the video clock signal on the display device side, and outputs the read data via the video output data terminal 28 every 16 bits. To output video output data V0 to the display device.

The control unit 16 responds to a control signal CONT and a clock signal CLK supplied from the outside to control the frame buffer memory 11, the register file 1
2, serial access memory 15, pixel processing unit 1
3 and a control signal for controlling the comparison unit 14. For example, the pixel processing unit 13 operates in response to the control signal CNT1, and the comparison unit 14 operates in response to the control signal CNT2. The data in the register file 12 can be transferred from the external input / output data terminal 25 to the outside via the data bus 19.

The control unit 16 uses the control signal SEL for the frame buffer memory 11
1 controls data transfer between the frame buffer memory 11 and the off-screen memory 20. The control unit 16 sets the control signal SEL to “H” during normal reading / writing via the external input / output data terminal 25, thereby connecting the frame buffer memory 11 and the register file 12 via the global bus 17. Data transfer. Note that the register file 12
The read / write addressing for
Given by

On the other hand, the control unit causes the transfer of data between the frame buffer memory 11 and the off-screen memory 20 via the bus 21 by setting the control signal SEL to “L”. That is, when saving some image data in the frame buffer memory 11 to the off-screen memory 20, the control signal SEL is set to "L" and the image data corresponding to the address designation indicated by the address DAD which is an external address Is transferred to the off-screen memory 20 via the bus 21. The address counter 20 sequentially increments the address of the off-screen memory 20 from “0”, and the transferred image data is sequentially written to the incremented address.

When the image data held in the off-screen memory 20 is transferred to the frame buffer memory 11, the control signal SEL is set to "L" similarly to the transfer from the frame buffer memory 11 to the off-screen memory 20. Is set to And off-screen memory 2
0 is stored in the off-screen memory 2
The image data is sequentially transferred from the address “0” of “0” to the frame buffer memory 11 via the bus 21, and the transferred image data is written to the address of the frame buffer memory 11 indicated by the address DAD.

According to the first embodiment, the off-screen memory 20 is provided as a save area for the image data which is stored in the frame buffer memory 11 and used repeatedly, and the space between the frame buffer memory 11 and the register file 12 is provided. Since the bus 21 for connecting between the frame buffer memory 11 and the off-screen memory 20 is provided separately from the global bus 17 for connection, the frame buffer memory 11 and the off-screen memory 20 via the bus 21 are provided. During the data transfer, the pixel processing unit 13 and the comparison unit 14 can store new data input from the external input / output data terminal 25 and register file data. Keep at 12 The arithmetic processing can be performed on the old data that has been transferred, and the data transfer between the off-screen memory 20 and the frame buffer memory 11 is completed by only one cycle of inputting the transfer source address. Reduced and high-speed data transfer is realized.

Embodiment 2 Next, a second embodiment will be described. In the second embodiment, the address of data transfer between the frame buffer memory 11 and the off-screen memory 20 can be further specified in the first embodiment. This is because in an actual three-dimensional graphics application, data to be transferred is rarely arranged in a continuous address area, and is often transferred in a rectangular area of dots as represented by characters. is there.

FIG. 2 is a block diagram showing a configuration of a semiconductor integrated circuit device according to the second embodiment of the present invention. FIG.
In the second embodiment, the external address DAD
And an internal address, a selector 30 for selecting and switching between the internal address, an internal address counter 31, an internal address register group 32, and an address calculation circuit 33, and other configurations are the same as those of the first embodiment. , The same components are denoted by the same reference numerals.

The address register group 32 is a data register having a start address 32a, a rectangular area width 32b, a rectangular area height 32c, and a rectangular area pitch 32d. The pitch 32d is the number of pixels in the horizontal direction of the entire display screen on which image data is displayed.

Here, the relationship between the entire display screen area and the rectangular area to be transferred will be described with reference to FIG.
In FIG. 3, the width of the region of the entire display screen is 1024 pixels, and the address is the coordinates of a two-dimensional region where the origin is the upper left of the region, x is the right direction from the origin, and y is the downward direction from the origin. Is expressed. The rectangular area to be transferred has the address of the pixel "A" as the start address 32a, the value of the width 32b is "W", and the value of the height 32c is "H". Therefore, the address corresponding to the rectangular area is, starting with the pixel "A" as the start address 32a, incrementing by one address corresponding to one pixel, and reaching the pixel "B" at the right end of the first line of the rectangular area. Then, it is necessary to calculate the address of the pixel "C" at the left end of the next second line.

Therefore, as described above, the number of pixels in the x direction of the entire display screen area is set to “1024” and the pixel “A”
Is (x1, y1) and the width of the rectangular area is “W”, the address value of the pixel “A” is “y1 × 1024”.
+ X1 ”, the address value of the pixel“ B ”is“ y ”
1 × 1024 + x1 + W ”, and the address value of the pixel“ C ”becomes“ (y1
+1) × 1024 + x1 ”. Therefore, the last address value of the pixel “D” at the lower right corner of the rectangular area is
Assuming that the height 32c of the rectangular area is “H”, “(y1 + (H
-1)) × 1024 + x1 + W ”.

The address calculation circuit 33 calculates the address of the rectangular area based on the start address 32a, width 32b, height 32c, and pitch 32d in the address register group 32, and loads the address into the address counter 31. With this load, the value of the address counter 31 is input to the selector 30. On the other hand, the control signal SEL is input not only to the frame buffer memory 11 but also to the selector 30. The selector 30 selects the internal address from the address counter 31 when the control signal SEL is “L”, and selects the external address DAD when the control signal SEL is “H”. This makes it possible to address the image data in the frame buffer memory 11 corresponding to the rectangular area in the display screen, and to transfer the image data in the addressed rectangular area to the off-screen memory 20 at high speed. Can be.

Similarly, when the image data stored in the off-screen memory 20 is transferred to the frame buffer memory 11 via the bus 21, the rectangular area in the frame buffer memory 11 corresponding to the rectangular area in the display screen is also displayed. You can specify the address to write to.

By providing the configuration corresponding to the address counter 31, the address register group 32, and the address calculation circuit 33 in the off-screen memory 20 instead of the configuration of the address counter 22, any of the components stored in the off-screen memory 20 can be stored. The address of the rectangular save area can be specified. By providing such a configuration, the image data in the rectangular save area can be transferred to the frame buffer memory 11 at high speed. In particular, the image data saved in the off-screen memory 20 is repeatedly used. This repetitive use is effective when using a part of the image data in the save area.

According to the second embodiment, it is possible to address image data of a rectangular area in a display screen, which frequently occurs in three-dimensional graphics, and to transfer the image data of the specified rectangular area to a frame buffer. The data can be transferred from the memory 11 to the off-screen memory 20 at high speed, and the data can be transferred from the off-screen memory 20 to the area of the frame buffer memory 11 corresponding to the specified rectangular area at high speed.

Embodiment 3 Next, a third embodiment of the present invention will be described. In the first embodiment, the bus 21
The frame buffer memory 11 and the off-screen memory 20 are connected to each other, but in the third embodiment, the register file 12 and the off-screen memory 20 are connected.

FIG. 4 is a block diagram showing a configuration of a semiconductor integrated circuit device according to the third embodiment of the present invention. FIG.
, The bus 40 connects the register file 12 and the off-screen memory 20. Other configurations are the same as those of the first embodiment, and the same components are denoted by the same reference numerals. However, the configuration of the bus 21 shown in the first embodiment is deleted.

The control unit 16 stores the register file 1
2, a control signal EN is provided, and the control signal EN controls data transfer between the register file 12 and the off-screen memory 20 via the bus 40.

The image data held in the frame buffer memory 11 is transferred to the global bus 1 for arithmetic processing by the pixel processing unit 13 and the comparing unit 14.
7, the image data written into the register file 12 is
At the same time, the image data is transferred to the off-screen memory 20 via the bus 40 and held as image data for evacuating. The control unit 16 sets the control signal EN to “L” when transferring the image data written in the register file 12 to the off-screen memory 20, and when not transferring the image data,
The control signal EN is set to “H”, and transfer of the image data written in the register file 12 to the off-screen memory 20 is prohibited.

On the other hand, data DQ0 to DQ31 input from the external input / output data terminal 25 are
3 performs predetermined arithmetic processing, and the data subjected to the arithmetic processing is transferred to the register file 12 via the data bus 19. When the data is transferred to the register file 12, the control unit 16 controls the control signal EN.
Is set to “L”, the image data saved in the off-screen memory 20 is overwritten in the register file 12 with priority. The overwritten image data is transferred from the register file 12 to the frame buffer memory 11 via the global bus 17 and written. When the image data saved in the off-screen memory 20 is not written in the frame buffer memory 11,
The control unit 16 sets the control signal EN to “H”.

When transferring from the off-screen memory 20 to the register file 12, mask processing for masking an arbitrary bit of the transferred image data can be performed. The bits masked by this masking process invalidate the pixel bits from the off-screen memory 20 and validate the pixel data calculated by the pixel processing unit 13. By performing this mask processing, a sprite operation in three-dimensional graphics is enabled.

In the sprite operation, when a predetermined figure is moved and displayed on the display screen at a high speed, a series of processing of “drawing a figure → erasing a figure → drawing a figure at the next position” must be repeated. However, the speed decreases when the number of displayed figures increases or when moving large figures, so let the hardware remember this figure in advance and just specify the figure number and position. Thus, a required graphic is immediately displayed and a high-speed operation is realized. By performing the mask processing, the sprite operation can be performed.

According to the third embodiment, the image data in the frame buffer memory 11, which is the image data used repeatedly, is saved in the off-screen memory 20 via the register file 12 and the bus 40, and is saved. Image data is stored in bus 40 and register file 1
2, the load on the three-dimensional graphics processing having image data used repeatedly is reduced, and high-speed processing can be realized, as in the first embodiment. .

Embodiment 4 FIG. Next, a fourth embodiment of the present invention will be described. In the fourth embodiment, addressing of a rectangular area similar to that of the second embodiment can be performed with respect to the third embodiment.

FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit device according to the fourth embodiment of the present invention. FIG.
In the fourth embodiment, a selector 50 for selectively switching between an external address and an internal address which are register file addresses RFAD, an internal address counter 31 and an internal address register group 3
2 and an address calculation circuit 33, and the other configuration is the same as that of the third embodiment, and the same components are denoted by the same reference numerals.

The address register group 32 corresponds to the second embodiment.
Similarly to the above, it is a data register having a start address 32a, a width 32b of a rectangular area to be specified, a height 32c of the rectangular area, and a pitch 32d of the rectangular area. The pitch 32d is the number of pixels in the horizontal direction of the entire display screen on which image data is displayed.

The address calculation circuit 33 calculates the register file 12 based on the start address 32a, width 32b, height 32c, and pitch 32d in the address register group 32.
The address of the rectangular area to be transferred from the off-screen memory 20 to the register file 12 is calculated from the off-screen memory 20 and loaded into the address counter 31. By this loading, the value of the address counter 31 is input to the selector 50.

On the other hand, the control signal EN is also input to the selector 50 and instructs the data transfer between the register file 12 and the off-screen memory 20 by “L” as in the third embodiment. , Control signal E
When N is "L", the internal address from the address counter 31 is selected, and when the control signal EN is "H", the external address which is the register file address RFAD is selected. As a result, the image data in the frame buffer memory 11 corresponding to the rectangular area in the display screen can be addressed, and the image data in the addressed rectangular area is stored in the register file 12 and the bus 4.
0 to the off-screen memory 20 at high speed.

Similarly, when transferring the image data stored in the off-screen memory 20 to the frame buffer memory 11 via the bus 40 and the register file 12, the frame buffer memory 11 corresponding to the rectangular area in the display screen is also required. Can specify a write address to a rectangular area in the box.

By providing a configuration corresponding to the address counter 31, the address register group 32, and the address calculation circuit 33 in the off-screen memory 20 instead of the configuration of the address counter 22, any data stored in the off-screen memory 20 can be stored. Of the rectangular save area can be addressed, and by providing such a configuration, the image data of the rectangular save area can be transferred to the bus 40.
In addition, data can be transferred at high speed to the frame buffer memory 11 via the register file 12. In particular, the image data saved in the off-screen memory 20 is repeatedly used. This repetitive use is effective when using a part of the image data in the save area.

According to the fourth embodiment, it is possible to address the image data of the rectangular area in the display screen, which frequently occurs in three-dimensional graphics, and to transfer the image data of the specified rectangular area to the frame buffer. The data can be transferred at high speed from the memory 11 to the off-screen memory 20 via the register file 12, and the register file 12 can be transferred from the off-screen memory 20 to the area of the frame buffer memory 11 corresponding to the specified rectangular area. Data can be transferred at a high speed via the interface, and more diverse attribute processing can be performed.

Embodiment 5 Next, a fifth embodiment of the present invention will be described. In the fifth embodiment, the frame buffer memory 11 and the off-screen memory 60 are connected via the bus 21 similarly to the first embodiment, and the register file 12 is connected to the off-screen memory 60 via the bus 40 similarly to the third embodiment. It is connected to the screen memory 60 so that flexible processing can be realized.

FIG. 6 is a block diagram showing a configuration of a semiconductor integrated circuit device according to the fifth embodiment of the present invention. FIG.
, The off-screen memory 60 accommodates a port accommodating the bus 21 connecting the off-screen memory 60 and the frame buffer memory 11 and a bus 40 connecting the off-screen memory 60 and the register file 12. And two ports.
Other configurations are the same as those of the first or third embodiment.
The same components are denoted by the same reference numerals.

Data transfer between the off-screen memory 60 and the frame buffer memory 11 is performed by the control unit 1.
6 is controlled by a control signal SEL, and data transfer between the off-screen memory 60 and the register file 12 is controlled by a control signal EN by the control unit 16.

Therefore, the control unit 16 always sets the control signal EN to "H", prohibits data transfer between the off-screen memory 60 and the register file 12 via the bus 40, and sets the control signal SEL to "H". By controlling to “L” or “H”, data transfer between the off-screen memory 60 and the frame buffer memory 11 via the bus 21 can be controlled as in the first embodiment.

Conversely, the control unit 16 outputs the control signal SEL
Is always set to “H” to prohibit data transfer between the off-screen memory 60 and the frame buffer memory 11 via the bus 21 and control the control signal EN to “L” or “H”. As in the third embodiment, data transfer between the off-screen memory 60 and the register file 12 via the bus 40 can be controlled. That is, data transfer via the bus 21 or the bus 40 can be selectively controlled.

A control unit SELR for the frame buffer memory 11 and the register file 12 is newly provided by the control unit, and the frame buffer memory 11 and the register file 12 via the global bus 17 are provided.
May be controlled. That is, by setting the control signal SELR to “H”, the frame buffer memory 11 and the register file 1
2 is permitted, and the control signal SELR is set to "L", thereby prohibiting data transfer between the frame buffer memory 11 and the register file 12. If the control signal SELR is set to “L”, data transfer via the global bus 17 becomes impossible, so that the bus 21, the off-screen memory 60 and the bus 4
0 will be transferred. In this case, the off-screen memory 60 functions as a secondary cache memory, and can perform flexible processing selectively.

According to the fifth embodiment, the off-screen memory 60 has two ports connected to the frame buffer memory 11 and the register file 12, respectively, and via any bus depending on the setting of the control signals SEL and EN. Since it is possible to selectively set whether to save the image data that is repeatedly used in the off-screen memory 60, it is possible to perform flexible processing and to use a global bus that connects the frame buffer memory 11 and the register file 12. Prohibition of data transfer can also be set, and in this case, the off-screen memory 60 can be used as a secondary cache memory.

Embodiment 6 FIG. Next, a sixth embodiment of the present invention will be described. In the sixth embodiment, in addition to the configuration of the fifth embodiment, a configuration for specifying an area shown in the fourth embodiment is added.

FIG. 7 is a block diagram showing a configuration of a semiconductor integrated circuit device according to the sixth embodiment of the present invention. FIG.
In this semiconductor integrated circuit device, the address D which is an external address to the frame buffer memory 11 is
A selector 30 for selectively switching between AD and an internal address, a selector 50 for selectively switching between an address RFAD, which is an external input address to the register file 12, and an internal address, an address counter 31, an address register group 32, and an address calculation circuit 33. Have. Other configurations are the same as those of the fifth embodiment, and the same components are denoted by the same reference numerals.

The address register group 32 corresponds to the second embodiment.
Similarly to the above, it is a data register having a start address 32a, a width 32b of a rectangular area to be specified, a height 32c of the rectangular area, and a pitch 32d of the rectangular area. The pitch 32d is the number of pixels in the horizontal direction of the entire display screen on which image data is displayed.

The address calculation circuit 33 calculates the register file 12 based on the start address 32a, width 32b, height 32c, and pitch 32d in the address register group 32.
Then, the address of a rectangular area to be transferred from the off-screen memory 60 to the register file 12 is calculated from the off-screen memory 60 and loaded into the address counter 31. By this loading, the value of the address counter 31 is input to the selector 30 and the selector 50. The selector 30 selects an internal address from the address counter 31 when the control signal SEL is “L”, and selects an address D which is an external address when the control signal SEL is “H”.
Select AD. On the other hand, the selector 50 outputs the control signal EN
Is "L", the internal address from the address counter 31 is selected, and when the control signal EN is "H", the address RFAD which is an external address is selected.

The image data stored in the off-screen memory 60 is transferred to the frame buffer 1 via the bus 21.
1 or when transferring the image data stored in the off-screen memory 60 to the register file 12 via the bus 40, the area or the register in the frame buffer memory 11 corresponding to the rectangular area in the display screen. A write address to an area in the file 12 can be specified.

By providing a configuration corresponding to the address counter 31, the address register group 32, and the address calculation circuit 33 in the off-screen memory 60 instead of the configuration of the address counter 22, an arbitrary configuration stored in the off-screen memory 60 can be obtained. Of the rectangular save area can be addressed, and by providing such a configuration, the image data in the rectangular save area can be transferred to the frame buffer memory 11 or the register file 12 at high speed. .

According to the sixth embodiment, it is possible to address the image data of the rectangular area in the display screen, which frequently occurs in three-dimensional graphics, and to transfer the image data of the specified rectangular area to the frame buffer. High-speed data transfer from the memory 11 to the off-screen memory 60 and high-speed data transfer from the off-screen memory 60 to an area of the frame buffer memory 11 corresponding to a specified rectangular area are possible. . Further, since data of an arbitrary rectangular area in the register file 12 can be saved in the off-screen memory 60, more various attribute processes can be performed.

Embodiment 7 FIG. Next, a seventh embodiment of the present invention will be described. The port of the external output terminal is connected to the off-screen memory in the configuration of the first embodiment, so that the processing load on the saved image data is reduced.

FIG. 8 is a block diagram showing a configuration of a semiconductor integrated circuit device according to the seventh embodiment of the present invention. FIG.
, The off-screen memory 80 connected to the bus 21 is connected to the external output terminal 81 and the external output terminal 8
1 to output the image data stored in the off-screen memory 80 as the external output signal TD. Other configurations are the same as those of the first embodiment, and the same components are denoted by the same reference numerals.

The external output signal TD is input to a drawing controller 82 formed on the same semiconductor substrate via a dedicated bus. The drawing controller 82 has a texture processing unit 83 for performing texture processing, a pixel processing unit 84 for performing pixel processing, and a frame memory control unit 85, and outputs a processing result to the external input / output data terminal 25. In the drawing process, there is an application that pastes image data as texture data to a three-dimensional graphics object. In this application, for example, data of an object in the frame buffer memory 11 that has been three-dimensionally processed is reflected on a mirror as data reflected on the mirror, thereby enabling high-speed display without performing complicated calculations and drawing processing. I do.

For such a pasting process, it is necessary to read out from the frame buffer memory 11 once and process it on the drawing controller 82 side. In the seventh embodiment, the image data transferred from the frame buffer memory 11 is Can be saved in the off-screen memory 80, and the image data saved from the off-screen memory 80 can be directly output from the external output terminal 81 to the drawing controller 82 by designating the address SAD.

Incidentally, similarly to the third embodiment, the case where a bus is provided between the register file 12 and the off-screen memory 80 can be similarly applied. Further, similarly to the fifth embodiment, a case where a bus is provided between the register file 12 and the off-screen memory 80 to selectively perform data transfer can be applied. Further, the configuration may be such that the address of an arbitrary rectangular area described in the second, fourth, and sixth embodiments is specified.

According to the seventh embodiment, by providing a dedicated bus connected to the external output terminal 81 of the off-screen memory 80 on the drawing controller 82 side, the calculation by the pixel processing unit 13 and the comparison unit 14 can be performed. In parallel with the processing, the image data saved in the off-screen memory 80 can be read, and the speeding up of the display processing can be promoted.

Embodiment 8 FIG. Next, an eighth embodiment of the present invention will be described. In the eighth embodiment, an enlargement / reduction circuit 90 is provided between the external output terminal 81 and the off-screen memory 80 in the configuration of the seventh embodiment, and enlargement / reduction processing is performed on the saved image data. The output signal TD is transferred to the frame buffer memory 11.

FIG. 9 is a block diagram showing a configuration of a semiconductor integrated circuit device according to the eighth embodiment of the present invention. FIG.
, The external output terminal 81 and the off-screen memory 8
An enlargement / reduction circuit 90 is provided between 0 and 0. Other configurations are the same as those of the seventh embodiment, and the same components are denoted by the same reference numerals. The scaling circuit 90 performs scaling processing on the image data saved in the off-screen memory 80. For example, the enlargement / reduction circuit 90 can be realized by a simple thinning process or a bilinear interpolation circuit.

The image data output from the frame buffer memory 11 to the outside via the off-screen memory 80 can be used, for example, as a texture. Textures need to be of the same shape but of different sizes so that, for example, trees planted along the road appear smaller as they get further away. Therefore, if the image data in the frame buffer memory 11 can be changed to an arbitrary size, the processing on the drawing controller 82 side is simplified, and the load is reduced. In the eighth embodiment, the off-screen memory 80
The image data once saved to the arbitrary size by the enlargement / reduction circuit 90 is output to the external output terminal 81.
, The load on the drawing controller 82 is reduced.

The image data saved in the off-screen memory 80 may be temporarily processed to an arbitrary size by an enlargement / reduction circuit and then transferred to the frame buffer memory 11 again. Furthermore, high-speed data transfer may be realized by applying the configuration for addressing an arbitrary rectangular area described in the second, fourth, and sixth embodiments.

According to the eighth embodiment, between the external output terminal 81 and the off-screen memory 80, the scaling circuit 90 for scaling the image data saved in the off-screen memory 80 is provided. Therefore, the load on image processing can be dispersed, and the processing speed can be improved.

[0090]

As described above, according to the present invention, the transfer control means makes the transfer of image information between the frame buffer memory and the first storage means via the first bus independent. Transferring part of image information in the image information stored in the frame buffer memory to the second storage means via a second bus connecting the frame buffer memory and the second storage means. Alternatively, a part of the image information stored in the second storage means is transferred to the frame buffer memory, so that a part of the image information can be transferred separately from the image calculation processing by the calculation means. Therefore, the load on the image calculation processing and the like by the calculation means is reduced, and the effect is achieved that high-speed data transfer of the entire semiconductor integrated circuit device is realized.

According to the next invention, when the transfer control means transfers the image information between the frame buffer memory and the first storage means via the first bus, the transfer control means sets the first storage means and the second storage means Via a third bus connecting the storage means, a part of the image information in the image information stored in the first storage means is transferred to the second storage means, or the second Since a part of the image information stored in the storage means is controlled to be transferred to the first storage means,
This has the effect of reducing the processing load on repeatedly used image data and realizing high-speed data transfer of the entire semiconductor integrated circuit device.

According to the next invention, the transfer control means controls the transfer of the frame buffer memory independently of the transfer of the image information between the frame buffer memory and the first storage means via the first bus. Via a second bus connecting the second storage means, transfer some image information in the image information stored in the frame buffer memory to the second storage means, or, A part of the image information stored in the storage means is transferred to the frame buffer memory so that a part of the image information can be transferred separately from the image calculation processing by the calculation means. When transferring image information between the frame buffer memory and the first storage means via the bus, the third bus connecting the first storage means and the second storage means, One memory Transferring a part of the image information in the image information stored in the row to the second storage means, or transferring a part of the image information stored in the second storage means to the first storage means Since the transfer control of causing the image information to be transferred is selectively performed, an effect is obtained that the transfer processing of a part of the image information that is repeatedly used can be flexibly performed.

According to the next invention, the area designating means designates a storage area of the partial image information, for example, a rectangular area, corresponding to the image information displayed on the display means. According to the designation, the transfer source area or the transfer destination area of the frame buffer memory, the first storage means or the second storage means is collectively specified and transferred, so that high-speed data transfer can be realized. This has the effect.

According to the next invention, the second storage means is connected to the external output terminal via the fourth bus, and the transfer output control means stores part of the image information stored in the second storage means. Since it is possible to output to the outside, for example, by providing a dedicated bus for connecting the drawing controller side and the external output terminal, the drawing controller side is stored in the second storage means in parallel with the arithmetic processing. Thus, it is possible to read some of the image information, and the speed of processing can be further accelerated.

According to the next invention, the enlargement / reduction processing means performs the enlargement / reduction processing on a part of the image information stored in the second storage means, and outputs the image information subjected to the enlargement / reduction processing to an external device. Since the data is transferred and output to the terminal or the frame buffer memory, it is possible to distribute the load on the image processing and improve the processing speed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention;

FIG. 2 is a block diagram illustrating a configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention;

FIG. 3 is a diagram illustrating the contents of an area designation address according to the second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a third embodiment of the present invention;

FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a fourth embodiment of the present invention;

FIG. 6 is a block diagram illustrating a configuration of a semiconductor integrated circuit device according to a fifth embodiment of the present invention;

FIG. 7 is a block diagram illustrating a configuration of a semiconductor integrated circuit device according to a sixth embodiment of the present invention;

FIG. 8 is a block diagram illustrating a configuration of a semiconductor integrated circuit device according to a seventh embodiment of the present invention;

FIG. 9 is a block diagram illustrating a configuration of a semiconductor integrated circuit device according to an eighth embodiment of the present invention;

FIG. 10 is a block diagram showing a configuration of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

11 frame buffer memory, 12 register file, 13 pixel processing unit, 14 comparison unit, 1
5 serial access memory, 16 control units, 1
7 Global bus, 18, 19 Global bus, 2
0, 60, 80 off-screen bus, 21, 40 bus, 22, 31 address counter, 30, 50 selector, 33 address calculation circuit, 32 address register group, DAD, RFAD address, DQ0-DQ31
External input / output data, CONT, SEL, EN, CNT
1, CNT2 control signal, V0 video output data, F
LAGIN, FLAGOUT flag signal, CLK clock signal.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 5/399

Claims (6)

[Claims] An image processing operation for image information to be output from a frame buffer memory to a display means based on a frame buffer memory and image information held in the frame buffer memory and image information externally input. The calculating means for performing the processing and the first storage means connected to the frame buffer memory via the first bus and storing the image information or the image processing result of the processing by the calculating means are at least on the same semiconductor substrate. In the semiconductor integrated circuit device formed in the above, the second storage means for storing a part of the image information in the image information stored in the frame buffer memory, the frame buffer memory and the second storage means A second bus to be connected, and a part of image information stored in the frame buffer memory via the second bus. A semiconductor integrated circuit device, comprising: transfer control means for performing control for mutually transferring image information and a part of the image information stored in the second storage means. 2. An image processing operation for image information to be output from the frame buffer memory to a display means based on a frame buffer memory and image information held in the frame buffer memory and image information input externally. The calculating means for performing the processing and the first storage means connected to the frame buffer memory via the first bus and storing the image information or the image processing result of the processing by the calculating means are at least on the same semiconductor substrate. In the semiconductor integrated circuit device formed in the above, a second storage means for storing a part of the image information stored in the first storage means, the first storage means and the second storage means A third bus to be connected; a part of image information stored in the first storage means via the third bus; and a part of image information stored in the second storage means. And a transfer control means for performing control to transfer image information to each other. 3. An image processing operation for image information to be output from a frame buffer memory to a display means based on a frame buffer memory and image information held in the frame buffer memory and image information input externally. The calculating means for performing the processing and the first storage means connected to the frame buffer memory via the first bus and storing the image information or the image processing result of the processing by the calculating means are at least on the same semiconductor substrate. In the semiconductor integrated circuit device formed in the above, the second storage for storing a part of the image information in the image information stored in the frame buffer memory or a part of the image information stored in the first storage means Means, a second bus connecting the frame buffer memory and the second storage means, and the first storage means and the second bus. A third bus connecting the second storage means, a part of the image information in the image information stored in the frame buffer memory via the second bus, and the third bus stored in the second storage means; A control for mutually transferring a part of the image information and a part of the image information stored in the first storage unit and the part of the image information stored in the second storage unit via the third bus. And a transfer control means for selectively performing control for mutually transferring image information. 4. The image processing apparatus according to claim 1, further comprising an area designating unit for designating a storage area of said part of the image information corresponding to the image information displayed on said display unit. A semiconductor integrated circuit device according to one of the above aspects. 5. An external output terminal; a fourth bus connecting the second storage means and the external output terminal; and a part of image information stored in the second storage means to the external bus. The semiconductor integrated circuit device according to any one of claims 1 to 4, further comprising: a transfer output control unit configured to perform transfer output via an output terminal. 6. A part of the image information provided between the second storage means and the external output terminal and transferred from the frame buffer memory to the second storage means or the second storage means. 6. The semiconductor integrated circuit device according to claim 5, further comprising an enlargement / reduction processing means for performing an enlargement / reduction processing on a part of the image information transferred from the memory to the frame buffer memory.