JP2012053762A - Data input/output control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data input/output control device which is excellent in reliability for writing control data in an input/output device without generating any error.SOLUTION: A CPU 1 address-designates an input terminal corresponding to a necessary control command, and outputs control data of 16 bits whose all bits are set to logic "1". A GPIO 30 fetches only input control data to the address-designated input terminal among control data input to each input terminal, and stores the fetched control data by a flip flop corresponding to the address-designated input terminal. The control data are output in which only the bits of an output terminal corresponding to the flip flop are set to logic "1" while the bits of the residual output terminals are not set to logic "1" from each output terminal.

Description

  Embodiments described herein relate generally to a data input / output control device including a controller and an input / output device that holds and outputs control data generated from the controller.

  A general-purpose input / output device so-called GPIO (General Purpose Input / Output) that is connected between a controller and a device to be controlled and holds and outputs control data emitted from the controller is known (for example, Patent Document 1).

  When the controller wants to change the control data held in GPIO to new control data, it reads the control data in GPIO and stores it in an internal register, modifies the control data in that register on the same register, and so on. Read / modify / write processing to write to GPIO.

JP 11-134250 A

  When an interrupt process is entered during the read / modify / write process, the controller saves the control data in the register to the memory at the timing between read and modify or between modify and write. The interrupt process is executed later, and after the interrupt process is completed, the process of returning the control data in the memory to the register is performed.

  In this case, an error may occur in the control data while the control data is saved or returned. As a countermeasure, it may be possible not to accept interrupt processing during read-modify-write processing. However, if this is done, there is a problem in that the performance of the device in which the controller is mounted deteriorates.

  An object of an embodiment of the present invention is to provide a highly reliable data input / output control apparatus capable of writing control data to an input / output device without error.

  A data input / output control device according to an embodiment of the present invention includes a controller that issues control data for a control target device, a plurality of input terminals connected to the controller, and a plurality of output terminals connected to the control target device. And an input / output device in which a plurality of control commands for the device to be controlled are assigned to each input terminal. When a control command for the control target device is required, the controller addresses the input terminal to which the required control command is assigned among the input terminals of the input / output device, and all the bits are predetermined. The control data that becomes the logical value of is output. The input / output device captures and holds only the input control data to the addressed input terminal among the control data input to each input terminal, so that the output terminal corresponding to the addressed input terminal Only the bits have a predetermined logical value, and the control data in which the remaining output terminal bits do not have the predetermined logical value is output from each output terminal.

The block diagram which shows the structure of one Embodiment. The block diagram which shows the principal part of GPIO of one Embodiment. The figure which shows the response | compatibility with each control command and the address of each input terminal to which each control command was allocated in one Embodiment, and the operation pattern of each flip-flop. The figure which shows the example of a response | compatibility with each control command and the address of each input terminal to which each control command was assigned, and the output of each output terminal in one Embodiment.

  1 ... CPU (controller), 2 ... internal memory, 3 ... internal register, 4 ... input / output interface, 11 ... address bus, 12 ... 16-bit data bus, 13 ... control bus, 20 ... memory, 30 ... GPIO (input Output device), 32 ... Data input port, 35 ... Data output port, 41, 51 ... 8-bit data bus, 42, 52 ... Driver (device to be controlled), 43, 53 ... Step motor, 60 ... Mode switch

Hereinafter, an embodiment will be described with reference to the drawings.
In FIG. 1, reference numeral 1 denotes a CPU which is a controller of an embedded device, which has an internal memory 2 and an internal register 3, and issues 16-bit control data as a control command for driving and controlling step motors 43 and 53 described later.

  The CPU 1 is connected to an input interface 4 that takes in input data from an external device or an operation unit. Further, a data storage memory 20 is connected to the CPU 1 via a several-bit address bus 11, a 16-bit data bus 12, and a several-bit control bus 13. Further, a general-purpose input / output device so-called GPIO (General Purpose Input / Output) 30 is connected to the CPU 1 through the address bus 11, the data bus 12, and the control bus 13.

  The GPIO 30 includes an address input port 31 to which the address bus 11 is connected, a data input port 32 to which the data bus 12 is connected, a control signal input port 33 to which the control bus 13 is connected, a mode signal input port 34, and a data output port. 35.

  As shown in FIG. 2, the data input port 32 includes 16 input terminals to which the 16-bit data bus 12 is connected. Addresses from 1000H to 1015H are set to these input terminals, and a plurality of control commands for drivers 42 and 52 described later are assigned.

  The mode signal input port 34 is connected to an interconnection point between a manually operated open / close mode switch 60 and a resistor 61 as mode setting means for selectively setting the first light mode and the second light mode. A DC voltage Vd is applied to the series circuit of the mode switch 60 and the resistor 61, and a voltage generated in the resistor 61 is input to the mode signal input port 34 as a mode setting signal. That is, when the mode switch 60 is turned on, the mode setting signal becomes logic “1” to set the first write mode, and when the mode switch 60 is turned off, the mode setting signal becomes logic “0” and the second The light mode is set. The mode setting signal is also supplied to the CPU 1.

  As shown in FIG. 2, the data output port 35 includes 16 output terminals for outputting 16-bit control data. These output terminals are named D0 to D15. Then, 16 flip-flops F0 to F15 corresponding to these output terminals D0 to D15 are provided in the GPIO 30, and output terminals of these flip-flops F0 to F15 are connected to the output terminals D0 to D15.

  Among the output terminals D0 to D15 of the data output port 35, the first control target device, for example, the driver 42 is connected to the output terminals D0 to D7 via the 8-bit data bus 41, and 8 is connected to the remaining output terminals D8 to D15. A second control target device such as a driver 52 is connected via a bit data bus 51.

  The driver 42 has a specification that matches the first write mode of the CPU 1 and the GPIO 30, and among the control data of 8 bits output from the output terminals D0 to D7 of the GPIO 30, a logical “1” (= predetermined logical value) The step motor 43 is driven by the operation mode assigned to the bit to be), for example, the excitation method and current. The driver 52 also has a specification adapted to the first write mode of the CPU 1 and the GPIO 30, and among the control data of 8 bits output from the output terminals D8 to D15 of the GPIO 30, a logic “1” (= predetermined logic) The step motor 53 is driven by the operation mode assigned to the bit (value), for example, the excitation method and current.

  The specifications of the drivers 42 and 52 include a specification corresponding to the read / modify / write processing corresponding to the second write mode of the CPU 1 and GPIO 30 in addition to the specification adapted to the first write mode of the CPU 1 and GPIO 30. . The driver 42 having the specifications corresponding to the read-modify-write process identifies the excitation method and current as the operation mode from the code pattern of the 8-bit control data output from the output terminals D0 to D7 of the GPIO 30, and identifies the identified excitation. The step motor 43 is driven by the method and current. Similarly, the driver 52 having the specifications corresponding to the read / modify / write process determines the excitation method and current as the operation mode based on the code pattern of the 8-bit control data output from the output terminals D8 to D15 of the GPIO 30. Then, the step motor 53 is driven with the determined excitation method and current.

  In the internal memory 2 of the CPU 1, the first data file in which a plurality of control commands for the drivers 42 and 52 are associated with the addresses 1000H to 1015H of the input terminals to which the control commands are assigned, and the control for the drivers 42 and 52. A second data file storing a plurality of different code patterns for each command is stored.

The CPU 1 has the following means (1) and (2) as main functions.
(1) At the time of setting the first light mode by turning on the mode switch 60, if a control command for the driver 42 or the driver 52 is required, the input to which the required control command is assigned among the input terminals of the GPIO 30 The address of the terminal is detected from the first data file in the internal memory 2, address designation data for designating the detected address is supplied to the GPIO 30, and all bits are set to logic “1” (= predetermined logic value). Means for outputting control data.

  (2) When the second write mode is set by turning off the mode switch 60, if a control command to the driver 42 or the driver 52 is required, the control required among the code patterns in the second data file of the internal memory 2 is required. The code pattern corresponding to the command is extracted, the control data held in the GPIO 30 is read and stored in the internal register 3, and the control data in the internal register 3 is matched with the extracted code pattern. Means for read-modify-write processing after modifying (including masking) and writing to GPIO 30 above. In this read-modify-write process, for example, when some interrupt process is performed by data input from the input interface 4, the control in the internal register 3 is performed at the timing between read and modify or at the timing between modify and write. The data is saved in the memory 20, interrupt processing is executed after the saving, and the control data in the memory 20 is returned to the internal register 3 after the interrupt processing is completed.

The GPIO 30 has the following means (11) and (12) as main functions.
(11) When the first write mode is set by turning on the mode switch 60, only the control data input to the input terminal addressed by the CPU 1 among the control data input to each input terminal of the data input port 32 is fetched. By holding the received control data in the flip-flop corresponding to the input terminal designated by the same address, only the bit of the output terminal corresponding to the flip-flop becomes logic “1” (= predetermined logic value) and the remaining Means for outputting control data from each output terminal of the data output port 35 in which the bit of the output terminal does not become logic “1” (= predetermined logic value).

  (12) When the second write mode is set by turning off the mode switch 60, the control data input to each input terminal of the data input port 32 is fetched and held by each flip-flop, and the held control data is sent to each output terminal. Function to output from.

Next, the operation will be described.
If the specifications of the drivers 42 and 52 are specifications that match the first write mode of the CPU 1 and the GPIO 30, the mode switch 60 is turned on. When the mode switch 60 is turned on, the CPU 1 and the GPIO 30 set the first write mode.

  For the first write mode, as shown in FIG. 3, among the input terminals of the addresses 1000H to 1015H in the GPIO 30, the operation mode “one phase excitation” of the driver 42 is applied to the input terminals of the 8-bit addresses 1000H to 1007H. “2-phase excitation” “1-2-phase excitation” “micro-step drive” “1-phase excitation and current increase” “2-phase excitation and current increase” “1-2-phase excitation and current increase” “micro-step drive and current increase” Each of the control commands for setting "" is assigned. For the remaining 8-bit addresses 1008H to 1015H, the operation mode of the driver 52 is “1 phase excitation”, “2 phase excitation”, “1-2 phase excitation”, “microstep drive”, “1 phase excitation and current increase” Control commands for setting “2-phase excitation and current increase”, “1-2-phase excitation and current increase”, and “microstep drive and current increase” are assigned.

  As shown in FIG. 3, when the input terminal at the address 1000H corresponding to the control command “one-phase excitation” for the driver 42 is designated, the GPIO 30 sets the flip-flop F0 in an active state (marked with a circle). Similarly, when the input terminal of the address 1001H corresponding to the control command “two-phase excitation” for the driver 42 is designated, the flip-flop F1 is activated. When the input terminal of the address 1002H corresponding to the control command “1-2 phase excitation” for the driver 42 is designated, the flip-flop F2 is activated. When the input terminal of the address 1003H corresponding to the control command “microstep drive” for the driver 42 is designated, the flip-flop F3 is activated. When the input terminal of the address 1004H corresponding to the control command “1 phase excitation and current increase” for the driver 42 is designated, the flip-flop F4 is activated. When the input terminal of the address 1005H corresponding to the control command “two-phase excitation and current increase” for the driver 42 is designated, the flip-flop F5 is activated. When the input terminal of the address 1006H corresponding to the control command “1-2 phase excitation and current increase” for the driver 42 is designated, the flip-flop F6 is activated. When the input terminal of the address 1007H corresponding to the control command “microstep drive and current increase” is designated, the flip-flop F7 is activated. The flip-flop corresponding to the input terminal without addressing is reset and made inactive.

  When the input terminal of the address 1008H corresponding to the control command “1 phase excitation” for the driver 52 is designated, the flip-flop F8 is activated. Similarly, when the input terminal of the address 1009H corresponding to the control command “two-phase excitation” for the driver 52 is designated, the flip-flop F9 is activated. When the input terminal of the address 1010H corresponding to the control command “1-2 phase excitation” for the driver 52 is designated, the flip-flop F10 is activated. When the input terminal of the address 1011H corresponding to the control command “microstep drive” for the driver 52 is designated, the flip-flop F11 is activated. When the input terminal of the address 1012H corresponding to the control command “1 phase excitation and current increase” for the driver 52 is designated, the flip-flop F12 is activated. When the input terminal of the address 1013H corresponding to the control command “two-phase excitation and current increase” for the driver 52 is designated, the flip-flop F13 is activated. When the input terminal of the address 1014H corresponding to the control command “1-2 phase excitation and current increase” for the driver 52 is designated, the flip-flop F14 is activated. When the input terminal of the address 1015H corresponding to the control command “microstep drive and current increase” is designated, the flip-flop F15 is activated. The flip-flop corresponding to the input terminal without addressing is reset and made inactive.

  When setting “2-phase excitation” of the driver 42 and “1-2-phase excitation” of the driver 52, the CPU 1 addresses the input terminal of the address 1001H and the input terminal of the address 1010H of the GPIO 30, respectively, and sets all bits. Outputs 16-bit control data “1111111111111111” having a logic “1”.

  In this case, in the GPIO 30, the flip-flop F1 corresponding to the input terminal of the address 1001H and the flip-flop F10 corresponding to the input terminal of the address 1010H are in the active state to accept the control data input, and the remaining flip-flops are reset. Moreover, it becomes inactive. When the control data “1111111111111111” is input in this state, as shown in FIG. 4, flip-flop F1 and flip-flop F10 are set and output logic “1”, and the output of the remaining flip-flops is logic “0”. " Thus, 16-bit control data “0000010000000010” is output from the output terminals D0 to D15.

  Of the output control data “0000010000000010”, the lower 8 bits “00000010” are supplied to the driver 42, and the upper 8 bits “00000100” are supplied to the driver 52.

  The driver 42 sets the two-phase excitation as the operation mode because the second bit of the input 8-bit control data “00000010” is logic “1”, and drives the step motor 43 by the two-phase excitation. Since the third bit of the input 8-bit control data “00000100” is logic “1”, the driver 52 sets the 1-2 phase excitation as the operation mode, and the step motor 43 is set by the 1-2 phase excitation. To drive.

  As described above, only the 16-bit control data “1111111111111111” in which all the bits are logic “1” is output and the input terminal corresponding to the necessary control command is addressed. Control data without error can be written into the GPIO 30. Therefore, an appropriate control command without error can be sent to the drivers 42 and 52, and high reliability as a data input / output control device can be secured. Even if an interrupt process is entered, the interrupt process can be executed immediately without requiring any action such as saving or returning the control data. This leads to an improvement in performance of an embedded device in which the data input / output control device is mounted.

  The drivers 42 and 52 only set the operation mode associated with the logic “1” bit among the bits of the input control data, and control is performed as in the case of the read-modify-write process. Since the process for identifying the data code pattern is not required, the configuration can be simplified and the cost can be reduced.

  If the specifications of the drivers 42 and 52 correspond to the read / modify / write process, the read / modify / write process can be executed by turning off the mode switch 60 and setting the second write mode. It is. In this respect, versatility can be improved.

  The above embodiment is presented as an example, and is not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, rewrites, and changes can be made without departing from the scope of the invention. The scope of the invention is included in the gist of the embodiments and modifications, and is included in the invention recorded in the claims and the equivalents thereof.

Claims (7)

A controller that emits control data for the control target device;
An input / output device having a plurality of input terminals connected to the controller and a plurality of output terminals connected to the control target device, wherein a plurality of control commands for the control target device are assigned to each input terminal;
With
When the control command for the control target device is required, the controller addresses the input terminal to which the required control command is assigned among the input terminals of the input / output device, and all bits are set. Output control data with a predetermined logical value,
The input / output device captures and holds only the input control data to the addressed input terminal among the control data input to each input terminal, so that an output terminal corresponding to the addressed input terminal Only the bits of the above become a predetermined logical value and the control data that does not become the predetermined logical value of the remaining output terminal bits are output from each output terminal.
A data input / output control device. The control target device operates in an operation mode assigned to a bit having a predetermined logical value among the bits of control data output from the input / output device.
The data input / output control device according to claim 1. Storage means for storing a plurality of control commands for the device to be controlled and addresses of input terminals to which the control commands are assigned in association with each other,
The data input / output control device according to claim 1, further comprising: The control target devices are a first control target device and a second control target device,
When the controller requires a control command for any of the devices to be controlled, among the input terminals of the input / output device, the input terminal to which the required control command is assigned is addressed, Output control data in which all bits have a predetermined logical value.
3. The data input / output control device according to claim 1, wherein the data input / output control device is a data input / output control device. The input / output device includes a plurality of input terminals connected to the controller and assigned with a plurality of control commands for the control target device at respective addresses, a plurality of flip-flops corresponding to the input terminals, and the flip-flops A plurality of output terminals connected to the control target device and connected to the output terminal of the control terminal, taking only the input control data to the addressed input terminal out of the control data input to each input terminal, By holding the captured control data in the flip-flop corresponding to the input terminal designated by the same address, only the bit of the output terminal corresponding to the flip-flop becomes a predetermined logical value, and the bits of the remaining output terminals are predetermined. Control data that does not become the logical value of is output from each output terminal.
5. The data input / output control device according to claim 1, wherein the data input / output control device is a data input / output control device. Mode setting means for selectively setting the first light mode and the second light mode;
When the controller requires a control command for the device to be controlled when the first light mode is set, an input terminal to which the required control command is assigned among the input terminals of the input / output device. Means for addressing and outputting control data in which all bits have a predetermined logical value, and when setting the second light mode, if a control command is required for the control target device, the required control command Is extracted from the storage means, and the control data held in the input / output device is read and stored in the internal register, and the control data in the internal register is matched with the extracted code pattern. Read-modify-write processing means to write to the input / output device after modifying on the internal register Look,
When the first write mode is set, the input / output device captures and holds only the input control data to the addressed input terminal among the control data input to each input terminal, thereby specifying the same address. Means for outputting control data from each output terminal in which only the bit of the output terminal corresponding to the inputted input terminal has a predetermined logical value and the bits of the remaining output terminals do not have the predetermined logical value; Means for fetching and holding control data input to each input terminal at the time of setting, and outputting the held control data from each output terminal;
The data input / output control device according to claim 1. The input / output device is connected to the controller and has a plurality of input terminals to which a plurality of control commands for the control target device are assigned to respective addresses, a plurality of flip-flops corresponding to these input terminals, A plurality of output terminals connected to the output terminal and connected to the device to be controlled, and the addressed input terminal of the control data input to each input terminal when the first light mode is set Only the input control data to the input terminal is fetched, and the fetched control data is held in the flip-flop corresponding to the input terminal designated by the same address, so that only the bit of the output terminal corresponding to the same flip-flop becomes a predetermined logical value. The remaining output terminal bits output control data from each output terminal that does not have a predetermined logic value. And stage, setting of the second write mode, and a function of said held by the flip-flops by captures and control data input to the input terminals, and outputs the held control data from the output terminals,
The data input / output control device according to claim 6.

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