JP2012050328A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2012050328A
JP2012050328A JP2011253468A JP2011253468A JP2012050328A JP 2012050328 A JP2012050328 A JP 2012050328A JP 2011253468 A JP2011253468 A JP 2011253468A JP 2011253468 A JP2011253468 A JP 2011253468A JP 2012050328 A JP2012050328 A JP 2012050328A
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mosfet
insulated gate
semiconductor element
terminal
power supply
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JP5041496B2 (en
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Takayuki Iwasaki
貴之 岩崎
Mitsuzo Sakamoto
光造 坂本
Masaki Shiraishi
正樹 白石
Nobuyasu Matsuura
伸悌 松浦
Tomoaki Uno
友彰 宇野
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that suppresses self-turn-on of a MOSFET, and enhances the power supply efficiency, without causing an increase in drive loss, in a power supply unit of synchronous rectification type.SOLUTION: In a power supply unit, the gate size of a MOSFET (2) for rectification, constituting a synchronous rectification circuit, is made smaller than the gate size of a MOSFET (3) for commutation. Furthermore, a threshold of the MOSFET for commutation is made higher than a threshold of the MOSFET for rectification. For example, the threshold of the MOSFET for commutation is set to be 0.5 V higher than the threshold of the MOSFET for rectification, the threshold of the MOSFET for rectification is set to be 1.5 V or less, and the threshold of the MOSFET for commutation is set to be 2.0 V or more.

Description

本発明は電源装置に係り、特に電子機器等に用いられる同期整流回路及び電源装置に関する。   The present invention relates to a power supply device, and more particularly, to a synchronous rectifier circuit and a power supply device used for electronic equipment and the like.

従来技術の電源装置として図2に示すものが知られており、直流入力電源60から入力コンデンサ61を含んで構成された入力部51に入力された直流電力を駆動部70から出力される制御信号に基づいてスイッチング部52でスイッチングし、ダイオード63や出力フィルタ55を含んで構成された出力部53から負荷66に対して電力を供給する。また、負荷66へ出力される電圧や電流は検出部67で検出され、この検出値と設定部68で設定された負荷66の制御目標値とが比較演算部69で比較され、駆動部70から比較結果に基づいた制御信号がスイッチング部52に出力される。   2 is known as a power supply device of the prior art, and a control signal output from a drive unit 70 is a DC power input from a DC input power source 60 to an input unit 51 including an input capacitor 61. Is switched by the switching unit 52, and power is supplied to the load 66 from the output unit 53 including the diode 63 and the output filter 55. The voltage or current output to the load 66 is detected by the detection unit 67, and the detected value and the control target value of the load 66 set by the setting unit 68 are compared by the comparison calculation unit 69. A control signal based on the comparison result is output to the switching unit 52.

図2の電源装置の具体的な回路構成を図3に示す。スイッチング部52は、能動素子(例えばトランジスタやMOSFET等)62で構成されている。出力部53は、転流ダイオード63と、チョークコイル64及びコンデンサ65で構成された出力フィルタ55とで構成されている。制御部54は、比較演算部69、設定部68、駆動部70で構成されている。さらに、制御部54は図示しない発振回路を備えており、駆動部70からパルス信号を能動素子62に出力する。これにより能動素子62に印加される直流入力電源60からの直流電圧Vinがスイッチングされる。   A specific circuit configuration of the power supply device of FIG. 2 is shown in FIG. The switching unit 52 includes an active element 62 (for example, a transistor or a MOSFET). The output unit 53 includes a commutation diode 63 and an output filter 55 including a choke coil 64 and a capacitor 65. The control unit 54 includes a comparison calculation unit 69, a setting unit 68, and a drive unit 70. Further, the control unit 54 includes an oscillation circuit (not shown), and outputs a pulse signal from the driving unit 70 to the active element 62. As a result, the DC voltage Vin from the DC input power supply 60 applied to the active element 62 is switched.

図3の電源装置では、能動素子62がオンの場合には、直流電力はチョークコイル64及びコンデンサ65にチャージされると共に負荷66へ供給される。能動素子62がオフの場合は、チョークコイル64及びコンデンサ65にチャージされていたエネルギーが転流ダイオード63を介して負荷66に供給される。   In the power supply device of FIG. 3, when the active element 62 is on, DC power is charged to the choke coil 64 and the capacitor 65 and supplied to the load 66. When the active element 62 is off, the energy charged in the choke coil 64 and the capacitor 65 is supplied to the load 66 through the commutation diode 63.

このとき、制御部54では、比較演算部69において検出部67で検出した出力電圧Voをモニタし、これと設定部68で設定された制御目標値と比較し、駆動部70から比較結果に基づいた制御信号をスイッチング部52に出力する。これにより能動素子62がオンオフ制御され、負荷に供給される電力が制御目標値と一致するように制御される。このときの出力電圧V0は以下の(数1)式で示される。   At this time, the control unit 54 monitors the output voltage Vo detected by the detection unit 67 in the comparison calculation unit 69, compares this with the control target value set by the setting unit 68, and based on the comparison result from the drive unit 70. The control signal is output to the switching unit 52. As a result, the active element 62 is controlled to be turned on / off, and the power supplied to the load is controlled to coincide with the control target value. The output voltage V0 at this time is expressed by the following (Equation 1).

V0=Vin×(Ton/T) …(数1)
ただし、Vinは入力直流電圧、Tは駆動部70から出力されるパルス信号の周期、Tonは周期Tのうち能動素子62がオンの時間を示す。すなわち、Ton/Tはデューティ比を示す。
V0 = Vin × (Ton / T) (Equation 1)
Where Vin is the input DC voltage, T is the period of the pulse signal output from the drive unit 70, and Ton is the period T during which the active element 62 is on. That is, Ton / T represents the duty ratio.

図5は別の従来技術を示し、転流側にMOSFET3を使用した同期整流方式の電源装置である。この電源装置は図6に示すように、MOSFETの電流−電圧特性がゲート電圧によっては線形になるので、電圧降下がダイオードの場合と比較して小さい。   FIG. 5 shows another conventional technique, which is a synchronous rectification type power supply device using a MOSFET 3 on the commutation side. As shown in FIG. 6, in this power supply device, the current-voltage characteristic of the MOSFET becomes linear depending on the gate voltage, so that the voltage drop is smaller than that of the diode.

図7に、同期整流方式電源装置の転流用MOSFET3の帰還容量Crssとゲート−ソース間容量Cissを模式的に示す。この図を用いて、整流用MOSFET2がオンした時に、オフ状態にある転流用MOSFET3がオンする現象、いわゆる「セルフターンオン」について説明する。転流用MOSFET3がオフ状態で、整流用MOSFET2がオンすると、転流用MOSFET3のドレイン電圧が入力電源1の電圧Vinに急激に変化するので、帰還容量Crssを通して、ゲート−ソース間容量Cissが充電され、本来オフしているべき転流用MOSFET3がオンになる。すなわち、転流用MOSFET3のゲート−ソース間電圧Vgs
Vgs=(Crss/Ciss+Crss)×dVds …(数2)
がしきい値Vthを越えるとセルフターンオンを起こす。ここで、dVdsは転流用MOSFET3のドレイン−ソース間電圧の変化量を表す。
FIG. 7 schematically shows the feedback capacitance Crss and the gate-source capacitance Ciss of the commutation MOSFET 3 of the synchronous rectification type power supply device. A phenomenon in which the commutation MOSFET 3 in the off state is turned on when the rectifying MOSFET 2 is turned on will be described with reference to FIG. When the commutating MOSFET 3 is turned off and the rectifying MOSFET 2 is turned on, the drain voltage of the commutating MOSFET 3 is suddenly changed to the voltage Vin of the input power supply 1, so that the gate-source capacitor Ciss is charged through the feedback capacitor Crss, The commutation MOSFET 3 that should be turned off is turned on. That is, the gate-source voltage Vgs of the commutation MOSFET 3
Vgs = (Crss / Ciss + Crss) × dVds (Expression 2)
When the value exceeds the threshold value Vth, self-turn-on occurs. Here, dVds represents the amount of change in the drain-source voltage of the commutation MOSFET 3.

図5や図7に示す同期整流方式の電源装置の負荷として、マイクロプロセッサーなどの半導体集積回路が想定される。近年、半導体集積回路の動作電圧は低下する傾向にあり、これに伴い電源の出力電圧も低減する必要がある。直流入力電源の電圧が一定の条件では、(数1)式の整流用MOSFET2のオン時間Tonを短く、逆に転流用MOSFET3のオン時間を長くして出力電圧を下げる。   A semiconductor integrated circuit such as a microprocessor is assumed as a load of the synchronous rectification type power supply device shown in FIGS. In recent years, the operating voltage of a semiconductor integrated circuit tends to decrease, and the output voltage of a power supply needs to be reduced accordingly. Under the condition that the voltage of the DC input power source is constant, the ON time Ton of the rectifying MOSFET 2 in the equation (1) is shortened, and conversely, the ON time of the commutation MOSFET 3 is lengthened to lower the output voltage.

同期整流方式の電源装置などのスイッチング電源に用いられるMOSFETは理想スイッチと異なり、損失を発生する。この損失は、オン状態で発生する損失、すなわち導通損失と、オン状態からオフ状態、またはオフ状態からオン状態に切り替わるときに発生する損失、すなわちスイッチング損失に分けることができる。   Unlike an ideal switch, a MOSFET used for a switching power supply such as a synchronous rectification type power supply device generates a loss. This loss can be divided into a loss occurring in the on state, that is, a conduction loss, and a loss occurring when switching from the on state to the off state or from the off state to the on state, that is, a switching loss.

出力電圧が低い電源装置では、オン時間が短い整流用MOSFET2はスイッチング損失が支配的になり、オン時間が長い転流用MOSFET3は導通損失が支配的になる。   In a power supply device with a low output voltage, the rectification MOSFET 2 with a short on-time has a dominant switching loss, and the commutation MOSFET 3 with a long on-time has a dominant conduction loss.

導通損失は、オン状態のMOSFETの抵抗であるオン抵抗に比例し、スイッチング損失は、帰還容量に比例する。よって、スイッチング損失が支配的な整流用MOSFET2には、帰還容量の小さい素子を、導通損失が支配的な転流用MOSFET3にはオン抵抗の小さい素子を用いて、トータル損失を低減している。   The conduction loss is proportional to the on-resistance which is the resistance of the MOSFET in the on state, and the switching loss is proportional to the feedback capacitance. Therefore, the total loss is reduced by using an element having a small feedback capacitance for the rectifying MOSFET 2 in which the switching loss is dominant and using an element having a small on-resistance in the commutation MOSFET 3 in which the conduction loss is dominant.

また、図9に示すように、整流用MOSFET2のオンするスピードを低減するため、抵抗21とダイオード22の並列回路をゲートに挿入するという従来術が知られている。整流用MOSFET2は抵抗21のため、ゲート電圧の立ち上がりは遅くなり、(数2)式に示すドレイン電圧Vdsの変化量dVdsが小さくなるので、セルフターンオンが生じにくくなる。一方、ターンオフのゲート電荷の引き抜きはダイオード22を通すので高速となる。   As shown in FIG. 9, a conventional technique is known in which a parallel circuit of a resistor 21 and a diode 22 is inserted into the gate in order to reduce the speed at which the rectifying MOSFET 2 is turned on. Since the rectifying MOSFET 2 is the resistor 21, the rise of the gate voltage is delayed, and the change amount dVds of the drain voltage Vds shown in the equation (2) becomes small, so that self-turn-on is less likely to occur. On the other hand, the turn-off gate charge is extracted at high speed because the diode 22 is passed.

また、図10に示すように転流用MOSFET3のゲートに容量23と放電抵抗24を接続するという従来技術も知られている。この手法は、容量23を介して、ゲート電圧を駆動するので、ゲート端子25を正電位からグランド電位にすると、転流用MOSFET3のゲート電位26はマイナスに振り込まれ、整流用MOSFET2がオンした時、転流用MOSFET3はセルフターンオンしにくくなる。   Further, as shown in FIG. 10, a conventional technique is known in which a capacitor 23 and a discharge resistor 24 are connected to the gate of the commutation MOSFET 3. Since this method drives the gate voltage via the capacitor 23, when the gate terminal 25 is changed from the positive potential to the ground potential, the gate potential 26 of the commutation MOSFET 3 is transferred to minus, and when the rectifying MOSFET 2 is turned on, The commutation MOSFET 3 is less likely to self-turn on.

前記図3に示した従来技術の電源装置では、出力部53の転流側に受動素子であるダイオードを使用している。転流ダイオード63は、図4に示すような電流−電圧特性を有しており、電流がある所定値以上になると、順方向電圧が飽和状態になる。この飽和電圧は、高速ダイオードにおいては0.9V〜1.3V、ショットキーダイオードでは0.45V〜0.55V程度となっているために電力損失が生じ、電源変換効率を悪化させるという問題があった。さらに、電力損失が大きく素子のジャンクション温度が上昇するため、出力電流を大きくする程、転流ダイオード63を多くして(2個や3個等)並列接続し、1素子当たりの電力損失を分散させ、ジャンクション温度を抑制する必要があるという問題もあった。   In the conventional power supply device shown in FIG. 3, a diode which is a passive element is used on the commutation side of the output unit 53. The commutation diode 63 has current-voltage characteristics as shown in FIG. 4, and the forward voltage becomes saturated when the current exceeds a certain value. This saturation voltage is about 0.9 V to 1.3 V for high-speed diodes, and about 0.45 V to 0.55 V for Schottky diodes. Therefore, there is a problem that power loss occurs and power conversion efficiency deteriorates. It was. Furthermore, since the power loss is large and the junction temperature of the element rises, the larger the output current is, the more commutation diodes 63 (two or three, etc.) are connected in parallel to distribute the power loss per element. There is also a problem that it is necessary to suppress the junction temperature.

前記図5や図7に示す従来技術の電源装置では、セルフターンオンが起きると、整流用MOSFET2と転流用MOSFET3が同時にオンとなり過大な損失が発生し、効率悪化の要因を引き起こし、最悪発熱により素子破壊する場合もある。   5 and FIG. 7, when the self-turn-on occurs, the rectifying MOSFET 2 and the commutation MOSFET 3 are simultaneously turned on, causing excessive loss, causing a factor of efficiency deterioration, and causing the element to deteriorate due to the worst heat generation. It may be destroyed.

前記図5や図7に示す従来技術の電源装置に用いられるMOSFETは、理想スイッチと異なり、損失を発生する。一般に、MOSFETにはオン抵抗の小さい素子は帰還容量が大きく、帰還容量の小さい素子はオン抵抗が大きいという関係がある。図8はオン抵抗と帰還容量の関係を示した図で、両者にはトレードオフの関係がある。そのために、転流用MOSFET3はオン抵抗が低い素子を選択するため、帰還容量Crssが大きくなり、セルフターンオンが起きやすいという問題があった。   Unlike the ideal switch, the MOSFET used in the conventional power supply device shown in FIGS. 5 and 7 generates a loss. In general, a MOSFET has a relationship that an element having a small on-resistance has a large feedback capacitance, and an element having a small feedback capacitance has a large on-resistance. FIG. 8 is a diagram showing the relationship between on-resistance and feedback capacitance, and there is a trade-off relationship between the two. Therefore, since the commutation MOSFET 3 selects an element having a low on-resistance, there is a problem that the feedback capacitance Crss becomes large and self-turn-on is likely to occur.

前記図9に示した従来技術では、整流用MOSFET2のターンオンが遅くなるので、整流用MOSFET2のターンオン損失が大きくなる。   In the prior art shown in FIG. 9, since the turn-on of the rectifying MOSFET 2 is delayed, the turn-on loss of the rectifying MOSFET 2 is increased.

前記図10に示した従来技術では、容量23の充放電損失のため、転流用MOSFET3のドライブ損失が大きくなるという問題がある。   The conventional technique shown in FIG. 10 has a problem that the drive loss of the commutation MOSFET 3 is increased due to the charge / discharge loss of the capacitor 23.

本発明の目的は、上記問題を解決すべくなされたものであり、ドライブ損失の増加を招くことなく、セルフターンオンを抑制し、低い損失の電源装置を提供することである。   SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problem, and to provide a low-loss power supply device that suppresses self-turn-on without causing an increase in drive loss.

本発明の前記並びにその他の目的と新規な特徴は本明細書の記述及び添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち代表的なものの概要を簡単に説明すれば下記の通りである。   The following is a brief description of an outline of typical inventions disclosed in the present application.

すなわち、本発明の電源装置は、同期整流回路を構成する、絶縁ゲート型電力半導体素子である転流用MOSFETと整流用MOSFETとを備え、前記転流用MOSFETのしきい値が前記整流用MOSFETのしきい値より高い。   That is, the power supply device of the present invention includes a commutation MOSFET and a rectification MOSFET which are insulated gate power semiconductor elements constituting a synchronous rectification circuit, and the threshold value of the commutation MOSFET is the threshold of the rectification MOSFET. Higher than threshold.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば下記のとおりである。   The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

すなわち、本発明の電源装置は、ドライブ損失の増加を招くことなく、MOSFETのセルフターンオンを抑制でき、電源効率を向上できる。   That is, the power supply device of the present invention can suppress the self-turn-on of the MOSFET without increasing the drive loss, and can improve the power supply efficiency.

本発明の電源装置のMOSFET特性の説明図。Explanatory drawing of the MOSFET characteristic of the power supply device of this invention. 従来技術の電源装置の概略構成図。The schematic block diagram of the power supply device of a prior art. 従来技術の電源装置の概略構成図。The schematic block diagram of the power supply device of a prior art. ダイオードの電圧降下と電流との関係を示す図。The figure which shows the relationship between the voltage drop of a diode, and an electric current. 従来技術の電源装置の概略構成図。The schematic block diagram of the power supply device of a prior art. ダイオード及びMOSFETの電圧降下と電流の関係を示す図。The figure which shows the voltage drop of a diode and MOSFET, and the relationship of an electric current. 転流用MOSFETの寄生容量の説明図。Explanatory drawing of the parasitic capacitance of MOSFET for commutation. オン抵抗と帰還容量の関係を示す図。The figure which shows the relationship between on-resistance and feedback capacity. 従来技術の電源装置に用いる整流用MOSFETの概略図。Schematic of rectification MOSFET used for the power supply device of a prior art. 従来技術の電源装置に用いる整流用MOSFETの概略図。Schematic of rectification MOSFET used for the power supply device of a prior art. 本発明の電源装置のMOSFETのしきい値と効率との関係を示す説明図。Explanatory drawing which shows the relationship between the threshold value and efficiency of MOSFET of the power supply device of this invention. 本発明の電源装置のMOSFETのしきい値と損失との関係を示す説明図。Explanatory drawing which shows the relationship between the threshold value and loss of MOSFET of the power supply device of this invention. 本発明の電源装置のMOSFETの電流、電圧波形の説明図。Explanatory drawing of the current of the MOSFET of the power supply device of this invention, and a voltage waveform.

以下、図面を参照しながら本発明の詳細を説明する。本発明の電源装置は、前記従来技術の説明に用いた図5と同じ回路構成である。図5に示すように、本発明の電源装置は整流用MOSFET2と転流用MOSFET3とを備えており、整流用MOSFET2のドレイン端子には直流入力電源1が接続されている。整流用MOSFET2のソース端子はチョークコイル4の一端及び転流用MOSFET3のドレイン端子が接続されている。チョークコイル4の他端は、コンデンサ5(例えば電解コンデンサ)の一端及び負荷抵抗に接続されている。コンデンサ5はグランド端子に接続されている。   Hereinafter, details of the present invention will be described with reference to the drawings. The power supply device of the present invention has the same circuit configuration as that of FIG. As shown in FIG. 5, the power supply device of the present invention includes a rectifying MOSFET 2 and a commutation MOSFET 3, and a DC input power supply 1 is connected to the drain terminal of the rectifying MOSFET 2. The source terminal of the rectifying MOSFET 2 is connected to one end of the choke coil 4 and the drain terminal of the commutation MOSFET 3. The other end of the choke coil 4 is connected to one end of a capacitor 5 (for example, an electrolytic capacitor) and a load resistor. The capacitor 5 is connected to the ground terminal.

本発明の電源装置に用いた整流用MOSFET2と転流用MOSFET3のしきい値を図1に示す。図1で横軸はゲート電圧、縦軸はドレイン電流である。本発明の電源装置では、転流用MOSFET3のしきい値と整流用MOSFET2とが異なっており、転流用MOSFET3のしきい値が整流用MOSFET2より高くなっている。   FIG. 1 shows threshold values of the rectifying MOSFET 2 and the commutation MOSFET 3 used in the power supply device of the present invention. In FIG. 1, the horizontal axis represents the gate voltage, and the vertical axis represents the drain current. In the power supply device of the present invention, the threshold value of the commutation MOSFET 3 and the rectification MOSFET 2 are different, and the threshold value of the commutation MOSFET 3 is higher than that of the rectification MOSFET 2.

ここで、しきい値とはドレイン、ソース間電圧が10Vの条件で、ドレイン電流が1mA流れる時のゲート、ソース間電圧と本明細書では定義する。   Here, the threshold value is defined in this specification as a gate-source voltage when a drain current of 1 mA flows under a condition where the drain-source voltage is 10V.

図11は転流用MOSFET3のしきい値Vthを横軸に、電源効率ηを縦軸にとった場合の関係を示す。図11に示すように、しきい値が高くなるに従い電源効率が上昇する。   FIG. 11 shows the relationship when the threshold Vth of the commutation MOSFET 3 is taken on the horizontal axis and the power supply efficiency η is taken on the vertical axis. As shown in FIG. 11, the power supply efficiency increases as the threshold value increases.

図12は、本願発明の電源装置のしきい値と電源の損失成分との関係を示す。図12の各棒グラフの内訳は上から順に、整流用MOSFET2の導通損失、整流用MOSFET2のターンオン損失、整流用MOSFET2のターンオフ損失、整流用MOSFET2のドライブ損失、転流用MOSFET3の導通損失、転流用MOSFET3のセルフターンオン損失、転流用MOSFET3のドライブ損失、ダイオード2A、3Aの導通損失、ダイオード2A、3Aのリカバリー損失を示している。   FIG. 12 shows the relationship between the threshold value of the power supply device of the present invention and the loss component of the power supply. The breakdown of each bar graph of FIG. 12 is, in order from the top, the conduction loss of the rectification MOSFET 2, the turn-on loss of the rectification MOSFET 2, the turn-off loss of the rectification MOSFET 2, the drive loss of the rectification MOSFET 2, the conduction loss of the commutation MOSFET 3, and the commutation MOSFET 3 Self turn-on loss, drive loss of commutation MOSFET 3, conduction loss of diodes 2A and 3A, and recovery loss of diodes 2A and 3A.

図12に示すように、しきい値が高くなるに従い、トータルの損失は低下する。成分の内訳で見ると、しきい値が低い(2.39V)場合、転流用MOSFET3のセルフターンオン損失が大きいが、しきい値が高くなると(3.39V)、転流用MOSFET3のセルフターンオン損失が発生しなくなる。一方、しきい値の増加に伴い、転流用MOSFET3の導通損失が増加する。しかし、この導通損失の増加量より、セルフターンオン損失が低下量の方が大きいので、電源装置トータルでの損失は減少し、図10に示すように電源効率が向上する。   As shown in FIG. 12, the total loss decreases as the threshold value increases. Looking at the breakdown of the components, when the threshold value is low (2.39 V), the self-turn-on loss of the commutation MOSFET 3 is large, but when the threshold value is high (3.39 V), the self-turn-on loss of the commutation MOSFET 3 is large. No longer occurs. On the other hand, as the threshold value increases, the conduction loss of the commutation MOSFET 3 increases. However, since the decrease amount of the self turn-on loss is larger than the increase amount of the conduction loss, the total loss of the power supply device is reduced, and the power supply efficiency is improved as shown in FIG.

図13は、本発明の電源装置の整流用MOSFET2がターンオンした場合の転流用MOSFET3のドレイン電圧、ドレイン電流、ゲート電圧の変化を示す。図13(a)はしきい値が2.39V の場合である。この時は、ドレイン電圧が上昇し、帰還容量を介してゲート電圧が上昇し、しきい値を超えるためドレイン電流が流れる。ドレイン電圧が高い状態で、ドレイン電流が流れるので、大きな損失を発生する。図13(b)はしきい値が2.89V の場合である。この時は、ドレイン電圧が上昇し、帰還容量を介してゲート電圧が上昇し、しきい値を超えるためドレイン電流が流れるが、ドレイン電流の大きさは図13(a)の場合に比べると小さいので、発生する損失も小さくなっている。図13(c)はしきい値が3.39V の場合である。この時には、ゲート電圧は上昇するがドレイン電流は流れていない。すなわち、損失は発生していない。   FIG. 13 shows changes in drain voltage, drain current, and gate voltage of the commutation MOSFET 3 when the rectification MOSFET 2 of the power supply device of the present invention is turned on. FIG. 13A shows the case where the threshold value is 2.39V. At this time, the drain voltage rises, the gate voltage rises through the feedback capacitance, and the drain current flows because it exceeds the threshold value. Since the drain current flows when the drain voltage is high, a large loss occurs. FIG. 13B shows the case where the threshold value is 2.89V. At this time, the drain voltage rises, the gate voltage rises through the feedback capacitance, and the drain current flows because it exceeds the threshold value. However, the magnitude of the drain current is smaller than that in the case of FIG. Therefore, the generated loss is also reduced. FIG. 13C shows the case where the threshold value is 3.39V. At this time, the gate voltage rises but no drain current flows. That is, no loss has occurred.

以上説明したように、本発明の電源装置では、ドライブ損失の増加を招くことなく、セルフターンオンを抑制し、電源効率を向上することができる。   As described above, in the power supply device of the present invention, self-turn-on can be suppressed and power supply efficiency can be improved without causing an increase in drive loss.

次に、整流用MOSFET2のしきい値と転流用MOSFET3のしきい値との差をどの程度とすれば、好ましいのかを説明する。整流用MOSFET2と転流用MOSFET3のしきい値は、量産ラインにおいては設計値に対して±0.5V 程度の範囲でばらつくので、このバラツキを考慮すると、転流用MOSFET3のしきい値を整流用MOSFET2より、0.5V 以上高くすることが望ましい。   Next, how much the difference between the threshold value of the rectifying MOSFET 2 and the threshold value of the commutation MOSFET 3 is preferable will be described. Since the threshold values of the rectifying MOSFET 2 and the commutation MOSFET 3 vary within a range of about ± 0.5 V with respect to the design values in the mass production line, considering this variation, the threshold of the commutation MOSFET 3 is set to the rectification MOSFET 2. Therefore, it is desirable to increase it by 0.5V or more.

次に、整流用MOSFET2と転流用MOSFET3のしきい値の具体的な数値について説明する。整流用MOSFET2のスイッチング損失を低減するためにはトランスコンダクタンスgmを高くすることが望ましい。トランスコンダクタンスgmを高くするには、整流用MOSFET2しきい値を低くすることが有効であり、具体的に整流用MOSFET2のしきい値を1.5V 以下とすることが望ましく、転流用MOSFET3のしきい値は2.0V 以上とする。   Next, specific numerical values of threshold values of the rectifying MOSFET 2 and the commutating MOSFET 3 will be described. In order to reduce the switching loss of the rectifying MOSFET 2, it is desirable to increase the transconductance gm. In order to increase the transconductance gm, it is effective to lower the threshold value of the rectifying MOSFET 2, specifically, it is desirable that the threshold value of the rectifying MOSFET 2 is 1.5 V or less. The threshold value shall be 2.0V or more.

本発明の電源装置の損失をより確実に低下させるためには、転流用MOSFET3のしきい値は整流用MOSFET2より1.0V 以上高くすることが望ましい。これは電源装置の配線インダクタンスが大きいと、整流用MOSFET2がオンした時、転流用MOSFET3ドレイン電圧の跳ね上がりが大きくなり、セルフターンオンしやすくなるためである。具体的には電源装置の主回路の配線インダクタンスの合計が10nHを越える場合が、これに相当する。   In order to reduce the loss of the power supply device of the present invention more surely, it is desirable that the threshold value of the commutation MOSFET 3 is higher than the rectification MOSFET 2 by 1.0 V or more. This is because when the wiring inductance of the power supply device is large, when the rectifying MOSFET 2 is turned on, the jumping of the drain voltage of the commutating MOSFET 3 becomes large, and self-turn-on is easily performed. Specifically, this corresponds to the case where the total wiring inductance of the main circuit of the power supply device exceeds 10 nH.

以上、本発明の実施例では整流用MOSFET2にn型MOSFETを用いて説明してきたが、p型MOSFETを用いることもできることは言うまでもない。   As described above, the embodiment of the present invention has been described using the n-type MOSFET as the rectifying MOSFET 2, but it goes without saying that a p-type MOSFET can also be used.

1,60…直流入力電源
2…整流用MOSFET
3…転流用MOSFET
4,64…チョークコイル
5…出力コンデンサ
6…負荷抵抗
7,61…入力コンデンサ
21,24…抵抗
22…ダイオード
23…容量
25…ゲート端子
26…ゲート電位
51…入力部
52…スイッチング部
53…出力部
54…制御部
55…出力フィルタ
62…能動素子
63…転流ダイオード
65…コンデンサ
66…負荷
67…検出部
68…設定部
69…比較演算部
70…駆動部
1,60 ... DC input power supply 2 ... Rectifying MOSFET
3 ... MOSFET for commutation
4, 64 ... Choke coil 5 ... Output capacitor 6 ... Load resistor 7, 61 ... Input capacitor 21, 24 ... Resistor 22 ... Diode 23 ... Capacitor 25 ... Gate terminal 26 ... Gate potential 51 ... Input unit 52 ... Switching unit 53 ... Output Unit 54 ... Control unit 55 ... Output filter 62 ... Active element 63 ... Commutation diode 65 ... Capacitor 66 ... Load 67 ... Detection unit 68 ... Setting unit 69 ... Comparison calculation unit 70 ... Drive unit

Claims (8)

第1の端子と直流入力電源の高電位側に接続される第2の端子とを含む第1の絶縁ゲート型電力半導体素子と、
第3の端子と前記直流入力電源の低電位側に接続される第4の端子とを含む第2の絶縁ゲート型電力半導体素子と、
前記第1の端子と前記第3の端子との接続部と、を有し、
前記第1の絶縁ゲート型電力半導体素子のゲートと前記第2の端子との間の帰還容量の容量値が、前記第2の絶縁ゲート型電力半導体素子のゲートと前記第3の端子と間の帰還容量の容量値より小さく、
前記第1の絶縁ゲート型電力半導体素子のしきい値電圧の絶対値が、前記第2の絶縁ゲート電力半導体素子のしきい値電圧の絶対値より低い半導体装置。
A first insulated gate power semiconductor element including a first terminal and a second terminal connected to the high potential side of the DC input power supply;
A second insulated gate type power semiconductor device including a third terminal and a fourth terminal connected to the low potential side of the DC input power source;
A connecting portion between the first terminal and the third terminal;
The capacitance value of the feedback capacitance between the gate of the first insulated gate power semiconductor element and the second terminal is between the gate of the second insulated gate power semiconductor element and the third terminal. Smaller than the value of the feedback capacitance,
A semiconductor device, wherein an absolute value of a threshold voltage of the first insulated gate power semiconductor element is lower than an absolute value of a threshold voltage of the second insulated gate power semiconductor element.
前記第1の絶縁ゲート型電力半導体素子のオン期間に前記第2の絶縁ゲート型電力半導体素子をオフとし、前記第1の絶縁ゲート型電力半導体素子のオフ期間に前記第2の絶縁ゲート型電力半導体素子をオンとし、かつ、前記第1の絶縁ゲート型電力半導体素子のオン期間は前記第2の絶縁ゲート型電力半導体素子のオン期間より短く制御される請求項1の半導体装置。   The second insulated gate power semiconductor element is turned off during an on period of the first insulated gate power semiconductor element, and the second insulated gate power semiconductor is turned off during an off period of the first insulated gate power semiconductor element. 2. The semiconductor device according to claim 1, wherein a semiconductor element is turned on, and an on period of the first insulated gate power semiconductor element is controlled to be shorter than an on period of the second insulated gate power semiconductor element. 前記直流入力電源の電圧より低い電圧を前記接続部から出力する請求項1の半導体装置。   The semiconductor device according to claim 1, wherein a voltage lower than a voltage of the DC input power supply is output from the connection portion. 前記第2の絶縁ゲート型電力半導体素子のしきい値電圧の絶対値が前記第1の絶縁ゲート型電力半導体素子のしきい値電圧の絶対値より0.5V以上高い請求項1の半導体装置。   2. The semiconductor device according to claim 1, wherein an absolute value of a threshold voltage of the second insulated gate power semiconductor element is 0.5 V or more higher than an absolute value of the threshold voltage of the first insulated gate power semiconductor element. 前記第1の絶縁ゲート型電力半導体素子のしきい値電圧の絶対値が1.5V以下であり、前記第2の絶縁ゲート型電力半導体素子のしきい値電圧の絶対値が2.0V以上である請求項1の半導体装置。   The absolute value of the threshold voltage of the first insulated gate power semiconductor element is 1.5 V or less, and the absolute value of the threshold voltage of the second insulated gate power semiconductor element is 2.0 V or more. The semiconductor device according to claim 1. 前記第1の端子はソース端子であり、前記第2の端子はドレイン端子であり、前記第3の端子はドレイン端子であり、前記第4の端子はソース端子である請求項1記載の半導体装置。   The semiconductor device according to claim 1, wherein the first terminal is a source terminal, the second terminal is a drain terminal, the third terminal is a drain terminal, and the fourth terminal is a source terminal. . 前記第1の絶縁ゲート型電力半導体素子は整流用MOSFETであり、前記第2の絶縁ゲート型電力半導体素子は転流用MOSFETである請求項1記載の半導体装置。   The semiconductor device according to claim 1, wherein the first insulated gate power semiconductor element is a rectifying MOSFET, and the second insulated gate power semiconductor element is a commutation MOSFET. 前記整流用MOSFETはn型MOSFETである請求項7記載の半導体装置。   The semiconductor device according to claim 7, wherein the rectifying MOSFET is an n-type MOSFET.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09307420A (en) * 1996-05-16 1997-11-28 Nippon Telegr & Teleph Corp <Ntt> Output butter
JPH10321855A (en) * 1997-03-18 1998-12-04 Toshiba Corp High withstand-voltage semiconductor device
JP2000312477A (en) * 1999-04-23 2000-11-07 Nippon Telegr & Teleph Corp <Ntt> Switching regulator
JP2002217416A (en) * 2001-01-16 2002-08-02 Hitachi Ltd Semiconductor device
JP2002369552A (en) * 2001-06-08 2002-12-20 Toshiba Corp Semiconductor integrated circuit device
JP2002368121A (en) * 2001-06-04 2002-12-20 Hitachi Ltd Semiconductor device for power

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09307420A (en) * 1996-05-16 1997-11-28 Nippon Telegr & Teleph Corp <Ntt> Output butter
JPH10321855A (en) * 1997-03-18 1998-12-04 Toshiba Corp High withstand-voltage semiconductor device
JP2000312477A (en) * 1999-04-23 2000-11-07 Nippon Telegr & Teleph Corp <Ntt> Switching regulator
JP2002217416A (en) * 2001-01-16 2002-08-02 Hitachi Ltd Semiconductor device
JP2002368121A (en) * 2001-06-04 2002-12-20 Hitachi Ltd Semiconductor device for power
JP2002369552A (en) * 2001-06-08 2002-12-20 Toshiba Corp Semiconductor integrated circuit device

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