JP2002369552A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce loss in operating state for achieving high efficiency, and reduce power consumption in a standby state, in a semiconductor integrated circuit device which includes a DC voltage transducer. SOLUTION: A semiconductor integrated circuit device has a semiconductor integrated circuit 30, and a DC voltage conversion circuit 21 for stepping down a power voltage Vdd (1.2 V) of a nickel metal hydride battery to a voltage Vdd- int (0.5 V) for feeding power to the semiconductor integrated circuit on the same chip. In this case, the semiconductor integrated circuit 30 has a pMOS transistor, having a threshold voltage Vth1 (-0.15 V) where a magnitude is smaller than Vdd- int/2, and an nMOS transistor having a threshold voltage Vth2 (0.15 V) being smaller than the Vdd- int/2, the DC voltage conversion circuit 21 has a pMOS transistor M1, having a threshold voltage Vth3 (--0.33 V) where the magnitude is larger than |Vth1| and also is smaller than Vdd/2, and an nMOS transistor having a threshold voltage Vth4 (0.33 V), that is larger than Vth2 and also is smaller than Vdd/2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device including a DC voltage conversion circuit, and more particularly to a MIS of each part.
(Metal Insulator Semiconductor) The present invention relates to a semiconductor integrated circuit device in which a threshold voltage of a transistor (for example, a MOS transistor) is optimized.

[0002]

2. Description of the Related Art In recent years, the degree of integration of semiconductor integrated circuits has been remarkably improved. In a gigabit-class semiconductor memory, hundreds of millions of semiconductor elements per chip, and in a 64-bit microprocessor, millions to 1,000 per chip. Ten thousand semiconductor elements have been integrated. The improvement in the degree of integration has been achieved by miniaturization of elements, and 1 Gbit DRAM (Dynamic Radar)
In an ndom access memory, a MOS transistor having a gate length of 0.15 μm is used, and as the degree of integration further increases, a MOS transistor having a gate length of 0.1 μm or less is used.

In such a fine MOS transistor, deterioration of transistor characteristics due to generation of hot carriers and TDDB (Time Dependent Dielectric Breakdown)
Insulation film breakdown due to n) occurs. Further, in order to suppress a decrease in threshold voltage due to a shortened channel length, if the impurity concentration in the substrate region or the channel region is increased, the junction breakdown voltage between the source and the drain is reduced.

In order to maintain the reliability of these fine elements, it is effective to lower the power supply voltage. That is, generation of hot carriers can be prevented by weakening the horizontal electric field between the source and drain, and TDDB can be prevented by weakening the vertical electric field between the gate and bulk. Further, by lowering the power supply voltage, the reverse bias applied to the junction between the source and the bulk and the junction between the drain and the bulk can be reduced to cope with the reduction in the withstand voltage. Driving at a low voltage also leads to low power consumption, which is very preferable.

[0005] By the way, in portable information devices whose market has remarkably expanded in recent years, a light-weight and high-energy-density power source represented by a nickel-metal hydride battery or a lithium ion battery is often used as a main power source. However, these batteries have a voltage of about 1.2 to 3.3 V, which is higher than the withstand voltage of the micro MOS transistor, and when applied to a circuit using such a micro transistor,
For example, it is necessary to use a DC voltage converter to reduce the voltage.

The usage time of a portable information device is determined by the power consumption of a power supply system and components. To use the portable information device for a longer time, a high energy density battery, a high efficiency DC voltage converter, and a low power consumption integrated circuit are required. Is required. In addition, since the portable information device has a function of performing intelligent communication with the outside, the portable information device includes a microprocessor and a communication circuit as a basic configuration. It can be said that it is desirable to use the stepped down power supply voltage particularly for the microprocessor and the baseband LSI from the viewpoint of reducing the power consumption of the LSI.

FIG. 10 shows a conventional example of a semiconductor integrated circuit device using a DC voltage converter for stepping down a battery voltage. In the figure, reference numeral 10 denotes a nickel-metal hydride battery which generates a voltage of about 1.2 V, and reference numeral 20 denotes a battery voltage of 1.2 V which is about 0.1 V.
DC voltage converter for stepping down to 5V, 30 is baseband L
This is an integrated circuit represented by SI. DC voltage converter 20
Is formed on the same semiconductor substrate as the semiconductor substrate on which the integrated circuit 30 is formed, the number of components constituting the system can be reduced, and an increase in cost can be suppressed.

In the integrated circuit 30, a pMOS transistor and an nMOS transistor are used in view of high-speed operation and low power consumption.
A CMOS logic circuit, a pass gate logic circuit, a dynamic circuit, or the like in which transistors are combined is often used. The threshold voltages of these transistors are determined by the operating voltage of the circuit and the required operating speed and power consumption. In addition, since each element circuit constituting the DC voltage converter 20 is formed on the same substrate as the integrated circuit 30 by the same process, it is preferable to constitute a circuit in which similar pMOS transistors and nMOS transistors are combined.

For example, taking the simplest inverter circuit in a CMOS logic circuit as an example, the threshold voltage (absolute value in the case of a pMOS transistor, the same applies hereinafter) of a transistor required for operation of the circuit is determined by a power supply. It is 1/2 or less of the voltage. When the threshold voltage is high, the driving capability of the transistor decreases, so that the operation speed of the circuit decreases. on the other hand,
If the threshold voltage becomes too low, the leakage current when the transistor is cut off increases. The increase in the leakage current increases not only the power consumption during operation but also the power consumption during non-operation (standby).

When the leakage current increases, the high level of the output signal of the circuit falls below the power supply voltage, and the low level rises above the ground voltage, so that the amplitude of the output signal decreases. The decrease in the amplitude decreases the operating speed of another circuit driven by this circuit, causes post-operation, or increases the through current. In addition, since a transistor having a low threshold voltage is likely to punch through, the drain withstand voltage is reduced.

From the above, the threshold voltage is normally set to a value of about 1/3 to 1/5 of the power supply voltage. When the power supply voltage is 0.5V, the threshold voltage is set to 0.1V to 0.1V. 0.
It is about 15V. However, if the element designed for the 0.5 V operation is directly applied to an element circuit constituting a DC voltage converter of 1.2 V or 3.3 V input, an increase in power consumption due to an increase in leakage current and no drain withstand voltage are obtained. Therefore, it is not preferable.

[0012]

As described above, in a conventional portable information device, a high-performance battery such as a nickel-metal hydride battery is used as a main power source, and the battery voltage is reduced using a DC voltage converter. Power is supplied to a semiconductor integrated circuit operating at a lower voltage. Here, the DC voltage converter is
Since each element circuit is formed on the same chip as the semiconductor integrated circuit by the same process, it is configured by the same transistors as those constituting the semiconductor integrated circuit.

In this case, in the DC voltage converter, the threshold voltage of the transistor is lower than the power supply voltage. If the threshold voltage of the transistor is too low, the leakage current increases, which causes a decrease in conversion efficiency during operation and an increase in power consumption during standby, which causes a problem that the life of the battery of the portable information device is reduced. Further, since the element circuits of the DC voltage converter are operated by the main power supply, they operate at a voltage higher than the operating voltage of the semiconductor integrated circuit. Therefore, if a low-voltage element designed to be suitable for the operation of the semiconductor integrated circuit is used in the element circuit of the DC voltage converter, there is a problem that the reliability is reduced.

The present invention has been made in view of the above circumstances, and has as its object to reduce the loss during operation to achieve high efficiency, and to reduce the power consumption during standby. An object of the present invention is to provide a semiconductor integrated circuit device provided with a voltage converter.

[0015]

(Structure) In order to solve the above problem, the present invention employs the following structure.

That is, the present invention provides a semiconductor integrated circuit having two modes of an operation mode in which power consumption is large and a standby mode in which power consumption is smaller than this operation mode, and a step in which a first DC voltage is reduced to a second DC voltage. A semiconductor integrated circuit device having a DC voltage conversion circuit for supplying power to the semiconductor integrated circuit on the same chip, wherein the semiconductor integrated circuit has a first DC voltage having an absolute value smaller than の of a second DC voltage. PMOS transistor having a threshold voltage of
An nMOS transistor having a second threshold voltage smaller than / 2, wherein the DC voltage conversion circuit has an absolute value larger than the absolute value of the first threshold voltage,
And a pMOS transistor having a third threshold voltage smaller than 1/2 of the first DC voltage, and a fourth PMOS transistor larger than the second threshold voltage and smaller than 1/2 of the first DC voltage. And an nMOS transistor having a threshold voltage. The MOS transistor described above includes a case where the gate insulating film is not only an oxide film but also a nitride film or another insulating film.

Here, preferred embodiments of the present invention include the following. (1) Output power and final stage efficiency in DC voltage conversion circuit,
Further, from the relationship between the on-resistance of the pMOS transistor having the third threshold voltage and the on-resistance of the nMOS transistor having the fourth threshold voltage, an on-resistance for obtaining a desired efficiency is obtained. Determining the relationship between the third and fourth threshold voltages and standby power, and setting the third and fourth threshold voltages in the DC voltage conversion circuit to values corresponding to allowable standby power.

(2) When the first DC voltage is a nickel-metal hydride battery having an electromotive force of about 1.2 V and the second DC voltage is about 0.5 V, the third threshold voltage is reduced. The threshold voltage is set to be smaller than -0.33 V, and the fourth threshold voltage is set to be larger than 0.33 V.

(3) The first DC voltage is about 3.3 to 3.
A lithium-ion battery having an electromotive force of 6 V;
The third threshold voltage is set to be smaller than -0.36 V and the fourth threshold voltage is set to be larger than 0.36 V when the DC voltage is approximately 0.5 V.

(Operation) According to the present invention, the absolute value of the third threshold voltage of the pMOS transistor in the DC voltage conversion circuit is made larger than the absolute value of the first threshold voltage of the pMOS transistor in the semiconductor integrated circuit. And the fourth of the nMOS transistors in the DC voltage conversion circuit.
Is made higher than the second threshold voltage of the nMOS transistor in the semiconductor integrated circuit, the leakage current of the DC voltage conversion circuit is reduced, so that the efficiency during operation is reduced and the consumption during standby is reduced. An increase in power can be suppressed. Further, since the withstand voltage of the elements constituting the DC voltage conversion circuit is increased, the reliability is improved.

That is, not only the semiconductor integrated circuit operating at the second DC voltage lower than the first DC voltage but also the first
In a DC voltage conversion circuit that operates with a DC voltage, the optimal threshold voltage for the power supply voltage can be set, thereby suppressing loss in the DC voltage conversion circuit and increasing efficiency, and further improving standby. It is possible to reduce power consumption at the time.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a diagram showing a circuit configuration of a semiconductor integrated circuit device according to the example. Reference numeral 10 in the figure denotes a main power supply for generating a voltage Vdd, which uses a high-performance battery such as nickel-metal hydride or lithium ion. Reference numeral 21 denotes a DC voltage converter that reduces the battery voltage to a voltage Vdd_int.
4 shows an example of a DC converter.

The DC voltage converter 21 includes a clock generation circuit (CG) 22 for generating a clock and a pulse width modulation circuit (PWM) for modulating the duty ratio of the generated clock.
23, a pre-buffer circuit (PB) 24 for amplifying a modulated clock signal, a pMOS transistor M1 and an nMOS transistor M2 constituting a final stage main buffer, and a voltage for passing a DC component of a signal from the main buffer. An inductor L1 and a capacitor C1, which constitute a low-pass filter that outputs Vdd_int, and a voltage Vdd
_int is compared with a reference potential Vref and a comparison result is output to PWM, and a capacitor C2 for stabilizing the system is provided.
And resistors R1 and R2.

In the figure, reference numeral 30 denotes a load circuit (semiconductor integrated circuit) comprising a pMOS transistor and an nMOS transistor, and includes a circuit driven by a stepped-down voltage Vdd_int. In this load circuit 30, the voltage Vdd_int
Is 0.5 V, for example, it is assumed that the threshold value of the pMOS transistor is set to -0.15 V and the threshold value of the nMOS transistor is set to 0.15 V.

The DC voltage converter 21 outputs a sleep signal Sleep
The operation mode and the standby mode are switched by p.
FIG. 2 is a diagram showing a time change of the sleep signal Sleep and the output voltage Vdd_int from the DC voltage converter 21. signal
When Sleep is in the high state, the clock generation circuit 22 and the comparator 25 are in an inactive state. The signal Sleep controls the pre-buffer circuit 24 so that the output voltage Vdd_int becomes the ground voltage Vss during standby. When the signal Sleep goes low, the DC voltage converter 21 becomes active, and the output voltage Vdd_int rises to the step-down potential. Again signal Sleep
Becomes high, the output voltage Vdd_int becomes the ground voltage Vss.
Down to

Next, a control method in which the output voltage Vdd_int becomes the ground voltage Vss during standby and a leak current at that time will be described.

When the load circuit 30 is a resistive circuit, the outputs SP and SN from the pre-buffer circuit 24 are high and
Set the pre-buffer circuit 24 to a sleep signal
Controlled by Sleep. Since both the pMOS transistor M1 and the nMOS transistor M2 are turned off, the output voltage Vdd_int becomes the ground voltage Vss through the resistive load circuit 30. In this case, the leak current from the power supply Vdd of the main buffer to the ground Vss is determined by the off-leak current of the pMOS transistor M1.

When the load circuit 30 is a capacitive circuit, the pre-buffer circuit 24 is controlled by the sleep signal Sleep so that both the outputs SP and SN from the pre-buffer circuit 24 become high. pMOS transistor M1 is off,
Since the nMOS transistor M2 is turned on, the output voltage Vdd_int becomes the ground voltage Vss through the nMOS transistor M2. Also in this case, the off-leak current is pMO
It is determined by the S transistor M1.

When the load circuit 30 is a capacitive circuit,
The pre-buffer circuit 24 is controlled by the sleep signal Sleep so that the outputs SP and SN from the pre-buffer circuit 24 become high and low, respectively.
The output voltage Vdd_int may be set to the ground voltage Vss by introducing the S transistor M3. In the nMOS transistor M3, the drain is connected to Vdd_int, Sleep is input to the gate, and the source is grounded to Vss. Also in this case, the leakage current from the power supply Vdd of the main buffer to the ground Vss is pM
It is determined by the off-leak current of the OS transistor M1.

In the system of this embodiment, the element circuits 22 to 25 and the capacitor C which constitute the DC voltage converter 21
2. The resistors R1 and R2 are integrally formed on the same semiconductor substrate on which the load circuit 30 is integrated. Capacitor C1 having a capacitance not less than microfarad
May be individual components, or may be formed on a semiconductor substrate on which component circuits of the load circuit 30 and the DC voltage converter 21 are formed by using a high dielectric material.

Similarly, the inductor L1 having an inductance equal to or greater than microhenry may be an individual component,
The load circuit and the element circuit of the DC voltage converter may be formed on a semiconductor substrate on which integrated circuits are formed using a magnetic thin film material having high magnetic permeability. Furthermore, at least one of C1 and L1 may be formed as individual components, and these components may be formed on a semiconductor substrate on which the load circuit 30 and the component circuits of the DC voltage converter 21 are integrally formed by using a superconnect technique or the like.

FIG. 4 shows the result of numerical analysis of the change in the final stage efficiency with respect to the on-resistance of the transistor constituting the main buffer of the DC voltage converter 21 at the output voltage Vdd_int = 0.5V. Here, it is assumed that the on-resistance of the pMOS transistor M1 is equal to the on-resistance of the nMOS transistor M2. Further, off-leakage currents of the transistors M1 and M2, a parasitic resistance of a power supply wiring, a parasitic resistance of an output system represented by the inductor L1, a parasitic capacitance of a transistor represented by a drain junction capacitance, a parasitic resistance and a parasitic resistance of the wiring It is assumed that the capacities are all zero. The on-resistance of the transistor is defined by the slope of the drain voltage with respect to the drain current when the voltage Vdd is applied between the gate and the source. The final stage efficiency is determined by the output power Po, the output power, the transistors M1 and M
Power consumed by the main buffer composed of
(Po + Pmain).

In FIG. 4, when the output power is 10 mW, the output stage efficiency of 90% or more can be obtained with an on-resistance of about 2.8 Ω or less regardless of whether the main power supply voltage Vdd is 1.2 V or 3.3 V. ing. When the output power is 20 mW, the on-resistance at which the output stage efficiency of 90% or more is obtained is about 1.4Ω or less. The efficiency of DC voltage converter is
Loss due to leakage current of the main buffer, power consumed by the pre-buffer circuit 24 and other circuits 22, 23, 25, parasitic resistance and parasitic capacitance of wiring, parasitic resistance of inductor, parasitic capacitance of transistor, and the like are added. Several percent lower than efficiency.

Therefore, when the output power is about 10 mW to 20 mW, the on-resistance needs to be about 1 Ω or less in order to obtain an efficiency of about 90%. Hereinafter, a numerical analysis result of the efficiency when the threshold voltage and the subthreshold coefficient of the transistors M1 and M2 are changed when the output voltage is 0.5 V and the on-resistance is 1Ω is shown.

FIG. 5 shows that the main power supply voltage Vdd is 1.2 V, the sub-threshold coefficient S is 80 mV / dec, and the output voltage Vdd
_int indicates the output power dependence of the efficiency at 0.5V.
The efficiency is the output power Po and the power consumption P of the DC voltage converter 21.
Is defined as the ratio. Here, the power consumption P is the output power Po, the power Pcntl consumed by the clock generation circuit 22, the PWM circuit 23, and the pre-buffer circuit 24, and the power consumed by the on-resistance of the main buffer including the transistors M1 and M2. Pon and the loss Pvx caused by the excess voltage of the main buffer output caused by the inductor
And the leakage power Pleak of the main buffer and the loss Pind caused by the parasitic resistance of the inductor.

For the same gate width, the threshold voltage V
As t increases, the on-resistance of the transistor increases. Therefore, in order to make the on-resistance constant (1 Ω in this example), it is necessary to increase the gate width as the threshold voltage increases. This causes an increase in power consumption of the pre-buffer circuit 24 for driving the main buffer. On the other hand, when the threshold voltage Vt decreases, the off-leak current of the transistor increases, so that power consumption due to the leak current flowing in the circuit increases. From FIG. 5, the efficiency decreases at all output powers as the threshold voltage decreases.

FIG. 6 shows that the main power supply voltage Vdd is 3.3 V, the sub-threshold coefficient S is 80 mV / dec, and the output voltage Vdd
_int indicates the output power dependence of the efficiency at 0.5V.
Also in this case, when the threshold voltage is lowered, the efficiency is greatly reduced at all output powers.

From the above, it can be said that the decrease in the efficiency due to the decrease in the threshold voltage is largely due to the increase in the off-leak current.

FIG. 7 shows a case where the main power supply voltage Vdd is 1.2 V and the output voltage Vdd_int is 0.5
V shows the efficiency of the DC voltage converter and the dependence of the standby power on the threshold voltage when the output power Po is 10 mW. here,
As for the standby power, only the power consumed by the main buffer and the pre-buffer 24 is considered. Transistor ON resistance is 1Ω
And

The DC voltage converter 21 is in a standby mode,
While the output voltage Vdd_int is grounded to Vss, the load circuit 3
0 does not consume power. However, as shown in FIG.
In the standby mode, there is a transition period during which Vdd_int falls to Vss, and power is consumed during this transition period. For example, see “IEEE Journal of Solid-State Circuits, Vol. 32, N
o.6, pp.861-869, June 1997 ”, a method of operating a part of the load circuit 30 in the standby mode has been proposed. In this case, the standby mode is less than 1 μW in the standby mode. It is desired that portable information terminals have as little standby power as possible, and in general, the standby power of LSIs, which occupy most of them, is one.
It is desirable not to greatly exceed μW.

The standby power of the load circuit 30 is equal to the operating power of 10
The case where the standby power of the DC voltage converter 21 is 0.01 μW which is 1/100 of the standby power of the load circuit 30 is considered as an example. Here, the setting that the standby power of the DC voltage converter 21 is 1/100 of the standby power of the load circuit 30 is equivalent to the standby power of the DC voltage converter 21 combined with the load circuit 30 with respect to the standby power of the entire system. It is a value that can be ignored, and if it does not greatly exceed this value, it is possible to prevent the standby performance from deteriorating by using the DC voltage converter 21.

From FIG. 7, it can be seen that a fully depleted SOI (Silicon
When the sub-threshold coefficient S has an ideal value of 60 mV / dec, as represented by a MOS transistor, the standby power can be reduced to 0.01 μW or less by setting the threshold voltage to 0.33 V or more. That is, by setting the threshold voltage of the pMOS transistor M1 in the DC voltage conversion writing 21 to −0.33 V or less and the threshold voltage of the nMOS transistor M2 to 0.331 V or more, the efficiency during operation decreases and the standby time decreases. Power consumption can be suppressed. The efficiency at this time hardly changes due to the threshold voltage. Further, assuming that the variation of the threshold voltage is 10%, it is more desirable to set the threshold voltage to 0.36 V or more.

In the case of a partially depleted SOI-MOS transistor or bulk MOS transistor, the subthreshold coefficient S is generally 80 mV / dec or more. From FIG. 7, when the threshold voltage is 0.45 V or higher, the standby power can be reduced to 0.01 μW or less while maintaining high efficiency. Also in this case, the variation of the threshold voltage is 10%.
In consideration of the above, it is more desirable to set the threshold voltage to 0.49 V or more.

FIG. 8 shows that the main power supply voltage Vdd is 3.3 V and the output voltage Vdd_int is 0.3 V when a lithium ion battery is used.
5 shows the efficiency of the DC voltage converter and the dependence of the standby power threshold voltage on the output power Po of 5 V and the output power Po of 10 mW. Also in this case, as in FIG. 7, when the variation is not taken into account, it is desirable to set the threshold voltage to 0.33 V or more when the sub-threshold coefficient S is 60 mV / dec, and the sub-threshold coefficient S is 80 mV / dec. At this time, it is desirable to set the threshold voltage to 0.43 V or more.

Although the case where the main power supply voltage Vdd is 1.2 V and the case where the main power supply voltage Vdd is 3.3 V have been described above, the same applies to the case where the voltage or Vdd during this period is about 3.6 V. Also,
The output voltage Vdd_int is shown for the case of 0.5V,
For other voltages, for example, when Vdd_int is 0.8 V or 0.3 V, the threshold voltage of the transistor forming the DC voltage converter is the threshold of the transistor forming the integrated circuit driven by Vdd_int. It is desirable to set higher than the value voltage.

(Second Embodiment) FIG. 9 shows a second embodiment of the present invention.
FIG. 9 is a diagram for explaining the semiconductor integrated circuit device according to the embodiment and is a diagram showing a circuit configuration of a DC voltage converter 21. In this embodiment, the DC voltage converter 21 is of a switched capacitor type.

The DC voltage converter 21 of this embodiment comprises a clock generation circuit 26 and nMOS transistors M4 to M7,
Consists of capacitors C3 and C4. Clock generation circuit 26
Is controlled by a sleep signal Sleep, and when the signal Sleep is at a low level, the clock CK and its inverted clock BC
When K is generated and the signal Sleep is at a high level, the operation is disabled.

The nMOS transistors M4 and M5 and the capacitors C3 and C4 are alternately connected in series between the power supply voltage Vdd and the ground voltage Vss.
K is input. Also, the nMOS transistor M6 is
The source is connected to the output Vdd_int, which is the connection point between M5 and C4, the clock BCK is input to the gate, and the drain is M
4 and C3. The source of the nMOS transistor M7 is grounded, and the gate thereof has the clock BCK.
And the drain is connected to the connection point between M5 and C3.

When the clock CK goes high, M4
And M5 are turned on, M6 and M7 are turned off, and the same amount of charge is stored in C3 and C4 connected in series between the power supply voltage Vdd and the ground voltage Vss. When the clock CK goes low, M4 and M5 are turned off, and M6 and M7
Is turned on, and C3 and C4 are connected in parallel between the output Vdd_int and the ground voltage Vss. By repeating this operation, a voltage determined by the capacitance of C3 and C4 is output. Now, assuming that the capacitances of C3 and C4 are equal, Vdd_int becomes Vdd / 2.

In this case, the sub-threshold coefficient S is 6
When 0 mV / dec, the threshold voltage of the MOS transistor is desirably set to 0.36 to 0.37 V or more. When the subthreshold coefficient S is 80 mV / dec or more, the threshold voltage is set to 0.49 to 0.39 V. It has been confirmed that it is desirable to set the voltage to 0.5 V or more.

In this embodiment, an nMOS transistor is used as a MOS transistor.
A transistor may be used, or an nMOS transistor and a pMOS transistor may be connected in parallel. Further, the number of capacitors is not limited to two. The number is determined by the power supply voltage Vdd and the desired output voltage Vdd_int, and the number may be two or more.

The power supply voltage converter has been described above.
The same applies when a regulator for keeping the voltage constant is added to this. A regulator that operates on a main power supply is integratedly formed on the same semiconductor substrate on which a load circuit is integratedly formed. Also in this case, the sub-threshold coefficient S is set to be 60 mV / dec.
, The threshold voltage of the MOS transistor is 0.33
It has been confirmed that it is desirable to set the threshold voltage to not less than V, and when the subthreshold coefficient S is not less than 80 mV / dec, it is desirable to set the threshold voltage to not less than 0.45 V.

(Modification) The present invention is not limited to the above embodiments. In the embodiment, when a nickel-metal hydride battery having a DC voltage of about 1.2 V is used, the threshold voltage of the pMOS transistor of the DC voltage conversion circuit is smaller than −0.33 V, and the threshold voltage of the nMOS transistor is set to 0. When a lithium ion battery having a DC voltage of about 3.3 to 3.6 V is set to be higher than .33 V and the threshold voltage of the pMOS transistor of the DC voltage conversion circuit is smaller than -0.33 V, the nMOS
Although the threshold voltages of the transistors are set to be higher than 0.33 V, these threshold voltages may be set to optimal values according to the output voltage of the battery used.

That is, the absolute value of the threshold voltage of the pMOS transistor of the DC voltage conversion circuit is
If it is set larger than the absolute value of the threshold voltage of the MOS transistor and smaller than 1/2 of the output voltage of the battery. Further, the threshold voltage of the nMOS transistor of the DC voltage conversion circuit is higher than the threshold voltage of the nMOS transistor of the semiconductor integrated circuit, and is one of the output voltage of the battery.
It may be set smaller than / 2.

More specifically, from the relationship between the output power and the final stage efficiency in the DC voltage conversion circuit and the on-resistance of the MOS transistor in the circuit, an on-resistance for obtaining a desired efficiency is obtained. The relationship between the threshold voltage and the standby power may be determined based on the threshold voltage, and the threshold voltage of the MOS transistor in the DC voltage conversion circuit may be set to a value corresponding to the allowable standby power.

Further, the circuit configuration of the DC voltage conversion circuit is not limited to those shown in FIGS. 1 and 9 and can be appropriately changed according to the specifications. In addition, various modifications can be made without departing from the scope of the present invention.

[0058]

As described above in detail, according to the present invention, by setting the threshold value of the MOS transistor in the DC voltage conversion circuit for lowering the voltage of the battery and supplying power to the semiconductor integrated circuit, the DC voltage can be reduced. Since the leak current of the voltage conversion circuit is reduced, a reduction in efficiency during operation and an increase in power consumption during standby can be suppressed, and the life of the battery can be extended. Further, the withstand voltage of a circuit driven by the main power supply is improved, so that reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a semiconductor integrated circuit device including a buck DC voltage converter according to a first embodiment.

FIG. 2 is a diagram showing a timing of a signal Sleep for switching an operation mode and a standby mode of a DC voltage converter and an output voltage Vdd_int.

FIG. 3 shows the output voltage V when the DC voltage converter is in a standby mode.
The figure which shows the example of the MOS transistor for setting dd_int to ground voltage Vss.

FIG. 4 is a diagram showing the relationship between the final-stage efficiency and the on-resistance of the DC voltage converter.

FIG. 5 is a diagram showing a relationship between the efficiency of a DC voltage converter and output power.

FIG. 6 is a diagram showing a relationship between the efficiency of a DC voltage converter and output power.

FIG. 7 is a diagram showing the relationship between the efficiency and the standby power of the DC voltage converter and the threshold voltage.

FIG. 8 is a diagram showing a relationship between the efficiency of a DC voltage converter, standby power, and a threshold voltage.

FIG. 9 is a diagram illustrating a circuit configuration of a switched capacitor DC voltage converter according to a second embodiment.

FIG. 10 is a diagram showing a circuit configuration of a semiconductor integrated circuit device using a conventional DC voltage converter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Main power supply 20,21 ... DC voltage converter 22,26 ... Clock generation circuit 23 ... Pulse width modulation circuit 24 ... Prebuffer circuit 25 ... Comparator 30 ... Load circuit (semiconductor integrated circuit) M1-M7 ... MOS transistor C1 C4: Capacitor L1: Inductor R1, R2: Resistance element

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F038 BG06 DF08 EZ06 EZ20 5H007 CA02 CB17 CC07 DA06 DB01 DC05

Claims (4)

[Claims] A semiconductor integrated circuit having two modes, an operation mode in which power consumption is large and a standby mode in which power consumption is smaller than the operation mode; and a step of lowering a first DC voltage to a second DC voltage, A semiconductor integrated circuit device having a DC voltage conversion circuit for supplying power to a semiconductor integrated circuit on a same chip, wherein the semiconductor integrated circuit has an absolute value of 1/2 of a second DC voltage.
A pMIS transistor having a first threshold voltage smaller than 2 and an nMIS transistor having a second threshold voltage smaller than の of the second DC voltage; A pMIS transistor having a third threshold voltage whose absolute value is larger than the absolute value of the first threshold voltage and smaller than の of the first DC voltage; NMI having a fourth threshold voltage higher than and less than half of the first DC voltage
A semiconductor integrated circuit device including an S transistor. 2. The relationship between output power and final stage efficiency of the DC voltage conversion circuit, and on-resistance of a pMIS transistor having a third threshold voltage and an nMIS transistor having a fourth threshold voltage. The on-resistance at which a desired efficiency is obtained is obtained, and the relationship between the third and fourth threshold voltages and the standby power is obtained based on the on-resistance. The third and fourth thresholds in the DC voltage conversion circuit are obtained. 2. The semiconductor integrated circuit device according to claim 1, wherein the value voltage is set to a value corresponding to an allowable standby power. 3. When the first DC voltage is a nickel-metal hydride battery having an electromotive force of about 1.2 V and the second DC voltage is about 0.5 V, the third threshold voltage is set to-
3. The semiconductor integrated circuit device according to claim 2, wherein the third threshold voltage is set to be higher than 0.33 V and the fourth threshold voltage is set to be lower than 0.33 V. 4. The method according to claim 1, wherein the first DC voltage is about 3.3 to 3.6 V.
And when the second DC voltage is approximately 0.5 V, the third threshold voltage is set lower than -0.33 V, and the fourth threshold voltage 3. The semiconductor integrated circuit device according to claim 2, wherein is set higher than 0.33V.