JP2012049510A - Chuck for prober, method of manufacturing chuck for prober, and inspection equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chuck for a prober which has an insulation resistance and is adjustable without changing characteristics other than the insulation resistance, provide a method of manufacturing the chuck for a prober, and provide prober inspection equipment.SOLUTION: A chuck for prober 1 comprises: an insulating substrate 2 made mainly of alumina or ceramics; a first conductive layer 3; and a second conductive layer 4. Arithmetic mean roughness Ra of the edge surface is set to be smaller than 0.7 μm, or smaller than the principal surface of the insulating substrate 2.

Description

  The present invention relates to a prober chuck for holding a wafer-like semiconductor substrate during inspection, a prober chuck manufacturing method, and an inspection apparatus.

  In a manufacturing process of a semiconductor substrate on which a semiconductor element is formed, an inspection process for inspecting electrical characteristics of the semiconductor element is performed. Specifically, the electrical characteristics of the semiconductor element are inspected by applying a voltage to the wiring of the semiconductor element using an inspection apparatus.

  A semiconductor device inspection apparatus includes, for example, a prober and a tester. The prober includes a prober chuck for holding a semiconductor substrate, a stage for moving the prober chuck in the horizontal direction and the vertical direction, an inspection probe in contact with an input / output terminal of the semiconductor element, and the like. The tester is electrically connected to the prober, and inspects the electrical characteristics of the semiconductor element by applying a voltage to the semiconductor element via the inspection probe and the inspection electrode.

  First, the semiconductor substrate is held by the prober chuck so that the terminals provided on the back surface of the semiconductor substrate and the conductive layer provided on the surface of the prober chuck are electrically connected. Thereafter, the inspection probe is brought into contact with a terminal provided on the surface of the semiconductor substrate, and a voltage is applied to the conductive layer of the inspection probe and the prober chuck by a tester.

  The prober chuck includes an insulating substrate, a first conductive layer provided on one main surface of the insulating substrate, and a second conductive layer provided on the other main surface of the insulating substrate. The insulating substrate is mainly composed of ceramics, and the first conductive layer and the second conductive layer are made of metal, for example.

  In the inspection of a semiconductor substrate, it is necessary to adjust the insulation resistance value of the insulating substrate according to the characteristics of the semiconductor element to be inspected, the contents of the inspection, and the like. In order to adjust the insulation resistance value, it is necessary to change the characteristics of an insulating material such as ceramics constituting the insulating substrate or to change the material itself.

  Patent Document 1 describes, for example, that the insulation resistance varies depending on the purity of the ceramic, and that the discharge time varies depending on the crystal grain size of the ceramic.

JP 2008-4673 A

  As described above, when trying to adjust the insulation resistance value of the insulating substrate, it is necessary to change the characteristics of the insulating material constituting the insulating substrate or the material itself. The characteristics will also change.

  An object of the present invention is to provide a prober chuck, a prober manufacturing method, and a prober inspection apparatus capable of adjusting an insulation resistance value while suppressing changes in characteristics other than the insulation resistance value.

The chuck for the prober of the present embodiment is a plate-like insulating substrate mainly composed of alumina, and has an arithmetic average roughness Ra of the end face of 0.7 μm or less,
A first conductive layer formed on one main surface of the insulating substrate.

The prober for a prober according to the present embodiment is a plate-like insulating substrate whose main component is ceramics, and has an insulating surface whose arithmetic average roughness Ra is smaller than the arithmetic average roughness Ra of one main surface and the other main surface. A substrate,
A first conductive layer formed on one main surface of the insulating substrate.

The method for manufacturing a prober for a prober according to the present embodiment manufactures a prober for a prober comprising a plate-like insulating substrate mainly composed of ceramics and a first conductive layer formed on one main surface of the insulating substrate. In the manufacturing method,
A manufacturing step of manufacturing the insulating substrate;
In order to adjust the insulation resistance value of the insulating substrate, a polishing step of polishing an end surface of the insulating substrate;
Forming a first conductive layer on one main surface of the insulating substrate.

The inspection apparatus of the present embodiment is the above prober chuck including an insulating substrate and a first conductive layer, and a prober chuck on which a semiconductor substrate having a semiconductor element is placed;
A mounting table on which the prober chuck is mounted, the mounting table having a third conductive layer provided so as to be in contact with the other main surface of the prober chuck;
Voltage applying means for applying a voltage between the first conductive layer of the prober chuck and the third conductive layer of the mounting table;
A prober for supplying an electric signal to the semiconductor element.

The inspection apparatus according to the present embodiment is the above-described prober chuck including an insulating substrate, a first conductive layer, and a second conductive layer, and a prober chuck on which a semiconductor substrate having a semiconductor element is placed;
Voltage applying means for applying a voltage between the first conductive layer and the second conductive layer of the prober chuck;
A prober for supplying an electric signal to the semiconductor element.

An inspection apparatus according to the present embodiment is the above-described prober chuck including an insulating substrate, a first conductive layer, and a power feeding pattern layer, and a prober chuck on which a semiconductor substrate having a semiconductor element is placed;
A mounting table on which the prober chuck is mounted, the mounting table having a third conductive layer provided so as to be in contact with the other main surface of the prober chuck;
Voltage applying means for applying a voltage between the first conductive layer of the prober chuck and the third conductive layer of the mounting table;
A prober for supplying an electric signal to the semiconductor element.

  According to the prober chuck of the present embodiment, the prober chuck includes an insulating substrate mainly composed of alumina and the first conductive layer, and the arithmetic average roughness Ra of the end face is 0.7 μm or less.

  The relationship between the arithmetic average roughness Ra of the end face of the insulating substrate and the insulation resistance value is such that the smaller the arithmetic average roughness Ra, the higher the insulation resistance value, and the larger the arithmetic average roughness Ra, the insulation resistance value. Becomes lower. Therefore, by adjusting the arithmetic average roughness Ra of the end face, the insulating substrate does not change the material, and the change in characteristics other than the insulating resistance value such as discharge property is suppressed, and the insulation resistance value is set to a predetermined value. It becomes possible to adjust to.

In particular, when used for high-precision inspection, it is necessary to reduce the leakage current. In the case of an insulating substrate mainly composed of alumina, it is possible to reduce insulation by setting the arithmetic average roughness Ra of the end face to 0.7 μm or less. The probe has a resistance value of about 1.0 × 10 ¹⁴ Ω, and a prober chuck capable of high-precision inspection with a small leakage current can be provided.

  Further, according to the prober chuck of the present embodiment, it is composed of the insulating substrate mainly composed of ceramics and the first conductive layer, and the arithmetic mean roughness Ra of the end surface is the arithmetic of the one main surface and the other main surface. It is smaller than the average roughness Ra.

  For this reason, the insulation resistance value is increased by reducing the arithmetic average roughness Ra of the end surface of the insulating substrate, while the arithmetic average roughness Ra of the one main surface and the other main surface is increased to insulate the first conductive layer. The adhesion of the substrate can be increased. As a result, it is possible to adjust the insulation resistance value to a higher value while suppressing changes in characteristics other than the insulation resistance value such as discharge property, and to obtain a prober with high reliability.

  Further, according to the method for manufacturing a prober chuck of the present embodiment, the end surface of the insulating substrate is polished in the polishing step in order to adjust the insulation resistance value of the insulating substrate.

  By adjusting the arithmetic average roughness Ra of the end face, the insulation resistance value can be adjusted without changing the material of the insulating substrate. Therefore, it is possible to easily obtain a prober chuck having a desired insulation resistance value while suppressing changes in characteristics other than the insulation resistance value such as dischargeability.

It is the schematic which shows the structure of the probe 1 for probers which is embodiment of this invention. It is a schematic diagram for demonstrating that the arithmetic mean roughness Ra of the end surface of the insulated substrate 2 affects an insulation resistance value. It is the schematic which shows the structure of the test | inspection apparatus 10 provided with the chuck | zipper 1 for probers. It is a schematic process drawing which shows the manufacturing method of the chuck | zipper 1 for probers. It is the schematic which shows the structure of 1 A of prober chucks which are other embodiment of this invention. It is the schematic which shows the structure of the chuck | zipper 1B for probers which is further another embodiment of this invention. It is a schematic diagram which shows the formation method which forms the pattern layer 3a for electric power feeding. It is a schematic diagram for demonstrating that arithmetic mean roughness Ra of the end surface of the insulated substrate 2 affects a conductor resistance value. 2 is a cross-sectional view showing an outer peripheral edge 2a of an insulating substrate 2. FIG. It is the schematic which shows the measuring method of an insulation resistance value. It is a graph which shows the relationship between the voltage application time when changing arithmetic average roughness Ra, and an insulation resistance value. It is a graph which shows the relationship between the voltage application time when changing a void ratio, and an insulation resistance value. It is the schematic which shows the measuring method of a conductor resistance value. It is a graph which shows the change of the conductor resistance value when changing the layer thickness of a chromium layer.

  FIG. 1 is a schematic view showing the configuration of a prober chuck 1 according to an embodiment of the present invention. 1A shows a cross-sectional view, and FIG. 1B shows a perspective view.

  The prober chuck 1 includes an insulating substrate 2, a first conductive layer 3, and a second conductive layer 4. The insulating substrate 2 is made of an insulating material such as ceramics. The shape of the insulating substrate 2 is not particularly limited. For example, the shape in plan view is formed in a rectangular plate shape or a circular disc shape. In this embodiment, as shown in the perspective view of FIG. 1B, the insulating substrate 2 is a disk-shaped member.

  Examples of ceramics that can be used as the insulating substrate 2 include metal oxide ceramics such as alumina and zirconia, carbonized ceramics such as silicon carbide, and nitride ceramics such as silicon nitride and boron nitride. Each ceramic has different electrical characteristics such as insulation resistance, heat transfer characteristics such as thermal resistance, and material characteristics such as mechanical strength, so it is necessary depending on the type of semiconductor substrate to be inspected and the contents of the inspection. What is necessary is just to select the ceramics which have the characteristic. Among these, alumina is preferably used because each characteristic is generally good as an insulating substrate for a prober chuck.

  The dimension of the insulating substrate 2 is not particularly limited and may be the same or larger than the semiconductor substrate to be held, but the larger one than the semiconductor substrate can support the semiconductor substrate more stably. preferable. The thickness of the insulating substrate 2 may be 2 mm to 30 mm, for example.

  The first conductive layer 3 is a layered member made of a conductive material and formed on one main surface of the insulating substrate 2. As the conductive material constituting the first conductive layer 3, various materials can be used as long as they can be formed on the main surface of the insulating substrate 2. For example, gold, silver, copper, aluminum, chromium, nickel, titanium, platinum, palladium, or the like can be used. The first conductive layer 3 may be composed of a plurality of layers, and each layer is formed of different metals. For example, a chromium layer may be formed on one main surface of the insulating substrate 2, and a nickel layer may be further formed on the chromium layer. A chromium layer may be formed on one main surface of the insulating substrate 2, and on the chromium layer. Further, a gold layer may be formed. Thus, when the chromium layer is interposed between the insulating substrate 2 and the nickel layer or the gold layer, the adhesive strength between the first conductive layer 3 and the insulating substrate 2 can be increased. Further, a titanium layer, a platinum layer, and a gold layer may be sequentially stacked on one main surface of the insulating substrate 2.

  The formation method for forming the first conductive layer 3 on one main surface of the insulating substrate 2 may be appropriately selected depending on the material of the insulating substrate 2 and the material of the first conductive layer 3. For example, sputtering, ion plating, plating For example, the first main surface of the insulating substrate 2 manufactured in advance may be formed to have a predetermined thickness. In the case where the first conductive layer 3 is composed of a plurality of layers, the layers may be formed a plurality of times by the same formation method or different methods by changing the type of metal used as a raw material.

  The first conductive layer 3 is formed on one main surface of the insulating substrate 2 so as to be in contact with a terminal formed on the back surface of the semiconductor substrate to be held. The first conductive layer 3 is preferably formed on the entire surface of the one main surface, but may be formed in a partial region of the one main surface as long as it can contact the terminal formed on the back surface of the semiconductor substrate. , It is not necessarily formed on the entire surface of the one main surface. Moreover, the thickness of the 1st conductive layer 3 is formed in 0.1 micrometer-500 micrometers, for example.

  The second conductive layer 4 has the same configuration as that of the first conductive layer 3, and the material used, the region formed on the other main surface, the thickness of the layer, and the like are appropriately selected from the above ranges. If it is in said range, it may differ from the 1st conductive layer 3, and may be the same.

  The prober chuck 1 of the present embodiment is configured so that the end surface of the insulating substrate 2 has a predetermined arithmetic average roughness Ra. The present inventors have found that the insulation resistance value of the insulating substrate 2 is affected by the arithmetic average roughness Ra of the end surface of the insulating substrate 2, and have completed the present invention.

  Specifically, the relationship between the arithmetic average roughness Ra of the end face of the insulating substrate 2 and the insulation resistance value is such that the smaller the arithmetic average roughness Ra, the higher the insulation resistance value and the larger the arithmetic average roughness Ra. The more it is done, the lower the insulation resistance value becomes.

Therefore, the insulating substrate 2 can be adjusted to a predetermined value without changing the material, suppressing changes in characteristics other than the insulating resistance value such as dischargeability, and the like. As the range of the insulation resistance value that can be adjusted, for example, when the arithmetic average roughness Ra is changed from 0.2 μm to 1.5 μm, the insulation resistance value is adjusted within the range of 10 ¹¹ Ω to 10 ¹⁶ Ω. Can do.

  In the inspection of the semiconductor substrate, for example, when a voltage is applied to the first conductive layer 3, a slight leakage current to the second conductive layer 4 is generated. Although depending on the contents of the inspection, this leakage current may affect the inspection result particularly when a highly accurate inspection is performed. Therefore, it is necessary to reduce the leakage current. The leakage current can be reduced by increasing the insulation resistance value of the insulating substrate 2.

  FIG. 2 is a schematic diagram for explaining that the arithmetic average roughness Ra of the end face of the insulating substrate 2 affects the insulation resistance value. FIG. 2 schematically shows a cross section of the end face of the insulating substrate 2. 2A shows a case where the arithmetic average roughness Ra is large, and FIG. 2B shows a case where the arithmetic average roughness Ra is small.

  First, a description will be given including a portion in which the arithmetic average roughness Ra of the end face of the insulating substrate 2 is estimated with respect to a mechanism that affects the insulation resistance value.

  Moisture (water vapor) in the atmosphere is taken in in a state where not only water but also organic substances and sulfur compounds are dissolved. When moisture in the atmosphere is adsorbed on the end face of the insulating substrate 2, the adsorbed moisture is detached from the end face as the ambient temperature increases and the humidity decreases. Although the water is released, the organic substances and sulfur compounds contained in the adsorbed water remain on the end face as they are.

  Since organic substances, sulfur compounds, and the like remaining on the end face have lower insulation resistance than alumina, the insulation resistance value of the insulating substrate 2 in a state where the residue is attached is affected by the residue and becomes low.

  The amount of the residue that affects the insulation resistance depends on the surface roughness of the end face. As shown in the schematic diagram of FIG. 2 (a), if the surface roughness is large, the amount of deposits 5 adhering to the end face increases, and also the amount of residue cannot be removed sufficiently even by washing. Become. As a result, when the surface roughness of the end face is large, the insulation resistance value is lowered. In particular, if left in the atmosphere for a long period of time, even if the temperature and humidity are constant, the amount of adhesion increases and the insulation resistance value further decreases. As shown in the schematic diagram of FIG. 2 (b), if the surface roughness is small, the amount of deposits 5 adhering to the end surface is reduced and can be sufficiently removed by washing, so the amount of residues is reduced. As a result, if the surface roughness of the end face is small, the insulation resistance value is increased.

  Therefore, it is preferable to increase the insulation resistance value of the insulating substrate 2 as the prober chuck 1 used for high-precision inspection. In order to increase the insulation resistance value of the insulating substrate 2, it is preferable to reduce the arithmetic average roughness Ra of the end surface of the insulating substrate 2. For example, the arithmetic average roughness Ra of the end surface of the insulating substrate 2 is It is preferable to make it smaller than the arithmetic average roughness Ra of the one main surface and the other main surface.

  The arithmetic mean roughness Ra of the one main surface and the other main surface is preferably increased in order to increase the bonding strength between the first conductive layer 3 and the second conductive layer 4 by the anchor effect, and the insulation resistance value is increased. Therefore, it is preferable to reduce the arithmetic average roughness Ra of the end face.

  Below, the case where an alumina is used as a main component as a ceramic material which comprises the insulated substrate 2 is demonstrated to an example.

  As described above, alumina generally has excellent characteristics and is often used as a material constituting the insulating substrate 2 of the prober chuck 1.

  In the insulating substrate 2 containing alumina as a main component, the arithmetic average roughness Ra of the end surface is made smaller than the arithmetic average roughness Ra of one main surface and the other main surface of the insulating substrate 2. The arithmetic average roughness Ra of the end surface is 0.7 μm or less, and the arithmetic average roughness Ra of the one main surface and the other main surface is larger than 0.7 μm.

  At the time of inspection, for example, a semiconductor substrate is placed in contact with the first conductive layer 3, the second conductive layer 4 is grounded, and a predetermined voltage is applied to the first conductive layer 3 for use. The insulation resistance of the insulating substrate 2 is measured by reproducing such a use state. Since it is not stable at the initial stage when a predetermined voltage is applied to the first conductive layer 3, the value after a certain time (for example, 12 hours) has passed is taken as the measured value of the insulation resistance.

When the first conductive layer 3 and the second conductive layer 4 were formed on an alumina substrate as the insulating substrate 2 and the insulation resistance value was measured, if the arithmetic average roughness Ra of the end face was 0.7 μm or less, the insulation resistance value was The prober chuck 1 is about 1.0 × 10 ¹⁴ Ω and can perform a high-precision inspection with a small leakage current.

  The arithmetic average roughness Ra of the end face of the insulating substrate 2 can be adjusted by appropriately replacing the grindstone used for polishing. The grindstone for polishing the end face of the insulating substrate 2 is provided with a resin layer in which diamond abrasive grains are dispersed in an aluminum base. By appropriately changing the particle diameter of the diamond abrasive grains, the arithmetic average roughness Ra of the end face of the insulating substrate 2 after polishing can be adjusted to a desired value.

  In order to set the arithmetic average roughness Ra to 0.2 μm, for example, the end surface of the insulating substrate 2 is polished with a # 140 grindstone having an abrasive grain size of 140 to 170 μm, and then the abrasive grain size is 25 to 35 μm. What is necessary is just to grind | polish the said end surface with the grindstone of count # 600, and finally grind | polish the said end surface with the grindstone of count # 2000 whose abrasive particle diameter is 5-10 micrometers. Similarly, in order to set the arithmetic average roughness Ra to 0.5 μm, the end surface of the insulating substrate 2 is sequentially polished with a grindstone with a count # 140 and a grindstone with a count # 600, and then a count with an abrasive grain size of 11 to 20 μm. The end surface may be polished with a # 1200 grindstone. In addition, in order to set the arithmetic average roughness Ra to 0.7 μm, the end surface of the insulating substrate 2 is sequentially polished with a grindstone with a count # 140 and a grindstone with a count # 600, and then the count # with an abrasive grain size of 18 to 25 μm. An 800 grindstone may be used. In addition, in order to set the arithmetic average roughness Ra to 1.5 μm, the end face of the insulating substrate 2 is polished with a count # 140, and then a grindstone with a count # 600 is used.

  Polishing of the end surface of the insulating substrate 2 can be performed by a known polishing method, and for example, a cylindrical grinder can be used.

  Furthermore, it has been clarified that the insulating substrate 2 has a plurality of voids, and these voids affect the insulation resistance value. This void (void) increases or decreases depending on various conditions at the time of manufacturing the insulating substrate 2. For example, if the pressure applied during molding (molding pressure) is increased, the amount of voids can be reduced and the insulation resistance can be increased. Furthermore, it is possible to further increase the insulation resistance by performing hot isostatic pressing (hereinafter referred to as “HIP”).

  The void amount is evaluated by a void ratio which is a ratio of an area occupied by the void in an arbitrary cross section of the insulating substrate 2. Since the void is a void, the void portion appears as a recess in a certain cross section. Therefore, in the measurement area of a certain cross section, the void ratio is obtained by measuring the opening area of the recess and expressing the ratio of the sum of the opening area to the entire area of the measurement area as a percentage.

  The void ratio is measured by first cutting an insulating substrate in an arbitrary cross section and mirror-polishing the cut surface. And the opening area of a recessed part is measured with this cut surface which carried out mirror polishing, and a void ratio is computed from the ratio of the opening area with respect to the whole area of a cut surface.

  The mirror polishing is performed to such an extent that the concave portion of the void portion can be visually recognized. For example, mirror polishing is performed through the steps of primary polishing, secondary polishing, and tertiary polishing. In the primary polishing, a flat roughing grindstone is used. The grindstone used here is one in which diamond abrasive grains having an average particle diameter of 45 μm are fixed in a state dispersed in a resin. In the secondary polishing, secondary polishing is performed using a copper surface plate. With the abrasive surface made of diamond having an average particle diameter of 3 μm and an aqueous polishing liquid interposed between the surface plate and the cut surface of the insulating substrate, the cutting surface is pressed against the surface plate, and the surface plate and the insulating substrate are Slide to polish. The polishing time is, for example, 1 hour. In the third polishing, third polishing is performed using a surface plate made of tin. A test piece is pressed against the surface plate with diamond abrasive grains having an average particle diameter of 1 μm and an aqueous polishing liquid interposed between the surface plate and the insulating substrate, and the surface plate and the insulating substrate are slid. Grind. The polishing time is, for example, 1 hour.

  The void ratio evaluated in this manner is preferably 0.9% or less. By setting the void ratio to 0.9% or less, the insulation resistance can be increased and the insulation resistance can be stabilized in a shorter time.

FIG. 3 is a schematic diagram showing a configuration of the inspection apparatus 10 including the prober chuck 1.
The inspection apparatus 10 includes a prober chuck 1, an XYZθ stage 11, a prober 12, a control unit 13, and a voltage application unit 14, and performs various inspections of the semiconductor substrate 15 held on the surface of the prober chuck 1.

  An XYZθ stage (hereinafter, also simply referred to as “stage”) 11 fixes a prober chuck 1 on the top, and moves the prober chuck 1 in the horizontal direction (XY direction) and the vertical direction (Z direction), The prober chuck 1 is rotated in the rotation direction θ in the horizontal plane. Since the prober chuck 1 holds the semiconductor substrate 15, by moving and rotating the prober chuck 1, the semiconductor substrate 15 can be moved and rotated to change the posture required for the inspection of the semiconductor substrate 15. .

  The prober 12 includes a plurality of probes 12 a that abut on the input / output terminals of the semiconductor elements included in the semiconductor substrate 15, and supplies electrical signals for inspection to the semiconductor elements in accordance with instructions from the control unit 13.

  The control unit 13 includes an information processing device, for example, and supplies an electrical signal for inspection to the semiconductor element in accordance with a program stored in advance, and analyzes the electrical signal output from the semiconductor element to generate a semiconductor. Judge whether the element is good or defective. The determination result may be further output to another information processing apparatus or display device.

  The voltage application unit 14 applies a voltage between the first conductive layer 3 and the second conductive layer 4 of the prober chuck 1. In the present embodiment, the second conductive layer 4 is grounded, and a DC voltage Vdc is applied to the first conductive layer 3.

  The prober chuck 1 is fixed to the stage 11 so that the first conductive layer 3 is on the upper side, and holds the semiconductor substrate 15 in contact with the first conductive layer 3.

  The prober 12 is arranged so that the probe 12a contacts a predetermined terminal of a semiconductor element, and an electric signal is supplied and detected by the control unit 13. At this time, a DC voltage Vdc is applied between the first conductive layer 3 and the second conductive layer 4 of the prober chuck 1 by the voltage application unit 14.

  In order to stabilize the insulation resistance value of the prober chuck 1, voltage application to the prober chuck 1 by the voltage application unit 14 may be performed for a predetermined time before the electric signal is supplied from the prober 12.

  If you change the insulation substrate material of the prober chuck to change the insulation resistance, the prober chuck characteristics will change, so it will be necessary to change the measurement conditions of the inspection device. Since the prober chuck 1 of this embodiment can suppress changes in characteristics other than the insulation resistance value, it is not necessary to change the measurement conditions of the inspection apparatus 10 and it is possible to perform a more accurate inspection. .

FIG. 4 is a schematic process diagram showing a method of manufacturing the prober chuck 1.
The manufacturing method according to the present embodiment includes a manufacturing step S1 for manufacturing the insulating substrate 2, a polishing step S2 for polishing the end surface of the insulating substrate 2 in order to adjust the insulation resistance value of the insulating substrate 2, and one of the insulating substrates 2. Forming step S3 for forming first conductive layer 3 and second conductive layer 4 on the main surface and the other main surface, respectively.

  A conventionally known ceramic substrate manufacturing process can be applied to the manufacturing process S1. Ceramic powder is prepared as a raw material, and this is formed by cold isostatic pressing (hereinafter referred to as “CIP”). The formed body is fired at a firing temperature corresponding to the raw material ceramics. You may give a HIP process, an annealing process, etc. at the time of baking. The void ratio can be adjusted according to the conditions of the manufacturing step S1. The insulating substrate 2 obtained by baking may be subjected to a grinding process for dimensional adjustment as necessary.

  In the polishing step S2, the end surface of the manufactured insulating substrate 2 is polished so as to have a desired arithmetic average roughness Ra.

  The correlation between the arithmetic average roughness Ra of the end face of the insulating substrate 2 and the insulation resistance value of the prober chuck 1 is determined in advance from the measurement results, and the insulation resistance of the prober chuck 1 required for the insulating substrate 2 is determined. The end face is polished to the arithmetic average roughness Ra according to the value. The end surface polishing is performed using a grinder that is previously associated with the arithmetic average roughness Ra using a cylindrical grinder or the like.

If necessary, at least one main surface or the other main surface of the insulating substrate 2 may be polished. At this time, the polishing process is performed so that the arithmetic average roughness Ra of the one main surface and the other main surface is larger than the arithmetic average roughness Ra of the end surface.
After the polishing treatment, cleaning may be performed as necessary, such as acid cleaning, ultrasonic cleaning, and solvent cleaning.

  In the formation step S3, the first conductive layer 3 and the second conductive layer 4 are formed on one main surface and the other main surface of the insulating substrate 2 whose end surfaces are subjected to polishing treatment, respectively. The formation of the first conductive layer 3 and the second conductive layer 4 is performed by sputtering, ion plating, plating, or the like. In the plating, components contained in the plating solution remain on the end surface of the insulating substrate 2 to increase the insulation resistance. Sputtering and ion plating are preferable because they may have an influence.

  FIG. 5 is a schematic view showing a configuration of a prober chuck 1A according to another embodiment of the present invention. Fig.5 (a) shows sectional drawing, FIG.5 (b) shows a perspective view.

  The prober chuck 1A of this embodiment includes an insulating substrate 2 and a first conductive layer 3 formed on one main surface of the insulating substrate 2, and the above-described prober chuck 1 includes a second conductive layer 4. Not only that it is different.

  As described above, the prober chuck is used by applying a voltage between two conductive layers sandwiching an insulating substrate. In the inspection apparatus using the prober chuck 1A, the prober chuck 1A does not include the second conductive layer 4, but the stage, which is a mounting table, includes the third conductive layer. When the prober chuck 1A is used, it is placed on the stage so that the other main surface of the insulating substrate 2, that is, the main surface on which the conductive layer is not formed, is in contact with the third conductive layer of the stage. Therefore, functionally, the third conductive layer exhibits the same function as the second conductive layer 4 of the prober chuck 1.

  The third conductive layer is formed of the same material as that of the second conductive layer 4, but is not formed on the insulating substrate 2. Therefore, the thickness of the layer is appropriately selected according to the stage.

  The third conductive layer is grounded in the same manner as the second conductive layer 4 when inspecting the semiconductor element. Since the third conductive layer is provided on the stage of the inspection apparatus, the ground potential can be made more stable than that provided on the insulating substrate 2, and inspection with higher accuracy can be performed.

  FIG. 6 is a schematic view showing a configuration of a prober chuck 1B which is still another embodiment of the present invention.

  The prober chuck 1 </ b> B of this embodiment includes a power feeding pattern layer 3 a that is partially formed on the end surface of the insulating substrate 2 and is electrically connected to the first conductive layer 3. One or a plurality of power supply pattern layers 3 a are provided on the end face of the insulating substrate 2, and can supply power to the first conductive layer 3 by being connected to a power source. For example, the voltage application unit 14 and the power feeding pattern layer 3 a are electrically connected, and the DC voltage Vdc is applied to the first conductive layer 3 by the voltage application unit 14.

  The power feeding pattern layer 3 a is formed in a rectangular shape, and is connected to the first conductive layer 3 so that any one side of the rectangle is along the outer edge portion of the first conductive layer 3. The power feeding pattern layer 3 a is preferably formed in the same process as the first conductive layer 3. FIG. 7 is a schematic view showing a forming method for forming the power feeding pattern layer 3a.

  An insertion hole 6 for inserting a helicate is provided in the end face of the insulating substrate 2 produced in advance (FIG. 7A). The insertion hole 6 may be formed in advance when the insulating substrate 2 is formed, or may be ground after sintering. A mask tape 9 is affixed to the entire end surface of the insulating substrate 2 (FIG. 7B), and the mask tape 9 is removed only from the portion where the power supply pattern layer 3a is to be formed (FIG. 7C). Here, a rectangular exposed portion including the opening of the insertion hole 6 inside is provided. Note that the mask tape 9 is formed of, for example, a polyimide resin.

  Next, a metal layer made of chromium is formed on the exposed portion of the insulating substrate 2 by, for example, sputtering (FIG. 7D). Since one main surface of the insulating substrate 2 is not masked, a chromium layer is formed. A chrome layer is also formed on the exposed portion of the end surface in the same manner as the one main surface. Similarly, a gold layer is further formed on the chromium layer. The gold layer is formed in the same region as the region where the chromium layer is formed. Thus, the first conductive wire layer 3 made of chrome-gold is formed on one main surface of the insulating substrate 2, and the power feeding pattern layer 3a made of chrome-gold is formed on the end surface (FIG. 7E). ). At this time, since the opening of the insertion hole 6 is not blocked by the mask tape 9, a chromium-gold layer similar to the first conductive layer 3 and the power feeding pattern layer 3 a is formed on the inner wall surface of the insertion hole 6. It is formed integrally with 3a.

  FIG. 7F is a cross-sectional view around the power feeding pattern layer 3a. After the first conductive wire layer 3 and the power feeding pattern layer 3a are formed, a helicate 6a made of SUS or the like is inserted into the insertion hole 6.

  When it is actually electrically connected to the voltage application unit 14, if it is attempted to directly connect the wiring provided in the voltage application unit 14 to the power supply pattern layer 3 a, it needs to be connected by solder or the like. It is difficult. Therefore, in order to easily attach and detach the wiring, it is preferable to attach the connection terminal 7 to the power supply pattern layer 3 a and connect the wiring to the connection terminal 7.

  The connection terminal 7 is a hook-shaped metal member made of, for example, SUS and having a rectangular plate member having a thickness of 0.2 to 1.5 mm and subjected to two 90-degree bending processes at one end in the longitudinal direction. However, what is necessary is just to be electrically connectable with the voltage application part 14 or the measurement terminal of the resistance meter mentioned later, and a material, a shape, etc. are not limited to these. Specifically, the contact portion 7a extending in the tangential direction of the end surface, the bent portion 7b provided parallel to the contact portion 7a and spaced from the contact portion 7a, and the contact portion 7a and the bent portion 7b, respectively. It consists of the junction part 7c provided over the edge part. A through hole is formed in the contact portion 7 a at a position corresponding to the insertion hole 6. With the contact portion 7a in contact with the power feeding pattern layer 3, a bolt 8 made of SUS or titanium or the like is inserted into the through hole of the contact portion 7a, screwed into the helisert 6a, and the connection terminal 7 Is fastened and fixed to the insulating substrate 2 (FIG. 7G).

  The connection terminal 7 is formed on the inner wall surface of the bolt 8, the helicate 6 a and the insertion hole 6 as well as being electrically connected to the power supply pattern layer 3 a by the contact portion 7 a contacting the power supply pattern layer 3 a. It is electrically connected to the power feeding pattern layer 3a through the chrome-gold layer.

  One or a plurality of power supply pattern layers 3a can be provided, and a plurality of power supply pattern layers 3a are previously provided so that the position and number of power supply can be appropriately changed according to the specifications of the inspection apparatus, the inspection method, and the like. It is preferable to provide it. In the above description, the power supply pattern layer 3a that is electrically connected to the first conductive layer 3 and supplies power to the first conductive layer 3 has been described. However, the power supply pattern layer 3a is electrically connected to the second conductive layer 4, and the second A power supply pattern layer for supplying power to the conductive layer 4 may be provided. The power feeding pattern layer connected to the second conductive layer 4 is configured similarly to the power feeding pattern layer 3 a connected to the first conductive layer 3.

  Further, electrical characteristics required for the prober chuck include a reduction in conductor resistance of the first conductive layer 3 and the second conductive layer 4. When the first conductive layer 3 and the second conductive layer 4 are independent conductor layers, it is preferable as the electrical characteristics of the prober chuck that the first conductive layer 3 and the second conductive layer 4 have lower conductor resistances.

  As described above, when inspecting the semiconductor element, the voltage application unit 14 and the connection terminal 7 are connected to apply a voltage to the first conductive layer 3. Since the electrical characteristics required for the prober chuck are those for actually inspecting the semiconductor element, it is necessary to reduce the conductor resistance when the connection terminal 7 is used.

  When the power supply pattern layer 3a for connecting the connection terminals 7 is provided as in the prober chuck 1B, the first conductive layer 3 can be obtained by reducing the arithmetic average roughness Ra of the end face of the insulating substrate 2. The conductor resistance can be reduced.

  For example, when the first conductive layer 3 and the power feeding pattern layer 3a are made of chrome-gold, the conductor resistance of the first conductive layer 3 when the arithmetic average roughness Ra of the end face of the insulating substrate 2 is less than 1.6 μm. The arithmetic average roughness Ra is preferably 1.0 μm or less.

  As described above, the arithmetic average roughness Ra of the end face of the insulating substrate 2 affects the conductor resistance of the first conductive layer 3 because the contact resistance between the connection terminal 7 and the power feeding pattern layer 3a is determined by the insulating substrate 2. This is considered to be because it is influenced by the arithmetic average roughness Ra of the end face.

  FIG. 8 is a schematic diagram for explaining that the arithmetic average roughness Ra of the end face of the insulating substrate 2 affects the conductor resistance value. FIG. 8 schematically shows a cross section when the end surface of the insulating substrate 2 provided with the power feeding pattern layer 3a is cut in parallel to the main surface. FIG. 8A shows a case where the arithmetic average roughness Ra is large, and FIG. 8B shows a case where the arithmetic average roughness Ra is small.

  As shown in FIG. 8A, when the arithmetic mean roughness Ra of the end face of the insulating substrate 2 is large, the surface roughness of the end face is reflected in the surface state of the feed pattern layer 3a, and the feed pattern layer 3a. The surface roughness of the material also increases. When the connection terminal 7 is connected to the power supply pattern layer 3a having a large surface roughness, the convex portion of the power supply pattern layer 3a comes into contact with the contact portion 7a of the connection terminal 7, so that a sufficient contact area is obtained. However, the contact resistance between the connection terminal 7 and the power feeding pattern layer 3a is increased. Thereby, the conductor resistance of the 1st conductive layer 3 including the terminal 7 for a connection and the pattern layer 3a for electric power feeding becomes high. As shown in FIG. 8B, when the surface roughness of the power feeding pattern layer 3a is reduced, the contact area between the power feeding pattern layer 3a and the contact portion 7a of the connection terminal 7 is increased, and the contact resistance is lowered. be able to. Thereby, the conductor resistance of the 1st conductive layer 3 including the terminal 7 for a connection and the pattern layer 3a for electric power feeding can be reduced.

  Note that the second conductive layer 4 is also provided with a power feeding pattern layer for feeding power to the second conductive layer 4. When the connection terminal is used, the insulating substrate 2 is the same as the first conductive layer 3. If the arithmetic average roughness Ra of the end face is reduced, the conductor resistance of the second conductive layer 4 can be reduced.

  Further, regarding the respective conductor resistances of the first conductive layer 3 and the second conductive layer 4, in particular, in the structure of chromium-nickel, chromium-gold, etc. with chromium as an underlayer, if the chromium layer thickness is reduced, the first conductivity The conductor resistance of each of the layer 3 and the second conductive layer 4 can be lowered.

  As an inspection condition when inspecting a semiconductor element using a prober chuck, for example, the inspection may be performed by heating to about 300 ° C. In particular, under such high temperature conditions, the conductor resistance of the first conductive layer 3 and the second conductive layer 4 tends to increase, and the increase in conductor resistance can be suppressed by reducing the chromium layer thickness.

  By setting the chromium layer thickness to 0.4 μm or less, an increase in the conductor resistance of the first conductive layer 3 and the second conductive layer 4 can be suppressed.

  As still another embodiment of the present invention, there is one in which the outer peripheral edge portion of the insulating substrate 2 is chamfered (C surface processing). FIG. 9 is a cross-sectional view showing the outer peripheral edge 2 a of the insulating substrate 2. FIG. 9 is a cross-sectional view when the insulating substrate 2 is cut so as to be orthogonal to the main surface. When the power supply pattern layer 3a is provided, the connection portion between the first conductive layer 3 and the power supply pattern layer 3a is the outer peripheral edge of the insulating substrate 2, and the outer peripheral edge has an angle formed between the end surface and the main surface. The corner is about 90 degrees. When the first conductive layer 3 and the power feeding pattern layer 3a are provided by ion plating or the like, the layer thickness of the connection portion covering the corner portion may be thin, and a crack or peeling may occur. When a crack or the like occurs, the conductor resistance of the connection portion increases, and as a result, the conductor resistance of the first conductive layer 3 increases. By chamfering the corners of the outer peripheral edge 2a of the insulating substrate 2, the angle formed between the chamfered portion, the end surface, and the main surface becomes an obtuse angle, so that it is possible to prevent the occurrence of defects such as cracks in the connection portion. .

  The chamfering process can be performed by cutting the insulating substrate 2 after firing, for example. The arithmetic average roughness Ra of the chamfered portion is preferably larger than the arithmetic average roughness Ra of the end face of the insulating substrate 2. By doing so, the adhesive strength of the connection part and chamfering part of the 1st conductive layer 3 and the pattern layer 3a for electric power feeding can be raised. The arithmetic average roughness Ra of the chamfered portion is preferably equal to the arithmetic average roughness Ra of the main surface of the insulating substrate 2, and may be within a range of ± 10% with respect to Ra of the main surface, for example. preferable. By doing so, the conductor resistance in the connection part of the 1st conductive layer 3 and the pattern layer 3a for electric power feeding can be made equivalent to the 1st conductive layer 3. FIG.

<Insulation resistance>
In the following, the prober chuck 1 was actually manufactured using the alumina substrate as the insulating substrate 2, and the relationship between the arithmetic average roughness Ra of the end face and the insulation resistance value and the relationship between the void ratio and the insulation resistance value were measured. The arithmetic average roughness Ra was measured using a stylus type surface roughness meter in accordance with JIS B 0651: 2001.

  As the alumina, high purity alumina having a purity of 99.7% was used, and a molded body was obtained by CIP. The molded body was fired at a firing temperature of 1600 degrees to obtain an insulating substrate 2. HIP treatment and annealing treatment were performed as necessary. In the first conductive layer 3 and the second conductive layer 4, a nickel layer having a thickness of 1.0 to 2.0 μm was formed on a chromium layer having a thickness of 0.1 to 0.2 μm by ion plating.

  The end surface of the insulating substrate 2 was polished with a grindstone while rotating the insulating substrate 2 at a rotational speed of 100 rpm using a cylindrical grinding machine (manufactured by Sanpo Seiki Kogyo Co., Ltd., stocker S30-12). A desired arithmetic average roughness Ra was obtained by appropriately changing the count of the used grindstone.

  The insulation resistance value was measured by a measurement method as shown in FIG. A PID temperature control heater 101 is provided inside the grounded shield box 100, an alumina insulating plate 102 is placed on the heater, and a prober chuck 1 is placed thereon so that the first conductivity 3 is on the upper side. Install.

  The thermometer 103 detects a temperature change by arranging a detection probe at a boundary portion between the insulating plate 102 and the prober chuck 1. The humidity inside the shield box 100 was measured with the hygrometer 104.

During the measurement, the inside of the shield box 100 was made a nitrogen atmosphere by introducing N ₂ gas. The resistance measuring device 105 applies a DC voltage of 250 V to the first conductive layer 3 and measures the change over time in the leakage current of the second conductive layer 4, so that the insulation resistance value is determined from the voltage value and the current value according to Ohm's law. Was calculated.

  First, the arithmetic average roughness Ra of the end face of the insulating substrate 2 is 0.2 μm (Example 1), 0.5 μm (Example 2), 0.7 μm (Example 3), 1.0 μm (Example 4), A prober chuck 1 having a thickness of 1.5 μm (Example 5) was produced, and the relationship between the voltage application time of the DC voltage and the insulation resistance value was measured. The arithmetic mean roughness Ra of one main surface and the other main surface of the insulating substrate 2 was 0.8 μm, and the void ratio was 0.8%.

  FIG. 11 is a graph showing the relationship between the voltage application time and the insulation resistance value when the arithmetic average roughness Ra is changed. The horizontal axis represents the voltage application time [hr], and the vertical axis represents the insulation resistance value [Ω].

The measurement result when the arithmetic average roughness Ra is 0.2 μm (Example 1) is indicated by a plot “□”, and the measurement result when the arithmetic average roughness Ra is 0.5 μm (Example 2) is indicated by a plot “◇”. And the measurement result when the arithmetic average roughness Ra is 0.7 μm (Example 3) is shown by a plot of “Δ”, and the measurement result when the arithmetic average roughness Ra is 1.0 μm (Example 4) is “×”. The results are shown in a plot, and the measurement results with an arithmetic average roughness Ra of 1.5 μm (Example 5) are shown as “*” plots.
The measured values are shown in Table 1.

From the graph, it can be seen that when the arithmetic average roughness Ra of the end face of the insulating substrate 2 is reduced, the insulation resistance value is increased. Assuming that a prober chuck is used in an inspection apparatus for a semiconductor substrate, an insulation resistance value of about 5 × 10 ¹³ Ω is required as an insulation resistance value. Therefore, the arithmetic average roughness Ra of the end face of the insulating substrate 2 is The thickness is preferably 0.7 μm or less. Further, when the arithmetic average roughness Ra of the end face of the insulating substrate 2 is 0.5 μm or less, the insulation resistance value is about 10 times or more compared with the case where the arithmetic average roughness Ra is 0.7 μm. It is more preferable because the insulation resistance value is remarkably high.

  Next, the prober chuck 1 and the HIP treatment with void ratios of 0.8% (Example 6), 0.9% (Example 7), and 1.5% (Example 8) without HIP treatment ( The prober chuck 1 with a void ratio of less than 0.1% at 1550 ° C. and 195 MPa and an annealing treatment temperature of 1400 ° C. (Example 9) and 1500 ° C. (Example 10) was produced. The relationship between voltage application time and insulation resistance value was measured. In addition, all surface roughness Ra of the end surface was 0.5 micrometer.

  The void ratio was obtained by cutting out a void ratio measuring sample (10 mm × 10 mm × 5 mm) from the finished resistance measurement and mirror-finishing it. Using this image analysis device (Mitani Corporation, WIN LOOF ver. 5.7), the opening area by the void was measured, and the ratio of the sum of the opening area to the area of the area to be analyzed was expressed as a percentage. .

  FIG. 12 is a graph showing the relationship between the voltage application time and the insulation resistance value when the void ratio is changed. The horizontal axis represents the voltage application time [hr], and the vertical axis represents the insulation resistance value [Ω].

The measurement result when the void ratio is 1.5% (Example 8) is indicated by a plot of “□”, the measurement result when the void ratio is 0.9% (Example 7) is indicated by a plot of “◇”, and the void ratio is Shows a measurement result of 0.8% (Example 6) by a plot of “Δ”, and a measurement result of a void ratio of less than 0.1% and an annealing temperature of 1400 ° C. (Example 9) is a plot of “◯” The measurement results at a void ratio of less than 0.1% and an annealing temperature of 1500 ° C. (Example 10) are shown by “x” plots.
The measured values are shown in Table 2.

As can be seen from the graph, since the arithmetic mean roughness Ra of the end face is 0.5 μm, a high insulation resistance value of 5 × 10 ¹³ or more is maintained regardless of the void ratio. Moreover, when the void ratio is 0.9% or less, an insulation resistance value of about 1 × 10 ¹⁵ can be achieved, which is particularly preferable.

<Conductor resistance>
In the following, the prober chuck 1B was actually manufactured using the alumina substrate as the insulating substrate 2, and the relationship between the arithmetic average roughness Ra of the end face and the conductor resistance value and the relationship between the chromium layer thickness and the conductor resistance value were measured. The arithmetic average roughness Ra was measured using a stylus type surface roughness meter in accordance with JIS B 0651: 2001 as described above.

  As the alumina, high purity alumina having a purity of 99.7% was used, and a molded body was obtained by CIP. The molded body was fired at a firing temperature of 1600 degrees to obtain an insulating substrate 2. HIP treatment and annealing treatment were performed as necessary.

  Arithmetic average roughness Ra obtained desired arithmetic average roughness Ra by using a cylindrical grinder (manufactured by Sanpo Seiki Kogyo Co., Ltd., stocker S30-12) and changing the count of the grindstone as appropriate.

  The conductor resistance value was measured by a measuring method as shown in FIG. As a measuring device, an ohmmeter (manufactured by Hioki Electric Co., Ltd., milliohm high tester 3540) 200 was used. In the prober chuck 1B, the power supply pattern layer 3a is provided on both sides of the center of the insulating substrate 2, and the connection terminal 7 is connected to each power supply pattern layer 3a.

  Further, in order to measure the conductor resistance at a plurality of locations of the first conductive layer, one measurement terminal (clip type) of the ohmmeter 200 is connected to one connection terminal 7 and the other measurement terminal is connected to a contact spring probe. Connected to 201. Further, a slide device 202 is provided so that the spring probe 201 can be moved in one direction along the surface of the first conductive layer 3.

  The slide device 202 moves the spring probe 201 from one connection terminal to the other connection terminal along the diameter of the prober chuck 1B, thereby bringing the spring probe 201 into contact with a plurality of predetermined measurement positions. At this time, the resistance meter 200 measures the conductor resistance from one connection terminal 7 to the contact point of the spring probe 201.

  First, the conductor resistance value of the first conductive layer 3 when the arithmetic average roughness Ra of the end face of the insulating substrate 2 was changed was measured.

  Arithmetic mean roughness Ra of the end face of the insulating substrate 2 is 0.2 μm (Example 11), 0.5 μm (Example 12), 0.8 μm (Example 13), 1.0 μm (Example 14). A prober chuck 1B having a thickness of 6 μm (Example 15) was produced, and the conduction resistance value between the two connection terminals 7 was measured.

The arithmetic mean roughness Ra of one main surface and the other main surface of the insulating substrate 2 was 0.5 μm, and the void ratio was 0.9%. In the first conductive layer 3 and the power feeding pattern layer 3a, a gold layer having a layer thickness of 1.5 μm was formed on a chromium layer having a layer thickness of 0.1 to 0.2 μm.
Table 3 shows the measurement results.

  As shown in Table 1, it can be seen that when the arithmetic average roughness Ra of the end face of the insulating substrate 2 is reduced, the conductor resistance value is reduced. When the arithmetic average roughness Ra is 0.2 μm to 1.0 μm, the conductor resistance value gradually increases as the arithmetic average roughness Ra increases, but when the arithmetic average roughness Ra becomes 1.6 μm, the conductor The resistance value increased rapidly. The arithmetic average roughness Ra of the end face of the insulating substrate 2 is preferably less than 1.6 μm, and more preferably the arithmetic average roughness Ra is 1.0 μm or less.

Next, the conductor resistance value of the first conductive layer 3 when the layer thickness of the chromium layer was changed was measured.
A prober chuck 1B having a chromium layer thickness of 0.1 μm (Example 16), 0.4 μm (Example 17), 0.5 μm (Example 18), and 2.0 μm (Example 19) was produced. The conduction resistance values of the plurality of measured values of the first conductive layer 3 were measured. The thickness of the gold layer formed on the chromium layer was 1.5 μm in all Examples 16 to 19.

  The arithmetic average roughness Ra of the end face of the insulating substrate 2 is 0.4 μm, the arithmetic average roughness Ra of one main surface and the other main surface is 0.4 μm, and the void ratio is 0.9%. .

  The conduction resistance value was measured under normal temperature conditions and heating conditions. As the heating condition, the prober chuck 1B was allowed to stand in an atmosphere of 300 ° C. for 24 hours.

  FIG. 14 is a graph showing changes in the conductor resistance value when the thickness of the chromium layer is changed. The horizontal axis indicates the measurement position [−], and the vertical axis indicates the conductor resistance value [Ω]. The measurement positions where the spring probe 201 is brought into contact are numbered 1 to 10 in order from the one connection terminal 7 connected to the prober chuck 1B, and the measurement position farthest from the one connection terminal 7 is designated. It was set to 10. Furthermore, the conductor resistance value when the spring probe 201 was brought into contact with the connection terminal 7 on the other side was also measured.

  The measurement result when the layer thickness of the chromium layer is 0.1 μm (Example 16) is indicated by a plot “◯”, and the measurement result when the layer thickness of the chromium layer is 0.4 μm (Example 17) is indicated by a plot “Δ”. The measurement result when the layer thickness of the chromium layer is 0.5 μm (Example 18) is indicated by a plot of “x”, and the measurement result when the layer thickness of the chromium layer is 2.0 μm (Example 19) is indicated by “□”. Shown in the plot.

The measurement result under normal temperature conditions is represented by a broken line, and the measurement result under heating conditions is represented by a solid line.
The measured values are shown in Table 4.

  From the graph, it was confirmed that the conductor resistance value increases as the number of the measurement position increases, that is, as the distance from one connection terminal increases. It can be seen that when the thickness of the chromium layer is reduced under such conditions, the conductor resistance value is reduced. Moreover, when the layer thickness of the chromium layer was 0.5 μm or more, the increase in the conductor resistance value under the heating condition became remarkable as compared with the normal temperature condition. Therefore, the layer thickness of the chromium layer is preferably 0.4 μm or less.

  Since the chromium layer is easily oxidized in air, for example, the diffusion of chromium into the gold layer and modification to chromium oxide increases the conductor resistance. Therefore, it is considered that the conductor resistance value of the second conductive layer 3 is increased as the thickness of the chromium layer is increased because the effect of the increase in the conductor resistance due to oxidation is more strongly affected when the thickness of the chromium layer is increased. Moreover, since the oxidation of chromium is further promoted under heating conditions, the increase in conductor resistance becomes more remarkable.

1, 1A, 1B Probe chuck 2 Insulating substrate 3 First conductive layer 3a Power supply pattern layer 4 Second conductive layer 7 Terminal for connection 10 Inspection device 11 XYZθ stage 12 Prober 12a Probe 13 Control unit 14 Voltage application unit 15 Semiconductor substrate

Claims (10)

An insulating substrate having a plate-like insulating substrate mainly composed of alumina and having an arithmetic average roughness Ra of the end surface of 0.7 μm or less;
A prober for a prober, comprising: a first conductive layer formed on one main surface of the insulating substrate.   2. The prober chuck according to claim 1, wherein a void ratio of the insulating substrate is 0.9% or less. A plate-shaped insulating substrate mainly composed of ceramics, wherein the arithmetic average roughness Ra of the end surface is smaller than the arithmetic average roughness Ra of the one main surface and the other main surface;
A prober for a prober, comprising: a first conductive layer formed on one main surface of the insulating substrate.   The prober chuck according to claim 1, further comprising a second conductive layer formed on the other main surface of the insulating substrate.   5. The power feeding pattern layer partially formed on the end surface of the insulating substrate and electrically connected to the first conductive layer is further provided. Prober chuck. In a manufacturing method for manufacturing a prober for a prober comprising: a plate-like insulating substrate mainly composed of ceramics; and a first conductive layer formed on one main surface of the insulating substrate.
A manufacturing step of manufacturing the insulating substrate;
In order to adjust the insulation resistance value of the insulating substrate, a polishing step of polishing an end surface of the insulating substrate;
And a forming step of forming a first conductive layer on one principal surface of the insulating substrate.   7. The prober chuck according to claim 6, wherein in the polishing step, the arithmetic average roughness Ra of the end surface is polished so as to be smaller than the arithmetic average roughness Ra of the one main surface and the other main surface. Method. The prober chuck according to any one of claims 1 to 3, wherein a prober chuck on which a semiconductor substrate having a semiconductor element is placed;
A mounting table on which the prober chuck is mounted, the mounting table having a third conductive layer provided so as to be in contact with the other main surface of the prober chuck;
Voltage applying means for applying a voltage between the first conductive layer of the prober chuck and the third conductive layer of the mounting table;
And a prober for supplying an electric signal to the semiconductor element. The prober chuck according to claim 4, wherein a prober chuck on which a semiconductor substrate having a semiconductor element is mounted;
Voltage applying means for applying a voltage between the first conductive layer and the second conductive layer of the prober chuck;
And a prober for supplying an electric signal to the semiconductor element. The prober chuck according to claim 5, wherein a prober chuck on which a semiconductor substrate having a semiconductor element is mounted;
A mounting table on which the prober chuck is mounted, the mounting table having a third conductive layer provided so as to be in contact with the other main surface of the prober chuck;
Voltage applying means for applying a voltage between the first conductive layer of the prober chuck and the third conductive layer of the mounting table via the power feeding pattern layer;
And a prober for supplying an electric signal to the semiconductor element.