JP2012043946A - Opto-electronic semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an opto-electronic integrated circuit (OEIC) in which an optical device and an electronic device having high performance are formed, and to provide a method of manufacturing the same.SOLUTION: The method of manufacturing the opto-electronic integrated circuit (OEIC) comprises the steps of: forming an optical element formation layer on one of a transparent substrate and an SOI substrate to form an optical element layer structure; joining the other substrate, which is different from the one substrate out of the transparent substrate and the SOI substrate, to the optical element layer structure with an Si substrate of the SOI substrate outside, to form an assembly; and polishing the Si substrate of the assembly to form an electronic element formation layer.

Description

  The present invention relates to an optoelectronic semiconductor device and a method for manufacturing the same, and more particularly to a method for manufacturing an optoelectronic integrated circuit (OEIC) substrate and a method for manufacturing an OEIC.

  Conventionally, a III-V group compound semiconductor layer such as GaAs and InP is formed on a Si (silicon) single crystal substrate (for example, Patent Document 1). This is because by using a large and inexpensive Si single crystal substrate, an optical device such as a light emitting element or a light receiving element, a high speed element, an MMIC (Monolithic Microwave Integrated Circuit), etc. that cannot be formed by Si are formed at low cost. Is. Further, in recent years, the Si integrated circuit has been increased in scale, and it has become difficult to perform signal transmission within a chip or between chips by a conventional electric wiring. In order to solve this problem, an opto-electronic integrated circuit (OEIC) in which signal transmission using light is incorporated in a Si integrated circuit is expected.

  In order to realize an optoelectronic integrated circuit (OEIC), it is necessary to form a semiconductor layer having a light emitting function on the integrated circuit (electronic circuit). A compound semiconductor such as InP or GaAs having an excellent light emitting function is made of Si and a lattice. Since the constants are greatly different, crystal defects such as dislocations are generated, and the concept has not been realized. In recent years, optical integrated circuits using Si have been studied. However, since there is a lack of a practical light source and light having a wavelength that transmits Si, it is necessary to introduce new materials into the photodetector. There are many challenges.

Japanese Patent No. 3784328

  The present invention has been made in view of the above-described points, and an object of the present invention is to provide a method for manufacturing an OEIC substrate capable of manufacturing an optoelectronic integrated circuit (OEIC) on which a high-performance optical device and an electronic device are formed, and a high performance. The object is to provide a high-performance OEIC and a manufacturing method thereof.

The method of the present invention is a method of manufacturing a substrate for an optoelectronic integrated circuit (OEIC) having an optical element formation layer and an electronic element formation layer for forming an optical element and an electronic element, respectively.
Providing a transparent substrate and an SOI substrate;
An optical element layer forming step of forming an optical element layer structure on one of the transparent substrate and the SOI substrate to form an optical element layer structure;
A bonding step in which another substrate different from the first substrate among the transparent substrate and the SOI substrate and the optical element layer structure are bonded to each other with the Si substrate of the SOI substrate facing outside to form a bonded body;
An electronic element layer forming step of polishing the Si substrate of the joined body to form an electronic element forming layer.

1 is a cross-sectional view illustrating a method for manufacturing an optoelectronic integrated circuit (OEIC) manufacturing substrate (OEIC substrate) including an Si layer and a compound semiconductor layer using an SOI substrate according to Example 1. FIG. FIGS. 2A to 2E are cross-sectional views schematically showing a method of manufacturing an optoelectronic integrated circuit (OEIC) using an OEIC substrate. FIGS. 2F to 2H are cross-sectional views schematically showing a method of manufacturing an optoelectronic integrated circuit (OEIC) using an OEIC substrate. It is sectional drawing which shows the description of operation | movement of OEIC, and the three-dimensional OEIC apparatus which laminated | stacked two OEIC. 6 is a cross-sectional view schematically showing a method for manufacturing an OEIC substrate according to Example 2. FIG. 6 is a cross-sectional view schematically showing a method for manufacturing an OEIC substrate according to Example 3. FIG. It is sectional drawing which shows typically OEIC which formed LED from which an emission wavelength mutually differs in the 1st and 2nd optical device layer.

  In the following, a semiconductor stacked structure composed of a Si (silicon) layer and a compound semiconductor layer was formed using an SOI (Silicon on Insulator) substrate, and an electronic device and an optical device were formed in the Si layer and the compound semiconductor layer, respectively. An optoelectronic integrated circuit (OEIC) and a manufacturing method thereof will be described in detail with reference to the drawings. A case where a light emitting device, particularly a light emitting diode (LED) is formed as the optical device will be described as an example. An example in which a signal processing circuit is formed as an electronic device will be described. However, the electronic device and the optical device are not limited to these, and can be appropriately selected from various devices (elements) or modified and applied. In the following description, the device layer refers to a layer composed of a semiconductor to be included in order for a semiconductor element to perform its function. For example, a simple transistor includes a structure layer (pnp structure, npn structure, etc.) constituted by an n-type semiconductor and a pn junction of a p-type semiconductor, a MOS (Metal Oxide Semiconductor) structure layer, and the like. In particular, a layer for forming an electronic element, an electronic circuit, or the like is referred to as an electronic device layer (or an electronic element layer). A semiconductor structure layer that performs a light receiving operation or a light emitting operation is referred to as an optical device layer (or an optical element layer). Furthermore, a semiconductor structure layer that includes a p-type semiconductor layer and an n-type semiconductor layer and performs a light receiving operation for converting incident light into a photocurrent is particularly referred to as a light receiving device layer. In addition, a semiconductor structure layer that includes a p-type semiconductor layer, a light-emitting layer, and an n-type semiconductor layer and emits light by recombination of injected carriers is particularly referred to as a light-emitting device layer. In particular, in the case of an LED, it is also referred to as an LED device layer. Further, “transparent” in a transparent substrate or the like means that it is transparent or translucent to the wavelength of light used in an optical device such as a light emitting element or a light receiving element.

  Moreover, the polarity (p-type, n-type), carrier concentration, composition, layer thickness, etc. of the semiconductor layer are examples, and can be applied with appropriate modifications.

  In the drawings described below, substantially the same or equivalent parts will be described with the same reference numerals.

FIG. 1 is a cross-sectional view illustrating a method for manufacturing a substrate (hereinafter also referred to as an OEIC substrate) for manufacturing an optoelectronic integrated circuit (OEIC) including an Si layer and a compound semiconductor layer using an SOI substrate. First, as shown in FIG. 1A, an SOI substrate 11 including a p-Si substrate 11A, a SiO ₂ layer 11B, and a p ⁺ -Si layer (also referred to as an SOI layer) 11C is prepared. More specifically, the carrier concentration of the p-Si substrate 11A is 5 × 10 ¹⁵ cm ⁻³ , and the carrier concentration of the p ⁺ -Si layer 11C is 1 × 10 ¹⁹ cm ⁻³ .

  Next, as shown in FIG. 1B, a light-emitting element which is a layer for forming a light-emitting element (light-emitting device), which is composed of a compound semiconductor layer on the Si layer (SOI layer) 11C of the SOI substrate 11. A formation layer (hereinafter also referred to as an optical device layer) 12 is formed (grown). The optical device layer 12 includes, for example, a plurality of compound semiconductor layers lattice-matched to the Si layer (SOI layer) 11C via the compound semiconductor buffer layer 12A. For example, the buffer layer 12A is a buffer layer made of a III-V group compound semiconductor, and the optical device layer 12 includes a buffer layer 12A, a p-type cladding (p-cladding) layer 12B, a light-emitting layer 12C, an n-type cladding (n− Clad) layer 12D and n-contact layer 12E. The buffer layer 12A, the p-cladding layer 12B, the light emitting layer 12C, the n-cladding layer 12D, and the n-contact layer 12E are III-V group compound semiconductor layers. Then, the Si layer 13 is formed on the optical device layer 12. By the above process, the device layer structure 14 in which the optical device layer 12 is formed on the SOI substrate 11 is configured.

An example will be described in which each layer of the optical device layer 12 and the Si layer 13 are continuously formed by MBE (Molecular Beam Epitaxy). For example, the buffer layer 12A is a p-GaP buffer layer doped with Mg (magnesium) as a p-type dopant (carrier concentration is 1 × 10 ¹⁹ cm ⁻³ ) and has a layer thickness of 10 nm (nanometers). In addition, the p-cladding layer 12B uses Mg as a p-type dopant (carrier concentration: 5 × 10 ¹⁷ cm ⁻³ ) and contains nitrogen (N) in an amount lattice-matched to the Si layer 11C (for example, 2%). It is a p-GaPN layer (layer thickness: 1 μm (micrometer)) which is an original compound (mixed crystal). The light emitting layer 12C is a GaAsN layer (undoped) composed of a single quantum well (SQW) having a layer thickness of 3 nm, similarly containing 2% nitrogen (N). The n-cladding layer 12D uses S (sulfur) as an n-type dopant (carrier concentration: 5 × 10 ¹⁷ cm ⁻³ ), and similarly includes an n-GaPN layer containing 2% nitrogen (N) (layer thickness: 1 μm). Further, ^{n +} - contact layer 12E was the S and n-type dopant (carrier ^{concentration: 5 × 10 19 cm -3)} , the layer thickness is ⁿ +-GAP layer of 0.1 [mu] m. Note that the n ⁺ -Si layer 13 has an action of offsetting or mitigating stress caused by a difference in thermal expansion coefficient between Si and the III-VN semiconductor layer in the cooling process after crystal growth. The Si layer 13 may be a thin film and has a layer thickness of, for example, 10 nm. More specifically, as will be described later, the Si layer 13 can have a thickness that does not attenuate the light of the light emitting element formed in the optical device layer 12 by absorption.

As shown in FIG. 1C, an SiO ₂ layer 22 is formed on a transparent substrate 21 such as SiO ₂ or spinel by sputtering, for example, and a transparent substrate structure 23 is formed. Next, as shown in FIG. 1D, the SiO ₂ layer 22 of the transparent substrate structure 23 and the uppermost Si layer 13 of the device layer structure 14 are activated by Ar (argon) plasma or the like, and Bonding is performed by pressurization to form a bonded body 24 of the device layer structure 14 and the transparent substrate structure 23. That is, bonding is performed with the Si substrate 11A of the SOI substrate 11 of the device layer structure 14 facing outside (that is, with the surface of the Si substrate 11A as a non-bonding surface). The SiO ₂ layer 22 of the transparent substrate structure 23 and the Si layer 13 of the device layer structure 14 have a function as a bonding layer. Note that in FIG. 1D, the joint surface is indicated by “F” and a broken line. Thereafter, as shown in FIG. 1E, the Si substrate 11A of the SOI substrate 11 is polished. The polished Si substrate has a layer thickness of 0.5 to 2 μm. In the following, for clarity of explanation and understanding, the layer remaining after the polishing (a part of the Si substrate) will be described as the Si layer 11D. Note that after the polishing, the Si layer 11D may be subjected to a surface treatment such as cleaning and etching. By such a process, the OEIC substrate 25 including the Si layer 11D and the optical device layer 12 which are electronic device forming layers is formed.

The electronic device forming layer (Si layer) 11D is electrically separated (insulated) from the optical device forming layer 12 by the insulating layer (SiO ₂ layer) 11B of the SOI substrate 11.

  In addition to the light emitting device such as LED or LD (laser diode), a light receiving device or an electronic device may be formed on the optical device forming layer 12. Further, in the electronic device forming layer, an optical device such as a light receiving device may be formed in addition to an electronic element or an electronic circuit.

  Although the case where a GaPN crystal layer is grown on the SOI substrate 11 as the optical device layer 12 has been described as an example, the present invention is not limited to this. That is, the present invention can also be applied to the case where a device layer including another crystal system, for example, a GaN compound semiconductor layer, is formed as the optical device layer 12.

[OEIC formation process]
Hereinafter, a method for manufacturing an optoelectronic integrated circuit (OEIC) using the OEIC substrate 25 will be described in detail with reference to the drawings. First, resist patterning is performed by photolithography using the Si layer 11D of the OEIC substrate 25, that is, the Si layer remaining after polishing in the Si substrate 11A of the SOI substrate 11, as a surface. As shown in FIGS. 2A and 2B, the photoresist is patterned so that the LED formation region 31R becomes an opening. Next, as shown in FIG. 2B, the Si layer 11D is removed by dry etching using, for example, SF ₆ , and the SiO ₂ layer 11B (insulating layer of the SOI substrate 11) is further removed, for example, by buffered foot. It is removed by wet etching using acid. Thereafter, the resist is removed with a remover solution or the like.

Next, an isolation process of the LED element unit 31 is performed. Specifically, as shown in FIG. 2C, resist patterning is performed by photolithography so that a region other than the LED element portion 31 in the LED forming region 31R becomes an opening. More specifically, the Si layer (SOI layer of the SOI substrate 11) 11C is removed by dry etching using, for example, SF _6, and the optical device layer 12 is further removed by dry etching using, for example, BCl ₃ , and Si The LED element portion 31 is formed by forming a groove or a recess reaching the layer 13 (that is, an opening through which the Si layer 13 is exposed). Thereafter, the resist is removed.

Next, after performing surface passivation, the passivation film in the element formation region is removed. Specifically, first, the surface of the OEIC substrate 25 after the isolation process is covered with the SiO ₂ film 32A. For example, the SiO ₂ film 32A having a thickness of about 2 μm is formed by thermal CVD using SiH ₄ gas at a temperature of 550 ° C. Next, as shown in FIG. 2 (D), the SiO ₂ film 32A of an electronic circuit forming region 33R, and the SiO ₂ film 32A in the region serving as the light receiving portion of the light receiving element formation region 34R (light receiving region) 34R1 removed Thus, an element region opening is formed. Specifically, resist patterning is performed so that these element formation regions become openings, and the SiO ₂ film 32A is removed with buffered hydrofluoric acid. Thereafter, the resist is removed.

  Next, resist patterning is performed, and phosphorus (P) is implanted by ion implantation, for example. More specifically, as shown in FIG. 2E, phosphorus is implanted into the Si layer 11D of the light receiving portion region 34R1 of the light receiving element formation region 34R and the drain region 33D and the source region 33S of the electronic circuit formation region 33R. . Here, a case where a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is formed in the electronic circuit formation region 33R will be described as an example. However, in general, an electronic circuit including a transistor, a passive element, etc. It can also be applied to the case of forming an electronic circuit used for signal processing, driving or the like of a light receiving element (sensor element).

Next, as shown in FIG. 2F, an oxide film (SiO ₂ film) 32B is formed on the Si layer surface of the electronic circuit formation region 33R and the light receiving portion region 34R1 of the OEIC substrate 25 by wet oxidation. For example, a 70 nm oxide film is formed by wet oxidation at 900 ° C. for 10 minutes.

Thereafter, contact holes and electrodes are formed. More specifically, as shown in FIG. 2G, resist patterning is performed by photolithography to remove the SiO ₂ film 32A on the LED element portion 31, and the n-contact layer 12E of the LED element portion 31 A part of the Si layer 13 that is in contact is exposed, the SiO ₂ film 32A is removed by wet etching, and an n-electrode forming portion 13A is formed. At the same time, the SiO ₂ film 32A of the electrode forming portion 34R2, which is a part of the light receiving element forming region 34R, is removed. Further, resist patterning is performed by photolithography to form contact holes in the light receiving part region 34R1 in the light receiving element forming region 34R, the drain region 33D in the electronic circuit forming region 33R, and the oxide film 32B in the source region 33S. Then, a metal electrode such as Al (aluminum) is formed on the semiconductor layer exposed from the contact holes in these regions. By such a process, as shown in FIG. 2H, an OEIC 35 including an LED element 31J, an electronic circuit (MOSFET) 33J, and a light receiving element 34J is formed. More specifically, the LED element 31J has a p-electrode and n-electrodes 31E, 31F, the electronic circuit 33J has a source electrode, a gate electrode and drain electrodes 33E, 33F, 33G, and the light-receiving element 34J has a p-electrode and n Electrodes 34E and 34F are provided. The light receiving element 34J receives the input light Pi and generates a light reception signal (reception data). The signal received by the light receiving element 34J is subjected to signal processing by the signal processing circuit 33J, the LED element 31 is driven to emit light based on the output after the signal processing, and the optical signal Po is output to the outside.

  As described above, for ease of explanation and understanding, the case where a MOSFET is formed in the electronic circuit formation region 33R has been described as an example. However, a signal processing circuit, a drive circuit, an amplifier circuit, or the like, or a combination thereof is used. Of course, the present invention can also be applied to the formation of various electronic circuits and integrated circuits.

As shown in FIG. 3, the OEIC 35-1 or 35-2 having the same configuration as the OEIC 35 described above receives the input light Pi from the outside and generates reception data, and signal processing which is an electronic circuit. The circuit 33J and the LED element 31J are included. The signal processing circuit 33J performs signal processing on the received data by the light receiving element 34J, and drives the LED element 31J to emit light based on the output after the signal processing. The output signal light Po from the LED element 31J is emitted to the outside through the thin Si layer 13 that hardly absorbs light and the SiO ₂ layer 22 that is transparent to the light from the LED element 31J. That is, the light extraction efficiency from the LED element 31J to the outside is extremely high.

  Further, FIG. 3 shows a three-dimensional OEIC device in which two OEIC 35-1 and OEIC 35-2 are stacked. More specifically, the output signal light Po1 from the first OEIC 35-1 is input to the second OEIC 35-2 as the input light Pi2. The optical element 34J2 of the second OEIC 35-2 receives the input light Pi2 and generates reception data. Then, the signal received by the light receiving element 34J2 is subjected to signal processing by the signal processing circuit 33J2 of the second OEIC 35-2, and the LED element 31J2 is driven to emit light based on the signal processing result, and light is emitted from the second OEIC 35-2. The signal Po2 is output to the outside.

  As described above, according to the present invention, a compound semiconductor device layer (optical device layer) is formed on an SOI substrate, and a thin film Si layer that also functions as a bonding layer (first bonding layer) on the optical device layer. To form a device layer structure. Further, an Si oxide film or the like that functions as a bonding layer (second bonding layer) that can be bonded to the first bonding layer is formed on the transparent substrate. And the said 1st and 2nd joining layer is joined by activation process and pressurization, and the joined body of a device layer structure and a transparent substrate is formed. Further, by polishing the Si substrate (the back surface of the SOI substrate) of the SOI substrate of the joined body to form an electronic device forming layer, an electronic device forming layer (Si layer after polishing) and an optical device are formed. An OEIC substrate including a layer (compound semiconductor device layer) is formed.

According to such a configuration, since light from the optical device is emitted to the outside through the transparent substrate, it is possible to provide an OEIC with extremely low light absorption and extremely high light extraction efficiency. The thin film after polishing the Si substrate of the SOI substrate is used as an electronic device (Si device) formation layer. Therefore, since an electronic device is formed on a high-quality Si layer, high-quality and high-performance electronic circuits and integrated circuits can be formed. In addition, since the SiO ₂ layer of the SOI substrate can be used for insulation (electrical isolation) between the electronic device formation layer and the optical device formation layer, the degree of freedom in circuit design is high.

  Furthermore, since high output light can be easily extracted to the back side of the substrate, a three-dimensional apparatus can be constructed by stacking such OEICs. Further, in such an OEIC three-dimensional apparatus, since signals are transmitted by light, a gap can be provided between the OEICs, and the three-dimensional OEIC apparatus can be easily cooled.

  FIG. 4 is a cross-sectional view showing a method of forming an OEIC manufacturing substrate (OEIC substrate) including an Si layer as an electronic device forming layer and a compound semiconductor layer (optical device forming layer) using an SOI substrate. First, as shown in FIG. 4A, an optical device layer 52 that is a compound semiconductor is grown on a light-transmitting substrate 51 such as a sapphire substrate. In the following, a case where a GaN-based crystal is grown as the optical device layer 52 will be described as an example. However, the present invention is not limited to this, and another crystal-based compound semiconductor layer may be used. Moreover, not only a III-V group compound semiconductor but an II-VI group compound semiconductor may be sufficient. For example, a crystal system such as a zinc oxide crystal (ZnO crystal, MgZnO crystal) may be used.

First, an n-GaN buffer layer 52A is grown on the sapphire substrate 51, and an n-cladding layer 52B, a light emitting layer 52C, and a p-cladding layer 52D are sequentially grown on the buffer layer 52A. Next, a p-electrode 53 is formed on the p-cladding layer 52D. For example, the p-electrode 53 is formed by a transparent electrode such as an ITO film (indium tin oxide film) or a reflective electrode such as an Ag (silver) film by vapor deposition or sputtering. Next, an insulating layer 54 such as SiO ₂ is formed on the p-electrode 53. By this process, an optical device layer structure 55 in which the optical device layer 52 is formed on the sapphire substrate 51 is formed.

For example, the buffer layer 52A is a low-temperature grown GaN buffer layer having a layer thickness of 25 nm (nanometers). The n-cladding layer 52B uses Si (silicon) as an n-type dopant (carrier concentration: 1.8 × 10 ¹⁸ cm ⁻³ ), n-GaN layer (layer thickness: 3.5 μm (micrometer)). It is. The light emitting layer 52C is a quantum well light emitting layer made of, for example, a quantum well (QW). For example, the composition of the well layer is In _0.25 Ga _0.75 N (layer thickness: 2.2 nm), the composition of the barrier layer is GaN (layer thickness: 15 nm), and the multi-quantum well (MQW) has a five-period structure. It is. The p-cladding layer 52D is a p-GaN layer (layer thickness: 150 nm) using Mg as a p-type dopant (carrier concentration: 3 × 10 ¹⁷ cm ⁻³ ). In addition to these layers, a contact layer, an electron or hole barrier layer (stopper layer), or the like may be provided as appropriate.

As shown in FIG. 4B, an SOI substrate 11 is prepared. The SOI substrate 11 includes, for example, a p-Si substrate 11A, a SiO ₂ layer 11B, and a p ⁺ -Si layer (also referred to as an SOI layer) 11C. More specifically, for example, the carrier concentration of the p-Si substrate 11A is 1 × 10 ¹⁹ cm ⁻³ , and the carrier concentration of the p ⁺ -Si layer 11C is 1 × 10 ¹⁹ cm ⁻³ .

  Next, as shown in FIG. 4C, the insulating layer 54 of the optical device layer structure 55 and the uppermost Si layer (SOI layer) 11C of the SOI substrate 11 are activated by Ar (argon) plasma or the like. And it joins by pressurization and the joined body 57 of the optical device layer structure 55 and the SOI substrate 11 is formed. That is, the insulating layer 54 and the Si layer 11C of the optical device layer structure 55 have a function as a bonding layer. In FIG. 4C, the joint surface is indicated by “F” and a broken line. Thereafter, as shown in FIG. 4D, the Si substrate 11A of the SOI substrate 11 is polished. The Si substrate after the polishing may have a layer thickness of 0.5 to 2 μm. As described above, the layer remaining after the polishing (a part of the Si substrate of the SOI substrate 11) will be described as the Si layer 11D for clarity of explanation and understanding. By such a process, the OEIC substrate 58 including the Si layer 11D as the electronic device forming layer and the optical device layer 52 is formed. In addition to the light emitting device such as LED or LD (laser diode), a light receiving device or an electronic device may be formed on the optical device forming layer 52. Further, in the electronic device forming layer, an optical device such as a light receiving device may be formed in addition to an electronic element or an electronic circuit.

  Although the case where a GaN-based crystal layer is grown on the SOI substrate 11 as the optical device layer 52 has been described as an example, the present invention is not limited to this. That is, another crystalline semiconductor layer may be formed as the optical device layer 52.

  Using the OEIC substrate 58 according to the present embodiment, an optoelectronic integrated circuit (OEIC) can be manufactured in the same manner as described in detail in the first embodiment. That is, the OEIC can be manufactured by applying the manufacturing method according to the first embodiment using the optical device layer 12 as the optical device layer 52.

  As described above, according to the present invention, the optical device layer 52 is grown on a light-transmitting substrate such as a sapphire substrate, and the insulating layer functions as a bonding layer (first bonding layer) on the optical device layer. (Si oxide film) is formed to form an optical device layer structure. That is, a Si oxide film or the like that functions as a bonding layer that can be bonded to the Si (SOI) layer (second bonding layer) of the SOI substrate is formed. Then, the Si oxide film (first bonding layer) of the optical device layer structure and the Si layer (second bonding layer) of the SOI substrate are bonded by activation treatment and pressurization, and on the light-transmitting substrate. A joined body of the optical device layer structure on which the optical device layer is formed and the SOI substrate is formed. Further, by polishing the Si substrate of the SOI substrate of the joined body to be an electronic device forming layer, an electronic device forming layer (Si layer after polishing) and an optical device forming layer (compound semiconductor device layer) OEIC substrate including

According to such a configuration, since light from the optical device is emitted to the outside through the light-transmitting substrate, it is possible to provide an OEIC with extremely low light absorption and extremely high light extraction efficiency. In addition, since the thin film after polishing the Si substrate of the SOI substrate is used as the electronic device forming layer and the electronic device is formed on the high-quality Si layer, high-quality and high-performance electronic circuits and integrated circuits can be formed. . Further, the SiO ₂ layer of the SOI substrate can be used for insulation between the electronic device forming layer and the optical device forming layer.

  In addition, since high-output light can be easily extracted to the back side of the substrate, it is possible to construct a three-dimensional apparatus by stacking such OEICs. Further, in such an OEIC three-dimensional apparatus, since signals are transmitted by light, a gap can be provided between the OEICs, and the three-dimensional OEIC apparatus can be easily cooled.

  In Example 2 described above, the optical device layer structure in which the optical device forming layer is grown on the light-transmitting substrate and the SOI substrate are bonded together, and the Si substrate remaining after polishing the Si substrate of the SOI substrate is used as the electronic device. An OEIC substrate having an optical device formation layer and an electronic device formation layer is formed as the formation layer.

  In this embodiment, a first optical device layer structure in which a first optical device formation layer is grown on a translucent substrate such as a sapphire substrate, and a second optical device formation on an SOI substrate (SOI layer). Form a layer. Then, the first and second optical device layer structures are joined, and the Si layer remaining after polishing the Si substrate of the SOI substrate is used as an electronic device forming layer. According to this embodiment, an OEIC substrate having an electronic device forming layer and two optical device forming layers can be formed.

  FIG. 5 is a cross-sectional view showing a method for forming an OEIC manufacturing substrate (OEIC substrate) including an Si layer as an electronic device forming layer and a compound semiconductor layer (optical device forming layer) using an SOI substrate.

  First, as shown in FIG. 5A, an optical device layer 62 that is a compound semiconductor is grown on a translucent substrate 61 such as a sapphire substrate. In the following, a case where a sapphire substrate is grown as the light-transmitting substrate and a GaN-based crystal is grown as the optical device layer 62 will be described as an example. For example, other crystalline compound semiconductor layers may be used. Moreover, not only a III-V group compound semiconductor but an II-VI group compound semiconductor may be sufficient.

  For example, the optical device layer 62 is made of a GaN-based compound semiconductor layer and has an n-cladding layer, a light emitting layer, and a p-cladding layer. Further, a buffer layer may be formed on the sapphire substrate 61, or the optical device layer 62 may have a contact layer, a current diffusion layer, an electron / hole barrier layer, and the like. The light emitting layer may be formed of a so-called bulk DH structure or a single / multiple quantum well (SQW / MQW) structure. Next, the p-electrode 63 is formed on the optical device layer 62. For example, a transparent electrode such as an ITO film (indium tin oxide film) is formed by vapor deposition or sputtering. Next, an insulating layer 64 is formed on the p-electrode (transparent electrode) 63. Note that the insulating layer 64 also has a function as a bonding layer. By this process, an optical device layer structure 67 in which the (first) optical device layer 62 is formed on the sapphire substrate 61 is formed.

Next, as shown in FIG. 5B, an optical device forming layer 72 composed of a compound semiconductor layer is formed (grown) on the Si layer (SOI layer) 11C of the SOI substrate 11. The SOI substrate 11 includes, for example, a p-Si substrate 11A, a SiO ₂ layer 11B, and a p ⁺ -Si layer (also referred to as an SOI layer) 11C.

  The optical device layer 72 is composed of a plurality of compound semiconductor layers lattice-matched to the Si layer (SOI layer) 11C through the compound semiconductor buffer layer. For example, the p-GaPN layer which is the ternary compound (mixed crystal) containing nitrogen (N) in an amount lattice-matched to the Si layer 11C described in the first embodiment. Similar to the optical device layer structure 67, the optical device layer 72 may include a contact layer, a current diffusion layer, an electron / hole barrier layer, and the like. The light emitting layer may be formed of a bulk DH structure or a single / multiple quantum well (SQW / MQW) structure.

  Next, an Si layer 73 is formed on the optical device layer 72. By the above process, the (electronic / optical) device layer structure 75 in which the (second) optical device layer 72 is formed on the SOI substrate 11 is configured.

  Next, as shown in FIG. 5C, the insulating layer 64 of the optical device layer structure 67 and the Si layer 73 of the device layer structure 75 are activated by Ar (argon) plasma or the like and pressurized. The bonded body 76 is formed by bonding. That is, the insulating layer 64 of the optical device layer structure 67 and the Si layer 73 of the device layer structure 75 have a function as a bonding layer. In FIG. 5C, the joint surface is indicated by “F” and a broken line. Thereafter, as shown in FIG. 5D, the Si substrate 11A of the SOI substrate 11 is polished. The layer thickness of the Si substrate after polishing, that is, the layer thickness of the Si layer 11D that is a layer remaining after polishing (a part of the Si substrate) is 0.5 to 2 μm. By such a process, the OEIC substrate 78 having the first optical device layer 62 and the second optical device layer 72 and the electronic device forming layer 11D is formed. Here, by changing the wavelengths of the light emitting elements formed in the first optical device layer 62 and the second optical device layer 72, an OEIC having a light emitting element of two wavelengths can be formed. As described above, for example, the optical device layer 62 is made of, for example, a GaN-based compound semiconductor layer to form a blue light emitting LED, and the device layer 72 is made of, for example, a III-VN semiconductor layer (GaPN semiconductor layer) to emit red light. An LED can be formed.

  FIG. 6 shows an OEIC in which LEDs 31K1 and 31K2 having different emission wavelengths are formed on the first optical device layer 62 and the second optical device layer 72, respectively. For example, the LED 31K1 is a red light emitting LED (λ1) having an active layer 72A and a blue light emitting LED (λ2) having an LED 31K2 active layer 62A. The formation process of the two LEDs 31K1 and 31K2 can be performed in the same manner as in the case of the first embodiment (FIGS. 2A to 2H). For example, the first optical device layer 62 and the second optical device layer 72 may be separated to form electrodes. More specifically, for example, grooves reaching the n-contact layer and the p-cladding layer (or p-contact layer) of the first optical device layer 62 are formed, and the electrodes 31P and 31Q connected to these layers are formed. The LED 31K1 is formed to form a groove reaching the p-contact layer and the n-cladding layer (or n-contact layer) of the second optical device layer 72, and electrodes 31R and 31S connected to these layers. The LED 31K2 can be formed. The method for forming the two LEDs having different emission wavelengths is not limited to this, and various forming methods can be applied.

  According to the present embodiment, in addition to the effects of the first and second embodiments, a device layer structure having an electronic device forming layer and a plurality of optical device forming layers that are electrically separated from each other can be formed. Therefore, as described above, for example, an OEIC including light emitting elements of two colors (red and blue) can be formed.

  The above-described embodiments can be applied by appropriately combining or modifying them. Moreover, the above numerical values are merely examples.

11 SOI substrate 11A Si substrate 11C SOI layer 11D Electronic device formation layer 12, 52, 62, 72 Optical device formation layer 21 Transparent substrate 25, 58, 78 OEIC substrate 35, 35-1, 35-2, 79 Optoelectronic integrated circuit ( OEIC)

Claims (7)

A method for manufacturing a substrate for an optoelectronic integrated circuit (OEIC) having an optical element formation layer and an electronic element formation layer for forming an optical element and an electronic element, respectively.
Providing a transparent substrate and an SOI substrate;
An optical element layer forming step of forming the optical element formation layer on one of the transparent substrate and the SOI substrate to form an optical element layer structure;
A bonding step of bonding another substrate different from the first substrate among the transparent substrate and the SOI substrate and the optical element layer structure with a Si substrate of the SOI substrate facing outside to form a bonded body;
An electronic element layer forming step of polishing the Si substrate of the joined body to form the electronic element forming layer;
The manufacturing method characterized by having. The optical element formation layer is formed on the SOI substrate, and a first bonding layer is formed on the optical element formation layer,
A second bonding layer that can be bonded to the first bonding layer is formed on the transparent substrate, and the bonded body is formed by bonding the first bonding layer and the second bonding layer. The manufacturing method of Claim 1 characterized by the above-mentioned.   2. The optical element forming layer is formed on the transparent substrate, and a bonding layer that can be bonded to an SOI layer of the SOI substrate is formed on the optical element forming layer. Manufacturing method. The optical element layer forming step includes forming first and second optical element formation layers on the transparent substrate and the SOI substrate,
The first and second optical element formation layers have light emitting layers having first and second emission wavelengths different from each other,
The manufacturing method according to claim 1, wherein first and second bonding layers that can be bonded to each other are formed on the first and second element formation layers. An OEIC manufacturing method using an optoelectronic integrated circuit (OEIC) substrate manufactured by the method of claim 2, comprising:
An electrode forming step of forming a light emitting element by forming a groove reaching the first bonding layer from the electronic element forming layer, and forming an electrode of the light emitting element in the first bonding layer exposed from the groove;
An electronic element forming step of forming an electronic element in the electronic element forming layer;
The manufacturing method characterized by having. An OEIC using an optoelectronic integrated circuit (OEIC) substrate manufactured by the method according to claim 1,
A light receiving element that is formed in the electronic element forming layer and generates a light receiving signal according to an input optical signal;
An electronic circuit formed in the electronic element formation layer and generating a drive signal based on the received light signal;
An OEIC comprising: a light emitting element that is formed in the optical element formation layer and emits output signal light corresponding to the drive signal.   The OEIC according to claim 6, wherein the light receiving element receives an optical signal input to a front side of the OEIC, and the light emitting element emits an output signal light from a back side of the OEIC.

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