JP2012039291A - Electronic camera - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic camera that can reduce power consumption when using a plurality of image engines.SOLUTION: The electronic camera includes an imaging section, a plurality of data processing sections, a plurality of memories and a switching section. The imaging section images a subject to generate an image. The data processing sections apply data processing to the image and system information. The memories are connected to the plurality of data processing sections, respectively, and record classified data classified for data processing. The switching section switches the destination memory of each classified data according to attribute information set for the classified data.

Description

  The present invention relates to an electronic camera.

  2. Description of the Related Art Conventionally, an image processing apparatus equipped with a plurality of image engines for image processing of image data is known (see, for example, Patent Document 1). In the image processing apparatus described above, the processing speed is improved by performing parallel image processing using two image engines.

JP-A-5-227519

  Incidentally, memories are connected to the plurality of image engines for image processing. The plurality of image engines, for example, distribute image processing data for image processing of image data to each memory. Here, when image processing is performed, when a plurality of image engines transfer data for image processing between the image engines, there is a problem that so-called traffic increases and power consumption increases depending on the amount of data.

  In view of the above circumstances, an object of the present invention is to provide an electronic camera that can suppress power consumption when a plurality of image engines are used.

  An electronic camera according to a first invention includes an imaging unit, a plurality of data processing units, a plurality of memories, and a switching unit. The imaging unit captures an image of a subject and generates an image. The data processing unit performs data processing of images and system information. The memory is connected to each of the plurality of data processing units, and records the classification data classified for data processing. The switching unit switches the memory to which the classification data is recorded in accordance with the attribute information set for each classification data.

  In a second aspect based on the first aspect, the attribute information is at least one of the use frequency of the classification data, the priority of the classification data, and the data capacity of the classification data.

  In a third aspect based on the second aspect, the priority is a priority of classification data set based on a user's selection input. The switching unit switches the memory to which the classification data is recorded according to the priority by the selection input.

  In a fourth aspect based on any one of the first to third aspects, each data processing unit includes a compression / expansion unit that compresses or expands the classification data. Each data processing unit transfers the expanded classification data when the transfer speed of the classification data between the data processing sections is faster than the expansion speed of the classification data, and the compressed classification when the transfer speed is equal to or lower than the expansion speed. Transfer data.

  According to the present invention, power consumption when a plurality of image engines are used can be suppressed.

FIG. 2 is a block diagram illustrating a configuration example of an electronic camera 1 according to the present embodiment. The figure which shows an example of the initial arrangement | positioning to the non-volatile memory of functional block data The figure which shows an example of the 1st table data 50 The figure which shows an example of the 2nd table data 51 The flowchart which shows an example of the operation | movement at the time of power-on of the electronic camera 1. The flowchart which shows an example of the operation | movement at the time of power-off of the electronic camera 1. The figure which shows an example of arrangement | positioning to the non-volatile memory of the functional block data after the setting of a priority and use frequency The flowchart which shows an example of the transfer process in the case of reading functional block data from the 2nd flash memory 19 The figure explaining the example of setting of the priority (priority function) by user input The figure explaining the example of setting of the priority (priority function) by user input

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration example of an electronic camera 1 according to the present embodiment. The electronic camera 1 of this embodiment has a power control system that suppresses power consumption by restricting access to a slave-side image engine, which will be described later. An example of this power supply control system is realized by processing of a flow to be described later.

  As shown in FIG. 1, the electronic camera 1 includes an imaging optical system 10, an imaging unit 11, a first ASIC (Application Specific Integrated Circuit) 12, a data bus 13, a second ASIC 14, a recording interface unit (hereinafter “ A recording I / F unit) 15, a display monitor 16, a first flash memory 17, a first SDRAM (Synchronous Dynamic Random Access Memory) 18, a second flash memory 19, a second SDRAM 20, and an operation unit 21. The power supply unit 22 and a CPU (Central Processing Unit) 23 are provided. Note that the imaging unit 11, the first ASIC 12, the operation unit 21, and the power supply unit 22 are connected to the CPU 23.

  The imaging optical system 10 includes a plurality of lens groups including a zoom lens and a focus lens. For simplicity, FIG. 1 shows the imaging optical system 10 as a single lens.

  The imaging unit 11 includes, for example, an imaging device, an analog front end (AFE) circuit, an A / D conversion unit, and a digital front end (DFE) circuit. The imaging element captures an image of a subject. The AFE circuit performs analog signal processing on the image signal output from the image sensor. The A / D converter converts an analog image signal into a digital image signal. The DFE circuit performs digital signal processing on the image signal after A / D conversion. The output of the imaging unit 11 is connected to the first ASIC 12 and the second ASIC 14. Then, for example, the imaging unit 11 outputs an image signal as image data to the first ASIC 12 and the second ASIC 14 by time division processing according to an instruction from the CPU 23.

  The first ASIC 12 and the second ASIC 14 are circuits that perform various types of image processing (for example, edge enhancement processing, color interpolation processing, etc.) on the image data output from the imaging unit 11. Both the first ASIC 12 and the second ASIC 14 have the same processing capability, and both are connected via a data bus 13 dedicated to the ASIC.

  A recording I / F unit 15, a display monitor 16, a first flash memory 17, and a first SDRAM 18 are connected to the first ASIC 12. A second flash memory 19 and a second SDRAM 20 are connected to the second ASIC 14. The first SDRAM 18 and the second SDRAM 20 are volatile buffer memories that temporarily record image data. The first flash memory 17 and the second flash memory 19 are nonvolatile memories that record functional block data described later. Note that there are two types of flash memory, a NOR (Negative OR) type and a NAND (Negative AND) type, depending on the configuration of the internal basic circuit. The NOR type can perform random access at a higher speed than the NAND type. On the other hand, the NOR type is not suitable for integration and has a problem in increasing the memory capacity. In addition, the NOR type requires more power consumption for data writing than the NAND type. In the present embodiment, a NOR type is adopted for the first flash memory 17 and the second flash memory 19 from the viewpoint of high-speed processing. Therefore, in this embodiment, a means for suppressing power consumption is provided for the flash memory.

  The first ASIC 12 includes a first compression / decompression unit 12a and a first ASIC interface unit (hereinafter referred to as a “first ASIC I / F unit”) 12b. The second SDRAM 20 incorporates a second compression / decompression unit 14a and a second ASIC interface unit (hereinafter referred to as “first ASIC I / F unit”) 14b. The first compression / decompression unit 12a and the second compression / decompression unit 14a perform compression processing or decompression processing on the image data or the functional block data according to an instruction from the CPU 23. Here, the first compression / decompression unit 12a and the second compression / decompression unit 14a perform compression processing or decompression processing based on, for example, data compression or data decompression algorithms for binary data. Note that the second compression / decompression unit 14 a performs a compression process when the functional block data is recorded in the second flash memory 19. The first ASIC I / F unit 12b and the second ASIC I / F unit 14b provide a communication interface for transmitting and receiving data via the dedicated data bus 13 for ASIC.

  Here, functional block data handled by the first ASIC 12 and the second ASIC 14 will be described. The function block data is data obtained by classifying image processing programs, parameter files, and the like into functions. Each ASIC reads the functional block data from the flash memory 17 and performs various image processes on the image data recorded in the first SDRAM 18.

  FIG. 2 is a diagram illustrating an example of an initial arrangement of functional block data in a nonvolatile memory. FIG. 2A shows an example of arrangement of functional blocks. In the first flash memory 17, functional blocks 1 to 3 are recorded. In the second flash memory 19, function blocks 4 to 6 are recorded. Each functional block stores functional block data corresponding to the functional block.

  FIG. 2B shows specific contents of the functional block data corresponding to the functional block of FIG. Examples of functional block data include an image processing gamma table (functional block 1) used for image processing, an imaging control parameter table (functional block 2) used for imaging control, and a GUI (Graphical User Interface) for image display. Image data (Function block 3), Japanese font data for GUI for Japanese display (Function block 4), English font data for GUI for English display (Function block 5), GUI for Chinese display Chinese font data (function block 6).

  The recording I / F unit 15 is formed with a connector (not shown) for connecting a detachable recording medium 30. The recording I / F unit 15 accesses the recording medium 30 connected to the connector and performs image recording processing and the like. The recording medium 30 is, for example, a non-volatile memory card. FIG. 1 shows the recording medium 30 after being connected to the connector. The display monitor 16 displays various images, an operation menu of the electronic camera 1 and the like according to instructions from the CPU 23.

  Further, the operation unit 21 has a plurality of buttons that receive instruction inputs for operating the electronic camera 1. For example, the operation unit 21 is a release button that receives an instruction input for a half-press operation and a full-press operation (imaging operation start), an operation button that selects or executes a setting condition of an operation menu of the electronic camera 1, and the electronic camera 1 main body And a power button for accepting power on or off. The power supply unit 22 supplies power to each unit of the electronic camera 1. The start and stop of the supply of power are performed according to instructions from the CPU 23.

  The CPU 23 is a processor that performs various calculations and control of the electronic camera 1. The CPU 23 also functions as a switching unit 23a and a power supply control unit 23b. In the present embodiment, the second ASIC 14 is not connected to the CPU 23. Therefore, the CPU 23 controls the second ASIC 14 via the first ASIC 12. Thus, the first ASIC 12 (master side) and the second ASIC 14 (slave side) form a master-slave relationship with respect to data processing. Thereby, the CPU 23 preferentially uses the first ASIC 12 (master side). However, the CPU 23 uses the second ASIC 14 together with the first ASIC 12 when performing, for example, image processing that requires parallel processing.

  The switching unit 23 a switches the recording destination of the functional block data between the first flash memory 17 or the second flash memory 19 according to the attribute information set for each functional block data. The attribute information is, for example, the priority and usage frequency of the function block data. Here, the recording destination of the functional block data is determined by the CPU 23. Specifically, the CPU 23 determines the recording destination of the functional block data based on, for example, first table data 50 (see FIG. 3 described later) that manages attribute information and the like. Note that the CPU 23 uses the second table data 51 (see FIG. 4 described later) for counting the number of times the function block data is used to determine the function block use frequency. These table data are recorded in a memory (not shown) in the CPU 23. The first table data 50 and the second table data 51 may be recorded in the first flash memory 17.

  FIG. 3 is a diagram illustrating an example of the first table data 50. FIG. 4 is a diagram illustrating an example of the second table data 51. The first table data 50 is data for managing, for each functional block, priority and usage frequency attribute information, the current flash memory recording destination, a flag indicating the presence or absence of functional block data decompression processing, and the like. Here, in the figure, the first FM represents the first flash memory 17, and the second FM represents the second flash memory 19. The second table data 51 is a memory that counts the history of the number of uses for each functional block. For example, the CPU 23 may calculate the number of times of use since the use of the electronic camera 1 (after purchase by the user) as the history of the number of times of use. Alternatively, the CPU 23 may calculate the number of uses in units of months based on the history of the number of uses. In FIG. 4, the number of times of use is represented by symbols N1 to N6 for convenience of explanation.

  The CPU 23 classifies the priorities in the first table data 50 into, for example, two types of “high” and “low”. Specifically, the CPU 23 may perform the classification of “high” and “low” according to the usage frequency on the first ASIC 12 side. Alternatively, the CPU 23 may classify “high” and “low” by user input. Furthermore, the CPU 23 may not only classify the priorities into two types, “high” and “low”, but also set the priorities in detail.

  Further, the CPU 23 classifies the usage frequency in the first table data 50 into “large”, “medium”, and “small”. Specifically, the CPU 23 classifies “large”, “medium”, and “small” according to the number of times the second table data 51 is used (for example, for the past several months). The switching unit 23a refers to the first table data 50 and performs functional block data transfer processing between the first flash memory 17 and the second flash memory 19 as necessary (details will be described later).

  Further, when the recording destination of the functional block data is switched, the CPU 23 rewrites the current recording destination (recording state) column of the corresponding functional block on the first table data 50. Further, the CPU 23 manages the decompressed or compressed state for each functional block data by turning on / off the flag on the first table data 50. For example, when the compressed functional block data is expanded, the CPU 23 turns on (decompresses) the flag column on the first table data 50 for the corresponding functional block.

  The power supply control unit 23 b controls the start or stop of power supply to each unit of the electronic camera 1 in units of each unit via the power supply unit 22.

  Next, an example of functional block data transfer processing in the electronic camera 1 of the present embodiment will be described. FIG. 5 is a flowchart showing an example of the operation when the electronic camera 1 is powered on. Here, when the operation unit 21 receives a power-on instruction input of the electronic camera 1, the CPU 23 starts the processing of the flow illustrated in FIG. 5.

  Step S101: The power control unit 23b of the CPU 23 turns on the power of the first ASIC 12 and starts supplying power. Further, the power control unit 23b turns on the power of the imaging unit 11, the display monitor 16, the first flash memory 17, and the first SDRAM 18, and starts supplying power.

  Step S102: The CPU 23 determines whether or not to transfer the functional block data from the second flash memory 19 to the first flash memory 17. Specifically, the CPU 23 refers to the first table data 50 and determines, for example, whether or not functional block data having a high priority and a medium usage frequency exists in the second flash memory 19. When the above functional block data exists (step S102: Yes), the CPU 23 proceeds to the process of step S103. If the functional block data does not exist (step S103: No), the CPU 23 proceeds to the process of step S106. The CPU 23 manages the memory capacity of the first flash memory 17. Then, when there is a margin in the remaining capacity of the memory, the CPU 23 may transfer the function block data having a low priority and a medium usage frequency to the first flash memory 17.

  Step S103: The power control unit 23b turns on the power of the second ASIC 14 and starts supplying power.

  Step S104: The switching unit 23a performs a function block data transfer process. Specifically, first, the switching unit 23a instructs the first ASIC 12 and the second ASIC 14 to transfer the functional block data. Next, the second ASIC 14 reads the functional block data to be transferred from the second flash memory 19 based on the instruction from the switching unit 23a. Subsequently, the second ASIC 14 transmits the functional block data from the second ASIC I / F unit 14 b to the first ASIC I / F unit 12 b via the data bus 13. Subsequently, the first ASIC 12 records the functional block data received by the first ASIC I / F unit 12 b in the first flash memory 17.

  Step S105: The power supply control unit 23b turns off the power supply of the second ASIC 14 and stops supplying power.

  Step S106: The CPU 23 performs activation processing of the system that controls the electronic camera 1, and ends the processing of the flow shown in FIG.

  As described above, when the power of the second ASIC 14 is turned on, the CPU 23 turns it off after the functional block data transfer processing. The CPU 23 can suppress power consumption on the slave side by restricting the use of the second ASIC 14, the second flash memory 19, and the second SDRAM 20 after turning on the power of the first ASIC 12.

  Next, an example of the operation when the electronic camera 1 is turned off will be described with reference to the processing of the flow of FIG. FIG. 6 is a flowchart illustrating an example of an operation when the electronic camera 1 is powered off. Here, when the operation unit 21 receives an instruction input for powering off the electronic camera 1, the CPU 23 starts the processing of the flow illustrated in FIG. 6.

  Step S201: The CPU 23 sets the power-off prohibition until the functional block data transfer process is completed.

  Step S202: The CPU 23 checks the priority of the Nth (initial value N = 1) functional block. Specifically, the CPU 23 refers to the first table data 50, and when the priority of the Nth (initial value N = 1) functional block is “low” (step S202: Yes), the CPU 23 The process proceeds to step S203. On the other hand, when the priority is not “low” (step S202: No), the CPU 23 proceeds to the process of step S203.

  Step S203: The CPU 23 checks the usage frequency of the Nth functional block. Specifically, the CPU 23 refers to the first table data 50, and when the use frequency of the Nth functional block is “low” (step S203: Yes), the CPU 23 proceeds to the process of step S204. . On the other hand, when the usage frequency is not “low” (step S203: No), the CPU 23 proceeds to the process of step S205.

  Step S204: In this case, the priority of the function block data is low and the usage frequency is low. Therefore, the CPU 23 determines the recording destination of the Nth functional block data in the second flash memory 19 on the slave side.

  Step S205: The CPU 23 determines the recording destination of the Nth functional block data in the first flash memory 17 on the master side.

  Step S206: The CPU 23 determines whether or not all functional block data have been checked. If all the functional block data have not been checked (step S206: No), the CPU 23 proceeds to the process of step S209 and increments the value of N (N = N + 1). Then, the CPU 23 returns to the process of step S202. On the other hand, when all the functional block data have been checked (step S206: Yes), the CPU 23 proceeds to the process of step S207.

  Step S207: The switching unit 23a performs functional block data transfer processing based on the first table data 50. However, the switching unit 23a does not perform the functional block data transfer process based on the first table data 50 when the transfer process is unnecessary.

  FIG. 7 is a diagram illustrating an example of the arrangement of the functional block data in the nonvolatile memory after setting the priority and the usage frequency. FIG. 7A is a diagram showing the arrangement of functional blocks after transfer from the initial state of FIG. In FIG. 7A, for convenience of explanation, the priority and the use frequency are shown for each functional block. Since the functional block data of the functional block 3 recorded in the first flash memory 17 has a low priority and a low usage frequency, it is recorded in the second flash memory 19 by the transfer process of the switching unit 23a. The function block data of the function block 5 recorded in the second flash memory 19 is recorded in the first flash memory 17 by the transfer process of the switching unit 23a because the use frequency is high although the priority is low.

  FIG. 7B shows specific contents of the functional block data corresponding to the functional block of FIG. In this example, the recording destination of the GUI image data (functional block data of the functional block 3) is switched from the first flash memory 17 to the second flash memory 19. In addition, the recording destination of the GUI English font data (functional block data of the functional block 5) is switched from the second flash memory 19 to the first flash memory 17.

  Step S208: The CPU 23 starts shutting off the power. Specifically, the power supply control unit 23b stops supplying power to each block. The CPU 23 turns off the power of the electronic camera 1 by finishing the processing of the flow shown in FIG.

  As described above, the CPU 23 replaces, for example, functional block data having a high use frequency with the first flash memory 17. Therefore, at the next use, the CPU 23 uses the functional block data having a high use frequency in the first ASIC 12 on the master side, so that it is not necessary to drive the circuit on the slave side unless necessary. As a result, the CPU 23 can suppress power consumption on the slave side.

  Next, an example of transfer processing when reading out functional block data from the second flash memory 19 during use of the electronic camera 1 will be described. For example, when the functional block data used for the process selected by the user from the operation menu of the operation unit 21 is recorded in the second flash memory 19, the process of the following flow is executed. Here, it is assumed that the power supply of the second ASIC 14 is off.

  FIG. 8 is a flowchart showing an example of a transfer process when functional block data is read from the second flash memory 19. Here, when the operation unit 21 receives an instruction input to use the functional block data recorded in the second flash memory 19, the CPU 23 starts the processing of the flow shown in FIG.

  Step S301: The power supply control unit 23b of the CPU 23 turns on the power supply of the second ASIC 14 and starts supplying power.

  Step S302: The CPU 23 determines whether or not the transfer speed between the first ASIC 12 and the second ASIC 14 is faster than the function block data expansion speed on the first ASIC 12 side. Specifically, the CPU 23 checks the usage status of the first ASIC 12.

  Here, if the load of image processing currently being performed by the first ASIC 12 is a certain level or more, the first ASIC 12 will not function even if the compressed functional block data of the second flash memory 19 is transferred to the first flash memory 17. The block data decompression process takes time (first case). That is, the first case corresponds to a case where the transfer rate is faster than the functional block data expansion rate on the first ASIC 12 side. Therefore, in the first case described above, it is preferable to perform the transfer process by the switching unit 23a after decompressing the compressed functional block data of the second flash memory 19 on the second ASIC 14 side.

  Further, for example, depending on the data capacity of the expanded functional block data, traffic is increased between the first ASIC 12 and the second ASIC 14, so that it takes time to transfer the functional block data (second case). That is, the second case corresponds to a case where the transfer rate is equal to or lower than the functional block data expansion rate on the first ASIC 12 side. Therefore, in the second case described above, it is preferable that the switching unit 23a performs the transfer process in the state of the compressed functional block data. Thereby, CPU23 can suppress the increase in the power consumption accompanying the traffic increase between 1st ASIC12 and 2nd ASIC14.

  Therefore, when the transfer rate is faster than the data decompression rate (step S302: Yes), the CPU 23 proceeds to the process of step S303. On the other hand, when the transfer rate is equal to or lower than the data decompression rate (step S302: No), the CPU 23 proceeds to the process of step S304.

  Step S303: Upon receiving the instruction from the CPU 23, the second ASIC 14 performs functional block data expansion processing and updates the flag of the first table data 50.

  Step S304: The switching unit 23a of the CPU 23 performs a function block data transfer process.

  Step S305: The power supply control unit 23b turns off the power supply of the second ASIC 14 after the data transfer process is completed, and stops the supply of power.

  Step S306: The first ASIC 12 refers to the setting of the flag of the first table data 50 corresponding to the functional block data transferred from the second ASIC 14. When the functional block data is expanded (step S306: Yes), the CPU 23 proceeds to the process of step S308. On the other hand, if the functional block data is not expanded (step S306: No), the CPU 23 proceeds to the process of step S307.

  Step S307: The first ASIC 12 performs functional block data expansion processing.

  Step S308: The CPU 23 performs data processing based on the functional block data transferred from the second ASIC 14. Thereafter, the CPU 23 ends the processing of the flow shown in FIG.

  As described above, the CPU 23 can suppress an increase in power consumption due to an increase in traffic between the first ASIC 12 and the second ASIC 14.

As described above, the electronic camera 1 according to the present embodiment can perform power control for suppressing power consumption with respect to the image engine, the nonvolatile memory, and the volatile memory on the slave side. Thereby, this invention can suppress the power consumption at the time of using a several image engine.
(Supplementary items of the embodiment)
(1) In the above-described embodiment, the switching unit 23a switches the recording destination of the flash memory in consideration of the priority and the usage frequency. However, the priority may be switched with priority given to the user input. 9 and 10 are diagrams for explaining an example of setting priority (priority function) by user input. FIG. 9A shows a priority setting menu screen displayed on the display monitor 16. FIG. 9A shows that, as priority settings, the items “tone correction strength”, “high-sensitivity high-speed shooting”, “coloring”, and “Japanese” are preferentially selected. “Others” indicates that further items can be selected from the hierarchical menu. FIG. 9B shows a state in which functional block data with high priority set by user input is recorded in the first flash memory 17. FIG. 10A shows that “English” is set as a higher priority item instead of “Japanese” compared to FIG. 9A. Thereby, the switching unit 23a replaces the functional block data according to the priority. FIG. 10B shows a state in which GUI English font data is recorded in the first flash memory 17 on the master side, and Japanese font data for GUI is recorded in the second flash memory 19 on the slave side.

  Note that after the priority is set by user input, the CPU 23 may further set the priority according to the usage frequency. The switching unit 23 a may record items with high priority in the first flash memory 17.

  Also, in the case of an electronic camera having a My Menu function that allows users to frequently register items that are frequently used, the switching unit 23a uses the function block data of the items set on the My Menu screen as a high-priority item in the master side memory (first One flash memory 17) may be recorded. In the case of an electronic camera having a function of recording a menu history, the switching unit 23a records function block data of items frequently used in the menu history in a memory (first flash memory 17) on the master side. Also good.

  (2) In the above-described embodiment, the CPU 23 sets the priority and the like using the camera-side GUI. However, for example, the CPU 23 may set the priority and the like by an instruction from PC communication or an external interface.

  (3) In the above embodiment, an example in which the flash memory and the SDRAM are wired and connected to the ASIC (image engine) has been described. However, an ASIC in which the flash memory and the SDRAM are built in the ASIC may be used.

  (4) In the above embodiment, the case where two ASICs (image engines) are used has been illustrated, but the present invention is not limited to this. For example, a plurality of slave side ASICs are used for one master side ASIC. May be.

  (5) In the above embodiment, priority and use frequency are adopted as the attribute information, but the data capacity of the functional block data may be added to the attribute information. Then, for example, the switching unit 23a may record functional block data having a large data capacity in the memory on the master side (first flash memory 17).

DESCRIPTION OF SYMBOLS 1 ... Electronic camera, 11 ... Imaging part, 12 ... 1st ASIC, 14 ... 2nd ASIC, 17 ... 1st flash memory, 19 ... 2nd flash memory, 23a ... Switching part

Claims (4)

An imaging unit that captures an image of a subject and generates an image;
A plurality of data processing units for performing data processing of the image and system information;
A plurality of memories that are connected to each of the plurality of data processing units and record classification data classified for the data processing;
In accordance with the attribute information set for each classification data, a switching unit that switches the memory of the classification data recording destination,
An electronic camera comprising: The electronic camera according to claim 1,
The electronic camera according to claim 1, wherein the attribute information is at least one of a use frequency of the classification data, a priority of the classification data, and a data capacity of the classification data. The electronic camera according to claim 2,
The priority is a priority of the classification data set based on a user's selection input,
The electronic camera according to claim 1, wherein the switching unit switches a memory of a recording destination of the classification data according to a priority by the selection input. The electronic camera according to any one of claims 1 to 3,
Each data processing unit includes a compression / decompression unit that compresses or decompresses the classification data,
Each data processing unit transfers the expanded classification data when the transfer speed of the classification data between the data processing sections is faster than the expansion speed of the classification data, and when the transfer speed is equal to or less than the expansion speed Is an electronic camera that transfers compressed classification data.

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