JP2012030991A - Method for producing semiconductor light-emitting element, semiconductor light-emitting element, and sapphire single crystal substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high quality and low-cost sapphire single crystal substrate which scarcely has any crystal defect part even when the diameter is as large as 100 mm or more, and which is suited for epitaxial formation of a compound semiconductor layer, and to stably provide a high quality semiconductor light-emitting element having the compound semiconductor layer deposited on the substrate.SOLUTION: The method for producing the semiconductor light-emitting element having a group III compound semiconductor layer includes: a substrate cutting off step S200 of cutting off a wafer from the ingot of a sapphire single crystal; a sorting step S500 of sorting a wafer including a crystal defect part of which the X-ray diffraction image is obtained with an X-ray corrected with a curvature correction value Δω taking the inside of a range of ±0.15° as the standard of determination with respect to an incident angle ω of an X-ray with which the X-ray diffraction image of the (11-20) surface is obtained, by measuring the cut-off wafer with X-ray topography according to the Lang method; and a semiconductor layer deposition step S800 of depositing the group III compound semiconductor layer on the deposition surface of the sorted wafer.

Description

  The present invention relates to a method for manufacturing a semiconductor light emitting device, a semiconductor light emitting device, and a sapphire single crystal substrate.

In general, in a semiconductor light emitting device having a compound semiconductor layer such as a III-V compound semiconductor layer, a compound semiconductor layer is formed on a substrate surface made of a sapphire single crystal or the like, and electrodes such as a positive electrode and a negative electrode are further formed thereon. After being provided, the back surface of the substrate is ground and polished, and then cut into an appropriate shape to prepare a light emitting element chip (see Patent Document 1).
As for a sapphire single crystal substrate, Patent Document 2 describes a semiconductor light-emitting element using a high-quality sapphire substrate whose X-ray rocking curve half-width is 20 arcsec or less (see Patent Document 2).

JP 2008-177525 A JP 2008-1000085 A

By the way, the sapphire single crystal substrate on which the compound semiconductor layers are stacked is obtained by cutting out a single crystal ingot manufactured by the Czochralski method (CZ method), for example. In general, in the CZ method, it is known that when a sapphire single crystal is grown from an alumina melt, crystal defects are generated in the sapphire single crystal due to slight fluctuations in manufacturing conditions. In particular, it is difficult to stably produce a large-diameter sapphire single crystal substrate having a diameter of 100 mm or more. When such a sapphire single crystal substrate with many crystal defects is used, desired performance such as a decrease in light emission efficiency of the light emitting element may not be achieved, and the yield may be decreased.
An object of the present invention is to provide a high-quality and low-cost sapphire single crystal substrate suitable for epitaxial formation of a compound semiconductor layer with few crystal defect portions even with a large diameter of 100 mm or more. Another object is to stably provide a high-quality semiconductor light emitting device having a compound semiconductor layer formed thereon.

According to the present invention, the inventions according to the following [1] to [11] are provided.
[1] A method for manufacturing a semiconductor light-emitting device having a group III compound semiconductor layer, in which a sapphire wafer having a predetermined thickness is cut out from a sapphire single crystal ingot, and a sapphire wafer cut out in the substrate cutting step The X-ray topography measurement is performed by the method, and the curvature is determined within the range of ± 0.15 ° with respect to the X-ray incident angle ω from which the X-ray diffraction image of the (11-20) plane of the sapphire single crystal is obtained. A selection process for selecting a sapphire wafer including a crystal defect portion from which an X-ray diffraction image is obtained by an X-ray corrected by the correction value Δω, and a deposition surface of the sapphire substrate using the sapphire wafer selected by the selection process as a sapphire substrate The semiconductor layer film forming process for forming the group III compound semiconductor layer on the surface and the sapha removed by the selection process. And a sapphire single crystal pulling step for reusing the Iau wafer as a raw material for growing an ingot of the sapphire single crystal.
[2] The method for manufacturing a semiconductor light-emitting element according to [1], wherein, in the substrate cutting step, a C-plane ((0001) plane) of a sapphire single crystal is cut out from an ingot as a sapphire wafer.
[3] In the semiconductor layer forming step, the n-type semiconductor layer, the light emitting layer, and the p-type semiconductor layer are sequentially stacked on the surface of the sapphire substrate from the sapphire substrate side. Or the manufacturing method of the semiconductor light-emitting device as described in [2].
[4] The above [1] to [3], further comprising an intermediate layer forming step of forming an intermediate layer made of a group III compound semiconductor by a sputtering method between the sapphire substrate and the group III compound semiconductor layer. The manufacturing method of the semiconductor light-emitting device in any one of.
[5] The method for manufacturing a semiconductor light-emitting element according to [4], further comprising forming an underlayer between the group III compound semiconductor layer and the intermediate layer.

    [6] A semiconductor light-emitting device manufactured by the method for manufacturing a semiconductor light-emitting device according to any one of [1] to [5].

[7] A sapphire single crystal substrate made of a sapphire single crystal on which a group III compound semiconductor layer is formed, and the sapphire single crystal is a sapphire single crystal in the X-ray topography measurement by the Lang method. It includes a crystal defect portion where an X-ray diffraction image can be obtained by an X-ray corrected with a curvature correction value Δω within a range of ± 0.15 ° with respect to an X-ray incident angle ω from which an X-ray diffraction image of the lattice plane can be obtained. A sapphire single crystal substrate characterized by the above.
[8] The sapphire single crystal substrate according to [7], which has a diameter of 100 mm or more.
[9] The sapphire single crystal substrate according to [7] or [8] above, which is made of a sapphire wafer obtained by cutting a C-plane of a sapphire single crystal from an ingot.
[10] The sapphire single crystal substrate according to any one of [7] to [9], wherein the lattice plane of the sapphire single crystal is an A plane ((11-20) plane).
[11] The sapphire according to any one of [7] to [10] above, wherein the diameter is 150 mm or more, the thickness is 0.8 mm or more, and the curvature correction value Δω is within ± 0.15 ° for the entire substrate. Single crystal substrate.

According to the present invention, it is possible to stably obtain a high-quality semiconductor light-emitting element in which a compound semiconductor layer is formed on a sapphire single crystal substrate with few crystal defect portions as compared with the case without this configuration.
Further, by reusing a sapphire single crystal substrate having many crystal defects as a raw material, a low-cost sapphire single crystal substrate can be obtained.

It is a flowchart explaining the flow of the manufacturing method of the semiconductor light-emitting device to which this Embodiment is applied. It is a figure explaining an example of a single crystal pulling device. The example of a structure of the sapphire ingot manufactured using the single crystal pulling apparatus shown in FIG. 2 is shown. It is a figure explaining an example of the X-ray topography measurement by the Lang method of a sapphire wafer. It is a figure explaining an example of a semiconductor light emitting element.

  Hereinafter, embodiments of the present invention will be described in detail. The present invention is not limited to the following embodiments, and various modifications can be made within the scope of the invention. The drawings used are examples for explaining the present embodiment and do not represent actual sizes.

  FIG. 1 is a flowchart for explaining the flow of a method for manufacturing a semiconductor light emitting device to which the present embodiment is applied. In the method for manufacturing a semiconductor light emitting device, first, a sapphire single crystal ingot is manufactured by a CZ method. To produce a sapphire single crystal ingot, the aluminum oxide filled in the crucible and the sapphire wafer excluded (NO) in step 500 (screening process) described later are melted (alumina melt), and the seed crystal is fused with alumina. The sapphire single crystal is grown by bringing it into contact with the liquid surface and pulling it upward while rotating the seed crystal (step 100: sapphire single crystal pulling step). Next, the obtained sapphire single crystal ingot is cut to a predetermined thickness to cut out a sapphire wafer (step 200: substrate cutting step).

  Next, the cut sapphire wafer is subjected to a wet etching process to remove processing damage (crushed layer) received by the cut (step 300). Subsequently, crystal defects of the sapphire single crystal in the sapphire wafer subjected to the wet etching process are measured by an X-ray topography measurement method (Lang method) (step 400). Subsequently, in the X-ray topography measurement of the sapphire wafer, the curvature within a range of ± 0.15 ° with respect to the incident angle ω of the transmitted X-ray from which the X-ray diffraction image of the (11-20) plane of the sapphire single crystal is obtained. A sapphire wafer including a crystal defect portion from which an X-ray diffraction image is obtained is selected by transmission X-rays corrected with the correction value Δω (step 500: selection step). The curvature correction value Δω will be described later.

  Next, the surface to be polished of the sapphire wafer selected by the selection process is polished to finish the surface to be polished in a mirror state (step 700). Subsequently, a sapphire wafer having a mirror-finished surface is used as a sapphire single crystal substrate, and a group III compound semiconductor layer is formed on the film formation surface of the sapphire single crystal substrate (step 800: semiconductor layer formation). Membrane process). Subsequently, an electrode is attached to the sapphire single crystal substrate on which the group III compound semiconductor layer is formed, and the ground surface of the sapphire single crystal substrate is ground to a predetermined thickness using, for example, a fixed grindstone, The thickness of the sapphire single crystal substrate is adjusted to a predetermined thickness on the surface to be ground of the substrate damaged by the grinding process by, for example, a lapping process and a polishing process using free abrasive grains (step 900). After the lapping process, the sapphire single crystal substrate is cut into a predetermined size to obtain a light emitting element chip (step 1000). Hereinafter, each step will be described.

(Step 100)
In this embodiment, a sapphire single crystal ingot is manufactured by a CZ method using a predetermined single crystal pulling apparatus.
FIG. 2 is a diagram illustrating an example of the single crystal pulling apparatus I. As shown in FIG. 2, the single crystal pulling apparatus I includes a heating furnace 10 for growing a sapphire ingot 30 made of a single crystal of sapphire. The heating furnace 10 includes a heat insulating container 11. The heat insulating container 11 has a columnar outer shape, and a columnar space is formed therein. The heat insulating container 11 is configured by assembling components made of a heat insulating member made of zirconia, for example. The heating furnace 10 includes a chamber 14 that accommodates the heat insulating container 11 in an internal space. The heating furnace 10 includes a gas supply pipe 12 that is formed through the side surface of the chamber 14 and supplies gas from the outside of the chamber 14 to the inside of the heat insulating container 11 through the chamber 14. Similarly, a gas exhaust pipe 13 that is formed through the side surface of the chamber 14 and exhausts gas from the inside of the heat insulating container 11 to the outside through the chamber 14 is further provided.

A crucible 15 is arranged below the inner side of the heat insulating container 11 so as to open vertically upward. The crucible 15 is made of, for example, iridium, and, as will be described later, sapphire excluded (NO) as not satisfying the range of the curvature correction value (Δω) in the X-ray topography measurement of the sapphire single crystal by the Lang method, as will be described later. An alumina melt 35 obtained by adding a wafer and melting them is accommodated. Furthermore, the shoulder part and tail part of other ingots already used for cutting out the sapphire wafer are added to the crucible 15, and these are also reused as raw materials for producing an ingot of a sapphire single crystal to prepare an alumina melt 35. Also good. The curvature correction value (Δω) will be described later.
The heating furnace 10 includes a metal heating coil 16. The heating coil 16 is wound around a portion that is outside the side surface on the lower side of the heat insulating container 11 and inside the side surface on the lower side of the chamber 14. The heating coil 16 is disposed so as to face the wall surface of the crucible 15 through the heat insulating container 11. The lower end of the heating coil 16 is located below the lower end of the crucible 15, and the upper end of the heating coil 16 is located above the upper end of the crucible 15.

  The heating coil 16 is constituted by, for example, a hollow copper tube, wound spirally, and has a cylindrical shape when viewed as a whole. In the present embodiment, the inner diameter on the upper side and the inner diameter on the lower side of the heating coil 16 are substantially the same. Thereby, the space formed in the inside by the wound heating coil 16 is cylindrical. Further, the central axis of the heating coil 16 passing through the cylindrical space is substantially perpendicular to the horizontal direction, that is, along the vertical direction. The crucible 15 is disposed inside a cylindrical space formed by the heating coil 16. Then, the crucible 15 is placed at a site that is substantially in the center of the circular region formed by the heating coil 16.

  The heating furnace 10 includes a pulling bar 17 that extends downward from above through through holes provided in the upper surfaces of the heat insulating container 11 and the chamber 14. The pulling rod 17 is attached so as to be able to move in the vertical direction and rotate around the axis. A sealing material (not shown) is provided between the through hole provided in the chamber 14 and the lifting rod 17. A holding member 18 for attaching and holding a seed crystal 31 (see FIG. 3 to be described later) as a base for growing the sapphire ingot 30 is attached to the end of the pulling bar 17 on the vertically lower side. Yes.

The single crystal pulling apparatus I includes a pulling drive unit 19 for pulling up the pulling bar 17 vertically upward and a rotation driving unit 20 for rotating the pulling bar 17. Here, the pulling drive unit 19 is constituted by a motor or the like, and the pulling speed of the pulling rod 17 can be adjusted. The rotation drive unit 20 is also composed of a motor or the like so that the rotation speed of the lifting rod 17 can be adjusted.
The single crystal pulling apparatus I includes a gas supply unit 21 that supplies gas into the chamber 14 via the gas supply pipe 12. In the present embodiment, the gas supply unit 21 supplies a mixed gas in which oxygen supplied from the O ₂ source 22 and nitrogen as an example of an inert gas supplied from the N ₂ source 23 are mixed. And the gas supply part 21 adjusts the oxygen concentration in mixed gas by changing the mixing ratio of oxygen and nitrogen. The flow rate of the mixed gas supplied into the chamber 14 is also adjusted.

The single crystal pulling apparatus I includes an exhaust unit 24 that exhausts gas from the inside of the chamber 14 via the gas exhaust pipe 13. The exhaust unit 24 includes, for example, a vacuum pump or the like, and is capable of decompressing the chamber 14 and exhausting the gas supplied from the gas supply unit 21.
The single crystal pulling apparatus I includes a coil power supply 25 that supplies current to the heating coil 16. The coil power supply 25 sets whether to supply current to the heating coil 16 and the amount of current to be supplied.
In addition, the single crystal pulling apparatus I includes a weight detection unit 27 that detects the weight of the sapphire ingot 30 that grows on the lower side of the pulling bar 17 through the pulling bar 17. The weight detection unit 27 includes, for example, a known weight sensor.

  The single crystal pulling apparatus I includes the pulling drive unit 19, the rotation drive unit 20, the gas supply unit 21, the exhaust unit 24, the coil power supply 25, and the control unit 26 that controls the operation of the coil drive unit. Further, the control unit 26 calculates the crystal diameter of the sapphire ingot 30 to be pulled up based on the weight signal output from the weight detection unit 27 and feeds it back to the coil power supply 25.

<Sapphire Ingot 30>
FIG. 3 shows an example of the configuration of the sapphire ingot 30 manufactured using the single crystal pulling apparatus I shown in FIG.
The sapphire ingot 30 includes a seed crystal 31 that is a base for growing the sapphire ingot 30, a shoulder portion 32 that extends under the seed crystal 31 and is integrated with the seed crystal 31, and a lower portion of the shoulder portion 32. A straight body portion 33 extending and integrated with the shoulder portion 32, and a tail portion 34 extending below the straight body portion 33 and integrated with the straight body portion 33 are provided. In the present embodiment, in this sapphire ingot 30, a single crystal of sapphire grows in the c-axis direction from the upper seed crystal 31 side toward the lower tail portion 34 side.

  Here, the shoulder portion 32 has a shape in which the diameter gradually increases from the seed crystal 31 side toward the straight body portion 33 side. Further, the straight body portion 33 has a shape such that the diameters thereof are substantially the same from the top to the bottom. The diameter of the straight body portion 33 is set to a value slightly larger than the diameter of a sapphire single crystal wafer designed in advance. The diameter (cross-sectional diameter) of the straight body portion 33 is referred to as an ingot diameter Ding. The tail portion 34 has a shape (convex shape) that gradually decreases in diameter from the upper side to the lower side and becomes convex from the upper side to the lower side. The length of the tail 34 in the vertical direction is referred to as tail length HT.

<Procedure for Producing Sapphire Ingot 30>
When manufacturing the sapphire ingot 30, first, solid aluminum oxide filled in the crucible 20 in the chamber 14 is melted by heating (alumina melt 35). Next, temperature adjustment is performed with the alumina melt 35 in contact with the lower end portion of the seed crystal 31. Next, the seed crystal 31 brought into contact with the alumina melt 35 is pulled upward while being rotated, and a shoulder portion 32 is formed below the seed crystal 31. Subsequently, the shoulder portion 32 is rotated upward through the seed crystal 31 while being pulled up, and the straight body portion 33 is formed below the shoulder portion 32. Subsequently, while rotating the straight body portion 33 through the seed crystal 31 and the shoulder portion 32, the straight body portion 33 is pulled upward and separated from the alumina melt 35, and a tail portion 34 is formed below the straight body portion 33. Then, after the obtained sapphire ingot 30 is cooled, it is taken out of the chamber 14. Thereafter, in order to remove the thermal strain of the sapphire ingot 30, it is desirable to add a heat treatment step.

(Step 200)
Next, the sapphire ingot 30 obtained in this way is first cut at the boundary between the shoulder portion 32 and the straight body portion 33 and at the boundary between the straight body portion 33 and the tail portion 34, and the straight body portion 33 is cut out. It is. Next, the cut out straight body portion 33 is further cut in a direction orthogonal to the longitudinal direction by, for example, a multi-wire saw, and cut out as a sapphire single crystal wafer (sapphire wafer). At this time, since the sapphire ingot 30 of the present embodiment is grown in the c-axis direction of the sapphire single crystal, the main surface of the obtained wafer is the C plane ((0001) plane) of the sapphire single crystal. Become.

(Step 300)
Next, the cut sapphire wafer is subjected to a wet etching process to remove processing damage (crushed layer) received by cutting using a multi-wire saw. The conditions for the wet etching treatment are not particularly limited, and examples thereof include a method of immersing a sapphire wafer in an acid solution such as phosphoric acid at a temperature of about 130 ° C., and a method of spraying an acid solution on the surface of the sapphire wafer. After the wet etching process, for example, the surface of the sapphire wafer is washed with hot water rinse or the like and then dried.

(Step 400)
Next, the X-ray topography measurement by the Lang method is performed about the sapphire wafer which performed the wet etching process, and the crystal defect of a sapphire single crystal is measured.
FIG. 4 is a diagram for explaining an example of X-ray topography measurement by the Lang method of a sapphire wafer. As shown in FIG. 4, a rung camera used for X-ray topography measurement includes an X-ray source 1 built in a predetermined X-ray tube (not shown), and a diverging slit 2 composed of a horizontal slit 2a and a vertical slit 2b. And a pair of limiting slit plates 3 that limit diffraction X-rays that satisfy the Bragg diffraction condition, and a film 4. Although not shown, the rung camera has a counter placed behind the film 4, a circular sample holder for holding the sapphire wafer 5 to be measured, and a slider for fixing the sample holder so that the sample holder can be moved back and forth in the horizontal direction. It has a fixed support frame, a support frame that supports the film 4, and an arm integral therewith.

As shown in FIG. 4, the X-ray radiated from the X-ray source 1 has its divergence angle limited by the divergence slit 2 and is incident on the sapphire wafer 5 that is a measurement object. At this time, the X-ray irradiation field irradiated to the sapphire wafer 5 is a strip-like region elongated in the vertical direction of the sapphire wafer 5.
The sapphire wafer 5 rotates in-plane around a central axis (not shown) extending in the horizontal direction, and performs rotation (ω rotation) for adjusting the incident angle of the X-ray around the vertical axis L2. Thereby, the angular position is adjusted so that X-ray diffraction satisfying the Bragg diffraction condition occurs from the entire X-ray irradiation field irradiated to the sapphire wafer 5. The diffracted X-rays 7 satisfying the Bragg diffraction condition with respect to the transmitted X-rays 6 transmitted through the sapphire wafer 5 pass through the slit formed between the limiting slit plates 3 and enter the film 4, and are elongated in a strip shape. The diffraction X-ray image 8 is formed.
In the present embodiment, a diffracted X-ray image is obtained by diffracted X-rays 7 obtained from the A plane ((11-20) plane) as the lattice plane of the sapphire single crystal from the entire X-ray irradiation field irradiated to the sapphire wafer 5. 8 is formed.

  Here, the sapphire wafer 5 and the film 4 are moved together in the direction A by a predetermined slider (not shown), and the X-ray irradiation field is scanned from one end to the other end of the sapphire wafer 5 at a constant speed. At this time, a diffracted X-ray image 8 of the diffracted X-rays 7 over the entire surface of the sapphire wafer 5 is imaged on the film 4 to create a so-called X-ray topograph. Then, by observing the diffracted X-ray image 8, crystal defects of the sapphire wafer 5 are determined. In the present embodiment, the diffracted X-ray image 8 is formed from the X-ray irradiation field irradiated to all regions except 3 mm around the sapphire single crystal substrate.

(Step 500)
As described above, the sapphire wafer 5 rotates (ω rotation) about the vertical axis L2 in order to adjust the incident angle of X-rays. Thereby, the incident angle (ω) position is adjusted from the sapphire wafer 5 so that X-ray diffraction satisfying the Bragg diffraction condition of the A plane ((11-20) plane) as the lattice plane of the sapphire single crystal occurs. The adjustment of the incident angle (ω) position is performed by irradiating the center of the sapphire wafer 5 with X-rays.
Next, in this embodiment, the incident angle (ω) of the X-rays incident on the sapphire wafer 5 is fixed, and the sapphire wafer 5 and the film 4 are translated in the direction A together. At this time, as a method of moving the sapphire wafer 5 and the film 4 in parallel, the sapphire wafer 5 and the film 4 may be moved continuously as a unit, or step scanning may be performed for every pitch of a certain width. In the present embodiment, a method of performing step scanning for each pitch having a constant width is employed.

  Here, when a crystal defect exists in the sapphire single crystal of the sapphire wafer 5, the diffraction X-ray image 8 by the diffraction X-ray 7 that satisfies the Bragg diffraction condition based on the (11-20) plane is not formed. In this embodiment, the sapphire wafer 5 is rotated (ω rotation) about the vertical axis L2 and is incident on the sapphire single crystal of the sapphire wafer 5 so that a diffraction X-ray image 8 satisfying the Bragg diffraction condition is obtained. The incident angle of X-ray is corrected. In the present embodiment, when the sapphire single crystal includes a crystal defect portion, X-rays are incident on the crystal defect portion, and X-ray incidence is obtained to obtain an X-ray diffraction image of the (11-20) plane of the sapphire single crystal. The operation of rotating the sapphire wafer 5 with respect to the angle (ω) to obtain the diffracted X-ray image 8 satisfying the Bragg diffraction condition is referred to as curvature correction, and the rotation angle at that time is referred to as a curvature correction value (Δω). Called.

In the present embodiment, in the X-ray topography measurement of the sapphire single crystal by the Lang method, the sapphire wafer 5 with the above-described range of the curvature correction value (Δω) (−0.15 ° ≦ Δω ≦ 0.15 °) as a criterion. Are sorted out.
That is, the sapphire single crystal adopts (YES) a sapphire wafer 5 that can obtain an X-ray diffraction image by X-rays corrected in the above-described range of the curvature correction value (Δω) within ± 0.15 ° (YES). Those having an excessively large (Δω) are excluded (NO) and selected.
The selected sapphire wafer 5 is used as a sapphire single crystal substrate in a film forming process of a group III compound semiconductor layer to be described later, and a semiconductor light emitting device is manufactured. Here, when the absolute value of the curvature correction value (Δω) is excessively large, a crystal plane orientation shift occurs due to high-density crystal defects. When such a sapphire wafer 5 is used as a sapphire single crystal substrate in a film forming process of a group III compound semiconductor layer, the epitaxial formation of the group III compound semiconductor layer is good on the film formation surface of such a sapphire single crystal substrate. Does not progress to.
It should be noted that the change in the curvature correction value (Δω) of the sapphire single crystal substrate desirably changes gently from one end of the sapphire wafer 5 to the other end. The gentle change of the curvature correction value (Δω) in the sapphire single crystal substrate is presumed that defects are less likely to occur when the group III compound semiconductor layer is epitaxially formed on the film formation surface of the sapphire single crystal substrate.

(Step 600)
Here, the sapphire wafer excluded (NO) because it does not satisfy the range of the curvature correction value (Δω) described above is added to the crucible 15 disposed inside and below the heat insulating container 11, and an ingot of a sapphire single crystal by the CZ method. It is reused as a raw material for reducing the manufacturing cost. The sapphire wafer eliminated (NO) in the sorting step (step 600) has more crystal defects in the sapphire single crystal than the sorted sapphire wafer. However, since the purity of alumina is sufficiently high as a raw material used for manufacturing the sapphire ingot 30, the quality as a raw material is satisfied.

(Step 700)
Next, the surface to be polished of the sapphire wafer selected by the selection step is polished, and the surface to be polished is finished in a mirror state. The method for polishing the surface to be polished of the sapphire wafer is not particularly limited. For example, it is desirable to polish the surface to be polished of a sapphire wafer using diamond abrasive grains, further etch the surface of the surface to be polished using acid, and then clean the surface.
Further, in order to increase the light emission efficiency of the light emitting element, it is desirable to perform fine uneven processing on the surface of the sapphire wafer. As the fine uneven processing, for example, convex portions having a diameter of about 2 μm and a height of about 1 μm are arranged on the surface of the sapphire wafer at intervals of about 3 μm. A known photolithography technique, dry etching technique, or wet etching technique can be used for processing the protrusion. The shape of the convex portion can be a hemisphere, a cone, a cylinder, a pyramid, a prism, or the like, and a cone or a hemisphere is preferable.

(Step 800)
In the present embodiment, the semiconductor light emitting device (LC) uses the sapphire wafer 5 selected through the above-described steps as a sapphire single crystal substrate, and forms a group III compound semiconductor layer on the sapphire single crystal substrate.
Next, the structure of the semiconductor light emitting device manufactured by the method for manufacturing the semiconductor light emitting device to which the present embodiment is applied will be described. The semiconductor light emitting device manufactured in the present embodiment has a substrate and a compound semiconductor layer formed on the substrate. Examples of the compound semiconductor constituting the compound semiconductor layer include a III-V group compound semiconductor, a II-VI group compound semiconductor, a IV-IV group compound semiconductor, and the like. In the present embodiment, a III-V group compound semiconductor is preferable, and among these, a group III nitride compound semiconductor is preferable. Hereinafter, a semiconductor light emitting device having a compound semiconductor layer composed of a group III nitride compound semiconductor will be described as an example.

(Semiconductor light emitting device)
FIG. 5 is a diagram for explaining an example of a semiconductor light emitting device manufactured in the present embodiment. As shown in FIG. 5, the semiconductor light emitting device (LC) has a base layer 130 and a group III compound semiconductor layer 100 on an intermediate layer 120 formed on a sapphire single crystal substrate 110. In the group III compound semiconductor layer 100, an n-type semiconductor layer 140, a light emitting layer 150, and a p-type semiconductor layer 160 are sequentially stacked.
Further, a transparent positive electrode 170 is laminated on the p-type semiconductor layer 160, a positive electrode bonding pad 180 is formed thereon, and a negative electrode 190 is formed in the exposed region 140c formed in the n-type contact layer 140a of the n-type semiconductor layer 140. Are stacked.

Here, the n-type semiconductor layer 140 formed on the base layer 130 includes an n-type contact layer 140a and an n-type cladding layer 140b. The light emitting layer 150 has a structure in which barrier layers 150a and well layers 150b are alternately stacked. In the p-type semiconductor layer 160, a p-type cladding layer 160a and a p-type contact layer 160b are stacked.
In the present embodiment, the total thickness of the compound semiconductor layers (a combination of the intermediate layer 120, the base layer 130, and the group III compound semiconductor layer 100) formed on the sapphire single crystal substrate 110 is preferably 3 μm. More preferably, it is 5 μm or more, and more desirably 8 μm or more. The total thickness of these is preferably 15 μm or less.
Next, the material of each layer constituting the semiconductor light emitting element (LC) will be described.

(Intermediate layer 120)
In the present embodiment, it is preferable to provide an intermediate layer 120 that exhibits a buffer function on the sapphire single crystal substrate 110 when the group III compound semiconductor layer 100 is formed by metal organic chemical vapor deposition (MOCVD). . In particular, the intermediate layer 120 preferably has a single crystal structure from the viewpoint of the buffer function. When the intermediate layer 120 having a single crystal structure is formed on the sapphire single crystal substrate 110, the buffer function of the intermediate layer 120 acts effectively, and the base layer 130 and the group III compound semiconductor formed on the intermediate layer 120 The layer 100 is a crystal film having good orientation and crystallinity.
The intermediate layer 120 preferably contains Al, and particularly preferably contains AlN which is a group III nitride. The material constituting the intermediate layer 120 is not particularly limited as long as it is a group III nitride compound semiconductor represented by the general formula AlGaInN. Furthermore, As and P may be contained as a group V. When the intermediate layer 120 has a composition containing Al, it is preferably AlGaN, and the composition of Al is preferably 50% or more.

(Underlayer 130)
As a material used for the underlayer 130, a group III nitride (GaN-based compound semiconductor) containing Ga is used, and in particular, AlGaN or GaN can be preferably used. The film thickness of the underlayer 130 is 0.1 μm or more, preferably 0.5 μm or more, and more preferably 1 μm or more.

(N-type semiconductor layer 140)
The n-type semiconductor layer 140 includes an n-type contact layer 140a and an n-type cladding layer 140b. As the n-type contact layer 140a, a GaN-based compound semiconductor is used in the same manner as the base layer 130. Further, the gallium nitride compound semiconductor constituting the base layer 130 and the n-type contact layer 140a preferably has the same composition, and the total film thickness thereof is 0.1 μm to 20 μm, preferably 0.5 μm to 15 μm, Preferably, it is set in the range of 1 μm to 12 μm.

  The n-type cladding layer 140b can be formed of AlGaN, GaN, GaInN, or the like. Alternatively, a heterojunction of these structures or a superlattice structure in which a plurality of layers are stacked may be used. In the case of using GaInN, it is desirable to make it larger than the GaInN band gap of the well layer 150b constituting the light emitting layer 150 described later. The film thickness of the n-type cladding layer 140b is preferably 5 nm to 500 nm, more preferably 5 nm to 100 nm.

(Light emitting layer 150)
The light emitting layer 150 includes a barrier layer 150a made of a gallium nitride-based compound semiconductor and a well layer 150b made of a gallium nitride-based compound semiconductor containing indium, which are alternately stacked, and the n-type semiconductor layer 140 side and the p-type layer. The barrier layers 150a are stacked in the order in which the barrier layers 150a are disposed on the type semiconductor layer 160 side. In the present embodiment, the light emitting layer 150 includes six barrier layers 150a and five well layers 150b that are alternately and repeatedly stacked, and the barrier layer 150a is disposed on the uppermost layer and the lowermost layer of the light emitting layer 150. A well layer 150b is arranged between the barrier layers 150a.
The well layer 150b can be indium as semiconductor gallium nitride-based compound containing, for _example, it can be used _{Ga 1-s In s N (} 0 <s <0.4) GaN such as indium.
The film thickness of the well layer 150b is not particularly limited, but it is a film thickness that allows the quantum effect to be obtained, and is preferably a region that is equal to or less than the critical film thickness. For example, the thickness of the well layer 150b is preferably in the range of 1 nm to 10 nm, and more preferably 2 nm to 6 nm.
As the barrier layer 150a, a gallium nitride-based compound semiconductor such as Al _c Ga _1-c N (0 ≦ c ≦ 0.3) having a larger band gap energy than the well layer 150b can be preferably used.

(P-type semiconductor layer 160)
The p-type semiconductor layer 160 includes a p-type cladding layer 160a and a p-type contact layer 160b. The p-type cladding layer 160a is preferably Al _d Ga _1-d N (0 <d ≦ 0.4). The film thickness of the p-type cladding layer 160a is preferably 1 nm to 400 nm, more preferably 5 nm to 100 nm.
Examples of the p-type contact layer 160b include a gallium nitride compound semiconductor layer containing at least Al _e Ga _1-e N (0 ≦ e <0.5). The thickness of the p-type contact layer 160b is not particularly limited, but is preferably 10 nm to 500 nm, and more preferably 50 nm to 200 nm.

(Transparent positive electrode 170)
Examples of the material constituting the transparent positive electrode 170 include ITO (In ₂ O ₃ —SnO ₂ ), AZO (ZnO—Al ₂ O ₃ ), IZO (In ₂ O ₃ —ZnO), and GZO (ZnO—Ga ₂ O). Conventionally known materials such as ₃ ) may be mentioned. Moreover, the structure of the transparent positive electrode 170 is not specifically limited, A conventionally well-known structure is employable. The transparent positive electrode 170 may be formed so as to cover almost the entire surface of the p-type semiconductor layer 160, or may be formed in a lattice shape or a tree shape.

(Positive electrode bonding pad 180)
The positive electrode bonding pad 180 as an electrode formed on the transparent positive electrode 170 is made of, for example, a conventionally known material such as Au, Al, Ni, or Cu. The structure of the positive electrode bonding pad 180 is not particularly limited, and a conventionally known structure can be adopted.
The thickness of the positive electrode bonding pad 180 is in the range of 100 nm to 1,000 nm, and preferably in the range of 300 nm to 500 nm.

(Negative electrode 190)
As shown in FIG. 5, the negative electrode 190 includes a group III compound semiconductor layer 100 (n-type semiconductor layer 140, n-type semiconductor layer 140, further formed on the intermediate layer 120 and the base layer 130 formed on the sapphire single crystal substrate 110. The light emitting layer 150 and the p-type semiconductor layer 160 are formed so as to be in contact with the n-type contact layer 140a of the n-type semiconductor layer 140. Therefore, when forming the negative electrode 190, the p-type semiconductor layer 160, the light emitting layer 150, and the n-type semiconductor layer 140 are partially removed to form an exposed region 140c of the n-type contact layer 140a, and the negative electrode is formed thereon. 190 is formed.
As the material of the negative electrode 190, negative electrodes having various compositions and structures are well known, and these well-known negative electrodes can be used without any limitation, and can be provided by conventional means well known in this technical field.

  In the present embodiment, first, an intermediate layer 120 made of a group III nitride is formed on a sapphire single crystal substrate 110 by activating and reacting a gas containing a group V element with a metal material. Subsequently, the base layer 130, the n-type semiconductor layer 140, the light emitting layer 150, and the p-type semiconductor layer 160 are sequentially stacked on the formed intermediate layer 120.

  In the present embodiment, when the group III nitride semiconductor crystal is epitaxially grown on the sapphire single crystal substrate 110, the intermediate layer 120 uses a sputtering method to activate the raw material that has been activated and reacted with plasma on the sapphire single crystal substrate 110. It is preferable to form a film. Here, the V group element is nitrogen, the gas fraction of nitrogen in the gas when forming the intermediate layer 120 is in the range of 50% to 99% or less, and the intermediate layer 120 is formed as a single crystal structure. . Thereby, the intermediate layer 120 having good crystallinity is formed on the sapphire single crystal substrate 110 in a short time. As a result, a group III nitride semiconductor with good crystallinity grows on the intermediate layer 120 as compared with the case where the intermediate layer 120 is not provided.

In this embodiment, after the intermediate layer 120 is formed by a sputtering method, an underlying layer 130, an n-type semiconductor layer 140, a light-emitting layer 150, and a p-type semiconductor are formed thereon by metal organic chemical vapor deposition (MOCVD). It is preferable to sequentially form the layer 160.
In the MOCVD method, for example, hydrogen (H ₂ ) or nitrogen (N ₂ ) is used as a carrier gas. Trimethylgallium (TMG), triethylgallium (TEG), or the like is used as a Ga source that is a group III raw material. As the Al source, trimethylaluminum (TMA), triethylaluminum (TEA), or the like is used. As the In source, trimethylindium (TMI), triethylindium (TEI), or the like is used. Ammonia (NH ₃ ), hydrazine (N ₂ H ₄ ), or the like is used as an N source that is a group V raw material.
As the dopant, monosilane (SiH ₄ ), disilane (Si ₂ H ₆ ), or the like is used as the Si raw material for the n-type. An organic germanium compound such as germane gas (GeH ₄ ), tetramethyl germanium ((CH ₃ ) ₄ Ge), tetraethyl germanium ((C ₂ H ₅ ) ₄ Ge) can be used as the Ge raw material.

  The gallium nitride compound semiconductor may contain other elements in addition to Al, Ga, and In. For example, dopant elements such as Ge, Si, Mg, Ca, Zn, and Be can be given. Furthermore, it is not limited to the element added intentionally, but may include impurities that are inevitably included depending on the film forming conditions, etc., and trace impurities that are included in the raw materials and reaction tube materials.

  In addition, after forming the base layer 130 by the MOCVD method, each layer of the n-type contact layer 140a and the n-type cladding layer 140b is formed by the sputtering method, and the light emitting layer 150 thereon is formed by the MOCVD method, and then the p-type Each layer of the p-type cladding layer 160a and the p-type contact layer 160b constituting the semiconductor layer 160 may be formed by reactive sputtering.

(Step 900)
After forming the intermediate layer 120, the underlayer 130, and the group III compound semiconductor layer 100 on the sapphire single crystal substrate 110, the transparent positive electrode 170 is stacked on the p-type semiconductor layer 160 of the group III compound semiconductor layer 100. Then, a positive electrode bonding pad 180 is formed. Further, a wafer having the negative electrode 190 provided in the exposed region 140c formed in the n-type contact layer 140a of the n-type semiconductor layer 140 is formed.

The sapphire single crystal substrate 110 on which the compound semiconductor layer described above is formed is then ground and polished until the surface to be ground (back surface) of the sapphire single crystal substrate 110 has a predetermined thickness. In the present embodiment, the wafer is attached to a commercially available grinder (not shown), and the thickness of the sapphire single crystal substrate 110 of the wafer is, for example, about 900 μm to about 125 μm by a grinding process for about 20 minutes. Decrease.
In the present embodiment, when the surface to be ground of the sapphire single crystal substrate 110 of each wafer is ground and polished, an abrasive or an abrasive is supplied. The kind of the abrasive or abrasive is not particularly limited, and a commercially available slurry-type abrasive or abrasive is used. Furthermore, in the present embodiment, the thickness of the sapphire single crystal substrate 110 is polished from about 125 μm to about 120 μm by performing a polishing process for about 15 minutes following the grinding process.

(Step 1000)
Next, the wafer in which the thickness of the sapphire single crystal substrate 110 is adjusted is cut into a square of 350 μm square, for example, so that the intermediate layer 120, the base layer 130, and the group III compound semiconductor layer 100 are formed on the sapphire single crystal substrate 110. A semiconductor light emitting device (LC) is formed. As the cutting method, a known technique such as laser, stealth laser, scribe break method or the like can be used.

  As described above, in the present embodiment, the X-ray diffraction of the (11-20) plane of the sapphire single crystal in the X-ray topography measurement on the sapphire single crystal substrate having a predetermined thickness cut out from the sapphire single crystal ingot. A sapphire single crystal substrate including a crystal defect portion in which an X-ray diffraction image is obtained by a transmission X-ray corrected with a curvature correction value Δω within a range of ± 0.15 ° with respect to an incident angle ω of the transmission X-ray from which an image is obtained Are sorted out. The sapphire single crystal substrate thus selected has few crystal defects of the sapphire single crystal. Further, the epitaxial formation of the group III compound semiconductor layer is favorably performed on the film formation surface of such a sapphire single crystal substrate. And the semiconductor light-emitting device which has a sapphire single crystal substrate and a group III compound semiconductor layer has favorable light emission performance.

On the other hand, the unselected sapphire wafer is desirably reused as a raw material for obtaining a sapphire single crystal ingot. For example, the weight of a sapphire wafer having a diameter of 100 mm and a thickness of 1 mm is about 30 g / sheet. If such 10 sapphire wafers are reused to obtain a sapphire single crystal ingot, the raw material cost of aluminum oxide can be reduced by about 300 g. The weight of a sapphire wafer having a diameter of 150 mm and a thickness of 1 mm is about 67 g / sheet. In this case, if 10 sapphire wafers are reused to obtain an ingot of a sapphire single crystal, the raw material cost of aluminum oxide can be reduced by about 670 g.
Further, by selecting the sapphire wafer described above, it is possible to eliminate useless processing steps and production of the semiconductor light emitting element, thereby reducing the overall manufacturing cost of the semiconductor light emitting element.

  Hereinafter, the present invention will be described in more detail based on examples. However, the present invention is not limited to the following examples unless it exceeds the gist.

(1) X-ray topography measurement of a sapphire single crystal substrate An 8-inch X-ray was obtained from a sapphire single crystal substrate (sample) having a diameter of 150 mm and a thickness of 1.0 mm that was cut out from an ingot of a sapphire single crystal and then subjected to wet etching. Using topography (RU-H3R, manufactured by Rigaku Corporation), X-ray topography measurement was performed with respect to an incident angle ω of transmitted X-rays from which an X-ray diffraction image of the (11-20) plane of a sapphire single crystal was obtained.
(Measurement condition)
X-ray source: MoKα
First slit width on the X-ray source side: 2.0 mm
Second slit width on the sample side: 1.0 mm
X-ray output: 250V x 300mA
Scanning speed: 1 mm / min Scanning frequency: 50-60 times (continuous scanning)

(2) Measurement of light emitting device characteristics After a semiconductor light emitting device (LC) is die-bonded to a surface-mount package using silicon paste, each electrode is wire-bonded to each terminal of the package with an Au wire, and electrical characteristics and optical properties are measured. Characteristics were measured. Luminous output was measured using an integrating sphere.

(Examples 1-4, Comparative Examples 1-3)
X-ray topography measurement was performed on four types of sapphire single crystal substrates (diameter 150 mm, thickness 1.0 mm: (SC-1) to (SC-4)) shown in Table 1. The measurement is performed by irradiating the vertical axis L2 passing through the center of the disk-shaped sapphire single crystal substrate with X-rays every 10 mm in pitch width in the range of 70 mm (+70 mm) on the plus side and 70 mm (−70 mm) on the minus side. A diffraction X-ray image obtained from the A plane ((11-20) plane) was obtained as the lattice plane of the sapphire single crystal. When the sapphire single crystal includes a crystal defect portion, X-rays are incident on the crystal defect portion, and an X-ray diffraction image of the (11-20) plane of the sapphire single crystal is obtained with respect to the X-ray incident angle (ω). The curvature correction value Δω (unit: °) was measured. The results are shown in Table 1.
Moreover, as a comparative example, three types of sapphire single crystal substrates different from the sapphire single crystal substrates used in Examples 1 to 4 (diameter 150 mm, thickness 1.0 mm: (SCR-1) to (SCR-3)) Also, X-ray topography measurement was performed. The results are shown in Table 1.

(Examples 5-8, Comparative Examples 4-7)
Subsequently, the surface of the sapphire single crystal substrate having a diameter of 6 inches (150 mm) from which the measurement result of the curvature correction value (Δω) shown in Table 1 was obtained was subjected to polishing treatment, and the sapphire single crystal substrate 110 having a thickness of 0.9 mm. Was prepared. Subsequently, as shown in FIG. 5, an intermediate layer 120 made of AlN is formed on the sapphire single crystal substrate 110 by a sputtering method, and a metal organic chemical vapor deposition (MOCVD) method is formed thereon. Thus, a compound semiconductor substrate on which an underlayer 130 made of undoped GaN having a thickness of 8 μm and an n-type contact layer 140a made of Si-doped GaN having a thickness of 2 μm was formed.
Furthermore, after forming an n-type cladding layer 140b made of In _0.1 Ga _0.9 N having a thickness of 250 nm on the compound semiconductor substrate by MOCVD, a barrier layer 150a made of Si-doped GaN having a thickness of 16 nm and a thickness A well layer 150b made of In _0.2 Ga _0.8 N having a thickness of 2.5 nm was stacked five times, and finally a light emitting layer 150 having a multiple quantum well structure in which a barrier layer 150a was provided was formed.

Further, a p-type cladding layer 160a made of Mg-doped Al _0.07 Ga _0.93 N having a thickness of 10 nm and a p-type contact layer 160b made of Mg-doped GaN having a thickness of 150 nm were formed in this order. The gallium nitride-based compound semiconductor layer was laminated by MOCVD under normal conditions well known in the technical field.
Next, a transparent positive electrode 170 made of IZO having a thickness of 250 nm was formed on the p-type contact layer 160b made of GaN. Thereafter, a blue color corresponding to each position of the sapphire single crystal substrate subjected to the usual processing well known in the technical field such as forming a protective film made of SiO ₂ and performing the X-ray topography measurement described above (dominant wavelength = (460 nm) A light emitting device chip was manufactured. The light emitting element chip has a size of 0.35 mm.

Next, the light emission output (unit: mW) of the blue light emitting element chip manufactured by the above-described operation under the condition of 20 mA energization was measured. The measurement of light emission output was made into the average value of the measured value measured about nine adjacent blue light emitting element chips | tips in each position of the sapphire single crystal substrate which performed X-ray topography measurement. The results are shown in Table 2.
For the three types of sapphire single crystal substrates ((SCR-1) to (SCR-3)) used in Comparative Examples 1 to 3, blue light emitting element chips were prepared, and similarly, the light emission output (unit: mW) Was measured. The results are shown in Table 2.

From the results shown in Table 2, in the X-ray topography measurement by the Lang method, the X-ray corrected for the curvature correction value (Δω) within the range of ± 0.1 ° (± 50 mm) and ± 0.15 ° (± 70 mm). It can be seen that the blue light-emitting element chips (Examples 5 to 8) using a sapphire single crystal substrate from which an X-ray diffraction image is obtained show good numerical values with a light emission output of 17 mW or more when energized at 20 mA.
On the other hand, a chip for a blue light emitting device using a sapphire single crystal substrate whose curvature correction value (Δω) exceeds the range of ± 0.1 ° (± 50 mm) and ± 0.15 ° (± 70 mm) at the periphery (comparison) In Examples 4 to 5), it can be seen that there is a low output region in which the light emission output is 15 mW or less in the energization of 20 mA, and the yield decreases.

DESCRIPTION OF SYMBOLS 1 ... X-ray source, 2 ... Divergence slit, 3 ... Restriction slit board, 4 ... Film, 5 ... Sapphire wafer, 6 ... Transmission X-ray, 7 ... Diffraction X-ray, 8 ... Diffraction X-ray image, 30 ... Sapphire ingot, DESCRIPTION OF SYMBOLS 100 ... Group III compound semiconductor layer, 110 ... Sapphire single crystal substrate, 120 ... Intermediate layer, 130 ... Underlayer, 140 ... N-type semiconductor layer, 150 ... Light emitting layer, 160 ... P-type semiconductor layer, 170 ... Transparent positive electrode, 180 ... Positive electrode bonding pad, 190 ... Negative electrode, I ... Single crystal pulling device, LC ... Semiconductor light emitting device

Claims (11)

A method of manufacturing a semiconductor light emitting device having a group III compound semiconductor layer,
A substrate cutting step of cutting a sapphire wafer of a predetermined thickness from a sapphire single crystal ingot;
The X-ray topography measurement by the Lang method is performed on the sapphire wafer cut out in the substrate cutting step, and the X-ray incident angle ω from which an X-ray diffraction image of the (11-20) plane of the sapphire single crystal is obtained is ± 0. A selection step of selecting the sapphire wafer including a crystal defect portion from which an X-ray diffraction image is obtained by an X-ray corrected by a curvature correction value Δω with a range of 15 ° as a determination criterion;
Using the sapphire wafer selected by the selection step as a sapphire substrate, a semiconductor layer film forming step of forming a group III compound semiconductor layer on the film formation surface of the sapphire substrate;
A sapphire single crystal pulling step for reusing the sapphire wafer excluded by the selection step as a raw material for growing an ingot of the sapphire single crystal,
A method for manufacturing a semiconductor light emitting device, comprising:   2. The method of manufacturing a semiconductor light emitting element according to claim 1, wherein in the substrate cutting step, a C plane ((0001) plane) of a sapphire single crystal is cut out from the ingot as the sapphire wafer.   2. The semiconductor layer forming step, wherein an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer are sequentially stacked on the film formation surface of the sapphire substrate from the sapphire substrate side. Or the manufacturing method of the semiconductor light-emitting device of 2.   4. The method according to claim 1, further comprising an intermediate layer forming step of forming an intermediate layer made of a group III compound semiconductor by a sputtering method between the sapphire substrate and the group III compound semiconductor layer. The manufacturing method of the semiconductor light-emitting device of item.   The method for manufacturing a semiconductor light emitting element according to claim 4, further comprising forming an underlayer between the group III compound semiconductor layer and the intermediate layer.   A semiconductor light emitting device manufactured by the method for manufacturing a semiconductor light emitting device according to claim 1. A sapphire single crystal substrate composed of a sapphire single crystal on which a group III compound semiconductor layer is formed on a deposition surface,
In the X-ray topography measurement by the Lang method, the sapphire single crystal has a curvature correction within a range of ± 0.15 ° with respect to an X-ray incident angle ω from which an X-ray diffraction image of the lattice plane of the sapphire single crystal is obtained. A sapphire single crystal substrate comprising a crystal defect portion from which an X-ray diffraction image is obtained by X-rays corrected with a value Δω.   The sapphire single crystal substrate according to claim 7, which has a diameter of 100 mm or more.   The sapphire single crystal substrate according to claim 7 or 8, comprising a sapphire wafer obtained by cutting out a C-plane of a sapphire single crystal from an ingot.   The sapphire single crystal substrate according to any one of claims 7 to 9, wherein the lattice plane of the sapphire single crystal is an A plane ((11-20) plane).   The sapphire single crystal substrate according to any one of claims 7 to 10, wherein the diameter is 150 mm or more, the thickness is 0.8 mm or more, and the curvature correction value Δω is within ± 0.15 ° for the entire substrate.

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