JP2012028969A - Data transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transmission system that detects transmission errors with much simplified process.SOLUTION: A transmission processing part 13 in an audio source device 1 generates and transmits 32-bit length transmission data TD32(N) of which all of low-order 16-bit values are set as 0, a value of the 17th low-order bit is set as 1, and remaining bits are set as 15 bits from the second low-order bit to the 16th low-order bit of the audio data D16(N)(a). The reception processing part 32 in an audio sync device 3 receives each bit of transmission data SD by a clock signal synchronized with a bit clock SCLK on the bus 2, monitors bit values from the first low-order bit to the 17th low-order bit of the received data RD32 which is converted from each received bit to a word, and detects a transmission error if all of the bits from the first low-order bit to the 16th low-order bit are not equal to zero or if the 17th low-order bit value is not equal to one.

Description

  The present invention relates to a technique for detecting the occurrence of a transmission error in a data transmission system for transmitting data.

  In a data transmission system that transmits data, the technology for detecting the occurrence of transmission errors is to transmit data with error detection codes such as checksum codes and parity bits on the transmission side, and to detect errors on the reception side. A technique for detecting the occurrence of a data transmission error based on a code for use is known (for example, Patent Document 1).

JP 2000-31927 A

  According to the technique for detecting the occurrence of a transmission error using the error detection code such as the checksum code and the parity bit described above, the arithmetic processing for generating the error detection code such as the checksum code and the parity bit In addition, special arithmetic processing such as arithmetic processing for data verification using an error detection code is required.

  Therefore, an object of the present invention is to make it possible to detect the occurrence of a transmission error, in particular, a missing bit reception or a multiple reception of a bit due to a transmission error of a transmission clock, with simpler processing.

  In order to achieve the above object, according to the present invention, the value of the least significant bit of the N-bit first data to be transferred is transmitted to the transmission device of the transmission system that transfers N-bit data from the transmission device to the reception device. , By concatenating M bits to the lower side of the second data set to the first predetermined value which is one of 0 and 1, the N-bit first data is converted into N + M bits. A data conversion unit for converting the third data into a third data, and a transmission unit for transmitting the N + M-bit third data converted by the data conversion unit by serial transmission. The reception device includes: A receiving unit that receives the N + M-bit third data transmitted by serial transmission, and data that includes the upper N bits of the N + M-bit third data received by the receiving unit. N-bit data transferred from And a data recovery unit that extracts the transmission error and a transmission error detection unit that detects a transmission error. Here, the data conversion unit of the transmission device sets the value of each of the M bits to a second predetermined value that is a value of 0 and 1 that is not the first predetermined value. The transmission error detecting unit of the receiving device, when the values of all the lower M bits in the N + M bit third data received by the receiving unit are not the second predetermined value, The transmission error occurs in one or both of the cases where the value of the upper N-th bit in the N + M-bit third data received by the receiving unit is not the first predetermined value. Is detected.

  In order to achieve the above object, according to the present invention, in the transmission system for transferring N-bit data from the transmission device to the reception device, the N-bit first data to be transferred is transferred to the transmission device. A data conversion unit that converts M bits into N + M bit second data concatenated on the lower side of the first data of bits, and serially converts the N + M bit second data converted by the data conversion unit A transmission unit that transmits by transmission, and the reception device receives the N + M bit second data transmitted by serial transmission from the transmission device, and the N received by the reception unit. A data restoration unit that extracts data consisting of upper N bits of second data of + M bits as N-bit data transferred from the transmission device, and a transmission error detection unit that detects a transmission error Is . Here, the data conversion unit of the transmission device sets the bit value of one or more predetermined bit positions in the M bits to a first predetermined value that is one of 0 and 1 values. And the value of each bit excluding the bit at the predetermined bit position in the M bits is set to a second predetermined value which is a value of 0 and 1 which is not the first predetermined value. In addition, the transmission error detection unit of the receiving device may be configured such that the value of the bit at the predetermined bit position in the lower M bits in the N + M bit second data received by the receiving unit is the first predetermined value. If not, the transmission error is detected.

  In such a data transmission system, M is a number equal to or greater than 3, and the data conversion unit of the transmission apparatus uses one of the K bits (where 1 <K <M) in the M bits. The value is set to be a first predetermined value that is one of 0 and 1, and the value of each bit excluding the Kth bit in the M bits is set to 0 or 1 The second predetermined value which is the value which is not the first predetermined value is set, and in the transmission error detecting unit of the receiving apparatus, the lower order in the N + M bit second data received by the receiving unit The transmission error may be detected when the value of the Kth bit in the M bits is not the first predetermined value.

  According to the above data transmission system, by utilizing the fact that the bit position of the bit in the N + M bit data received by the receiving device shifts due to the multiple reception or reception omission of the bits, Detects transmission errors due to missing reception. Therefore, transmission is performed by simple processing that does not require arithmetic processing for generating error detection codes such as checksum codes and parity bits, and arithmetic processing for data verification using error detection codes. An error can be detected.

  In each transmission system described above, the N-bit first data may be audio data, for example.

  As described above, according to the present invention, the occurrence of a transmission error can be detected with simpler processing.

It is a block diagram which shows the structure of the audio system which concerns on embodiment of this invention. It is a figure which shows the transmission error detection operation | movement which concerns on embodiment of this invention. It is a figure which shows the transmission error detection operation | movement which concerns on embodiment of this invention. It is a figure which shows the transmission error detection operation | movement which concerns on embodiment of this invention.

Hereinafter, embodiments of the present invention will be described by taking the application to an audio system as an example.
FIG. 1 shows the configuration of an audio system according to this embodiment.
As shown in the figure, the audio system includes an audio source device 1 that distributes audio data via a bus 2 and an audio sink device 3 that receives audio data from the audio source device 1 via a bus 2.
Then, the audio source device 1 reads out the audio data from the storage device 11 storing the audio data, and performs a sound process such as a predetermined equalizer process on the read-out audio data, and has a 16-bit length after the sound process. An audio data processing unit 12 that generates audio data D16, a transmission processing unit 13, and a source bus controller 14 that controls transmission and reception of data via the bus 2 are provided. Here, the transmission processing unit 13 performs a conversion process for converting the 16-bit audio data D16 generated by the audio data processing unit 12 into 32-bit transmission data TD32, and the converted 32-bit transmission data TD32 after conversion. Is supplied to the source bus controller 14, and the source bus controller 14 is sent to the audio sink device 3.

  Next, the audio sink device 3 includes a sync bus controller 31 that controls transmission / reception of data via the bus 2, and the received data RD 32 having a 32-bit length received from the audio source device 1 by the sync bus controller 31. The reception processing unit 32 that converts to the data RD16, the amplification processing of the 16-bit audio data RD16 converted by the reception processing unit 32, and the like are performed, and then the audio represented by the audio stream of the 16-bit audio data RD16 is sent to the speaker 34. And an audio data output unit 33 for outputting.

  Here, the 16-bit audio data D16 generated by the audio data processor 12 performed by the transmission processor 13 of the audio source device 1 is converted into 32-bit transmission data TD32, and the 32-bit length on the bus 2 is set. The details of the transmission sequence of the transmission data TD32 and the conversion of the 32-bit reception data RD32 received by the sync bus controller 31 performed by the reception processing unit 32 of the audio sink device 3 into the 16-bit audio data RD16 will be described. .

First, the conversion of 16-bit audio data D16 generated by the audio data processor 12 performed by the transmission processor 13 of the audio source device 1 into transmission data TD32 having a 32-bit length will be described.
The transmission processing unit 13 of the audio source device 1 converts the 16-bit audio data D16 (N) generated by the audio data processing unit 12 shown in FIG. 2a into the 32-bit transmission data TD32 (N) shown in FIG. 2b. Convert. Note that (N) represents the Nth audio data in the audio stream.

  Now, as shown in FIG. 2b, in this conversion, the lower 16 bits of the transmission data TD32 (N) having a 32-bit length are all set to 0, and the lower 17th bit is set to 1. Then, 15 bits from the lower 18th bit to the 32nd bit of the transmission data TD32 (N) having a 32-bit length are changed to 15 bits from the lower 2nd bit to the lower 16th bit of the 16-bit audio data D16 (N) shown in FIG. The 15 bits up to the bit are stored from the lower order.

Next, a transmission sequence of transmission data TD32 having a 32-bit length on the bus 2 is shown in FIG.
This transmission sequence is in accordance with the I2S bus standard. As shown in the figure, the source bus controller 14 sequentially transmits each of the 32-bit transmission data TD32 as transmission data SD in the order in the audio stream. In transmission of each transmission data TD32, each bit of the transmission data TD32 is serially transmitted. The source bus controller 14 also outputs on the bus 2 a bit clock SCLK synchronized with each bit of the transmission data SD and a word select WS synchronized with each transmission data TD32 in the transmission data SD.

Next, conversion of the reception data RD32 having a 32-bit length received by the sync bus controller 31 performed by the reception processing unit 32 of the audio sink device 3 into the audio data RD16 having a 16-bit length will be described.
The sync bus controller 31 receives each bit of the transmission data SD with a clock synchronized with the bit clock SCLK on the bus 2, converts the received bits into words according to the word select WS, and receives the 32-bit length received data shown in FIG. 2d. RD32 is generated.
Then, as shown in FIG. 2e, the reception processing unit 32 of the audio sink device 3 converts the 16 bits from the lower 17th bit to the 32nd bit of the reception processing unit 32 of the audio sink device 3 into the lower 1 bit in this order. The 16-bit data having 16 bits from the first to the lower 16 bits is referred to as audio data RD16.

  As can be seen from a comparison between FIG. 2a and FIG. 2e, the 16-bit audio data D16 (N) generated by the audio data processing unit 12 of the audio source device 1 and the reception processing unit 32 of the audio sink device 3 are This differs from the generated 16-bit audio data RD16 (N) in that the least significant bit of the 16-bit audio data RD16 (N) is fixedly set to 1.

However, in 16-bit audio data, the difference in audio output from the speaker 34 based on the audio data due to the difference in the least significant bit is different from the level that human hearing cannot perceive. Does not occur.
Hereinafter, a transmission error detection operation performed in such a configuration will be described.
The reception processing unit 32 of the audio sink device 3 receives each bit of the transmission data SD with a clock synchronized with the bit clock SCLK on the bus 2, and receives the received data RD32 of the received data RD32 obtained by wording according to the word select WS. Monitors the values of the lower 1st bit to the 16th bit and the lower 17th bit, and transmits when all the bits of the lower 1st bit to the 16th bit are not 0 and when the value of the lower 17th bit is not 1. Detect errors.

  Here, as shown in FIG. 3a, since the 16-bit values of the lower 1st bit to the 16th bit of the transmission data TD32 are all set to 0 by the transmission processing unit 13 of the audio source device 1, the reception processing unit When the transmission data TD32 can be correctly received at 32, the 16-bit value from the lower 1st bit to the 16th bit (Rb0-15) of the reception data RD32 is always 0. Further, since the lower 17th bit (Rb16) of the transmission data TD32 is set to 1 by the transmission processing unit 13 of the audio source device 1, when the transmission data TD32 can be correctly received by the reception processing unit 32, The value of the lower 17th bit of the reception data RD32 is always 1.

  On the other hand, when the bit clock SCLK cannot be correctly received by the sync bus controller 31 due to waveform distortion of the bit clock SCLK on the bus 2 and the bit is multiplexed and received by the clock synchronized with the bit clock SCLK. Therefore, the bits on the lower side of the multiple received bits are shifted to the lower side.

  That is, for example, when b5 of the lower 22 bits of the transmission data TD32 (N) is multiplexed and received twice, as shown in FIG. 3b, the lower 22 bits of the transmission data TD32 (N) are lower. The bit position of each bit of the received data RD32 (N) is a position shifted one bit lower than the bit position in the transmission data TD32 (N).

  Further, for example, when the b27 of the lower 27 bits of the transmission data TD32 (N) and the b3 of the lower 20 bits of the transmission data TD32 (N) are respectively received twice, FIG. As shown in the figure, the bit position in the reception data RD32 (N) of each bit lower than the lower 20th bit of the transmission data TD32 (N) is lower than the bit position in the transmission data TD32 (N). The position is shifted one by one.

  Then, when multiple reception of 16 bits or less occurs with respect to the bits higher than the lower 17th bit of the transmission data TD32 (N), the lower order of the transmission data TD32 (N) as shown in FIGS. 3b and 3c. The 17th bit having a value of 1 is shifted to any of the bits between the lower 1st bit and the 16th bit (Rb0-15) of the received data RD32 (N).

Therefore, by detecting a transmission error when all of the lower 1st bit to the 16th bit of the reception data RD32 are not 0, a multiplex reception that has occurred with respect to the upper bits of the lower 17th bit of the transmission data TD32 is detected as a transmission error. Can be detected as
Note that multiplex reception of bits lower than the lower 16th bit of the transmission data TD32 does not affect the audio data RD16, so that no trouble occurs even if a transmission error in that portion cannot be detected.
Next, because of the waveform distortion of the bit clock SCLK on the bus 2, the bit clock SCLK cannot be correctly received by the sync bus controller 31, and a bit synchronization failure occurs due to the clock synchronized with the bit clock SCLK. When this occurs, the lower bits of the lost bits are shifted upward.

  That is, for example, when reception loss of b7 of the lower 24 bits of transmission data TD32 (N) occurs, each bit lower than the lower 24 bits of transmission data TD32 (N) as shown in FIG. The bit position in the reception data RD32 (N) is a position shifted one by one to the upper side of the bit position in the transmission data TD32 (N).

  When reception loss of 16 bits or less occurs in the upper bits of the lower 17 bits or more of the transmission data TD32 (N) as described above, as shown in FIG. 3d, the lower 17 of the reception data RD32 (N). As the bit of the bit (Rb17), one of the bits having the value 0 between the lower 1st bit and the 16th bit of the transmission data TD32 (N) is shifted and appears.

Accordingly, by detecting a transmission error when the lower 17th bit of the reception data RD32 is not 1, a reception omission that occurs for the upper 17 bits or more of the lower 17th bit of the transmission data TD32 can be detected as a transmission error. it can.
Note that even when multiple reception of bits occurs, the lower 17th bit of the reception data RD32 may not be 1, but in any case, it is still a transmission error. Further, missing reception of bits lower than the lower 17th bit of the transmission data TD32 does not affect the audio data RD16. Therefore, no trouble occurs even if a transmission error in this portion cannot be detected.
The embodiment of the present invention has been described above.
By the way, in the above embodiment, in the transmission processing unit 13 of the audio source device 1, as the transmission data TD32 (N) having a 32-bit length, all the lower 16-bit values are set to 0 and the lower 17-bit bit value is set. The transmission error is detected by generating and transmitting data in which the remaining bits are 15 bits from the lower 2nd bit to the lower 16th bit of the audio data D16 (N). A transmission error may be detected as follows.

That is, the transmission processing unit 13 of the audio source device 1 converts the 16-bit audio data D16 (N) generated by the audio data processing unit 12 into 32-bit transmission data TD32 (N) in FIG. 4a. Do as shown.
As shown in the figure, in this conversion, the transmission data TD32 (N) having a length of 32 bits, 8 bits from the lower 1st bit to the lower 8th bit, 7 bits from the lower 10th bit to the 16th bit, All 15 bits are set to 0, and the lower 9 bits are set to 1. Then, the 16 bits from the lower 17th bit to the 32nd bit of the transmission data TD32 (N) of 32 bit length are changed to the lower 1st bit to the lower 16th bit of the audio data D16 (N) of 16 bit length. 15 bits are stored from the lower order.

  Then, the reception processing unit 32 of the audio sink device 3 receives each bit of the transmission data SD with a clock synchronized with the bit clock SCLK on the bus 2, and receives the received data RD32 obtained by wording each received bit according to the word select WS. A transmission error is detected when the value of the lower 9 bits is not 1.

  Here, as shown in FIG. 4b, since the lower 9 bits of the transmission data TD32 are set to 1 by the transmission processing unit 13 of the audio source device 1, the reception processing unit 32 correctly sets the transmission data TD32 (N). When reception is possible, the value of the lower 9th bit (Rb8) of the reception data RD32 (N) is always 1.

  On the other hand, when the bit clock SCLK cannot be correctly received by the sync bus controller 31 due to waveform distortion of the bit clock SCLK on the bus 2 and the bit is multiplexed and received by the clock synchronized with the bit clock SCLK. Therefore, the bits on the lower side of the multiple received bits are shifted to the lower side.

  That is, for example, when b5 of the lower 22 bits of the transmission data TD32 (N) is multiplexed and received twice, as shown in FIG. 4c, the lower 22 bits of the transmission data TD32 (N) are lower. The bit position of each bit in the received data RD32 is shifted one by one to the lower side of the bit position in the transmission data TD32 (N).

  Also, because of the waveform distortion of the bit clock SCLK on the bus 2, the bit clock SCLK cannot be correctly received by the sync bus controller 31, and a bit is lost due to the clock synchronized with the bit clock SCLK. In some cases, the lower bits of the missing bits are shifted upward.

  That is, for example, when reception loss of b7 of the lower 24 bits of transmission data TD32 (N) occurs, as shown in FIG. 4d, each bit lower than the lower 24 bits of transmission data TD32 (N) The bit position in the reception data RD32 (N) is a position shifted one by one to the upper side of the bit position in the transmission data TD32 (N).

  In this way, when multiple reception of 7 bits or less or reception loss of 8 bits or less occurs in the upper 9 bits or more of the transmission data TD32, reception data as shown in FIGS. The lower 9th bit (Rb8) of RD32 has a value 0 between the lower 10th bit and the 16th bit of transmission data TD32, or a value 0 between the lower 1st bit and the 8th bit. Any of the bits will appear shifted.

Therefore, when the transmission data is detected when the lower 9th bit of the reception data RD32 (N) is not 1, a reception omission that has occurred with respect to the upper 10th bit or more of the transmission data TD32 (N). Or multiple reception can be detected as a transmission error.
Note that multiplex reception and reception omission of bits lower than the lower 10th bit of the transmission data TD32 do not affect the audio data RD16, so that no trouble occurs even if a transmission error in that portion cannot be detected.
In FIG. 4, the lower 16-bit bit pattern of the transmission data TD32 is a bit pattern in which only the lower 9th bit is 1, but there are various bits as the lower 16-bit bit pattern of the transmission data TD32. A pattern can be used. For example, as the lower 16-bit bit pattern of the transmission data TD32, a bit pattern in which only the lower 8 bits are set to 1, or a bit pattern in which both the lower 8 bits and 9 bits are set to 1 can be used. .

In any case, the reception processing unit 32 of the reception apparatus detects a shift of the lower 16-bit bit pattern of the reception data RD32 (N) from the lower 16-bit bit pattern of the transmission data TD32 (N) as a transmission error. To do.
As described above, according to the present embodiment, the bit position of the bit in the reception data RD32 (N) received by the audio sink device 3 due to the multiple reception or reception failure of the bit is the transmission data TD32 (N). By using the shift from the bit position, a multiplex reception of these bits and a transmission error due to reception failure are detected. Therefore, transmission is performed by simple processing that does not require arithmetic processing for generating error detection codes such as checksum codes and parity bits, and arithmetic processing for data verification using error detection codes. An error can be detected.

  Here, the configuration of the audio source device 1 and the audio sink device 3 in the above embodiment is configured to include a computer, and an application or a source / sink bus controller driver realized by executing a computer program on the computer is used as an audio. The transmission processing unit 13 of the source device 1 and the reception processing unit 32 of the audio sink device 3 may be provided.

In addition, the operation of the transmission processing unit 13 of the audio source device 1 and the operation of the reception processing unit 32 of the audio sink device 3 in the above embodiment are configured to be performed in the source bus controller 14 and the sync bus controller 31. May be.
Further, the transmission error detection technique shown in FIG. 3 of the present embodiment can be similarly applied to arbitrary data whose least significant bits other than audio data are not practically significant. Further, the transmission error detection technique shown in FIG. 4 of the present embodiment can be similarly applied to arbitrary data other than audio data.

  DESCRIPTION OF SYMBOLS 1 ... Audio source device, 2 ... Bus, 3 ... Audio sink device, 11 ... Storage device, 12 ... Audio data processing part, 13 ... Transmission processing part, 14 ... Source bus controller, 31 ... Sink bus controller, 32 ... Reception process Unit 33, audio data output unit 34, speaker.

Claims (6)

A transmission system for transferring N-bit data from a transmission device to a reception device,
The transmitter is
M bits are set on the lower side of the second data in which the value of the least significant bit of the N-bit first data to be transferred is set to the first predetermined value which is one of 0 and 1 A data converter for converting the N-bit first data into N + M-bit third data by concatenation;
A transmission unit that transmits N + M-bit third data converted by the data conversion unit by serial transmission;
The receiving device is:
A receiver that receives the N + M-bit third data transmitted by serial transmission from the transmitter;
A data restoration unit that extracts data composed of upper N bits of the N + M-bit third data received by the reception unit as N-bit data transferred from the transmission device;
A transmission error detection unit for detecting a transmission error;
The data converter of the transmitting device sets the value of each of the M bits to a second predetermined value that is a value that is not the first predetermined value of 0 and 1,
The transmission error detection unit of the receiving device receives the transmission error when the values of all the lower M bits in the N + M bit third data received by the receiving unit are not the second predetermined value. A data transmission system characterized by detecting the above. The data transmission system according to claim 1, wherein
The transmission error detection unit of the receiving device reports the transmission error when the value of the upper N-bit bit in the N + M-bit third data received by the receiving unit is not the first predetermined value. A data transmission system characterized by detecting. A transmission system for transferring N-bit data from a transmission device to a reception device,
The transmitter is
M bits are set on the lower side of the second data in which the value of the least significant bit of the N-bit first data to be transferred is set to the first predetermined value which is one of 0 and 1 A data converter for converting the N-bit first data into N + M-bit third data by concatenation;
A transmission unit that transmits N + M-bit third data converted by the data conversion unit by serial transmission;
The receiving device is:
A receiver that receives the N + M-bit third data transmitted by serial transmission from the transmitter;
A data restoration unit for extracting data consisting of upper N bits of the third data of the N + M bits received by the reception unit as N-bit data transferred from the transmission device;
A transmission error detection unit for detecting a transmission error;
The data converter of the transmitting device sets the value of each of the M bits to a second predetermined value that is a value that is not the first predetermined value of 0 and 1,
The transmission error detection unit of the receiving device reports the transmission error when the value of the upper N-bit bit in the N + M-bit third data received by the receiving unit is not the first predetermined value. A data transmission system characterized by detecting. A transmission system for transferring N-bit data from a transmission device to a reception device,
The transmitter is
A data converter that converts the N-bit first data to be transferred into N + M-bit second data in which M bits are connected to the lower side of the N-bit first data;
A transmission unit that transmits N + M bit second data converted by the data conversion unit by serial transmission;
The receiving device is:
A receiver for receiving the second data of N + M bits transmitted by serial transmission from the transmitter;
A data restoration unit that extracts data composed of upper N bits of the N + M-bit second data received by the reception unit as N-bit data transferred from the transmission device;
A transmission error detection unit for detecting a transmission error;
The data converter of the transmitting device sets the value of the bit at one or more predetermined bit positions in the M bits to be a first predetermined value that is one of 0 and 1, A value of each bit excluding the bit at the predetermined bit position in the M bits is set to a second predetermined value which is a value of 0 or 1 which is not the first predetermined value;
The transmission error detection unit of the receiving device is configured such that all of the bit values at the predetermined bit positions in the lower M bits in the N + M-bit second data received by the receiving unit are the first predetermined value. If not, the data transmission system detects the transmission error. The data transmission system according to claim 4, wherein
M is a number of 3 or more;
The data conversion unit of the transmission apparatus sets the value of one bit of K (where 1 <K <M) in the M bits to a first predetermined value that is one of 0 and 1 And the value of each bit excluding the Kth bit in the M bits is set to a second predetermined value that is a value of 0 or 1 that is not the first predetermined value. ,
The transmission error detection unit of the receiving device, when the value of the Kth bit in the lower M bits in the N + M bit second data received by the receiving unit is not the first predetermined value, A data transmission system for detecting the transmission error. The data transmission system according to claim 1, 2, 3, 4 or 5,
The data transmission system, wherein the N-bit first data is audio data.