WO2024095739A1

WO2024095739A1 - Reception device

Info

Publication number: WO2024095739A1
Application number: PCT/JP2023/037287
Authority: WO
Inventors: 峻井手口; 落合　一夫; 雄介村田
Original assignee: ザインエレクトロニクス株式会社
Priority date: 2022-10-31
Filing date: 2023-10-13
Publication date: 2024-05-10
Also published as: JP2024065771A

Abstract

This reception device comprises: a special code detection circuit 2 which outputs a first correction value DET-COM; a byte alignment circuit 3 which performs byte alignment according to the first correction value DET-COM outputted from the special code detection circuit 2; and a decoder 4. The decoder 4 comprises a data string generation circuit 41 which generates a plurality of data strings from an output signal from the byte alignment circuit 3, and a correction value generation circuit 43 to which a plurality of error signals that have performed error determination of the plurality of data strings outputted from the data string generation circuit 41 are inputted, and which generates a second correction value θK including information relating to a data string in which no error occurs. Even before the reception of a special code, byte alignment can be performed according to the second correction value θK.

Description

Receiving device

The present invention relates to a receiving device.

In environments with a lot of external noise, such as inside a car, there is a demand for data communication technology that can improve electromagnetic compatibility (EMC). In particular, as equipment becomes more sophisticated, data communication volume is increasing, and there is a demand for receiving devices that can receive data signals, such as image data signals, at high speeds in EMC environments.

Serial data communication is used to transmit data at high speeds. Conventionally, serial data communication techniques such as those described in Patent Document 1 are known, and data is received using control codes. In general, control codes (K codes) are used as codes that indicate data that is different from the code (D code) related to the image data itself.

The symbol mapping method is a type of transmission coding method, and is a coding method in which m-bit data characters are mapped to n (m<n) bits to create a coding symbol. By taking advantage of the redundancy created by this m-bit to n-bit expansion mapping, a control code that is not a code representing data can be generated. Among the control codes, the delimiter symbol that indicates the beginning of serial data, for example, the comma character in the 8b/10b method, is called a special code. That is, in the 8b10b coding method, which is one of the symbol mapping methods, comma characters (K28.1, K28.5, K28.7) are known as special codes. In this method, the image data receiving device receives the special code periodically (for example, at a rate of about one pixel per line included in one image). When the image data receiving device receives the special code, it performs byte alignment (byte boundary alignment) on the received image data signal. Patent Document 2 discloses a method of performing byte alignment.

International Publication No. 2012/049815 U.S. Pat. No. 8,867,683

When a conventional home image data receiving device is used in an environment with a lot of external noise, the image may become distorted. If one piece of data contained in a serial data signal is lost due to the effects of noise, an error occurs in which the position (timing) that divides the blocks of the subsequent data string (e.g. 10 bits) deviates from the normal value, causing a distorted image. The lower the frequency of occurrence of the special code, the more the actual amount of image data that can be received per unit time can be increased, so it is preferable for the special code to appear less frequently. However, if byte alignment is performed in conjunction with the reception of the special code, it takes a long time to return to a normal data signal (image) after an error occurs. Therefore, a receiving device that can quickly return to a normal data signal is desired.

The first receiving device includes a special code detection circuit that receives a data signal that includes a special code encoded by a symbol mapping method and outputs a first correction value that corresponds to the position of the special code included in the data signal; a byte alignment circuit that receives the first and second correction values and performs byte alignment of the data signal according to the first and second correction values; a data string generation circuit that generates a plurality of data strings having different delimiter positions in the data string from the output signal of the byte alignment circuit; a decoder that decodes and outputs a specific data string from the plurality of data strings output from the data string generation circuit and performs an error determination for the specific data string; a plurality of error detectors that perform an error determination for each of the remaining data strings other than the specific data string from the plurality of data strings output from the data string generation circuit; and a correction value generation circuit that receives a plurality of error signals indicating the results of the error determination output from the decoder and the plurality of error detectors and generates the second correction value including information on a data string without an error according to the plurality of error signals input.

In this receiving device, the first correction value corresponds to the position of the special code indicating normal timing, and when the first correction value is received, the byte alignment circuit performs byte alignment. The second correction value has information on an error-free data string based on multiple error signals. If an error occurs before the reception of the special code due to external noise or the like, byte alignment of the data signal is performed according to the second correction value generated by the correction value generation circuit. This allows for an early return to a normal data signal even before the reception of the special code. If the data signal is an image data signal, image distortion can be eliminated early. This receiving device controls by feeding back the second correction value generated by the correction value generation circuit to the byte alignment circuit in the previous stage, and does not require many circuits, so it can be realized with a relatively small circuit scale.

The second receiving device includes a special code detection circuit that receives a data signal containing a special code encoded by a symbol mapping method and outputs a first correction value corresponding to the position of the special code contained in the data signal, a byte alignment circuit that performs byte alignment of the data signal according to the first correction value output from the special code detection circuit, a data string generation circuit that generates multiple data strings having different delimiter positions in the data string from the output signal of the byte alignment circuit, multiple decoders that decode each of the multiple data strings output from the data string generation circuit and perform error judgment on each of them, a correction value generation circuit that receives multiple error signals indicating the results of the error judgment output from the multiple decoders and generates a second correction value including information on a data string without errors according to the multiple error signals input, and a selection circuit that selects and outputs a data string corresponding to the second correction value from the multiple data strings output from the multiple decoders.

In this receiving device, the first correction value corresponds to the position of the special code indicating normal timing, and when the first correction value is received, the byte alignment circuit performs byte alignment. The second correction value has information about an error-free data string based on multiple error signals. If an error occurs before the special code is received due to external noise or the like, the selection circuit selects and outputs a data string without byte alignment deviation according to the second correction value generated by the correction value generation circuit. This allows for an early return to a normal data signal even before the special code is received. If the data signal is an image data signal, image distortion can be eliminated early.

In the second receiving device, multiple decoders are prepared in advance. A normal data signal is a data signal that is output by separating a data string at the position of a normal block, and an error data signal is a data signal that is output by separating a data string at the position of a block where an error occurs. Normal data signals and groups of error data signals can be output from the multiple decoders. This receiving device performs byte alignment of the data signal by selecting a normal data signal using the second correction value. Since this receiving device does not require feedback of the second correction value to the byte alignment circuit, the circuit structure is simple and has excellent maintainability and robustness.

In addition, in the second receiving device, the byte alignment circuit outputs a notification signal that byte alignment has been completed, and when the notification signal is input to the correction value generation circuit, the selection circuit selects and outputs a data string from the decoder with the default settings among the decoders. Even if there is no change in the second correction value, the correction value generation circuit receives the first correction value, and the selection circuit can output a data string with correct divisions.

The third receiving device includes a special code detection circuit that receives a data signal that includes a special code encoded by a symbol mapping method and outputs a first correction value that corresponds to the position of the special code included in the data signal; a data string generation circuit that generates a plurality of data strings from the data signal, the data strings having different delimiter positions; a plurality of decoders that decode each of the plurality of data strings output from the data string generation circuit and perform an error determination for each of the plurality of data strings; a correction value generation circuit that receives a plurality of error signals that indicate the results of the error determination output from the plurality of decoders and generates a second correction value that includes information about a data string that does not include an error in accordance with the plurality of error signals that have been input; and a byte alignment circuit that selects and outputs a data string that corresponds to the first correction value and the second correction value from the plurality of data strings output from the plurality of decoders.

In this receiving device, the first correction value corresponds to the position of the special code indicating normal timing. The second correction value has information on an error-free data string based on multiple error signals. The byte alignment circuit selects and outputs a data string corresponding to the first and second correction values from the multiple data strings output from the multiple decoders. If an error occurs before the reception of the special code due to external noise or the like, the byte alignment circuit selects and outputs a data string without byte alignment deviation according to the second correction value generated by the correction value generation circuit. This makes it possible to quickly return to a normal data signal even before the reception of the special code. If the data signal is an image data signal, image distortion can be quickly eliminated. This receiving device can achieve early recovery from byte alignment deviation with a simple configuration.

The above-mentioned receiving device includes a deserializer that receives a serial data signal transmitted from a transmitting device, converts it into a parallel data signal, and inputs it as the data signal to the special code detection circuit. The deserializer can convert the serial data signal into a parallel data signal.

The receiving device of the present invention can quickly restore a normal data signal even if an error occurs in the data signal.

FIG. 1 is a diagram showing a circuit configuration of a transmission/reception system including a first receiving device. FIG. 2 is a diagram showing the circuit configuration of the special code detection circuit. FIG. 3 is a diagram showing the data string generating circuit and the special code detecting circuit. FIG. 4 is a diagram illustrating an example of a data string generating circuit. FIG. 5 is a diagram showing a first type of byte alignment circuit. FIG. 6 is a diagram showing a circuit configuration of a decoder with a correction value generating function. FIG. 7 is a flow chart for explaining a procedure for correcting the phase of an image data signal in the first receiving device. FIG. 8 is a diagram for explaining the timing of byte alignment. FIG. 9 is a diagram for explaining the states of a plurality of error signals. FIG. 10 is a diagram showing a circuit configuration of a transmission/reception system including a second receiving device. FIG. 11 is a diagram showing a second type of byte alignment circuit. FIG. 12 is a diagram showing a circuit configuration of a decoder with a correction value generating function. FIG. 13 is a flow chart for explaining a procedure for correcting the phase of an image data signal in the second receiving device. FIG. 14 is a diagram for explaining the states of a plurality of error signals. FIG. 15 is a timing chart for explaining an example of timing of data transmission and reception in the first receiving device. FIG. 16 is a timing chart for explaining an example of timing of data transmission and reception in the second receiving device. FIG. 17 is a diagram showing a circuit configuration of a transmission/reception system including a third receiving device. FIG. 18 is a diagram showing a circuit configuration of a decoder with a correction value generating function. FIG. 19 is a diagram showing a third type of byte alignment circuit. FIG. 20 is a diagram showing the circuit configuration of a transmission/reception system equipped with the improved first receiving device. FIG. 21 is a diagram showing the circuit configuration of a transmission/reception system equipped with an improved second receiving device. FIG. 22 is a diagram showing the circuit configuration of a transmitting/receiving system equipped with an improved third receiving device.

Below, the embodiments for carrying out the present invention will be described in detail with reference to the attached drawings. In the description of the drawings, the same elements are given the same reference numerals, and duplicate explanations will be omitted. The present invention is not limited to these examples, but is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

FIG. 1 shows the circuit configuration of a transmission/reception system equipped with a first receiving device.

The transmission/reception system includes a transmitting device TX and a receiving device RX.

The transmitting device TX includes an encoder 201 and a serializer 202. The encoder 201 receives a parallel data signal DATA-P (IN) as an image data signal, and also receives a signal FLAG-K (IN) corresponding to a control code (K code in 8b10b). This signal FLAG-K can also function as an identifier of the type of data. The encoder 201 performs encoding using a symbol mapping method. In this example, an 8-bit parallel data signal is input to the encoder 201, and the encoder 201 is an 8b10b encoder. The encoder 201 outputs an encoded 10-bit parallel data signal DATA-P (EE). The parallel data signal DATA-P (EE) is input to the serializer 202. The serializer 202 converts the parallel data signal DATA-P (EE) into an encoded serial data signal DATA-S (E) and outputs it to the transmission line. The encoded serial data signal DATA-S(E) is transmitted from the transmitter TX and received by the receiver RX via the transmission line.

The receiving device RX includes a deserializer 1, a special code detection circuit 2, a byte alignment circuit 3, and a decoder 4 with a correction value generation function.

The deserializer 1 converts the received serial data signal DATA-S (E) into a 10-bit parallel data signal DATA-P (E*). When converting a serial data signal into a parallel data signal, continuous serial data is divided at equal intervals to generate blocks of data strings. The deserializer 1 divides the continuous serial data every 10 bits and outputs a temporary parallel data signal DATA-P (E*). In this way, the receiving device RX is equipped with a deserializer 1 that receives a data signal from the transmitting device TX as a serial data signal, converts it into a parallel data signal, and inputs this parallel data signal to the special code detection circuit 2 and the byte alignment circuit 3. The deserializer 1 can convert serial data signals into parallel data signals.

The special code detection circuit 2 receives the parallel data signal DATA-P (E*). The special code detection circuit 2 generates multiple data strings (for example, 10 data strings) from the parallel data signal DATA-P (E*) by shifting each bit, and compares each data string with a string of special codes (comma characters). If the special code detection circuit 2 detects a data string that matches a special code, it outputs a first correction value DET-COM that contains information on the position (timing) of the special code. The first correction value DET-COM is used to correct the delimiter position (phase) of the aforementioned data. For example, when multiple data strings are generated, the first correction value DET-COM contains information on the position of the data string in which the special code was detected (the Xth data string).

The parallel data signal DATA-P (E*) is input to the byte alignment circuit 3. The byte alignment circuit 3 performs correction of the delimitation position of the provisional parallel data signal DATA-P (E*) according to the first correction value DET-COM, i.e., byte alignment. In the image data signal, the special code is embedded at the start and end of the blanking period, and the reception of the actual image data starts from the bit next to the time (t0) when the special code at the end is received. The byte alignment circuit 3, like the special code detection circuit 2, generates multiple data strings (for example, 10 data strings) shifted by one bit from the parallel data signal DATA-P (E*), and any of the data strings is delimited at the correct position. If the position of the data string where the special code detection circuit 2 received the special code is the Xth, then the byte alignment circuit 3 also correctly delimits the Xth data string with the special code. The first correction value DET-COM indicates the Xth position information to the byte alignment circuit 3. The byte alignment circuit 3 outputs a parallel data signal DATA-P(E) that has been byte aligned based on the correct delimiter information.

After byte alignment is performed, external noise, etc. may cause byte alignment to be performed at a position that is shifted from the correct delimiter position (this is called "byte alignment deviation").

"Byte alignment deviation" is a state in which the receiving device does not perform serial-parallel conversion on the correct data block. When noise is present in the data, the recovered clock of the clock data recovery (CDR) circuit is shifted, the timing of the receiving device's serial data acquisition is shifted, and the number of received data items increases or decreases. In this case, a deviation in the number of data items occurs between the transmitting device and the receiving device, and the data boundary position is shifted. Note that a deviation in the frequency of the sending clock on the sending side and the recovered clock on the receiving side is called a recovered clock deviation. If the recovered clock of the receiving device is slower than the sending clock of the transmitting device, it may not be possible to sample the transmitted (1 bit) data. Conversely, if the recovered clock is faster than the sending clock of the transmitting device, the transmitted (1 bit) data will be sampled multiple times, and the number of data received by the receiving device may increase. In this way, if the number of data bits sent by the transmitting device and the number of data bits received by the receiving device differ, this can cause a "byte alignment deviation".

In this receiving device, byte alignment is performed again before receiving the next special code, and the data signal is quickly restored to the correct state. In the first receiving device, the second correction value θK is generated in the decoder 4 at the subsequent stage. Like the first correction value DET-COM, the second correction value θK contains information on the position of the data string separated at the correct position (the Yth data string). When the byte alignment circuit 3 receives the second correction value θK, it performs byte alignment in the same way as when it receives the first correction value DET-COM, and outputs a parallel data signal DATA-P(E) that has been byte aligned based on the correct separation information.

The parallel data signal DATA-P(E) is input to the decoder 4. The decoder 4 decodes the received parallel data signal DATA-P(E) and outputs the parallel data signal DATA-P(OUT) and a signal FLAG-K(OUT) corresponding to the K code as a control code.

The decoder 4 also has a correction value generation function, and generates a second correction value θK based on the received parallel data signal DATA-P(E). Like the byte alignment circuit 3, the decoder 4 also generates multiple data strings shifted by one bit at a time, and when decoding each data string, it identifies information on the position of the data string where no error occurred (the Yth data string has no error). When the byte alignment circuit 3 receives the second correction value θK, it determines that the Yth data string is separated at the correct position, and performs byte alignment by outputting a signal of the Zth data string corresponding to the Yth. Note that the Zth is X+Y, and if Z exceeds the maximum value of 10, the maximum value is subtracted. The structure of each circuit will be explained in detail below.

Figure 2 shows the circuit configuration of the special code detection circuit 2.

The special code detection circuit 2 includes a data string generation circuit 21, a number of special code detection units 22, and a correction value generation circuit 23. A parallel data signal DATA-P (E*) is input to the data string generation circuit 21. In this example, the data string generation circuit 21 generates 10 data strings by shifting the parallel data signal DATA-P (E*) by one bit at a time. Each data string (DATA-ARRAY (0) to DATA-ARRAY (9)) is input to the corresponding special code detection unit 22 (0) to special code detection unit 22 (9). An 8b10b code is also input to each special code detection unit 22, and the received data string determines where the special code is located. Comma characters (K28.1, K28.5, K28.7) are known as 8b10b special codes.

Special code detection units 22(0) to 22(9) respectively output special code detection signals COMMA-DET(0) to COMMA-DET(9) indicating whether a special code (comma character) is included in the received data string. The ten special code detection signals COMMA-DET(0) to COMMA-DET(9) are input to the correction value generation circuit 23. If the Xth (X=5) special code detection signal indicates that a special code has been detected, for example, the sequence of special code detection signals will be (0,0,0,0,1,0,0,0,0,0,0). The correction value generation circuit 23 generates a first correction value DET-COM from the received sequence of special code detection signals, indicating that a special code is present in the Xth position. The first correction value DET-COM is input to the selection circuit of the byte alignment circuit 3, so as long as it is a signal that is appropriately synchronized with the parallel data signal DATA-P(E*) input to the byte alignment circuit 3, the data sequence of the special code detection signal may be used as is.

Figure 3 shows the data string generation circuit and the special code detection circuit.

The data string generation circuit 21 combines the first data string (data D0-D9) and the second data string (D10-D19) that are input consecutively, and generates a data string consisting of 20 pieces of data (D0-D19). Furthermore, from the 20 data strings, it extracts data strings DATA-ARRAY(n) that are divided into 10 pieces of data (bits) (n=0-9). The nth data string and the n+1th data string are shifted by 1 bit (data). The special code detection unit 22(n) is a logic circuit that compares the input data string (D(19-n)-D(10-n)) with the comma character data string (C0-C9). If they match, the level of the special code detection signal COMMA-DET(n) rises, and the position (timing) of the special code can be identified.

Figure 4 shows an example of a data string generation circuit.

The data string generation circuit 21 has 10 D flip-flops, each of which receives 10 bits of data at its D terminal. In synchronization with the input of the first data string (data D0 to D9), the rising edge of the sampling clock signal CLKφ is input to the clock terminal, the first data string is output to the Q terminal, and the 10-bit first data string output from the lower terminal is maintained. Next, when the second data string (D10 to D19) is input to the data string generation circuit 21, the sampling clock signal CLKφ is not changed, and the 10-bit second data string is output from the upper terminal. In this way, a 20-bit data string is generated, and this generation process is repeated thereafter.

FIG. 5 shows a first type of byte alignment circuit 3.

The first type byte alignment circuit 3 applied to the first receiving device comprises a data string generation circuit 31, a selection circuit 32, and a byte alignment determination circuit 33. The structure of the data string generation circuit 31 is the same as that of the data string generation circuit 21 described above, and outputs 10 data strings (DATA-ARRAY(0) to DATA-ARRAY(9)) with phases shifted by one bit at a time. The selection circuit 32 performs byte alignment by outputting a data string corresponding to the information indicated by the input first correction value DET-COM and second correction value θK (the position of the data string separated at the correct position).

The first correction value DET-COM is generated depending on the timing of receiving a special code (comma character) that is received periodically. When the byte alignment determination circuit 33 receives this, it inputs a first selection instruction signal (for example, a selection instruction signal that selects the fifth data string (DATA-ARRAY (4))) to the selection circuit 32, which selects the error-free data string indicated by the information of the first correction value DET-COM. When the byte alignment determination circuit 33 receives the second correction value θK, it inputs a second selection instruction signal to the selection circuit 32, which selects the error-free data string indicated by the information of the second correction value θK.

The byte alignment determination circuit 33 gives priority to the first selection instruction signal generated in response to receiving the first correction value DET-COM over the second selection instruction signal generated in response to receiving the second correction value θK, and inputs it to the selection circuit 32. In other words, if the byte alignment determination circuit 33 receives the first correction value DET-COM after receiving the second correction value θK, it stops performing byte alignment using the second correction value θK and outputs the first selection instruction signal.

In the first receiving device, the second correction value θK indicates the position of a data string where no error occurs, and the second correction value θK is input to the byte alignment circuit 3, which performs byte alignment of the input data signal according to the second correction value θK. The first receiving device performs control by feeding back the second correction value θK generated in the correction value generation circuit to the byte alignment circuit 3 in the preceding stage, and does not require many circuits, so the circuit scale can be relatively small.

FIG. 6 shows the circuit configuration of a decoder 4 with a correction value generation function.

The decoder 4 includes a data string generation circuit 41, an 8b10b decoder with error detection 42(0), multiple 8b10b error detectors 42E(1)-42E(9), and a correction value generation circuit 43.

The structure of the data string generation circuit 41 is the same as that of the data string generation circuit 21 described above, and outputs 10 data strings (DATA-ARRAY(0) to DATA-ARRAY(9)) whose phases are shifted by one bit each. The decoder 4 has 10 channels through which these data strings flow.

A typical 8b10b decoder has the functions of decoding the input signal, detecting errors during 8b10b conversion, and generating an identification signal FLAG-K (OUT) corresponding to the control code (K code). An 8b10b error detector can use part of the 8b10b decoder functions, but it may also be configured by removing unnecessary parts from an 8b10b decoder. An 8b10b decoder with error detection or an 8b10b error detector outputs an error signal ERROR(n) that is the result of determining whether or not there is an error in the input signal (in this example, n is an integer from 0 to 9). It is determined that there is an error when a code error is detected or when an error is detected in the running disparity. Error detection may be performed in only one case, or in both cases.

The correction value generation circuit 43 receives 10 error signals (ERROR(0) to ERROR(9)). If the Yth error signal (Y=3) indicates that there is no error, for example, the sequence of error signals will be (1, 1, 0, 1, 1, 1, 1, 1, 1, 1). The correction value generation circuit 43 generates a second correction value θK from the received sequence of error signals, indicating that there is no error in the Yth signal. The second correction value θK may be generated, for example, by inverting the logic of the sequence of error signals and shifting the phase by an amount equivalent to the input to the byte alignment circuit 3 so that a correctly delimited data sequence is selected.

In the figure, the first 8b10b decoder with error detection 42(0) is placed, and outputs the decoded parallel data signal DATA-P (OUT) as well as the identification signal FLAG-K (OUT). However, the circuit that performs the decoded output does not need to be set to the first 8b10b decoder with error detection 42(0), and may be set to a position corresponding to another channel of the data array. For example, the fifth 8b10b error detector 42E(4) or the sixth 8b10b error detector 42E(5) can also be an 8b10b decoder. In this case, the 8b10b decoder is located in the center of the channel of the data array, which has the advantage of increasing symmetry during data processing.

FIG. 7 is a flowchart explaining the phase correction procedure for the image data signal in the first receiving device.

The decoder 4 shown in FIG. 6 detects whether an error has occurred in a specific channel (8b10b decoder with error detection 42(0)) that is currently decoding and outputting 10 channels (data string: DATA-ARRAY(0) to DATA-ARRAY(9)) (step S1). This can be determined by detecting the data string of the error signal. If an error has occurred in a specific channel, there is a channel in which no error has occurred, so that channel is selected (step S2). If an error has occurred in the target channel currently being decoded, this means that the division of the data string of this channel is incorrect. At a position where the phase is shifted from this channel, there is a correct data string among the data strings that have been divided. The correction value generation circuit 43 selects the data string with the correct division, generates the second correction value θK corresponding to the selected channel, and outputs it (step S3). The byte alignment circuit 3 performs byte alignment according to the input second correction value θK (step S4). If byte alignment is performed using the first correction value DET-COM while this flow is being executed, the input to the decoder will be a correctly delimited data string, so the error in the decoder will be resolved, byte alignment using the second correction value θK will be stopped, and the flow will return to step S1 again.

Figure 8 is a diagram to explain the timing of byte alignment.

The timing of the encoded parallel data signal DATA-P(E) is shown. The image data signal includes a blanking start signal BS (a comma character in the K code) at the start of the blanking period (D code), and a blanking end signal BE (a comma character in the K code) at the end. The active period (D code) during which image data is transmitted begins from the bit following the blanking end signal BE. At time t0 immediately after receiving the blanking end signal BE, byte alignment is performed using the first correction value DET-COM. If an error is detected during 8b10b decoding at time t1 due to external noise or the like, byte alignment is performed at time t2 using the above-mentioned second correction value θK. Unless time t1 is immediately before time t3 of the byte alignment using the next first correction value DET-COM after the error occurs, time t2 is earlier than time t3 of the byte alignment using the next first correction value DET-COM after the error occurs. Therefore, with this receiving device, the normal image data signal can be quickly restored even before the special code is received.

Figure 9 is a diagram to explain the state of multiple error signals.

In the decoder 4 shown in FIG. 6, a configuration is shown in which multiple error signals ERROR(0) to ERROR(9) are constantly monitored. Assume that the first 8b10b decoder with error detection 42(0) in FIG. 6 switches from an error-free state (No error) to an error-present state at time t1. In this case, for example, the error signal ERROR(1) output from the second 8b10b error detector 42E(1) changes to an error-free state (No error) immediately after time t1. The correction value generation circuit 43 generates the second correction value θK and inputs it to the byte alignment circuit 3. At time t2, byte alignment is performed, and then the first 8b10b decoder with error detection 42(0) returns to an error-free state (No error). Note that, among the multiple channels, there is only one channel in which no errors occur, and errors frequently occur in the other channels.

FIG. 10 shows the circuit configuration of a transmission/reception system equipped with a second receiving device.

Compared to the transmission/reception system shown in FIG. 1, this transmission/reception system differs in the structure of the byte alignment circuit 3 and the decoder 4. Unlike the first type (FIG. 5), in which the second correction value θK is input to the byte alignment circuit 3, this byte alignment circuit 3 (second type) outputs a notification signal DONE indicating that byte alignment has been completed, and inputs this to the decoder 4. The other configurations of this transmission/reception system are the same as those of the transmission/reception system shown in FIG. 1.

The decoder 4 has multiple (sub) decoders corresponding to multiple channels inside, and the output signal of any of the (sub) decoders is an output signal in which data has been correctly delimited. Therefore, if an error is detected in any of the (sub) decoders, the output of the decoder in which no error occurs is selected and output as the parallel data signal DATA-P (OUT).

Figure 11 shows a second type of byte alignment circuit.

The second type byte alignment circuit 3 applied to the second receiving device differs from the first type byte alignment circuit 3 (Figure 5) only in the function of the byte alignment determination circuit 33, and the other configurations are the same. As with the first type, when the second type byte alignment determination circuit 33 receives the first correction value DET-COM, it inputs a first selection instruction signal that selects the corresponding error-free data string to the selection circuit 32, and performs the same byte alignment as described above.

The second type byte alignment determination circuit 33 inputs the first selection instruction signal to the selection circuit 32, and then outputs a notification signal (DONE) indicating that byte alignment has been completed. The notification signal (DONE) is input to the decoder 4 with a correction value generation function located downstream.

FIG. 12 shows the circuit configuration of a decoder 4 with a correction value generation function.

The decoder 4 includes a data string generation circuit 41, ten 8b10b decoders with error detection 42(0)-42(9), a correction value generation circuit 43A, a first selection circuit 44, and a second selection circuit 45.

The data string generation circuit 41 has the structure described above, and outputs 10 data strings (DATA-ARRAY(0) to DATA-ARRAY(9)) whose phases are shifted by one bit each. The decoder 4 has 10 channels through which these data strings flow.

The ten 8b10b decoders with error detection 42(0)-42(9) are general 8b10b decoders, each of which has the function of decoding the input signal, the function of detecting errors during 8b10b conversion, and the function of generating identification signals FLAG-K(0)-FLAG-K(9) corresponding to the control code (K code).

Each 8b10b decoder 42(n) with error detection (n is an integer from 0 to 9) outputs an output signal DATA(n) obtained by decoding the input data string, an error signal ERROR(n) that determines whether or not there is an error, and an identification signal FLAG-K(n) that corresponds to the control code (K code). The 8b10b decoder 42(n) with error detection outputs an error signal ERROR(n) that is the result of determining whether or not there is an error in the input signal (in this example, n is an integer from 0 to 9). It is determined that there is an error when a code error is detected or when an error is detected in the running disparity. Error detection may be performed in only one case, or in both cases.

The correction value generation circuit 43A receives 10 error signals (ERROR(0) to ERROR(9)). If the Yth error signal (Y=3) indicates that there is no error, for example, the data string of the error signals will be (1, 1, 0, 1, 1, 1, 1, 1, 1, 1). From the received string of error signals, the correction value generation circuit 43A generates a second correction value θK* indicating that there is no error in the Yth signal. The second correction value θK* is, for example, the inverted logic of the data string of the error signals.

The ten decoded output signals DATA(n) are input to the first selection circuit 44. The first selection circuit 44 selects and outputs the output signal DATA(n) of the Y-th data string indicated by the second correction value θK* output from the correction value generation circuit 43A.

The ten identification signals FLAG-K(n) are input to the second selection circuit 45. The second selection circuit 45 selects the identification signal FLAG-K(n) of the Y-th data string indicated by the second correction value θK* output from the correction value generation circuit 43A, and outputs it as FLAG-K(OUT).

As explained above, the receiving device RX is equipped with multiple 8b10b decoders 42(n) that respectively decode multiple data strings, and the second correction value θK* indicates a data string that is error-free. The receiving device performs byte alignment of the data signal by selecting a data signal obtained by decoding the data string indicated by the second correction value θK* and outputting it as a parallel data signal DATA-P (OUT). The receiving device has multiple decoders prepared in advance.

The normal data signal is a data signal that is output by separating a data string at the position of a normal block, and the error data signal is a data signal that is output by separating a data string at the position of a block where an error occurs. Normal data signals and groups of error data signals can be output from the multiple 8b10b decoders 42(n). This receiving device performs byte alignment of the data signal by selecting a normal data signal using the second correction value θK*. This receiving device does not require feedback of the second correction value to the byte alignment circuit 3, so the circuit structure is simple and has excellent maintainability and robustness.

When the byte alignment circuit 3 executes byte alignment using the first correction value DET-COM generated in synchronization with the detection of the special code, it inputs a notification signal DONE indicating that the byte alignment has been executed to the correction value generation circuit 43A of the decoder 4. After the byte alignment is executed, the first selection circuit 44 selects and outputs the parallel data signal DATA-P (OUT) that has been delimited at the correct timing. When the notification signal DONE indicating that the byte alignment has been executed is input to the correction value generation circuit 43A, it can be determined that the default alignment state (a state in which normal byte alignment has been executed in synchronization with the detection of the special code and the correct delimitation has been performed) is in effect. In the initial settings, if there is a specific default channel (any of DATA-ARRAY (0) to DATA-ARRAY (9)) that is set to output the correct parallel data signal DATA-P (OUT) in this state, then that specific channel can be selected. In other words, in this case, the second correction value θK* is a signal that instructs the first selection circuit 44 and the second selection circuit 45 to select the data signal output from the 8b10b decoder 42 that corresponds to a specific channel.

FIG. 13 is a flowchart explaining the phase correction procedure for the image data signal in the second receiving device.

The decoder 4 shown in FIG. 12 detects whether an error has occurred in a specific channel (e.g., 8b10b decoder 42(0) with error detection) that is currently decoding and outputting 10 channels (data string: DATA-ARRAY(0) to DATA-ARRAY(9)) (step S11). This can be determined by detecting the data string of the error signal. If an error has occurred in a specific channel, there is a channel in which no error has occurred. If an error has occurred in the target channel currently being decoded, this means that the division of the data string of this channel is incorrect and the data string with the division at the out-of-phase position is correct, so the correction value generation circuit 43A generates and outputs a second correction value θK* indicating a channel without errors (step S12). The first selection circuit 44 selects and outputs an error-free data signal according to the input second correction value θK*, thereby performing byte alignment (step S13). When byte alignment is performed using the first correction value DET-COM, the correction value generation circuit 43A receives a notification signal DONE indicating that byte alignment has been completed, and regardless of the step, the initially selected decoder (the default decoder that is selected when the data signal DATA-P(E) has correct data delimiters and there is no error) is selected, and the process transitions to step S11.

Figure 14 is a diagram to explain the states of multiple error signals.

In the decoder 4 shown in FIG. 12, a configuration is shown in which multiple error signals ERROR(0) to ERROR(9) are constantly monitored. Assume that the first 8b10b decoder with error detection 42(0) in FIG. 12 switches from an error-free state (No error) to an error-present state (error) at time t1. In this case, for example, the error signal ERROR(1) output from the second 8b10b decoder 42(1) changes to an error-free state (No error) immediately after time t1. The correction value generation circuit 43A generates the second correction value θK*, byte alignment is performed at time t2, and then the output signal of the second 8b10b decoder 42(1) is selected and output as an output signal in an error-free state (No error). Note that, among the multiple channels, there is only one channel in which no errors occur, and errors frequently occur in the other channels.

FIG. 15 is a timing diagram illustrating an example of the timing of data transmission and reception in the first receiving device.

On the transmitting device TX side, an 8-bit parallel data signal DATA-P (IN) hex (hexadecimal notation) or DATA-P (IN) bin (binary notation) is input, which is converted to a 10-bit encoded parallel data signal DATA-P (EE), and then transmitted as a serialized serial data signal DATA-S (E).

On the receiving device RX side, the serial data signal DATA-S (E) is received, deserialized, and converted to a parallel data signal DATA-P (E*), and a byte-aligned parallel data signal DATA-P (E) is generated. After that, data strings DATA-ARRAY (0) to DATA-ARRAY (9) that flow through the 10 channels are generated. The parallel data signal DATA-P (OUT) bin (binary notation) or DATA-P (OUT) hex (hexadecimal notation) is output from the decoder.

If an error (NG) is detected in the parallel data signal DATA-P(OUT)hex (in hexadecimal notation) after 8b10b encoding, for example due to a code error, this output signal will be an indefinite value. Code errors are detected by an 8b10b decoder with error detection. For example, if an error (ERROR) occurs in the first data string (DATA-ARRAY(0)) and the second data string (DATA-ARRAY(1)) becomes normal (OK), then byte alignment is performed at time t2 using the second correction value θK as described above. In this case, the error in the first data string (DATA-ARRAY(0)) is eliminated and the data can be restored to a normal (OK) state.

FIG. 16 is a timing diagram illustrating an example of the timing of data transmission and reception in the second receiving device.

If an error (NG) is detected in the parallel data signal DATA-P(OUT)hex (in hexadecimal notation) after 8b10b encoding, for example due to a code error, this output signal becomes an indefinite value. If the currently selected data string is the first data string (DATA-ARRAY(0)) (selected decoder output: DATA(0)), and an error (ERROR) occurs in this data string, and the second data string (DATA-ARRAY(1)) is determined to be normal (OK), then byte alignment is performed at time t2 using the second correction value θK*, as described above. In this case, the output of the second data string (DATA-ARRAY(1)) (selected decoder output: DATA(1)) is subsequently selected, allowing the normal (OK) state to be restored.

FIG. 17 shows the circuit configuration of a transmission/reception system equipped with a third receiving device.

Compared to the transmission/reception system shown in FIG. 1, this transmission/reception system differs in the structure and arrangement of the decoder 4 and the byte alignment circuit 3. The other configurations of this transmission/reception system are the same as those of the transmission/reception system shown in FIG. 1.

The decoder 4 has multiple (sub) decoders corresponding to multiple channels inside, and the output signal of any of the (sub) decoders is an output signal in which data has been correctly delimited. Therefore, if an error is detected in any of the (sub) decoders, it outputs a second correction value θK* that selects the output of a decoder in which no error has occurred. The decoder 4 also outputs multiple parallel data signals DATA-P(M) that are generated by decoding the input signal, and multiple identification signals FLAG-K(M).

The byte alignment circuit 3 (third type) is placed after the decoder 4, and receives multiple parallel data signals DATA-P (M) (e.g., 10 8-bit data strings) and multiple identification signals FLAG-K (M) (e.g., 10 bits) output from the decoder 4. From each input signal, a signal with correct data division is selected using the first correction value DET-COM and the second correction value θK, and is output as the parallel data signal DATA-P (OUT) and the identification signal FLAG-K (OUT), resulting in byte alignment of the input parallel data signal.

FIG. 18 shows the circuit configuration of a decoder 4 with a correction value generation function.

The decoder 4 includes a data string generation circuit 41, ten 8b10b decoders with error detection 42(0)-42(9), and a correction value generation circuit 43A. In this example, the decoder 4 is located immediately after the deserializer 1, so the parallel data signal DATA-P(E*) before byte alignment is input.

The structure and function of the data string generation circuit 41 and the 8b10b decoders with error detection 42(0)-42(9) are the same as the corresponding circuits in the decoder 4 of the second receiving device (see FIG. 12).

The ten 8b10b decoders with error detection 42(0)-42(9) are general 8b10b decoders, each of which has the function of decoding the input signal, the function of detecting errors during 8b10b conversion, and the function of generating identification signals FLAG-K(0)-FLAG-K(9).

The correction value generation circuit 43A receives 10 error signals (ERROR(0) to ERROR(9)). For example, if the Yth error signal (Y=3) indicates that there is no error, the data string of the error signals will be (1, 1, 0, 1, 1, 1, 1, 1, 1, 1). From the received string of error signals, the correction value generation circuit 43A generates a second correction value θK* indicating that there is no error in the Yth signal. The second correction value θK* is, for example, the inverted logic of the data string of the error signals.

FIG. 19 shows a third type of byte alignment circuit 3.

This byte alignment circuit 3 includes a byte alignment determination circuit 33, a first selection circuit 34, and a second selection circuit 35.

The byte alignment judgment circuit 33 receives the first correction value DET-COM and the second correction value θK*. When the byte alignment judgment circuit 33 receives the first correction value DET-COM, it generates a first selection instruction signal that selects an error-free data string (e.g., Xth) and inputs this to the first selection circuit 34 and the second selection circuit 35. When the byte alignment judgment circuit 33 receives the second correction value θK*, it generates a second selection instruction signal that selects an error-free data string (e.g., Yth) and inputs this to the first selection circuit 34 and the second selection circuit 35. The byte alignment judgment circuit 33 gives priority to the first selection instruction signal generated in response to receiving the first correction value DET-COM over the second selection instruction signal generated in response to receiving the second correction value θK*, and inputs this to the first selection circuit 34 and the second selection circuit 35. That is, if the byte alignment determination circuit 33 receives the first correction value DET-COM after receiving the second correction value θK*, it stops performing byte alignment using the second correction value θK* (selecting an error-free data signal) and performs byte alignment using the first correction value DET-COM (selecting an error-free data signal).

The first selection circuit 34 receives the ten output signals DATA(n) decoded by the preceding decoder 4. The first selection circuit 34 selects the error-free data string DATA(n) according to the first selection instruction signal generated from the first correction value DET-COM or the second selection instruction signal generated from the second correction value θK*, and outputs it as a parallel data signal DATA-P(OUT).

The second selection circuit 35 receives ten identification signals FLAG-K(n) decoded by the previous decoder 4. The second selection circuit 35 selects the signal FLAG-K(n) corresponding to an error-free channel according to the first selection instruction signal generated from the first correction value DET-COM or the second selection instruction signal generated from the second correction value θK*, and outputs it as the identification signal FLAG-K(OUT).

The serializer 202 of the transmitting device TX can be equipped with a pre-emphasis circuit (amplifier) that amplifies the high-frequency components of the transmission signal. The deserializer 1 of the receiving device RX can be equipped with an adaptive equalizer that automatically amplifies the high-frequency components that are attenuated according to the characteristics of the transmission line. This makes it possible to suppress degradation of signal quality during signal transmission, and preferably to increase the data transmission speed of the symbol mapping method to 4 Gbps or more with one pair of differential lines, and the transmission distance to 10 m or more. A flexible flat cable (FFC) can also be used for the transmission line of the serial data signal.

Next, we will explain a transmission/reception system equipped with a receiving device that is an improvement over the first to third receiving devices described above.

Figure 20 shows the circuit configuration of a transmission/reception system equipped with an improved first receiving device.

The transmitting device TX shown in the figure includes a packer PC (Packer), a symbol generating circuit SG, and a multiplexer MUX in addition to the first receiving device shown in FIG. 1.

The packer PC receives, for example, a video signal DATA-IN for each RGB and a sync signal SYNC-IN. The packer PC generates a byte clock signal from the pixel clock signal of the video signal, and performs packet processing of the video signal using the byte clock signal to generate a packet signal that will be the video signal in the active period (ACTIVE). The packer PC performs packet processing of signals corresponding to the blank start (BS) period, blank end (BE) period, and blank (BP) period from the sync signal SYNC-IN, and generates a packet signal corresponding to each period. Each packet signal is an 8-bit parallel data signal, but it is also possible to process N times (N is a natural number) of 8-bit parallel data signals.

The symbol generation circuit SG receives the data enable signal DE-IN, and generates and outputs an identification signal FLAG-K (IN) corresponding to the control code (K code) from the data enable signal DE-IN. The signal FLAG-K (IN) contains information indicating the BS period, BE period, and BP period. For example, the BS period can be set immediately after the falling edge of the data enable signal DE-IN, and the blank end BE period can be set immediately before the rising edge.

The multiplexer MUX receives the multiple signals output from the packer PC and the identification signal FLAG-K (IN), and outputs an 8xN-bit parallel data signal obtained by combining these signals to the encoder 201. The multiplexer MUX also receives the identification signal FLAG-K (IN) that contains information about the BS, BE, and BP periods, and can use this signal to perform operations. For example, the multiplexer MUX can output a video signal containing image information during the active period, and output a signal generated from the sync signal SYNC-IN corresponding to each period during the BS, BE, and BP periods.

Encoder 201 is an 8b10b encoder that receives the 8-bit parallel data signal PATA-P (IN) output from the multiplexer MUX, encodes it into a 10-bit parallel data signal, and outputs it. This parallel data signal can also be processed as a parallel data signal that is N times the 10-bit parallel data signal. Encoder 201 also receives an identification signal FLAG-K (IN) that corresponds to a control code (K code) output from the symbol generation circuit SG, and can optimize the encoding operation according to the type of signal. Serializer 202 is disposed after encoder 201, and outputs serial data signal DATA-S (E). Serializer 202 may also include a pre-emphasis circuit (amplifier) that amplifies high-frequency components.

The first receiving device RX shown in the figure includes a symbol detection circuit SD, a demultiplexer DMUX, an unpacker UP, and a data enable signal generation circuit DE in addition to the first receiving device shown in FIG. 1.

The deserializer 1 of the receiving device RX receives the serial data signal DATA-D(E). The deserializer 1 may be equipped with an adaptive equalizer. The special code detection circuit 2, byte alignment circuit 3, and decoder 4 are arranged downstream of the deserializer 1. The structure and operation of these circuits are as explained for the first receiving device (Figure 1), but the parallel data signals output from these circuits can also be N times the 10-bit parallel data signal.

A symbol detection circuit SD is arranged after the decoder 4, and a data enable signal generation circuit DE is arranged after that. Also, a demultiplexer DMUX is arranged after the decoder 4. The symbol detection circuit SD receives a parallel data signal DATA-P (OUT) and an identification signal FLAG-K (OUT). The symbol detection circuit SD detects information corresponding to the BS period, BE period, and BP period from the received signal, and inputs a symbol detection signal containing the detected information to the demultiplexer DMUX and the data enable signal generation circuit DE.

The unpacker UP (Un-packer) is placed after the demultiplexer DMUX. The demultiplexer DMUX has the function of recovering the RGB video signals and the sync signal from the received parallel data signal DATA-P (OUT). To recover the sync signal, it can switch the output terminal of the input parallel data signal according to each period (BS period, BE period, BP period) indicated by the symbol detection signal output from the symbol detection circuit SD. The parallel data signals separated from each output terminal corresponding to the active period, BS period, BE period, and BP period are input to the unpacker UP.

The unpacker UP generates a pixel clock signal from the parallel data signal received from the demultiplexer DEMUX, and uses the pixel clock signal to unpacketize the 8-byte packet signal, regenerating and outputting the RGB video signal DATA-OUT and the sync signal SYNC-OUT.

The data enable signal generation circuit DE generates and outputs a data enable signal DE-OUT according to each period (BS period, BE period, BP period) indicated by the symbol detection signal output from the symbol detection circuit SD. Note that the parallel data signals output from the decoder 4, demultiplexer DMUX, and unpacker UP can also be N-times the size of an 8-bit parallel data signal.

Figure 21 shows the circuit configuration of a transmission/reception system equipped with an improved second receiving device.

The transmitting device TX shown in the figure is the same as the transmitting device shown in FIG. 20. The second receiving device RX shown in the figure is a circuit in which a symbol detection circuit SD, a demultiplexer DMUX, an unpacker UP, and a data enable signal generation circuit DE are added to the second receiving device shown in FIG. 10.

The deserializer 1 of the receiving device RX receives the serial data signal DATA-D(E). The deserializer 1 may be equipped with an adaptive equalizer. The special code detection circuit 2, byte alignment circuit 3, and decoder 4 are arranged downstream of the deserializer 1. The structures and operations of these are as described for the second receiving device (Figure 10). The parallel data signal output from the deserializer 1 and byte alignment circuit 3 may be N times a 10-bit parallel data signal. The parallel data signal output from the decoder 4 may be N times an 8-bit parallel data signal.

After the decoder 4, there are a symbol detection circuit SD, a data enable signal generation circuit DE, a demultiplexer DMUX, and an unpacker UP, whose structures and operations are the same as those shown in FIG. 20.

Figure 22 shows the circuit configuration of a transmission/reception system equipped with an improved third receiving device.

The transmitting device TX shown in the figure is the same as the transmitting device shown in FIG. 20. The second receiving device RX shown in the figure is a circuit in which a symbol detection circuit SD, a demultiplexer DMUX, an unpacker UP, and a data enable signal generation circuit DE are added to the third receiving device shown in FIG. 17.

The deserializer 1 of the receiving device RX receives the serial data signal DATA-D (E). The deserializer 1 may be equipped with an adaptive equalizer. The special code detection circuit 2, the decoder 4, and the byte alignment circuit 3 are arranged downstream of the deserializer 1. The structure and operation of these are as explained for the third receiving device (FIG. 17). The parallel data signal output from the decoder 4 is 8×n bits (n=10 in FIG. 19). The parallel data signal DATA-P (OUT) output from the byte alignment circuit 3 may also be a parallel data signal that is N times the 8-bit parallel data signal.

As explained above, the first receiving device includes a special code detection circuit 2 that receives a data signal DATA-P(E*) that includes a special code and is encoded using a symbol mapping method, and outputs a first correction value DET-COM that corresponds to the position of the special code included in this data signal, a byte alignment circuit 3 that receives the first correction value DET-COM and the second correction value θK and performs byte alignment of the data signal according to the first correction value and the second correction value, a data string generation circuit 41 that generates a plurality of data strings having different delimiter positions in the data string from the output signal of the byte alignment circuit 3, and a data string generation circuit 42 that generates a plurality of data strings having different delimiter positions in the data string from the output signal of the data string generation circuit 41. The data string generating circuit 41 includes a decoder 42(0) that decodes and outputs a specific data string from among the multiple data strings generated, and performs an error determination for the specific data string; multiple error detectors 42E(1)-42E(9) that perform an error determination for each of the remaining data strings other than the specific data string from among the multiple data strings output from the data string generating circuit 41; and a correction value generating circuit 43 that receives multiple error signals ERROR(0)-(9) indicating the results of the error determination output from the decoder 42(0) and the multiple error detectors 42E(1)-42E(9) and generates a second correction value θK including information on data strings without errors in response to the multiple error signals received.

In this receiving device, the first correction value DET-COM corresponds to the position of the special code indicating normal timing, and when the first correction value DET-COM is received, the byte alignment circuit 3 performs byte alignment. The second correction value θK has information on an error-free data string based on multiple error signals. If an error occurs before the reception of the special code due to external noise or the like, byte alignment of the data signal is performed according to the second correction value generated by the correction value generation circuit 43. This allows for an early return to a normal data signal even before the reception of the special code. If the data signal is an image data signal, image distortion can be eliminated early. This receiving device controls by feeding back the second correction value generated by the correction value generation circuit to the byte alignment circuit in the previous stage, and does not require many circuits, so it can be realized with a relatively small circuit scale.

The second receiving device includes a special code detection circuit 2 that receives a data signal DATA-P(E*) that includes a special code and is encoded using a symbol mapping method, and outputs a first correction value DET-COM that corresponds to the position of the special code included in the data signal, a byte alignment circuit 3 that performs byte alignment of the data signal according to the first correction value DET-COM output from the special code detection circuit 2, a data string generation circuit 41 that generates multiple data strings with different delimiter positions in the data string from the output signal of the byte alignment circuit 3, and a data string generation circuit 42 that generates a data string with different delimiter positions in the data string from the output signal of the data string generation circuit 41. The system includes a plurality of decoders 42(0)-42(9) that decode the plurality of data strings outputted from the plurality of decoders 42(0)-42(9) and perform an error determination for each of the plurality of data strings; a correction value generation circuit 43A that receives a plurality of error signals ERROR(0)-(9) that indicate the results of the error determination outputted from the plurality of decoders 42(0)-42(9) and generates a second correction value θK* that includes information on data strings that are free of errors in accordance with the plurality of error signals that have been inputted; and a selection circuit (44) that selects and outputs a data string that corresponds to the second correction value θK* from the plurality of data strings outputted from the plurality of decoders 42(0)-42(9).

In this receiving device, the first correction value DET-COM corresponds to the position of the special code indicating normal timing, and when the first correction value DET-COM is received, the byte alignment circuit 3 performs byte alignment. The second correction value θK* has information on an error-free data string based on multiple error signals. If an error occurs before the reception of the special code due to external noise or the like, the selection circuit 44 selects and outputs a data string without byte alignment deviation according to the second correction value θK* generated by the correction value generation circuit 43A. This allows for early recovery to a normal data signal even before the reception of the special code. If the data signal is an image data signal, image distortion can be eliminated early. Furthermore, this receiving device can achieve early recovery from byte alignment deviation with a simple modification of existing technology.

In addition, in the second receiving device, the byte alignment circuit outputs a notification signal DONE indicating that byte alignment has been completed, and when the notification signal DONE is input to the correction value generation circuit 43, the selection circuit 44 selects and outputs a data string from the default decoder among the decoders. Even if there is no change in the second correction value θK*, the correction value generation circuit 43 receives the first correction value DET-COM, and the selection circuit 44 can output a correctly delimited data string.

The third receiving device includes a special code detection circuit 2 that receives a data signal DATA-P(E*) that includes a special code and is encoded using a symbol mapping method, and outputs a first correction value DET-COM that corresponds to the position of the special code included in the data signal; a data string generation circuit 41 that generates multiple data strings from the data signal, the data string having different delimiter positions; and multiple decoders 42(0) to 42(9) that decode each of the multiple data strings output from the data string generation circuit 41 and determine whether there is an error in each of the data strings. , a correction value generation circuit 43A receives a plurality of error signals ERROR(0)-(9) indicating the results of the error determination output from a plurality of decoders 42(0)-42(9) and generates a second correction value θK including information on a data string without errors according to the plurality of error signals input, and a byte alignment circuit 3 selects and outputs a data string corresponding to the first correction value DET-COM and the second correction value θK* from the plurality of data strings DATA(0)-DATA(9) output from the plurality of decoders 42(0)-42(9).

In this receiving device, the first correction value DET-COM corresponds to the position of the special code indicating normal timing. The second correction value θK* has information on a data string without errors based on multiple error signals. The byte alignment circuit 3 selects and outputs a data string corresponding to the first correction value DET-COM and the second correction value θK* from multiple data strings output from multiple decoders. If an error occurs before the reception of the special code due to external noise or the like, the byte alignment circuit selects and outputs a data string without byte alignment deviation according to the second correction value θK* generated by the correction value generation circuit 43A. This allows for early recovery to a normal data signal even before the reception of the special code. If the data signal is an image data signal, image distortion can be eliminated early. This receiving device can achieve early recovery from byte alignment deviation with a simple configuration.

The above-mentioned receiving device includes a deserializer 1 that receives a serial data signal DATA-S transmitted from a transmitting device, converts it into a parallel data signal, and inputs it as a data signal DATA-P (E*) to a special code detection circuit 2. The deserializer can convert a serial data signal into a parallel data signal.

In the receiving device described above, byte alignment is performed not only by relying on special codes, but also by using transmission code errors. Taking advantage of the redundant characteristics of the symbol mapping method, transmission code errors are detected on the receiving side. If the deserialized data is a block of erroneous data, there is a high possibility that it will deviate from the DC balance and run length rules, so if a byte alignment shift occurs, it is possible to detect an error. By arranging transmission code error detectors for a length equal to or greater than the code length and monitoring all possible blocks of parallel data during parallel conversion, it is possible to detect the correct data delimiters and perform byte alignment again before receiving the special code.

In the above configuration, 10 data strings are observed simultaneously, but it is also possible to configure it so that detection is performed with two or more. In the above configuration, when the data width (code length) is 10 bits, 20-bit data is combined to generate a data string, but detection can also be performed with a data width of 11 bits or more (code length + data strings observed simultaneously -1). In error detection, if one error is detected, it may be determined that an error has occurred, but if several errors occur consecutively, it may be determined that an error has occurred and byte alignment may be performed. In the above, a channel that is determined to have no errors is specified, but the channel that is determined to have the least frequent errors among the channels may also be determined to have no errors. In the above configuration, the bit shift can only be adjusted in one direction, forward or backward, using the second correction value θK (or θK*). However, by shifting the parallel data signal DATA-P, which is the output of the byte alignment circuit, or by increasing the data width (code length) from 10 bits, which is generated by combining 20 bits of data, to 21 bits or more, it becomes possible to adjust the byte alignment in both directions using the second correction value θK (or θK*).

In addition, in the first receiving device, the output of the 8b10b decoder is fixed, so the decoder that is not connected to the output can be configured with only an error detection unit. Although there is a feedback circuit, the circuit area can be made relatively small compared to the second receiving device. On the other hand, in the second receiving device, a selection circuit is placed at the output of the 8b10b decoder, and the feedback circuit to the byte alignment can be omitted, resulting in a simple configuration with excellent maintainability and robustness. Byte alignment deviation caused by external noise can be restored without waiting for a special code (comma character). Therefore, noise can be suppressed to pixel units, improving the image display, and especially when image data signals are transmitted to the display device of a mobile device such as an automobile, the convenience of the driver can be improved.

1...deserializer, 2...special code detection circuit, 3...byte alignment circuit, 4...decoder, 21...data string generation circuit, 22...special code detection unit, 23...correction value generation circuit, 31...data string generation circuit, 32...selection circuit, 41...data string generation circuit, 42...8b10b decoder, 42E...8b10b error detector, 43, 43A...correction value generation circuit, 44...first selection circuit, 45...second selection circuit, 201...encoder, 202...serializer, ERROR...error signal, RX...receiving device, TX...transmitting device.

Claims

a special code detection circuit that receives a data signal that includes a special code and is encoded by a symbol mapping method, and outputs a first correction value that corresponds to the position of the special code included in the data signal;
a byte alignment circuit that receives the first correction value and the second correction value and performs byte alignment of the data signal in accordance with the first correction value and the second correction value;
a data string generating circuit that generates a plurality of data strings, each of which has a different delimiter position, from an output signal of the byte alignment circuit;
a decoder that decodes and outputs a specific data string from among the multiple data strings output from the data string generation circuit, and that performs error determination on the specific data string;
a plurality of error detectors for determining whether or not there is an error in each of the remaining data strings other than the specific data string among the plurality of data strings output from the data string generation circuit;
a correction value generating circuit to which a plurality of error signals indicating the results of the error determination output from the decoder and the plurality of error detectors are input, and which generates the second correction value including information on a data string having no error in response to the input plurality of error signals;
Equipped with
A receiving device comprising:
a special code detection circuit that receives a data signal that includes a special code and is encoded by a symbol mapping method, and outputs a first correction value that corresponds to the position of the special code included in the data signal;
a byte alignment circuit that performs byte alignment of the data signal in response to the first correction value output from the special code detection circuit;
a data string generating circuit that generates a plurality of data strings, each of which has a different delimiter position, from an output signal of the byte alignment circuit;
a plurality of decoders for decoding the plurality of data strings output from the data string generating circuit and for determining whether there is an error in each of the data strings;
a correction value generating circuit which receives a plurality of error signals indicating the results of the error determination output from the plurality of decoders, and generates a second correction value including information on a data string having no error in response to the plurality of error signals;
a selection circuit that selects and outputs a data sequence corresponding to the second correction value from among a plurality of data sequences output from a plurality of the decoders;
Equipped with
A receiving device comprising:
a special code detection circuit that receives a data signal that includes a special code and is encoded by a symbol mapping method, and outputs a first correction value that corresponds to the position of the special code included in the data signal;
a data string generating circuit for generating a plurality of data strings, each of which has a different delimiter position, from the data signal;
a plurality of decoders each for decoding the plurality of data strings output from the data string generating circuit and for determining whether there is an error in each of the data strings;
a correction value generating circuit which receives a plurality of error signals indicating the results of the error determination output from the plurality of decoders, and generates a second correction value including information on a data string having no error in response to the plurality of error signals;
a byte alignment circuit that selects and outputs a data string corresponding to the first correction value and the second correction value from among a plurality of data strings output from a plurality of the decoders;
Equipped with
A receiving device comprising:
a deserializer that receives a serial data signal transmitted from a transmitting device, converts the serial data signal into a parallel data signal, and inputs the parallel data signal to the special code detection circuit as the data signal;
2. The receiving device according to claim 1 .
a deserializer that receives a serial data signal transmitted from a transmitting device, converts the serial data signal into a parallel data signal, and inputs the parallel data signal to the special code detection circuit as the data signal;
3. The receiving device according to claim 2.
a deserializer that receives a serial data signal transmitted from a transmitting device, converts the serial data signal into a parallel data signal, and inputs the parallel data signal to the special code detection circuit as the data signal;
4. The receiving device according to claim 3.
The byte alignment circuit includes:
A notification signal is output to notify completion of byte alignment.
When the notification signal is input to the correction value generating circuit,
The selection circuit selects and outputs a data string from a decoder having a default setting among the decoders.
3. The receiving device according to claim 2.