JP2012028606A - Nonvolatile semiconductor memory device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device and a manufacturing method of the same having less incidence of degradation in memory properties even after performing heat treatment.SOLUTION: The nonvolatile semiconductor memory device manufacturing method comprises the steps of forming bit lines 180 above a substrate 110, forming an interlayer insulation film 100 on the substrate 110 so as to cover the bit lines 180, planarizing a top face of the interlayer insulation film 100, forming a hydrogen barrier film 200 on the interlayer insulation film 100, forming a capacitative element 380 including a ferroelectric material or a high dielectric material on the hydrogen barrier film 200 and performing heat treatment of sintering the ferroelectric material or the high dielectric material included in the capacitative element 380. Film thickness variation of the interlayer insulation film 100 caused by the heat treatment is 2.3% and under.

Description

  The technology described in this specification relates to a nonvolatile semiconductor memory device and a method for manufacturing the same, and in particular, a capacitor over bit line (COB) using a ferroelectric layer, a high dielectric layer, or a resistance change layer as a memory layer. The present invention relates to a nonvolatile semiconductor memory device having a structure.

  In recent years, with the development of electronic money and the like, there is an increasing demand for non-volatile semiconductor memory devices that have a low operating voltage and can be read and written at high speed. As a nonvolatile semiconductor memory device having this characteristic, a nonvolatile semiconductor memory device using a ferroelectric film or a high dielectric film as a capacitive insulating film, or a material whose resistance value reversibly changes when an electric pulse is applied. A variable resistance nonvolatile semiconductor memory device or the like that uses and stores data is used.

  On the other hand, in the nonvolatile semiconductor memory device, it is essential to increase the memory capacity per unit area in order to accumulate a large amount of information as the application and functions expand. As a structure in which more memory cells can be mounted with the same area, a COB structure in which a capacitor element is formed above a bit line has been actively developed. According to this structure, adjacent capacitor elements can be separated without considering the bit line contact portion, and the mounted memory capacity can be increased while maintaining the capacitance value of the capacitor element. Become.

  By the way, in the nonvolatile semiconductor memory device using the above-described ferroelectric film or high dielectric film as a capacitive insulating film, heat treatment at 600 ° C. or higher is essential in order to develop ferroelectric characteristics or high dielectric characteristics. Further, in a resistance change type nonvolatile semiconductor memory device that utilizes the fact that the resistance state of the thin film is rapidly changed by a specific voltage applied to the thin film, the thin film material has a thickness of 400 to 1000 in order to obtain a desired resistance value. It is necessary to apply a heat treatment at 0 ° C.

  Furthermore, as a characteristic common to the processes for manufacturing these nonvolatile semiconductor memory devices, the characteristics as a nonvolatile semiconductor memory device deteriorate when a thin film used as a capacitor insulating film or a resistance film is exposed to a hydrogen atmosphere in a wiring process or the like. Therefore, it is essential to cover the capacitive element with a hydrogen barrier film (see, for example, Patent Document 1).

  Therefore, when the COB structure is employed in the nonvolatile semiconductor memory device described above, since a capacitive element is formed above the bit line, for example, after a borophosphosilicate glass (BPSG) film is deposited on the bit line, chemical vapor deposition ( Planarization is performed by a CMP method. Next, after forming a hydrogen barrier film and a capacitor element in this order on the BPSG film to protect the capacitor element from deterioration due to hydrogen reduction, a ferroelectric film or a high dielectric film required for the nonvolatile semiconductor memory device is baked. A heat treatment (400 to 1000 ° C.) is performed for sinter.

JP 2007-067066 A

  In the above prior art, a BPSG film having a flat upper surface is formed under the capacitive element. When the above-described COB structure is adopted in this prior art, when a BPSG film is planarized by a chemical mechanical polishing (CMP) method, a pressure applied by a CMP pad is applied to the BPSG film as a planarized film, and as a result, the BPSG film There is a risk of scratching. When a hydrogen barrier film and a capacitive element are formed in the post-process in the state where the BPSG film is scratched, and a heat treatment (400 to 1000 ° C.) for sintering the ferroelectric film or the high dielectric film is performed, Due to scratches generated in the BPSG film, a local stress imbalance occurs in the hydrogen barrier film, and cracks occur in the hydrogen barrier film.

  As a result, when the capacitive element is exposed to a hydrogen atmosphere in a subsequent process, hydrogen penetrates into the capacitive element from the crack, and the ferroelectric oxide or the like exhibiting hysteresis characteristics is reduced, resulting in a decrease in the residual polarization amount and the like. As a result, the retention (data retention) characteristics of the nonvolatile semiconductor memory device deteriorate. And finally, the problem that the yield of a nonvolatile semiconductor memory device falls occurs.

  This problem will be described with reference to the drawings. 4A and 4B are cross-sectional views showing problems in a conventional nonvolatile semiconductor memory device.

  First, as shown in FIG. 4A, the element isolation region 2 is formed at a predetermined position on the semiconductor substrate 1, and the gate structure 40 including the gate insulating film and the gate electrode of the transistor is formed on the semiconductor substrate 1. To do. Next, the silicide layer 30 is formed by silicidizing the upper surface portion of the semiconductor substrate 1 except for the region where the gate structure 40 is formed, surrounded by the element isolation region 2. Next, a gate structure 40 including a gate insulating film and a gate electrode of the transistor is formed on the semiconductor substrate 1.

  Next, a first interlayer insulating film 60 covering the transistor is formed on the semiconductor substrate 1, and the upper surface thereof is planarized by CMP. Next, a bit line contact 70 connected to one diffusion layer of the transistor is formed in the first interlayer insulating film 60. Next, a bit line 80 connected to the bit line contact 70 is formed on the first interlayer insulating film 60. Next, a second interlayer insulating film 10 made of a BPSG film is formed on the first interlayer insulating film 60 so as to cover the bit line 80, and the upper surface thereof is planarized by CMP.

  Here, when the upper surface of the second interlayer insulating film 10 made of the BPSG film is flattened by the CMP method, pressure by the polishing pad is applied to the BPSG film that is the flattened film, and scratches 19 are generated in the BPSG film. .

  Next, as shown in FIG. 4B, a hydrogen barrier film 20 is formed on the second interlayer insulating film 10 whose upper surface is planarized. Next, after a capacitor electrode composed of a lower electrode, a ferroelectric film or a high dielectric film, and a capacitor element 38 formed of an upper electrode is formed on a predetermined region of the hydrogen barrier film 20, the ferroelectric film Alternatively, a sintering heat treatment is performed at, for example, 600 ° C. or higher in order to develop the characteristics of the high dielectric film.

  Here, when the sintering heat treatment is performed, a local stress imbalance occurs in the hydrogen barrier film 20 due to the scratch 19 generated in the second interlayer insulating film 10, and cracks 21 are generated in the hydrogen barrier film 20. appear.

  When the crack 21 occurs in the hydrogen barrier film 20, hydrogen enters the capacitor element 38 through the crack 21 when the capacitor element is exposed to a hydrogen atmosphere in a subsequent process. For example, hydrogen is formed by plasma nitridation before forming a pad when a contact adhesion layer connecting the semiconductor substrate 1 and a metal wiring is formed by a chemical vapor deposition (CVD) method or when tungsten or the like is buried in a contact hole (via hole). It occurs when a film is formed. As a result of the penetration of hydrogen into the capacitor element 38, the ferroelectric oxide or the like exhibiting hysteresis characteristics is reduced, the residual polarization amount and the like are lowered, the retention (data retention) characteristics are degraded, and finally the nonvolatile semiconductor memory The device yield decreases.

  In particular, in recent years, the memory capacity of nonvolatile semiconductor memory devices tends to increase, the area of the hydrogen barrier film increases, and the stress of the hydrogen barrier film also tends to increase. For this reason, the influence when the sintering heat treatment is applied becomes more prominent, and the above-mentioned problems tend to increase.

  Note that even in a resistance change type nonvolatile semiconductor memory device that utilizes the fact that the resistance state of the thin film is rapidly changed by a specific voltage applied to the thin film, in order to obtain a desired resistance value, 400 to Since heat treatment at 1000 ° C. may be applied, it has the same problem as the ferroelectric memory.

  Therefore, in view of the above problems, the present invention is less likely to cause cracks in the hydrogen barrier film formed under the capacitor element or the variable resistance element even when heat treatment is performed in the nonvolatile semiconductor memory device having a COB structure. An object of the present invention is to provide a non-volatile semiconductor memory device in which memory characteristics are not easily deteriorated even after heat treatment in a hydrogen atmosphere performed in a later process, and a manufacturing method thereof.

  In order to solve the above problems, a method of manufacturing a nonvolatile semiconductor memory device according to an example of the present invention includes a step (a) of forming a bit line on a substrate, and a step of covering the bit line on the substrate. A step (b) of forming an interlayer insulating film, a step (c) of planarizing the upper surface of the interlayer insulating film by polishing, and a hydrogen barrier film is formed on the interlayer insulating film after the step (c). A step (d), a step (e) of forming a capacitive element including a ferroelectric or a high dielectric on the hydrogen barrier film, and sintering the ferroelectric or the high dielectric included in the capacitive element. And (f) performing a heat treatment. The interlayer insulating film has a film thickness variation rate of 2.3% or less due to the heat treatment in the step (f).

  According to this method, since the film thickness variation rate before and after the heat treatment of the interlayer insulating film is 2.3% or less, scratches are less likely to occur when the interlayer insulating film is polished. Therefore, generation of cracks in the hydrogen barrier film can be effectively suppressed. Therefore, it is possible to prevent the ferroelectric or high dielectric material from being deteriorated by hydrogen through cracks when heat treatment is performed in a hydrogen atmosphere or the like. Therefore, the retention (data retention) characteristic is hardly deteriorated, and according to this method, a highly reliable nonvolatile semiconductor memory device can be obtained with a high yield.

  The same effect can be obtained by providing a variable resistance element in place of the capacitive element including a ferroelectric or high dielectric.

  A nonvolatile semiconductor memory device according to an example of the present invention is formed on a bit line formed on a substrate, an interlayer insulating film formed on the substrate so as to cover the bit line, and the interlayer insulating film. A hydrogen barrier film, and a capacitor element formed on the hydrogen barrier film and including a ferroelectric substance or a high dielectric substance. The interlayer insulating film includes a first insulating film that covers the bit line, and a second insulating film having a film density higher than that of the first insulating film.

  According to this configuration, since the interlayer insulating film has the second insulating film having a high film density, it is difficult for scratches to enter the interlayer insulating film during the polishing process during manufacturing. Therefore, almost no cracks are generated in the hydrogen barrier film. Therefore, the penetration of hydrogen into the ferroelectric or high dielectric due to cracks is effectively suppressed.

  According to the nonvolatile semiconductor memory device and the method for manufacturing the same according to an example of the present invention, the hydrogen barrier film formed under the capacitive element or the resistance change element in the COB structure nonvolatile semiconductor memory device even if heat treatment is performed. Cracks are hardly generated in the memory, and deterioration of memory characteristics can be suppressed even after heat treatment in a hydrogen atmosphere, for example.

(A)-(c) is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on one Embodiment of this invention. (A)-(c) is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on one modification of embodiment of this invention. (A) is a figure which shows the result of having implemented the simulation manufacturing process with respect to three types of insulating films, and having investigated the number of generated scratches, (b) is the film thickness fluctuation | variation by heat processing about each insulating film. It is a figure which shows the relationship between a rate and the number of generated cracks. (A), (b) is sectional drawing which shows the subject in the conventional non-volatile semiconductor memory device.

(Embodiment)
A nonvolatile semiconductor memory device and a manufacturing method thereof according to an embodiment of the present invention will be described below with reference to the drawings. 1A to 1C are cross-sectional views illustrating the manufacturing process of the nonvolatile semiconductor memory device according to this embodiment. Note that when not specifically formed, each step is performed using a known method.

  First, as shown in FIG. 1A, an element isolation region 120 is formed at a predetermined location on a semiconductor substrate 110 made of silicon or the like. Next, a gate structure 140 including a gate insulating film and a gate electrode of a transistor is formed on a portion of the semiconductor substrate 110 surrounded by the element isolation region 120. Next, the silicide layer 130 is formed by silicidizing the upper surface portion of the semiconductor substrate 1 except for the region where the gate structure 140 is formed. Note that the sidewalls provided on the side surfaces of the gate structure 140 and the source / drain regions formed on both sides of the gate structure 140 are not shown.

  Next, a first interlayer insulating film 160 made of a sub-atmospheric non-doped silicate glass (SA-NSG) film which is a thermal oxide film covering the transistor is formed on the semiconductor substrate 110 with a film thickness of about 600 nm, for example. The upper surface is planarized by the CMP method.

  Next, a contact hole is formed in the first interlayer insulating film 160 using a lithography method and a dry etching method, and then a Ti / TiN adhesion layer and tungsten (film) are formed in the contact hole by a CVD method. Embed using. Next, the bit line contact 170 is formed by removing the Ti / TiN adhesion layer and the tungsten film remaining on the first interlayer insulating film 160.

  Next, after depositing a Ti / TiN adhesion layer and a tungsten film on the bit line contact 170 in this order, the Ti / TiN adhesion layer and the tungsten film are patterned using a lithography method and a dry etching method to obtain a desired Bit line 180 is formed.

  Next, an SA-NSG film is deposited on the bit line 180 to a thickness of, for example, about 100 nm, and then an HDP-NSG film is deposited to a thickness of, for example, about 500 nm to 700 nm to form a second interlayer insulating film. 100 is formed. Here, the SA-NSG film is an NSG film formed by a thermal CVD method. Thereafter, the upper surface of the second interlayer insulating film 100 is polished and planarized using a CMP method. Note that the thickness of the second interlayer insulating film 100 after polishing is about 250 nm.

  Here, when polishing and planarizing the upper surface of the second interlayer insulating film 100 using the CMP method, a polishing pressure is applied to the second interlayer insulating film 100 by the polishing pad. Scratches do not occur. Hereinafter, the reason will be described with reference to FIGS. 3 (a) and 3 (b).

  The inventors of the present application presumed that the cause of scratches when planarizing the upper surface of the interlayer insulating film by the CMP method is related to the film quality (denseness) and film thickness of the interlayer insulating film, and conducted the following experiment. It was.

  First, as an interlayer insulating film, a BPSG film having a thickness of 500 nm and 1000 nm and an HDP-NSG film were used. The HDP-NSG film is an insulating film grown by a high-density plasma chemical vapor deposition method, and has a very dense film quality as compared with the BPSG film.

  FIG. 3A is a diagram showing the results of examining the number of scratches generated by performing the following simulated manufacturing steps (1) to (4) for the above three types of insulating films.

  (1) Each of the insulating films is formed on a semiconductor substrate.

  (2) The top surface of each insulating film is polished and planarized by the CMP method.

  (3) Each insulating film is heat-treated at 600 ° C. in an oxidizing atmosphere.

  (4) The surface of each insulating film after the heat treatment is observed to determine the number of scratches generated.

  As can be seen from FIG. 3A, the 500 nm BPSG film having the smaller film thickness has the smaller number of scratches in the same film type (BPSG film), and the different film types (500 nm BPSG film, 590 nm film having the same film thickness). In the HDP-NSG film, the HDP-NSG film has a smaller number of scratches.

  The inventors of the present application estimated from this result that the occurrence of scratches is related to the film thickness variation rate due to the heat treatment of the insulating film. Here, the film thickness variation rate is the final film thickness after flattening by polishing or the like after the film thickness reduction due to shrinkage obtained by subtracting the film thickness after shrinkage by heat treatment from the initial growth film thickness of the insulating film (the figure described below) 3 (b) is defined as a percentage expressed by dividing by 250 nm.

  Based on the above definition, it is obvious that the film thickness variation rate due to the heat treatment is smaller when the initial film thickness is smaller in the same film type (BPSG film), and the HDP-NSG film having a dense film quality is almost the same in different film types. It is also obvious that the film thickness fluctuation rate is smaller than that of the BPSG film having no film thickness fluctuation and hence a large film thickness fluctuation.

  Therefore, the inventors of the present invention perform the following simulated manufacturing steps (5) to (7) after performing the simulated manufacturing steps (1) to (4) for the three types of insulating films. The number of cracks generated in the hydrogen barrier film was examined. FIG. 3B is a diagram showing the relationship between the film thickness variation rate due to heat treatment and the number of cracks generated for each insulating film. Note that the number of cracks is standardized as the number per wafer with reference to the case where the insulating film is an HDP-NSG film.

  (5) A hydrogen barrier film made of a TiAlOx film is formed on each insulating film.

  (6) Heat treatment is performed at 600 ° C. in an oxidizing atmosphere for each insulating film and hydrogen barrier film.

  (7) The surface of the hydrogen barrier film after the heat treatment is observed to determine the number of cracks generated.

  From the result shown in FIG. 3 (b), a BPSG film having a film thickness variation rate of about 12% and a film thickness of 1000 nm, a film thickness variation rate of about 6% and a film thickness of 500 nm, and a film thickness variation rate of about 0%. It can be seen that the number of cracks generated in the hydrogen barrier film decreases in the order of the HDP-NSG films. In particular, cracks are not generated in the HDP-NSG film having a film thickness variation rate of about 0%.

  On the other hand, in FIG. 3B, when the experimental value indicating the relationship between the film thickness fluctuation rate of the BPSG film and the number of cracks is extrapolated, the film thickness fluctuation rate is about 2.3% and the number of cracks becomes zero. I understand. Here, the experimental values shown in FIG. 3B are for the case where a BPSG film is used as the insulating film, but among the interlayer insulating films generally used in the semiconductor manufacturing process, the film thickness variation due to the heat treatment is very large. Even if the BPSG film is very large, it can be estimated that the number of cracks will be zero when the film thickness variation rate is about 2.3%, and as an interlayer insulating film formed between the bit line and the capacitor element, Since the final film thickness of the interlayer insulating film after flattening is 250 nm or less, assuming a film type generally used as an interlayer insulating film, the film thickness variation rate is about 2.3% or less. It can be said that almost no cracks occur.

  Based on the results of FIGS. 3 (a) and 3 (b), if an insulating film that hardly causes scratches is formed and a hydrogen barrier film is grown thereon, a local stress imbalance occurs in the hydrogen barrier film. It can be seen that cracks in the hydrogen barrier film can be suppressed.

  In the manufacturing method of this embodiment, after depositing an HDP-NSG film having a thickness of 500 nm to 700 nm on an SA-NSG film having a thickness of about 100 nm, the insulating film is polished to, for example, 250 nm by CMP. Yes. At this time, the film thickness variation before and after the heat treatment of the SA-NSG film is approximately 0 nm, and the film thickness variation of the HDP-NSG film is approximately 0 nm. Therefore, the film thickness variation rate is approximately 0%, which is the above-described 2.3%. Is below.

  For this reason, according to the method of the present embodiment, the second interlayer insulating film 100 is hardly scratched. Therefore, the ferroelectric property or the high dielectric property is hardly deteriorated without being affected by the heat treatment in the hydrogen atmosphere represented by the deposition of the passivation film later. Accordingly, since retention (data retention) characteristics such as the amount of remanent polarization are not deteriorated, a highly reliable nonvolatile semiconductor memory device can be obtained with a high yield according to the method of this embodiment.

  Next, as illustrated in FIG. 1B, a hydrogen barrier film 200 made of TiAlOx is formed on the second interlayer insulating film 100. The hydrogen barrier film 200 has a function of preventing hydrogen from diffusing from below the capacitor 380 (or cell) to the capacitor 380 (cell) in a later step.

  Next, the contact that penetrates the hydrogen barrier film 200, the second interlayer insulating film 100, and the first interlayer insulating film 160 and reaches the silicide layer 130 located on one diffusion layer (not shown) of the transistor. A hole is formed. Subsequently, after the Ti / TiN adhesion layer and tungsten (W) are buried in the contact holes, the Ti / TiN adhesion layer and W formed outside the desired region are removed by CMP to form the capacitor contact 220. Form.

Next, on the capacitor contact 220 and the hydrogen barrier film 200, a barrier layer 230 made of TiN, a conductive hydrogen / oxygen barrier layer 240 made of TiAlN, a first oxygen barrier layer 250 made of iridium (Ir), and IrOx. A second oxygen barrier layer 260 made of Pt, a lower electrode 270 made of Pt, a ferroelectric film 280 made of SBT (SrBi ₂ Ta ₂ O ₉ ) having a crystal structure called a perovskite structure, and an upper electrode 290 made of Pt in this order. Form. In addition, said each film thickness shall be 10-100 nm. The stacked film thus obtained is patterned into a desired shape by a lithography method and a dry etching method to form a capacitor element 380.

  Next, as shown in FIG. 1C, on the substrate (nonvolatile semiconductor memory device being manufactured) including the capacitor element 380, a third interlayer composed of a SA-CVD film which is a thermal oxide film. After the insulating film 400 is deposited with a film thickness of 600 nm, the upper surface of the third interlayer insulating film 400 is planarized by CMP. Next, a heat treatment at 600 to 850 ° C., which is essential for developing ferroelectric characteristics, is applied.

  As described above, in the present embodiment, since the laminated film of the thin SA-NSG film and the HDP-NSG film is adopted as the second interlayer insulating film 100, the film thickness variation rate of the second interlayer insulating film 100. Is 2.3% or less. Scratches hardly occur on the upper surface of the second interlayer insulating film 100 after the CMP process. Therefore, local stress imbalance hardly occurs in the hydrogen barrier film 200 formed on the second interlayer insulating film 100, and cracks in the hydrogen barrier film 200 can be suppressed.

  Therefore, the capacitor element 380 is not affected by the heat treatment in a hydrogen atmosphere, which is typified by deposition of a passivation film later, and the ferroelectric characteristics or the high dielectric characteristics are hardly deteriorated. Therefore, since the retention (data retention) characteristics such as the amount of remanent polarization are hardly deteriorated, according to the manufacturing method of this embodiment, a highly reliable nonvolatile semiconductor memory device can be obtained with a high yield.

  In the above manufacturing method, an example in which a capacitor element having a ferroelectric film is formed has been described. However, by forming a metal oxide film whose resistance value changes in place of the ferroelectric film, reliability is improved with high yield. A high resistance change memory can also be manufactured.

  As shown in FIG. 1C, the nonvolatile semiconductor memory device of this embodiment manufactured by the above method covers a MIS transistor having a gate structure 140 formed on a semiconductor substrate 110 and a MIS transistor. A first interlayer insulating film 160 formed on the semiconductor substrate 110 and a source / drain region (diffusion layer; not shown) of the MIS transistor formed on the first interlayer insulating film 160 via the bit line contact 170. ), The second interlayer insulating film 100 formed on the bit line 180 and on the first interlayer insulating film 160, and the second interlayer insulating film 100. Hydrogen barrier film 200, capacitive element 380 formed on hydrogen barrier film 200, and third interlayer insulation formed on capacitive element 380 and hydrogen barrier film 200 And a 400.

  The capacitor element 380 is formed on the barrier layer 230 formed on the hydrogen barrier film 200, the conductive hydrogen / oxygen barrier layer 240 formed on the barrier layer 230, and the conductive hydrogen / oxygen barrier layer 240. The first oxygen barrier layer 250, the second oxygen barrier layer 260 formed on the first oxygen barrier layer 250, the lower electrode 270 formed on the second oxygen barrier layer 260, and the lower electrode 270 It has a ferroelectric film 280 formed thereon and an upper electrode 290 formed on the ferroelectric film 280.

  The lower electrode 270 is a source / drain of the MIS transistor through the barrier layer 230, the conductive hydrogen / oxygen barrier layer 240, the first oxygen barrier layer 250, the second oxygen barrier layer 260, the capacitor contact 220, and the silicide layer 130. Connected to the other side of the region.

  The second interlayer insulating film 100 is formed on the first insulating film formed on the first interlayer insulating film 160 and the first insulating film, and has a film density higher than that of the first insulating film. 2 insulating films. The first insulating film is, for example, an SA-NSG film, and the second insulating film is, for example, an HDP-NSG film. The HDP-NSG film may be the uppermost layer in the second interlayer insulating film 100, but it is preferable that the HDP-NSG film is not in direct contact with the first interlayer insulating film 160 and the bit line 180.

  Since the second interlayer insulating film 100 has such a configuration, it is difficult for scratches to occur after polishing, and cracks after the heat treatment are hardly seen in the hydrogen barrier film 200.

-Modification of the embodiment-
2A to 2C are cross-sectional views illustrating a manufacturing process of a nonvolatile semiconductor memory device according to a modification of the embodiment of the present invention. Hereinafter, a method for manufacturing the nonvolatile semiconductor device according to this modification will be described.

  First, similarly to the first embodiment, the structure shown in FIG. 2A is obtained through the manufacturing process shown in FIG. Also in this modification, the second interlayer insulating film 100 is a laminated film of a thin SA-NSG film and an HDP-NSG film, and the effects described in the above embodiments can be obtained.

  Next, as illustrated in FIG. 2B, a hydrogen barrier film 200 made of, for example, LP-SiN is formed on the second interlayer insulating film 100. Here, the film thickness of the hydrogen barrier film 200 is, for example, 150 nm, which is thicker than the example shown in FIG.

  Next, it penetrates through the hydrogen barrier film 200, the second interlayer insulating film 100, and the first interlayer insulating film 160 and reaches the silicide layer 130 formed on one source / drain region (not shown) of the MIS transistor. A contact hole is formed.

  Next, after filling the contact hole with a Ti / TiN adhesion layer and tungsten (W) in the contact hole, the Ti / TiN adhesion layer and W formed outside the desired region are removed by CMP to form the capacitor contact 220. Form.

  At this time, when the Ti / TiN adhesion layer and W formed in a region other than the desired region are removed by CMP, the upper end of the plug of the capacitor contact 220 has a concave shape 225 with respect to the upper surface of the surrounding hydrogen barrier film 200. May be. When the capacitor element 380 is formed on the capacitor contact 220 in this state, a gap is formed between the capacitor contact 220 and the bottom portion of the capacitor element 380, and the adhesion between the bottom portion of the capacitor element 380 and the hydrogen barrier film 200 is improved. Deteriorate.

  If the concave shape 225 is left as it is, when hydrogen is subsequently exposed to a heat treatment in a hydrogen atmosphere typified by deposition of a passivation film, hydrogen enters from the above-mentioned poorly adhering portions, resulting in ferroelectric characteristics or high dielectric properties. There is a concern that the body characteristics deteriorate.

  Therefore, for the purpose of relaxing the concave shape 225 at the upper end of the plug of the capacitor contact 220, the upper portion of the hydrogen barrier film 200 is partially polished using the CMP method. The film thickness of the hydrogen barrier film 200 after polishing is, for example, about 130 nm. At the time of polishing, the polishing pressure of the CMP pad is applied to the hydrogen barrier film 200.

  Here, as in the prior art, if there is a scratch when the second interlayer insulating film is planarized by the CMP method, the hydrogen barrier film formed on the second interlayer insulating film is subjected to CMP polishing. Due to the pressure applied to the pad, a local stress imbalance occurs based on the scratch present in the second interlayer insulating film 100. In this case, cracks may occur in the hydrogen barrier film. However, in the method of this modification, the second interlayer insulating film 100 is the same as the method according to the embodiment shown in FIGS. Is a laminated film of a thin SA-NSG film and HDP-NSG film, so that scratches hardly occur. Further, even when the polishing pressure of the polishing pad is applied when polishing the hydrogen barrier film 200 using the CMP method, no scratch is generated in the second interlayer insulating film 100. For this reason, cracks hardly occur in the hydrogen barrier film.

  Note that although an example in which the upper portion of the hydrogen barrier film 200 is removed using the CMP method is shown here, the upper portion of the hydrogen barrier film 200 may be removed by anisotropic etching or the like. However, the effect of the present embodiment that suppresses the generation of cracks can be more exhibited by using the CMP method in which the occurrence of cracks is increased.

  Next, as shown in FIG. 2C, the non-volatile semiconductor device according to this modification can be manufactured through the same steps as in FIG.

  As described above, in the nonvolatile semiconductor memory device according to the present modification, the thin film stack of the SA-NSG film and the HDP-NSG film is used as the second interlayer insulating film 100. Is 2.3% or less. Therefore, even if the hydrogen barrier film 200 is grown on the second interlayer insulating film 100, local stress imbalance does not occur in the hydrogen barrier film, and the generation of cracks in the hydrogen barrier film 200 can be suppressed.

  For this reason, the ferroelectric element or the high dielectric characteristic is hardly deteriorated in the capacitor 380 because it is hardly affected by heat treatment in a hydrogen atmosphere typified by deposition of a passivation film later. Accordingly, since retention (data retention) characteristics such as residual polarization amount are not deteriorated, a highly reliable nonvolatile semiconductor memory device can be obtained with a high yield.

In the embodiment of the present invention and the modification thereof, the lower electrode 270 and the upper electrode 290 are both made of Pt, but are not limited to this, and are made of a noble metal or a conductive compound thereof. Just do it. The lower electrode 270 and the upper electrode 290 include, for example, Ir, ruthenium (Ru), gold (Au), silver (Ag), palladium (Pd), rhodium (Rh) or osmium (Os) oxide, iridium oxide (IrO _2). ), Ruthenium oxide (RuO ₂ ), iron oxide (Fe ₂ O ₃ , Fe ₃ O ₄ ), silver oxide (Ag ₂ O), or the like, or a laminated film thereof can provide the same effect.

In addition, although the material of the ferroelectric film is SBT, the same effect can be obtained if it is a compound having a perovskite structure represented by the general formula ABO ₃ (where A and B are different elements). I can do it. Here, the element A is, for example, lead (Pb), barium (Ba), strontium (Sr), calcium (Ca), lanthanum (La), lithium (Li), sodium (Na), potassium (K), magnesium. (Mg) and at least one selected from the group consisting of bismuth (Bi), and the element B is, for example, titanium (Ti), zirconium (Zr), niobium (Nb), tantalum (Ta), tungsten (W ), Iron (Fe), nickel (Ni), scandium (Sc), cobalt (Co), hafnium (Hf), magnesium (Mg), and molybdenum (Mo). Moreover, the ferroelectric film may be comprised with the bismuth layered compound containing those elements.

In addition to Ir, IrTaOx, RuO ₂ , and Ru can be used for the first oxygen barrier layer 250. For the second oxygen barrier layer 260, any conductive oxide of IrTaOx / RuO ₂ can be used in addition to IrOx.

  Furthermore, in the above embodiment, the hydrogen barrier film 200 is a TiAlOx film, and in the modification, the hydrogen barrier film 200 is an LP-SiN film. However, the TiN film, the TiAlN film, the AlOx film, and the SiN film are the same as described above. The effect of can be obtained.

  When a SiN film by LP-CVD is used as the hydrogen barrier film 200 as in the method according to this modification, the film formation temperature is 600 ° C. or higher, and the second interlayer insulating film 100 is exposed to a high temperature. A hydrogen barrier film 200 is deposited. Therefore, the hydrogen barrier film 200 is easily affected by the scratch of the second interlayer insulating film 100. Therefore, in the present modification, a particularly great effect can be obtained by making the second interlayer insulating film 100 a film with little film thickness variation in the heat treatment at 600 ° C. or higher.

  In the method according to the present embodiment and the modification thereof, the second interlayer insulating film 100 on the bit line 180 is a laminated film of SA-NSG film / HDP-NSG film, but the HDP-NSG film is a single layer. Even in the configuration, there is an effect of preventing the occurrence of cracks in the hydrogen barrier film 200, and there is an effect that the characteristic deterioration of the capacitor element due to hydrogen intrusion from the cracks can be greatly reduced.

  However, if the HDP-NSG film is directly deposited on the bit line 180, there is a concern that plasma damage or sputter damage may occur in the underlying portion. Therefore, as in the above-described embodiment, the second interlayer insulating film 100 has a stacked structure of a film formed without using plasma and an HDP-NSG film, thereby causing plasma damage in the base portion. The fear is removed.

  Further, in the method according to the present embodiment and its modification, the same effect can be obtained by using a BPSG film, a PSG film, and a high aspect ratio process (HARP) film instead of the SA-NSG film. However, when a BPSG film is used, the BPSG film itself undergoes a film thickness variation due to heat treatment, so that the second interlayer insulating film 100 is scratched by sufficiently reducing the film thickness ratio of the BPSG film / HDP-NSG film. It is necessary to make it not in range.

  Further, in the method according to the present embodiment and its modification, the same effect can be obtained even if the HDP-NSG film is replaced with a film type having a small film thickness variation rate such as a PE-TEOS film or LP-SiN.

Further, in the nonvolatile semiconductor memory device according to the present embodiment and its modification, the memory mounting capacity is increased, and the size (surface area) of the hydrogen barrier film 200 covering the substrate exceeds 200 μm × 200 μm (40000 μm ² ) in length and width. In this case, the heat treatment at 600 to 850 ° C., which is indispensable for developing the ferroelectric characteristics, is applied, so that cracks are more likely to be generated due to the local stress imbalance caused by the scratch of the second interlayer insulating film. . Therefore, when the surface area of the hydrogen barrier film 200 is large, the effect of the configuration described in this embodiment is particularly large.

  In addition, when a SiN film having a large film stress is used as the hydrogen barrier film 200, the stress imbalance applied to the film tends to increase locally, so it is desirable that the film thickness be 250 nm or less (greater than 0 nm). .

  Note that even in a variable resistance nonvolatile semiconductor memory device that utilizes the fact that the resistance state of the thin film changes abruptly by a specific voltage applied to the thin film, a metal (refractory metal: W, Mo, Ta, Ti, Ni, In some cases, an oxide of platinum group: Au, Pt and alloys thereof may be used as a thin film material, and a heat treatment at 400 to 1000 ° C. may be applied to the thin film material in order to obtain a desired resistance value. By applying the configuration and method according to the embodiment and its modification, a highly reliable nonvolatile semiconductor memory device can be obtained with high yield.

  As described above, the nonvolatile semiconductor memory device and the manufacturing method thereof according to the present invention are a COB structure nonvolatile semiconductor memory device using a ferroelectric, high-dielectric, or variable resistance layer as a memory layer, and the manufacturing thereof. It is useful as a method and can be mounted on various electronic devices.

100 Second interlayer insulating film 110 Semiconductor substrate 120 Element isolation region 130 Silicide layer 140 Gate structure 160 First interlayer insulating film 170 Bit line contact 180 Bit line 200 Hydrogen barrier film 220 Capacitor contact 225 Concave shape 230 Barrier layer 240 Conductivity Reactive hydrogen / oxygen barrier layer 250 first oxygen barrier layer 260 second oxygen barrier layer 270 lower electrode 280 ferroelectric film 290 upper electrode 380 capacitor 400 third interlayer insulating film

Claims (17)

Forming a bit line on the substrate (a);
Forming an interlayer insulating film on the substrate so as to cover the bit line;
Flattening the upper surface of the interlayer insulating film by polishing (c);
After the step (c), a step (d) of forming a hydrogen barrier film on the interlayer insulating film;
Forming a capacitive element including a ferroelectric or a high dielectric on the hydrogen barrier film (e);
A step (f) of performing a heat treatment for sintering the ferroelectric or the high dielectric contained in the capacitive element,
The method for manufacturing a nonvolatile semiconductor memory device, wherein the interlayer insulating film has a film thickness variation rate of 2.3% or less due to the heat treatment in the step (f). The method for manufacturing a nonvolatile semiconductor memory device according to claim 1,
The heat treatment in the step (f) is a method for manufacturing a nonvolatile semiconductor memory device that is performed at 600 ° C. or higher. Forming a bit line on the substrate (a);
Forming an interlayer insulating film on the substrate so as to cover the bit line;
Flattening the upper surface of the interlayer insulating film by polishing (c);
After the step (c), a step (d) of forming a hydrogen barrier film on the interlayer insulating film;
Forming a variable resistance element on the hydrogen barrier film (e);
And (f) performing a heat treatment at 400 ° C. to 1000 ° C. on the variable resistance element,
The method for manufacturing a nonvolatile semiconductor memory device, wherein the interlayer insulating film has a film thickness variation rate of 2.3% or less due to the heat treatment in the step (f). In the manufacturing method of the non-volatile semiconductor memory device according to claim 1,
A method for manufacturing a nonvolatile semiconductor memory device, further comprising a step of removing an upper portion of the hydrogen barrier film between the steps (d) and (e). The method for manufacturing a nonvolatile semiconductor memory device according to claim 4,
The step of removing the upper portion of the hydrogen barrier film is a method for manufacturing a nonvolatile semiconductor memory device, which is performed by polishing using a CMP method. In the manufacturing method of the non-volatile semiconductor memory device according to claim 1,
The method for manufacturing a nonvolatile semiconductor memory device, wherein a size of the hydrogen barrier film formed in the step (d) is 200 μm × 200 μm or more. In the manufacturing method of the non-volatile semiconductor memory device according to claim 1,
The method for manufacturing a nonvolatile semiconductor memory device, wherein the interlayer insulating film formed in the step (b) has a high-density plasma CVD film that is not in direct contact with the bit line. The method for manufacturing a nonvolatile semiconductor memory device according to claim 7,
In the step (d), an SA-NSG film is formed by thermal CVD so as to cover the bit line, and then an HDP-NSG film is formed on the SA-NSG film by high-density plasma CVD. A method of manufacturing a nonvolatile semiconductor memory device for forming the interlayer insulating film. In the manufacturing method of the non-volatile semiconductor memory device according to claim 1,
In the step (d), a method of manufacturing a nonvolatile semiconductor memory device in which the hydrogen barrier film made of silicon nitride is formed by an LP-CVD method. The method of manufacturing a nonvolatile semiconductor memory device according to claim 9.
A method for manufacturing a nonvolatile semiconductor memory device, wherein the hydrogen barrier film has a thickness of 250 nm or less. A bit line formed on the substrate;
An interlayer insulating film formed on the substrate so as to cover the bit line;
A hydrogen barrier film formed on the interlayer insulating film;
A capacitor element formed on the hydrogen barrier film and including a ferroelectric or a high dielectric;
The nonvolatile semiconductor memory device, wherein the interlayer insulating film includes a first insulating film that covers the bit line and a second insulating film having a film density higher than that of the first insulating film. A bit line formed on the substrate;
An interlayer insulating film formed on the substrate so as to cover the bit line;
A hydrogen barrier film formed on the interlayer insulating film;
A variable resistance element formed on the hydrogen barrier film,
The nonvolatile semiconductor memory device, wherein the interlayer insulating film includes a first insulating film that covers the bit line and a second insulating film having a film density higher than that of the first insulating film. The nonvolatile semiconductor memory device according to claim 11 or 12,
The non-volatile semiconductor memory device, wherein the hydrogen barrier film has a size of 200 μm × 200 μm or more. The nonvolatile semiconductor memory device according to any one of claims 11 to 13,
The non-volatile semiconductor memory device, wherein the interlayer insulating film has a high-density plasma CVD film that is not in direct contact with the bit line as the second insulating film. The nonvolatile semiconductor memory device according to claim 14,
The nonvolatile semiconductor memory device, wherein the first insulating film is an SA-NSG film that covers the bit line, and the second insulating film is an HDP-NSG film formed on the SA-NSG film. The nonvolatile semiconductor memory device according to any one of claims 11 to 15,
The hydrogen barrier film is a nonvolatile semiconductor memory device made of silicon nitride. The nonvolatile semiconductor memory device according to claim 16,
The nonvolatile semiconductor memory device, wherein the hydrogen barrier film has a thickness of 250 nm or less.

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