JP2012015418A - Semiconductor device - Google Patents

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JP2012015418A
JP2012015418A JP2010152377A JP2010152377A JP2012015418A JP 2012015418 A JP2012015418 A JP 2012015418A JP 2010152377 A JP2010152377 A JP 2010152377A JP 2010152377 A JP2010152377 A JP 2010152377A JP 2012015418 A JP2012015418 A JP 2012015418A
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stray capacitance
semiconductor
terminal
output terminal
electrode member
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JP5355506B2 (en
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Tomoyo Egoshi
智代 江越
Sadao Shinohara
貞夫 篠原
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Honda Motor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which reduces a common noise.SOLUTION: The semiconductor device 10 comprises: a semiconductor module 16 including series-connected semiconductor switching elements 11, 12, a positive electrode terminal 13, a negative electrode terminal 14 and an output terminal 15; and a body 17 insulated from the semiconductor module 16. With respect to floating capacitance C1, C3 between the body 17 and the terminals 13, 14, the terminals 13, 14, 15 are disposed in such a manner that between the output terminal 15 and the body 17, floating capacitance C2 of the output terminal 15 and the floating capacitance C1 are connected in series or the floating capacitance C2 of the output terminal 15 is connected in series with the floating capacitance C3.

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

従来、例えば電流経路のインダクタンスが異なる複数の半導体素子に対して、インダクタンス差を相殺するようにインピーダンス差を設けた半導体装置が知られている（例えば、特許文献１参照）。   2. Description of the Related Art Conventionally, for example, a semiconductor device is known in which an impedance difference is provided so as to cancel out an inductance difference for a plurality of semiconductor elements having different current path inductances (see, for example, Patent Document 1).

特開２００５−２６１０３５号公報Japanese Patent Laid-Open No. 2005-261035

ところで、上記従来技術に係る半導体装置においては、インバータモジュールなどの高電圧のパワーモジュールと、例えばパワーモジュールを保持する筐体などのボディとの間は絶縁されており、この絶縁に起因してコモンノイズが発生する。コモンノイズは、スイッチング素子をなす半導体素子のスイッチング速度が速くなるほど増大することから、コモンノイズを低減することが望まれている。   By the way, in the semiconductor device according to the above prior art, a high voltage power module such as an inverter module is insulated from a body such as a housing holding the power module, for example. Noise is generated. Since the common noise increases as the switching speed of the semiconductor element constituting the switching element increases, it is desired to reduce the common noise.

本発明は上記事情に鑑みてなされたもので、コモンノイズを低減することが可能な半導体装置を提供することを目的とする。   The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device capable of reducing common noise.

上記課題を解決して係る目的を達成するために、本発明の第１態様に係る半導体装置は、直列に接続された１対の半導体素子（例えば、実施の形態での半導体スイッチング素子１１，１２）と、前記１対の半導体素子の一方（例えば、実施の形態での半導体スイッチング素子１１）に接続された正極部材（例えば、実施の形態での正極端子（Ｐ）１３）と、前記１対の半導体素子の他方（例えば、実施の形態での半導体スイッチング素子１２）に接続された負極部材（例えば、実施の形態での負極端子（Ｎ）１４）と、前記１対の半導体素子の接続点に接続された出力部材（例えば、実施の形態での出力端子（ＯＵＴ）１５）とを具備する半導体モジュール（例えば、実施の形態での半導体モジュール１６）と、前記半導体モジュールに対して絶縁されたボディ（例えば、実施の形態でのボディ１７）とを備える半導体装置であって、前記ボディと前記正極部材との間の浮遊容量Ｃ１と、前記ボディと前記負極部材との間の浮遊容量Ｃ３とに対して、前記出力部材と前記ボディとの間で、前記出力部材の浮遊容量Ｃ２と前記浮遊容量Ｃ１とが直列接続または前記出力部材の浮遊容量Ｃ２と前記浮遊容量Ｃ３とが直列接続になるようにして、前記出力部材は、前記正極部材または前記負極部材の表面上に積層されて配置されている。   In order to solve the above problems and achieve the object, the semiconductor device according to the first aspect of the present invention includes a pair of semiconductor elements connected in series (for example, the semiconductor switching elements 11 and 12 in the embodiment). ), A positive electrode member (for example, positive electrode terminal (P) 13 in the embodiment) connected to one of the pair of semiconductor elements (for example, the semiconductor switching element 11 in the embodiment), and the one pair The negative electrode member (for example, the negative electrode terminal (N) 14 in the embodiment) connected to the other of the semiconductor elements (for example, the semiconductor switching element 12 in the embodiment) and the connection point of the pair of semiconductor elements A semiconductor module (for example, the semiconductor module 16 in the embodiment) having an output member (for example, the output terminal (OUT) 15 in the embodiment) connected to the semiconductor module, and the semiconductor module A semiconductor device including an insulated body (for example, the body 17 in the embodiment), the stray capacitance C1 between the body and the positive electrode member, and the floating between the body and the negative electrode member The stray capacitance C2 of the output member and the stray capacitance C1 are connected in series between the output member and the body, or the stray capacitance C2 of the output member and the stray capacitance C3 are in series with the capacitance C3. The output member is stacked on the surface of the positive electrode member or the negative electrode member so as to be connected.

さらに、本発明の第２態様に係る半導体装置は、前記浮遊容量Ｃ１と、前記浮遊容量Ｃ２と、前記浮遊容量Ｃ３と、前記ボディとデバイス（例えば、実施の形態でのバッテリ１９）との間の浮遊容量Ｃ０と、前記ボディの浮遊インダクタンスＬｂと、コモンノイズの電流経路に応じた角速度ωとに対して、下記数式（１）および下記数式（２）を満たす。   Furthermore, the semiconductor device according to the second aspect of the present invention includes the stray capacitance C1, the stray capacitance C2, the stray capacitance C3, and the body and the device (for example, the battery 19 in the embodiment). The following mathematical expression (1) and the following mathematical expression (2) are satisfied with respect to the floating capacitance C0, the floating inductance Lb of the body, and the angular velocity ω corresponding to the current path of the common noise.

Figure 2012015418
Figure 2012015418

Figure 2012015418
Figure 2012015418

本発明の第１態様に係る半導体装置によれば、出力部材とボディとの間に正極部材または負極部材が配置されるようにして、正極部材または負極部材の表面上に出力部材を積層して配置することによって、出力部材とボディとの間で、出力部材の浮遊容量Ｃ２と浮遊容量Ｃ１とを直列接続または出力部材の浮遊容量Ｃ２と浮遊容量Ｃ３とを直列接続にすることができる。これにより、出力部材とボディとの間で浮遊容量Ｃ２のみが生じる場合に比べて、出力部材とボディとの間で、出力部材の浮遊容量Ｃ２と浮遊容量Ｃ１とが直列接続または出力部材の浮遊容量Ｃ２と浮遊容量Ｃ３とが直列接続になることで、浮遊容量Ｃ２を小さくすることができる。そして、半導体素子によるスイッチング時の浮遊容量Ｃ２の電圧変動を小さくすることができ、コモンノイズを低減することができる。   According to the semiconductor device of the first aspect of the present invention, the output member is laminated on the surface of the positive electrode member or the negative electrode member so that the positive electrode member or the negative electrode member is disposed between the output member and the body. By arranging, the stray capacitance C2 and stray capacitance C1 of the output member can be connected in series or the stray capacitance C2 and stray capacitance C3 of the output member can be connected in series between the output member and the body. Thereby, compared with the case where only the stray capacitance C2 is generated between the output member and the body, the stray capacitance C2 and the stray capacitance C1 of the output member are connected in series or the floating of the output member between the output member and the body. Since the capacitance C2 and the stray capacitance C3 are connected in series, the stray capacitance C2 can be reduced. And the voltage fluctuation of the stray capacitance C2 at the time of switching by a semiconductor element can be made small, and common noise can be reduced.

本発明の第２態様に係る半導体装置によれば、各浮遊容量Ｃ１，Ｃ３または浮遊容量Ｃ２、あるいは、各浮遊容量Ｃ１，Ｃ３および浮遊容量Ｃ２の大きさを、上記数式（１）および上記数式（２）を満たすようにして、相対的に設定することによって、半導体素子によるスイッチング時の浮遊容量Ｃ２の電圧変動を小さくすることができる。
しかも、浮遊容量Ｃ２で発生した電流は、浮遊容量Ｃ１と浮遊容量Ｃ０、または、浮遊容量Ｃ１と浮遊容量Ｃ３とに分かれて通流することになるが、相対的に浮遊容量Ｃ０に比べてインピーダンスが低い浮遊容量Ｃ１と浮遊容量Ｃ３とに、より大きな電流が流れることから、コモン電流を小さくすることができ、コモンノイズの発生を低減することができる。 According to the semiconductor device of the second aspect of the present invention, the size of each stray capacitance C1, C3 or stray capacitance C2, or each stray capacitance C1, C3 and stray capacitance C2, is expressed by the above formula (1) and the above formula. By relatively setting so as to satisfy (2), the voltage fluctuation of the stray capacitance C2 at the time of switching by the semiconductor element can be reduced.
In addition, the current generated in the stray capacitance C2 is divided into the stray capacitance C1 and the stray capacitance C0, or the stray capacitance C1 and the stray capacitance C3, but the impedance is relatively larger than that of the stray capacitance C0. Since a larger current flows through the low stray capacitance C1 and the stray capacitance C3, the common current can be reduced and the generation of common noise can be reduced.

本発明の実施形態に係る半導体装置の構成図である。1 is a configuration diagram of a semiconductor device according to an embodiment of the present invention. 本発明の実施形態に係る半導体装置の一部の構成図である。It is a partial block diagram of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の実施例と比較例とにおけるコモン電流の時間変化の例を示す図である。It is a figure which shows the example of the time change of the common current in the Example and comparative example of the semiconductor device which concern on embodiment of this invention. 本発明の実施形態の第１変形例に係る半導体装置の一部の構成図である。It is a partial block diagram of the semiconductor device which concerns on the 1st modification of embodiment of this invention. 本発明の実施形態の第２変形例に係る半導体装置の構成図である。It is a block diagram of the semiconductor device which concerns on the 2nd modification of embodiment of this invention. 本発明の実施形態の第２変形例に係る半導体装置の一部の構成図である。It is a one part block diagram of the semiconductor device which concerns on the 2nd modification of embodiment of this invention. 本発明の実施形態の第２変形例に係る半導体装置の実施例と比較例とにおけるコモン電流の時間変化の例を示す図である。It is a figure which shows the example of the time change of the common electric current in the Example and comparative example of the semiconductor device which concern on the 2nd modification of embodiment of this invention. 本発明の実施形態の第３変形例に係る半導体装置の一部の構成図である。It is a one part block diagram of the semiconductor device which concerns on the 3rd modification of embodiment of this invention.

以下、本発明の半導体装置の一実施形態について添付図面を参照しながら説明する。
この実施の形態による半導体装置１０は、例えば車両に搭載されたモータ制御系のインバータ装置などを構成し、例えば図１に示すように、直列に接続された１対の半導体スイッチング素子１１，１２と、正極端子（Ｐ）１３と、負極端子（Ｎ）１４と、出力端子（ＯＵＴ）１５とを具備する半導体モジュール１６と、半導体モジュール１６に対して絶縁されたボディ１７と、負荷１８と、バッテリ１９とを備えて構成されている。 Hereinafter, an embodiment of a semiconductor device of the present invention will be described with reference to the accompanying drawings.
A semiconductor device 10 according to this embodiment forms, for example, an inverter device of a motor control system mounted on a vehicle, and a pair of semiconductor switching elements 11 and 12 connected in series as shown in FIG. A semiconductor module 16 having a positive terminal (P) 13, a negative terminal (N) 14, and an output terminal (OUT) 15, a body 17 insulated from the semiconductor module 16, a load 18, and a battery. 19.

半導体スイッチング素子１１，１２は、例えばＭＯＳＦＥＴ（Metal Oxide Semi-conductor Field Effect Transistor）であって、ハイ側の半導体スイッチング素子１１のソースとロー側の半導体スイッチング素子１２のドレインとが出力端子（ＯＵＴ）１５で接続されていることで、１対の半導体スイッチング素子１１，１２が直列に接続されている。
そして、ハイ側の半導体スイッチング素子１１はドレインが正極端子（Ｐ）１３に接続され、ロー側の半導体スイッチング素子１２はソースが負極端子（Ｎ）１４に接続されている。
なお、各半導体スイッチング素子１１，１２のドレイン−ソース間には、ソースからドレインに向けて順方向となるようにして、各ダイオードが接続されている。
なお、半導体スイッチング素子１１，１２は、例えばＩＧＢＴ（Insulated Gate Bipolar mode Transistor）などであってもよい。 The semiconductor switching elements 11 and 12 are, for example, MOSFETs (Metal Oxide Semi-conductor Field Effect Transistors), and the source of the high-side semiconductor switching element 11 and the drain of the low-side semiconductor switching element 12 are output terminals (OUT). The pair of semiconductor switching elements 11 and 12 are connected in series.
The drain of the high-side semiconductor switching element 11 is connected to the positive terminal (P) 13, and the source of the low-side semiconductor switching element 12 is connected to the negative terminal (N) 14.
In addition, each diode is connected between the drain-source of each semiconductor switching element 11 and 12 so that it may become a forward direction toward a drain from a source.
The semiconductor switching elements 11 and 12 may be, for example, IGBT (Insulated Gate Bipolar Mode Transistor).

そして、正極端子（Ｐ）１３と出力端子（ＯＵＴ）１５との間には負荷１８が接続され、正極端子（Ｐ）１３はバッテリ１９の正極側に接続され、負極端子（Ｎ）１４はバッテリ１９の負極側に接続されている。   A load 18 is connected between the positive terminal (P) 13 and the output terminal (OUT) 15, the positive terminal (P) 13 is connected to the positive side of the battery 19, and the negative terminal (N) 14 is a battery. 19 is connected to the negative electrode side.

正極端子（Ｐ）１３および負極端子（Ｎ）１４は、例えば図２に示す実施例のように、ヒートシンクおよびヒートスプレッタなどから構成される放熱部材２１に共通の絶縁部材２２を介して装着された各電極部材２３Ａ，２３Ｂにより構成されている。
また、出力端子（ＯＵＴ）１５は、負極端子（Ｎ）１４の電極部材２３Ｂの表面上に絶縁部材２２Ｃを介して積層するようにして配置された電極部材２３Ｃにより構成されている。 Each of the positive electrode terminal (P) 13 and the negative electrode terminal (N) 14 is mounted via a common insulating member 22 on a heat radiating member 21 composed of a heat sink and a heat spreader, for example, as in the embodiment shown in FIG. It is comprised by electrode member 23A, 23B.
Further, the output terminal (OUT) 15 is constituted by an electrode member 23C disposed so as to be laminated on the surface of the electrode member 23B of the negative electrode terminal (N) 14 via an insulating member 22C.

そして、正極端子（Ｐ）１３の電極部材２３Ａに半導体スイッチング素子１１が装着されて、半導体スイッチング素子１１のドレインが電極部材２３Ａに接続され、出力端子（ＯＵＴ）１５の電極部材２３Ｃに半導体スイッチング素子１２が装着されて、半導体スイッチング素子１２のドレインが電極部材２３Ｃに接続されている。
そして、半導体スイッチング素子１１のソースは導線２４Ａによって出力端子（ＯＵＴ）１５の電極部材２３Ｃに接続され、半導体スイッチング素子１２のソースは導線２４Ｂによって負極端子（Ｎ）１４の電極部材２３Ｂに接続されている。
なお、各導線２４Ａ，２４Ｂは、例えば複数本のボンディングワイヤが重ねられて形成されることでインダクタンスが低減されて、サージ電圧が低減される。 The semiconductor switching element 11 is mounted on the electrode member 23A of the positive terminal (P) 13, the drain of the semiconductor switching element 11 is connected to the electrode member 23A, and the semiconductor switching element is connected to the electrode member 23C of the output terminal (OUT) 15. 12 is mounted, and the drain of the semiconductor switching element 12 is connected to the electrode member 23C.
The source of the semiconductor switching element 11 is connected to the electrode member 23C of the output terminal (OUT) 15 by the conductive wire 24A, and the source of the semiconductor switching element 12 is connected to the electrode member 23B of the negative electrode terminal (N) 14 by the conductive wire 24B. Yes.
Each of the conductive wires 24A and 24B is formed by, for example, overlapping a plurality of bonding wires, thereby reducing inductance and reducing surge voltage.

この半導体装置１０では、負極端子（Ｎ）１４の表面上に出力端子（ＯＵＴ）１５が積層されて配置されることで、ボディ１７と負極端子（Ｎ）１４との間の浮遊容量Ｃ３に対して、出力端子（ＯＵＴ）１５とボディ１７との間で、出力端子（ＯＵＴ）１５の浮遊容量Ｃ２と浮遊容量Ｃ３とが直列接続になる。このため、浮遊容量Ｃ２が出力端子（ＯＵＴ）１５とボディ１７との間で生じる場合（例えば、出力端子（ＯＵＴ）１５が放熱部材２１に絶縁部材２２Ｃを介して装着された電極部材２３Ｃにより構成される場合など）に比べて、浮遊容量Ｃ２を小さくすることができる。   In the semiconductor device 10, the output terminal (OUT) 15 is stacked on the surface of the negative electrode terminal (N) 14, so that the stray capacitance C 3 between the body 17 and the negative electrode terminal (N) 14 is reduced. Thus, between the output terminal (OUT) 15 and the body 17, the stray capacitance C2 and the stray capacitance C3 of the output terminal (OUT) 15 are connected in series. Therefore, when the stray capacitance C2 is generated between the output terminal (OUT) 15 and the body 17 (for example, the output terminal (OUT) 15 is configured by the electrode member 23C attached to the heat dissipation member 21 via the insulating member 22C). The stray capacitance C2 can be reduced as compared with the case of the above.

例えば図３に示すように、出力端子（ＯＵＴ）１５とボディ１７との間で出力端子（ＯＵＴ）１５の浮遊容量Ｃ２と浮遊容量Ｃ３とが直列接続になる実施例では、各端子１５，１４とボディ１７との間で浮遊容量Ｃ２と浮遊容量Ｃ３とが独立に生じる比較例に比べて、コモン電流のピーク値（Ｉｐｅａｋ）が低減されて、コモンノイズが減少している。   For example, as shown in FIG. 3, in the embodiment in which the stray capacitance C2 and stray capacitance C3 of the output terminal (OUT) 15 are connected in series between the output terminal (OUT) 15 and the body 17, the terminals 15, 14 are connected. As compared with the comparative example in which the stray capacitance C2 and the stray capacitance C3 are generated independently between the body 17 and the body 17, the peak value (Ipeak) of the common current is reduced and the common noise is reduced.

さらに、この半導体装置１０では、ボディ１７と正極端子（Ｐ）１３との間の浮遊容量Ｃ１と、出力端子（ＯＵＴ）１５の浮遊容量Ｃ２と、ボディ１７と負極端子（Ｎ）１４との間の浮遊容量Ｃ３と、ボディ１７と、バッテリ１９およびモータ（図示略）および三相線（図示略）などからなるデバイスとの間の浮遊容量Ｃ０と、ボディ１７の浮遊インダクタンスＬｂと、コモンノイズの電流経路に応じた角速度ωとに対して、下記数式（３），（４）を満たすように設定されている。   Further, in the semiconductor device 10, the stray capacitance C 1 between the body 17 and the positive terminal (P) 13, the stray capacitance C 2 of the output terminal (OUT) 15, and between the body 17 and the negative terminal (N) 14. Stray capacitance C3, the body 17, the stray capacitance C0 between the battery 19 and a device including a motor (not shown), a three-phase wire (not shown), the stray inductance Lb of the body 17, and the common noise The angular velocity ω corresponding to the current path is set so as to satisfy the following formulas (3) and (4).

Figure 2012015418
Figure 2012015418

Figure 2012015418
Figure 2012015418

例えば上記数式（４）に示す浮遊容量Ｃ１，Ｃ３と浮遊容量Ｃ２との相対的な大小は、正極端子（Ｐ）１３の板状の電極部材２３Ａおよび負極端子（Ｎ）１４の板状の電極部材２３Ｂと、出力端子（ＯＵＴ）１５の板状の電極部材２３Ｃとに対して、面積Ｓと厚さｄと誘電率εとのパラメータの少なくとも何れかの大小に応じて設定される。   For example, the relative size of the stray capacitances C1 and C3 and the stray capacitance C2 shown in the above formula (4) is the plate-like electrode member 23A of the positive electrode terminal (P) 13 and the plate-like electrode of the negative electrode terminal (N) 14. For the member 23B and the plate-like electrode member 23C of the output terminal (OUT) 15, it is set according to the size of at least one of the parameters of area S, thickness d, and dielectric constant ε.

上述したように、本発明の実施形態による半導体装置１０によれば、出力端子（ＯＵＴ）１５および負極端子（Ｎ）１４とボディ１７との間で浮遊容量Ｃ２と浮遊容量Ｃ３とが独立に生じる場合に比べて、出力端子（ＯＵＴ）１５とボディ１７との間で、出力端子（ＯＵＴ）１５の浮遊容量Ｃ２と浮遊容量Ｃ３とが直列接続になることで、浮遊容量Ｃ２を小さくすることができる。これにより、半導体スイッチング素子１１，１２によるスイッチング時の浮遊容量Ｃ２の電圧変動を小さくすることができ、コモンノイズを低減することができる。   As described above, according to the semiconductor device 10 according to the embodiment of the present invention, the stray capacitance C2 and the stray capacitance C3 are independently generated between the output terminal (OUT) 15 and the negative electrode terminal (N) 14 and the body 17. Compared to the case, the stray capacitance C2 can be reduced by connecting the stray capacitance C2 and the stray capacitance C3 of the output terminal (OUT) 15 in series between the output terminal (OUT) 15 and the body 17. it can. Thereby, voltage fluctuation of the stray capacitance C2 at the time of switching by the semiconductor switching elements 11 and 12 can be reduced, and common noise can be reduced.

さらに、出力端子（ＯＵＴ）１５とボディ１７との間に負極端子（Ｎ）１４が配置されるようにして、負極端子（Ｎ）１４の表面上に出力端子（ＯＵＴ）１５を積層して配置することによって、出力端子（ＯＵＴ）１５とボディ１７との間で、出力端子（ＯＵＴ）１５の浮遊容量Ｃ２と浮遊容量Ｃ３とを直列接続にすることができる。
しかも、出力端子（ＯＵＴ）１５は負極端子（Ｎ）１４の表面上に配置されることで、放熱性を向上させることができる。 Further, the output terminal (OUT) 15 is laminated on the surface of the negative electrode terminal (N) 14 so that the negative electrode terminal (N) 14 is disposed between the output terminal (OUT) 15 and the body 17. By doing so, the stray capacitance C2 and the stray capacitance C3 of the output terminal (OUT) 15 can be connected in series between the output terminal (OUT) 15 and the body 17.
In addition, the output terminal (OUT) 15 is arranged on the surface of the negative electrode terminal (N) 14, so that heat dissipation can be improved.

さらに、各浮遊容量Ｃ１，Ｃ３または浮遊容量Ｃ２、あるいは、各浮遊容量Ｃ１，Ｃ３および浮遊容量Ｃ２の大きさを、上記数式（３）および上記数式（４）を満たすようにして、相対的に設定することによって、半導体スイッチング素子１１，１２によるスイッチング時の浮遊容量Ｃ２の電圧変動を小さくすることができる。
しかも、浮遊容量Ｃ２で発生した電流は、浮遊容量Ｃ１と浮遊容量Ｃ０、または、浮遊容量Ｃ１と浮遊容量Ｃ３とに分かれて通流することになるが、相対的に浮遊容量Ｃ０に比べてインピーダンスが低い浮遊容量Ｃ１と浮遊容量Ｃ３とに、より大きな電流が流れることから、コモン電流を小さくすることができ、コモンノイズの発生を低減することができる。 Further, the stray capacitances C1 and C3 or the stray capacitance C2, or the stray capacitances C1 and C3 and the stray capacitance C2 are relatively set so that the formulas (3) and (4) are satisfied. By setting, the voltage fluctuation of the stray capacitance C2 at the time of switching by the semiconductor switching elements 11 and 12 can be reduced.
In addition, the current generated in the stray capacitance C2 is divided into the stray capacitance C1 and the stray capacitance C0, or the stray capacitance C1 and the stray capacitance C3, but the impedance is relatively larger than that of the stray capacitance C0. Since a larger current flows through the low stray capacitance C1 and the stray capacitance C3, the common current can be reduced and the generation of common noise can be reduced.

さらに、各電極部材２３Ａ，２３Ｂ，２３Ｃの面積Ｓと厚さｄと誘電率εとのうちの少なくとも何れかにより、各浮遊容量Ｃ０，…，Ｃ３の相対的な大小を容易に設定することができる。
なお、各電極部材２３Ａ，２３Ｂの面積Ｓは、例えば相違していてもよいし、例えば同一であってもよく、例えば同一であれば生産性を向上させることができる。 Furthermore, the relative size of each of the stray capacitances C0,..., C3 can be easily set by at least one of the area S, the thickness d, and the dielectric constant ε of each electrode member 23A, 23B, 23C. it can.
In addition, the area S of each electrode member 23A, 23B may differ, for example, for example, may be the same, for example, if it is the same, productivity can be improved.

なお、上述した実施の形態においては、例えば図４に示す第１変形例のように、正極端子（Ｐ）１３および負極端子（Ｎ）１４に対して、共通の絶縁部材２２の代わりに、個別の各絶縁部材２２Ａ，２２Ｂが備えられてもよい。   In the above-described embodiment, for example, as in the first modification shown in FIG. 4, the positive terminal (P) 13 and the negative terminal (N) 14 are individually provided instead of the common insulating member 22. Insulating members 22A and 22B may be provided.

なお、上述した実施の形態においては、例えば図５，図６に示す第２変形例のように、出力端子（ＯＵＴ）１５は、正極端子（Ｐ）１３の電極部材２３Ａの表面上に絶縁部材２２Ｃを介して積層するようにして配置された電極部材２３Ｃにより構成されてもよい。   In the above-described embodiment, the output terminal (OUT) 15 is an insulating member on the surface of the electrode member 23A of the positive electrode terminal (P) 13, as in the second modification shown in FIGS. You may be comprised by the electrode member 23C arrange | positioned so that it may laminate | stack via 22C.

この第２変形例の半導体装置１０では、正極端子（Ｐ）１３の表面上に出力端子（ＯＵＴ）１５が積層されて配置されることで、ボディ１７と正極端子（Ｐ）１３との間の浮遊容量Ｃ１に対して、出力端子（ＯＵＴ）１５とボディ１７との間で、出力端子（ＯＵＴ）１５の浮遊容量Ｃ２と浮遊容量Ｃ１とが直列接続になる。このため、浮遊容量Ｃ２が出力端子（ＯＵＴ）１５とボディ１７との間で生じる場合（例えば、出力端子（ＯＵＴ）１５が放熱部材２１に絶縁部材２２Ｃを介して装着された電極部材２３Ｃにより構成される場合など）に比べて、浮遊容量Ｃ２を小さくすることができる。   In the semiconductor device 10 according to the second modification, the output terminal (OUT) 15 is stacked on the surface of the positive electrode terminal (P) 13, so that the space between the body 17 and the positive electrode terminal (P) 13 is increased. The stray capacitance C2 and the stray capacitance C1 of the output terminal (OUT) 15 are connected in series between the output terminal (OUT) 15 and the body 17 with respect to the stray capacitance C1. Therefore, when the stray capacitance C2 is generated between the output terminal (OUT) 15 and the body 17 (for example, the output terminal (OUT) 15 is configured by the electrode member 23C attached to the heat dissipation member 21 via the insulating member 22C). The stray capacitance C2 can be reduced as compared with the case of the above.

例えば図７に示すように、出力端子（ＯＵＴ）１５とボディ１７との間で出力端子（ＯＵＴ）１５の浮遊容量Ｃ２と浮遊容量Ｃ１とが直列接続になる実施例では、各端子１５，１３とボディ１７との間で浮遊容量Ｃ２と浮遊容量Ｃ１とが独立に生じる比較例に比べて、コモン電流のピーク値（Ｉｐｅａｋ）が低減されて、コモンノイズが減少している。   For example, as shown in FIG. 7, in the embodiment in which the stray capacitance C2 and the stray capacitance C1 of the output terminal (OUT) 15 are connected in series between the output terminal (OUT) 15 and the body 17, the terminals 15 and 13 are connected. As compared with the comparative example in which the stray capacitance C2 and the stray capacitance C1 are independently generated between the body 17 and the body 17, the peak value (Ipeak) of the common current is reduced and the common noise is reduced.

なお、上述した実施の形態の第２変形例においては、各電極部材２３Ａ，２３Ｂの面積Ｓは、例えば相違していてもよいし、例えば同一であってもよく、例えば同一であれば生産性を向上させることができる。また、負極端子（Ｎ）１４の電極部材２３Ｂには導線２４Ｂが接続されるだけであるから、負極端子（Ｎ）１４の電極部材２３Ｂは、正極端子（Ｐ）１３の電極部材２３Ａに比べて、より小さな面積Ｓであってもよい。   In the second modification of the embodiment described above, the areas S of the electrode members 23A and 23B may be different, for example, may be the same, for example, if they are the same, the productivity Can be improved. Further, since only the conductive wire 24B is connected to the electrode member 23B of the negative electrode terminal (N) 14, the electrode member 23B of the negative electrode terminal (N) 14 is compared with the electrode member 23A of the positive electrode terminal (P) 13. The area S may be smaller.

なお、上述した実施の形態の第２変形例においては、例えば図８に示す第３変形例のように、正極端子（Ｐ）１３および負極端子（Ｎ）１４に対して、共通の絶縁部材２２の代わりに、個別の各絶縁部材２２Ａ，２２Ｂが備えられてもよい。   In the second modification of the above-described embodiment, for example, as in the third modification shown in FIG. 8, a common insulating member 22 is provided for the positive terminal (P) 13 and the negative terminal (N) 14. Instead, individual insulating members 22A and 22B may be provided.

なお、上述した実施の形態および第１〜第３の変形例において、各電極部材２３Ａ，２３Ｂ，２３Ｃの厚さ、あるいは、単一の絶縁部材２２の厚さは、各電極部材２３Ａ，２３Ｂ，２３Ｃに対して異なっていてもよい。   In the above-described embodiment and the first to third modifications, the thickness of each electrode member 23A, 23B, 23C or the thickness of a single insulating member 22 is the same as each electrode member 23A, 23B, It may be different for 23C.

１０ 半導体装置
１１，１２ 半導体スイッチング素子（半導体素子）
１３ 正極端子（正極部材）
１４ 負極端子（負極部材）
１５ 出力端子（出力部材）
１６ 半導体モジュール
１９ バッテリ（デバイス） 10 Semiconductor device 11, 12 Semiconductor switching element (semiconductor element)
13 Positive terminal (positive electrode member)
14 Negative terminal (negative electrode member)
15 Output terminal (output member)
16 Semiconductor module 19 Battery (device)

Claims (2)

直列に接続された１対の半導体素子と、前記１対の半導体素子の一方に接続された正極部材と、前記１対の半導体素子の他方に接続された負極部材と、前記１対の半導体素子の接続点に接続された出力部材とを具備する半導体モジュールと、前記半導体モジュールに対して絶縁されたボディとを備える半導体装置であって、
前記ボディと前記正極部材との間の浮遊容量Ｃ１と、前記ボディと前記負極部材との間の浮遊容量Ｃ３とに対して、前記出力部材と前記ボディとの間で、前記出力部材の浮遊容量Ｃ２と前記浮遊容量Ｃ１とが直列接続または前記出力部材の浮遊容量Ｃ２と前記浮遊容量Ｃ３とが直列接続になるようにして、前記出力部材は、前記正極部材または前記負極部材の表面上に積層されて配置されていることを特徴とする半導体装置。 A pair of semiconductor elements connected in series, a positive electrode member connected to one of the pair of semiconductor elements, a negative electrode member connected to the other of the pair of semiconductor elements, and the pair of semiconductor elements A semiconductor module comprising an output member connected to the connection point, and a body insulated from the semiconductor module,
The stray capacitance of the output member between the output member and the body with respect to the stray capacitance C1 between the body and the positive electrode member and the stray capacitance C3 between the body and the negative electrode member. The output member is laminated on the surface of the positive electrode member or the negative electrode member such that C2 and the stray capacitance C1 are connected in series or the stray capacitance C2 of the output member and the stray capacitance C3 are connected in series. A semiconductor device characterized by being arranged. 前記浮遊容量Ｃ１と、前記浮遊容量Ｃ２と、前記浮遊容量Ｃ３と、前記ボディとデバイスとの間の浮遊容量Ｃ０と、前記ボディの浮遊インダクタンスＬｂと、コモンノイズの電流経路に応じた角速度ωとに対して、下記数式（１）および下記数式（２）を満たすことを特徴とする請求項１に記載の半導体装置。
Figure 2012015418
Figure 2012015418
 The stray capacitance C1, the stray capacitance C2, the stray capacitance C3, the stray capacitance C0 between the body and the device, the stray inductance Lb of the body, and the angular velocity ω corresponding to the current path of common noise, On the other hand, the following mathematical formula (1) and the following mathematical formula (2) are satisfied.
Figure 2012015418
Figure 2012015418
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