JP2005192328A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that has the mounting area reduced by improving a structure of arranging electrode wires. <P>SOLUTION: A positive conductor substrate 10, a negative conductor substrate 12, and an output conductor substrate 14 are provided on an insulated substrate 34. A positive bus bar 16 and a negative one 18 are connected to the positive conductor substrate 10 and the negative conductor substrate 12, and are arranged in an erect condition, in substantially the normal line direction of each corresponding conductor substrate. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to an arrangement structure of electrode lines for inputting / outputting current to / from a circuit provided on a substrate.

  When two wide electrodes are arranged to face each other through an insulator, when currents flowing in opposite directions flow through these electrodes, the magnetic field generated from each electrode is canceled and reduced, and the inductance of the electrodes can be reduced. Is generally known.

  In Japanese Patent Laid-Open No. 2001-332688, two switching elements that open and close complementarily are connected in series, and a high-potential power line and a low voltage from a power source are respectively connected to both ends of the two switching elements connected in series. A potential power line is connected, and further, an output line to the load is drawn from the connection point of the two switching elements, and each power line and output line is formed by a wide electrode having a width larger than the thickness, In addition, a semiconductor device having a three-layer wide electrode structure in which a high potential power line, an output line, and a low potential power line are stacked in this order through an insulator in the thickness direction is disclosed.

According to the present invention, since the same current that flows in the output line flows in either the high-potential power line or the low-potential power line in the opposite direction to the output line, the magnetic field generated by the current can be canceled, thereby reducing the wiring inductance. Can be effectively reduced.
JP 2001-332688 A JP-A-6-38507

  However, in the semiconductor device described in Japanese Patent Laid-Open No. 2001-332688, the three-layer wide electrode is provided in parallel to the insulating substrate on which the switching element is mounted, so that the mounting area of the semiconductor device is increased.

  Accordingly, the present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor device having a reduced mounting area by improving the arrangement structure of electrode lines.

  Another object of the present invention is to provide a semiconductor device in which the arrangement structure of electrode lines is improved to reduce the mounting area and the wiring inductance of the electrodes is reduced.

  According to the present invention, the semiconductor device includes the first and second electrode lines that input and output current to a circuit provided on the substrate, and each of the first and second electrode lines is an abbreviated method of the substrate. It is pulled out from the substrate in the line direction.

  Preferably, each of the first and second electrode lines is a wide electrode plate having a width larger than the thickness.

  Preferably, the second electrode line inputs and outputs a current to and from the circuit in a direction opposite to the direction of the current flowing through the first electrode line, and the first and second electrode lines are arranged close to and parallel to each other. Established.

  Preferably, the first and second electrode lines are stacked in the thickness direction via an insulating layer.

  According to the invention, the semiconductor device includes the first and second switching circuits connected in series between the first and second power lines, and having the third power line connected to each connection portion. A first power line, a first electrode line for inputting / outputting current to / from a first switching circuit provided on the substrate, and a second power line. And the 3rd electrode line which constitutes the 2nd electrode line which inputs and outputs current to the 2nd switching circuit provided on the substrate, and the 3rd power line, and inputs and outputs current to the connection part And the first to third electrode lines are drawn from the substrate in a substantially normal direction of the substrate.

  Preferably, the third electrode line inputs / outputs a current to / from the connection portion in a direction opposite to the direction of the current flowing through the first electrode line, and the second electrode line transmits / receives a current flowing through the third electrode line. A current is input to and output from the second switching circuit in a direction opposite to the direction, and each of the first to third electrode lines is a wide electrode plate having a width larger than the thickness, and the first to third electrode lines Are laminated in the thickness direction through an insulating layer in the order of the first electrode line, the third electrode line, and the second electrode line.

  Preferably, the semiconductor device further includes first to third conductor substrates which are provided on the substrate and to which the first to third electrode lines are respectively connected, and the first and third conductor substrates are: The second conductor substrate is disposed so as to be surrounded by the third conductor substrate, and the first to third electrode lines are disposed from the first to third conductors. A part of each of the substrates is connected to a portion disposed in the order of the first conductor substrate, the third conductor substrate, and the second conductor substrate.

  Preferably, the first and second switching circuits are mounted on the first and third conductor substrates, respectively, and are electrically connected to the third and second conductor substrates, respectively.

  Preferably, the semiconductor device further includes first to third conductor substrates that are provided on the substrate and to which the first to third electrode lines are connected, respectively, and the second and third conductor substrates are: The first conductor substrate is disposed so as to be surrounded by the third conductor substrate, and the first to third electrode lines are disposed from the first to third conductors. A part of each of the substrates is connected to a portion disposed in the order of the first conductor substrate, the third conductor substrate, and the second conductor substrate.

  Preferably, the first and second switching circuits are mounted on the third and second conductor substrates, respectively, and are electrically connected to the first and third conductor substrates, respectively.

  Preferably, each of the first and second switching circuits includes a switching transistor and a free-wheeling diode provided in parallel with the switching transistor, and the first and second electrode lines are positive and negative power lines, respectively. Yes, the third electrode line is connected to an electrical load.

  In the semiconductor device according to the present invention, since the first and second electrode lines are drawn from the substrate in the substantially normal direction of the substrate, the first and second electrode lines do not occupy a large area in the planar direction of the substrate. .

  Therefore, according to the present invention, the mounting area of the semiconductor device can be reduced.

  In the semiconductor device according to the present invention, the first and second electrode lines are formed of wide electrode plates, but the first and second electrode lines are drawn from the substrate in a direction substantially normal to the substrate. The second electrode line does not occupy a large area in the plane direction of the substrate.

  Therefore, according to the present invention, the mounting area of the semiconductor device can be reduced.

  In the semiconductor device according to the present invention, the first and second electrode lines through which currents in opposite directions flow are arranged close to each other in parallel, so that the magnetic fields generated from the electrodes are canceled out.

  Therefore, according to the present invention, the wiring inductance of each electrode can be reduced.

  In the semiconductor device according to the present invention, since the wide first and second electrode lines are laminated in the thickness direction via the insulating layer, the magnetic field generated from each electrode is canceled out.

  Therefore, according to the present invention, the wiring inductance of each electrode can be reduced.

  In the semiconductor device according to the present invention, since the first to third electrode lines are drawn from the substrate in a direction substantially normal to the substrate, the first to third electrode lines have a large area in the plane direction of the substrate. Do not occupy.

  Therefore, according to the present invention, the mounting area of the semiconductor device can be reduced.

  In the semiconductor device according to the present invention, the wide first to third electrode lines through which the current in the direction opposite to that of the adjacent electrode lines flows are stacked in the thickness direction via the insulating layer. The generated magnetic field is canceled out.

  Therefore, according to the present invention, the wiring inductance of each electrode can be reduced.

  In the semiconductor device according to the present invention, the first and third conductor substrates are disposed adjacent to each other in the plane direction of the substrate, and the second conductor substrate is disposed so as to be surrounded by the third conductor substrate. Since the first to third electrode lines are connected to portions where a part of each of the first to third conductor substrates is arranged in the order of the first, third, and second conductor substrates, The third electrode lines are close to each other and stacked, and are drawn from the substrate in a direction substantially normal to the substrate.

  Therefore, according to the present invention, the mounting area of the semiconductor device can be reduced, and the wiring inductance of each electrode can be reduced.

  In the semiconductor device according to the present invention, the second and third conductor substrates are disposed adjacent to each other in the plane direction of the substrate, and the first conductor substrate is disposed so as to be surrounded by the third conductor substrate. Since the first to third electrode lines are connected to portions where a part of each of the first to third conductor substrates is arranged in the order of the first, third, and second conductor substrates, The third electrode lines are close to each other and stacked, and are drawn from the substrate in a direction substantially normal to the substrate.

  Therefore, according to the present invention, the mounting area of the semiconductor device can be reduced, and the wiring inductance of each electrode can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a circuit diagram showing a configuration of a main part of a load driving device shown as an example of a semiconductor device according to the present invention.

  Referring to FIG. 1, load driving apparatus 100 includes a converter 210, an inverter 220, signal generation circuits 230 and 240, a control circuit 250, a current sensor 260, and smoothing capacitors C1 and C2. Converter 210 includes a reactor L1, power transistors Q1 and Q2, drivers 271 and 272, and diodes D1 and D2. Inverter 220 includes power transistors Q3 to Q8, drivers 273 to 278, and diodes D3 to D8.

  The battery 200 that is a DC power source is made of, for example, a secondary battery such as nickel metal hydride or lithium ion, and supplies a DC voltage to the load driving device 100 and is charged by the DC voltage from the load driving device 100.

  The rotating machine M1 is a three-phase AC synchronous rotating machine or an induction rotating machine, and receives AC power from the inverter 220 to generate a rotational driving force. The rotating machine M1 is also used as a generator, and the voltage generated by the power generation action (regenerative power generation) during deceleration is stepped down using the converter 210 and supplied to the battery 200.

  Power transistors Q1 and Q2 constituting converter 210 are made of, for example, an IGBT (Insulated Gate Bipolar Transistor). Power transistors Q1, Q2 are connected in series between power supply line 292 and ground line 293. In addition, diodes D1 and D2 are connected between the collector and emitter of each of the power transistors Q1 and Q2 so that current flows from the emitter side to the collector side.

  Drivers 271 and 272 receive PWM (Pulse Width Modulation) signals S1 and S2 from signal generation circuit 230, respectively, and perform switching operations of power transistors Q1 and Q2 based on the PWM signals S1 and S2, respectively.

  Reactor L1 boosts the DC voltage from battery 200 by accumulating the current flowing through the coil as magnetic field energy in accordance with the switching operation of power transistor Q2, and power transistor Q2 is turned off from the boosted DC voltage. The power is supplied to the power supply line 292 through the diode D1 in synchronization with the timing.

  Smoothing capacitor C1 is connected between power supply line 291 and ground line 293, and reduces the influence on battery 200 and converter 210 due to voltage fluctuation.

  Similarly to power transistors Q1 and Q2, power transistors Q3 to Q8 constituting inverter 220 are made of IGBT, for example. Power transistors Q3 and Q4 constitute a U-phase arm 281; power transistors Q5 and Q6 constitute a V-phase arm 282; power transistors Q7 and Q8 constitute a W-phase arm 283; V-phase arm 282 and W-phase arm 283 are connected in parallel between power supply line 292 and ground line 293. Further, diodes D3 to D8 that flow current from the emitter side to the collector side are connected between the collectors and emitters of the power transistors Q3 to Q8, respectively.

  Drivers 273 to 278 receive PWM signals S3 to S8 from signal generation circuit 240, respectively, and perform switching operations of power transistors Q3 to Q8 based on the PWM signals S3 to S8, respectively.

  And the connection point of each power transistor in each phase arm is connected to each phase end of each phase coil of rotating machine M1. That is, the rotating machine M1 is configured such that one end of three coils of U, V, and W phases is commonly connected to the middle point, and the other end of the U phase coil is connected to the connection point of the power transistors Q3 and Q4. The other end of the V-phase coil is connected to the connection point of the transistors Q5 and Q6, and the other end of the W-phase coil is connected to the connection point of the power transistors Q7 and Q8.

  Smoothing capacitor C2 is connected between power supply line 292 and ground line 293, and reduces the influence on inverter 220 and converter 210 due to voltage fluctuation.

  The signal generation circuit 230 receives the calculation result of the duty ratio of the power transistors Q1 and Q2 calculated by the control circuit 250 from the control circuit 250, and generates PWM signals S1 and S2 for turning on / off the power transistors Q1 and Q2. Output to the drivers 271 and 272 of the converter 210, respectively.

  The signal generation circuit 240 receives the voltage calculation result of each phase calculated by the control circuit 250 from the control circuit 250, generates PWM signals S3 to S8 for turning on / off the power transistors Q3 to Q8, and each driver of the inverter 220 273 to 278.

  The control circuit 250 inputs the motor torque command value, the current value of each phase of the rotating machine M1, and the input voltage of the inverter 220, calculates the voltage of each phase coil of the rotating machine M1, and calculates the calculation result as a signal generation circuit. Output to 240. The current value of each phase of the rotating machine M1 is detected by the current sensor 260, and the input voltage of the inverter 220 is detected by a voltage sensor (not shown).

  In addition, the control circuit 250 calculates the optimum value (target value) of the input voltage of the inverter 220 by inputting the motor torque command value and the motor rotation speed described above. Based on the target value of the input voltage, the input voltage of the inverter 220, and the voltage of the battery 200, the control circuit 250 uses the duty ratios of the power transistors Q1 and Q2 for setting the input voltage of the inverter 220 to the target value. And the calculation result is output to the signal generation circuit 230.

  In the above, each upper arm in inverter 220 and converter 210 constitutes a “first switching circuit”, and each lower arm in inverter 220 and converter 210 constitutes a “second switching circuit”. The power supply line 292 and the ground line 293 constitute a “first power line” and a “second power line”, respectively, and the output lines 294 to 296 constitute a “third power line”. The power transistors Q1 to Q8 constitute a “switching transistor”, and the diodes D1 to D8 constitute a “freewheeling diode”.

  In the load driving device 100, the chopper converter 210 boosts the DC voltage received from the battery 200 based on a command from the signal generation circuit 230 and supplies it to the power supply line 292. Inverter 220 receives the DC voltage smoothed by smoothing capacitor C2 from power supply line 292, converts the received DC voltage into an AC voltage, and outputs the AC voltage to rotating machine M1.

  The inverter 220 converts the AC voltage generated by the rotating machine M1 into a DC voltage and outputs the DC voltage to the power line 292. Converter 210 receives the DC voltage smoothed by smoothing capacitor C <b> 2 from power supply line 292, steps down the received DC voltage, and supplies it to battery 200.

  As described above, the load driving device 100 boosts the DC voltage from the battery 200 to drive the rotating machine M1, and supplies the battery 200 with the electric power generated by the rotating machine M1.

  2 is a plan view showing the structure of the U-phase arm of inverter 220 shown in FIG. 1, and FIG. 3 is a cross-sectional view showing the structure of section UIII-III of the U-phase arm shown in FIG. is there. As shown in FIG. 3, a bus bar ASSY 42 is provided on the upper surface of the U-phase arm. However, in FIG. 2, the bus bar ASSY 42 is not shown because the inside of the U-phase arm is shown. . The structure of each of the other phase arms of inverter 220 shown in FIG. 1 and the arm of converter 210 are also the same as the structure of the U-phase arm shown in FIGS.

  2 and 3, the U-phase arm includes power transistors Q31, Q32, Q41, and Q42, diodes D31, D32, D41, and D42, a positive conductor substrate 10, a negative conductor substrate 12, and an output. The conductive substrate 14, the positive electrode bus bar 16, the negative electrode bus bar 18, the insulating layer 22, the wires 26 to 32, the insulating substrate 34, the bolt 36, the support column 37, and the cooler 38 are included.

  Power transistors Q31 and Q32 and diodes D31 and D32 constitute the U-phase upper arm shown in FIG. That is, the U-phase upper arm shown in the circuit diagram of FIG. 1 is actually composed of two power transistors Q31 and Q32 connected in parallel and two diodes D31 and D32 connected in parallel to them. ing. The power transistors Q31 and Q32 and the diodes D31 and D32 are mounted on the positive conductor substrate 10 and are electrically connected to the positive conductor substrate 10.

  Power transistors Q41 and Q42 and diodes D41 and D42 constitute the U-phase lower arm shown in FIG. That is, the U-phase lower arm shown in the circuit diagram of FIG. 1 is actually composed of two power transistors Q41 and Q42 connected in parallel and two diodes D41 and D42 connected in parallel to them. ing. The power transistors Q41 and Q42 and the diodes D41 and D42 are mounted on the output conductor substrate 14 and are electrically connected to the output conductor substrate 14.

  The positive conductor substrate 10, the negative conductor substrate 12 and the output conductor substrate 14 are electrode plates made of, for example, copper, and are provided on the insulating substrate 34. A positive electrode bus bar 16 and a negative electrode bus bar 18 are connected to the positive electrode conductor substrate 10 and the negative electrode conductor substrate 12, respectively, and an output bus bar (not shown) is also connected to the output conductor substrate 14.

  That is, the positive conductor substrate 10 electrically connects the power transistors Q31 and Q32 and the diodes D31 and D32 mounted on the positive conductor substrate 10 to the positive bus bar 16.

  The output conductor substrate 14 has a concave shape, and is disposed adjacent to the positive electrode conductor substrate 10 so that the concave portion faces the positive electrode conductor substrate 10. The power transistors Q 31 and Q 32 and the diodes D 31 and D 32 and the wires 26, 28, and is electrically connected. That is, the output conductor substrate 14 includes power transistors Q31, Q32 and diodes D31, D32 electrically connected by wires 26, 28, and power transistors Q41, Q42 and diodes D41, D42 mounted on the output conductor substrate 14. Connect electrically.

  The negative electrode conductor substrate 12 is disposed adjacent to the positive electrode conductor substrate 10 so as to fit in the recess of the output conductor substrate 14, and is mounted on the output conductor substrate 14 with power transistors Q 41 and Q 42 and diodes D 41 and D 42 and wires 30. , 32 are electrically connected. In other words, the negative conductor substrate 12 electrically connects the power transistors Q41 and Q42 and the diodes D41 and D42 electrically connected by the wires 30 and 32 to the negative bus bar 18.

  The positive electrode bus bar 16 and the negative electrode bus bar 18 are wide electrodes wider than a thickness made of, for example, copper.

  The positive electrode bus bar 16 is erected on the positive electrode conductor substrate 10 so as to be close to the negative electrode conductor substrate 12 and so that the wide surface faces the negative electrode conductor substrate 12. The positive bus bar 16 constitutes the power supply line 292 shown in FIG. 1, is wired in the bus bar ASSY 42, and is connected to the positive conductor substrate of each other upper arm in the inverter 220.

  The negative electrode bus bar 18 is erected on the negative electrode conductor substrate 12 so as to be close to the positive electrode bus bar 16 and so that the wide surface faces the wide surface of the positive electrode bus bar 16. This negative electrode bus bar 18 constitutes the ground line 293 shown in FIG. 1, is wired in the bus bar ASSY 42, and is connected to the negative electrode conductor substrate of each other lower arm in the inverter 220.

  The insulating layer 22 is provided between the positive electrode bus bar 16 and the negative electrode bus bar 18 and electrically insulates the positive electrode bus bar 16 and the negative electrode bus bar 18.

  The wires 26 to 32 are electric wires made of aluminum, for example. The wire 26 electrically connects the power transistor Q31 and the diode D31 to the output conductor substrate 14, and the wire 28 electrically connects the power transistor Q32 and the diode D32 to the output conductor substrate 14. The wire 30 electrically connects the power transistor Q41 and the diode D41 to the negative electrode conductor substrate 12, and the wire 32 electrically connects the power transistor Q42 and the diode D42 to the negative electrode conductor substrate 12.

  The insulating substrate 34 electrically insulates the positive conductor substrate 10, the negative conductor substrate 12 and the output conductor substrate 14 from the cooler 38. On the other hand, insulating substrate 34 contains a filler having a high thermal conductivity such as alumina, for example, and heat transferred from power transistors Q31 and Q32 and diodes D31 and D32 to positive electrode conductor substrate 10 and power transistors Q41 and Q42 and Heat transferred from the diodes D41 and D42 to the output conductor substrate 14 is transferred to the cooler 38.

  The cooler 38 includes a plurality of refrigerant paths 40 therein, and dissipates heat generated from the power transistors Q31, Q32, Q41, Q42 and the diodes D31, D32, D41, D42 to the refrigerant flowing through the refrigerant path 40.

  The bus bar ASSY 42 is a housing and wiring case for the positive electrode bus bar 16 and the negative electrode bus bar 18 that are provided on the upper side of the substrate in parallel with the substrate and are drawn out from the positive electrode conductor substrate 10 and the negative electrode conductor substrate 12 in the normal direction.

  In the above, the positive electrode bus bar 16 and the negative electrode bus bar 18 constitute a “first electrode line” and a “second electrode line”, respectively.

  In this U-phase arm, positive electrode bus bar 16 and negative electrode bus bar 18 stand on positive electrode conductor substrate 10 and negative electrode conductor substrate 12, respectively. That is, each bus bar is drawn from the corresponding conductor substrate in the normal direction of the substrate. Therefore, the positive electrode bus bar 16 and the negative electrode bus bar 18 do not occupy a large area in plan in this semiconductor device.

  Further, in this U-phase arm, power transistor Q31 and diode D31 mounted on positive conductor substrate 10 and power transistor Q32 and diode D32 are arranged symmetrically on both sides of positive conductor substrate 10, and output conductor substrate By arranging the power transistor Q41 and the diode D41, and the power transistor Q42 and the diode D42 mounted on the board 14 symmetrically toward the center of the output conductor substrate 14, the wiring distance of each wire 26 to 32 is made as short as possible and evenly. It is. Therefore, the wiring inductance variation in each of the wires 26 to 32 is small.

  As described above, according to the first embodiment of the present invention, the positive electrode bus bar 16 and the negative electrode bus bar 18 are drawn in the normal direction of the positive electrode conductor substrate 10 and the negative electrode conductor substrate 12, respectively. Can reduce the mounting area of the load driving device 100 without occupying a large area in the plane direction of the device.

[Embodiment 2]
The overall configuration of the load driving device 100A according to the second embodiment is the same as the configuration of the load driving device 100 according to the first embodiment shown in FIG.

  4 is a plan view showing the structure of the U-phase arm of the inverter according to the second embodiment, and FIG. 5 is a cross-sectional view showing the structure of the cross-section VV of the U-phase arm shown in FIG. As shown in FIG. 5, a bus bar ASSY 42 is provided on the upper surface of the U-phase arm. However, in FIG. 4, the bus bar ASSY 42 is not shown because the inside of the U-phase arm is shown. . In addition, the structure of each of the other phase arms in the inverter and the arm of the converter is the same as the structure of the U-phase arm shown in FIGS.

  Referring to FIGS. 4 and 5, this U-phase arm has the same structure as that of the first embodiment shown in FIGS. 2 and 3, but negative electrode substrate 12, output conductor substrate 14, positive electrode bus bar 16, negative electrode bus bar. 18 and the insulating layer 22 are replaced with a negative electrode conductor substrate 12A, an output conductor substrate 14A, a positive electrode bus bar 16A, a negative electrode bus bar 18A, and insulating layers 22A and 22B, and further includes an output bus bar 20.

  The negative conductor substrate 12A and the output conductor substrate 14A are electrode plates made of, for example, copper, and are provided on the insulating substrate 34. A negative electrode bus bar 18A and an output bus bar 20 are connected to the negative electrode conductor substrate 12A and the output conductor substrate 14A, respectively.

  The output conductor substrate 14 </ b> A is disposed adjacent to the positive electrode conductor substrate 10. Power transistors Q41 and Q42 and diodes D41 and D42 are mounted on the output conductor substrate 14A, and the power transistors Q41 and Q42 and the diodes D41 and D42 are electrically connected. The output conductor substrate 14A is electrically connected to the power transistors Q31 and Q32 and the diodes D31 and D32 by wires 26 and 28. That is, the output conductor substrate 14A electrically connects the power transistors Q31 and Q32 and the diodes D31 and D32 electrically connected by the wires 26 and 28 to the output bus bar 20, and is further mounted on the output conductor substrate 14A. Power transistors Q41 and Q42 and diodes D41 and D42 are electrically connected to output bus bar 20.

  The negative conductor substrate 12A is disposed so as to be surrounded by the output conductor substrate 14A, and is electrically connected to the power transistors Q41 and Q42 and the diodes D41 and D42 mounted on the output conductor substrate 14A by the wires 30 and 32. That is, negative electrode conductor substrate 12A electrically connects power transistors Q41 and Q42 and diodes D41 and D42, which are electrically connected by wires 30 and 32, to negative electrode bus bar 18A.

  The positive electrode bus bar 16A, the negative electrode bus bar 18A, and the output bus bar 20 are wide electrodes that are wider than a thickness made of, for example, copper.

  The positive electrode bus bar 16A is erected on the positive electrode conductor substrate 10 so as to be close to the output conductor substrate 14A and to have a wide surface facing the output conductor substrate 14A. The positive bus bar 16A constitutes the power supply line 292 shown in FIG. 1, is wired in the bus bar ASSY 42, and is connected to the positive conductor substrate of the other upper arm of each inverter 220.

  The output bus bar 20 is erected on the output conductor substrate 14A so as to be close to the positive electrode bus bar 16A and so that the wide surface faces the wide surface of the positive electrode bus bar 16A. The output bus bar 20 constitutes a U-phase output line 294 shown in FIG. 1, and is wired in the bus bar ASSY 42 and connected to a U-phase coil of a rotating machine M1 (not shown).

  The negative electrode bus bar 18 </ b> A is erected on the negative electrode conductor substrate 12 </ b> A so as to be close to the output bus bar 20 and so that the wide surface faces the wide surface of the output bus bar 20. The negative bus bar 18A constitutes the ground line 293 shown in FIG. 1, is wired in the bus bar ASSY 42, and is connected to the negative conductor substrate of the other lower arm of each inverter 220.

  The insulating layers 22A and 22B are provided between the positive electrode bus bar 16A and the output bus bar 20, and between the negative electrode bus bar 18A and the output bus bar 20, respectively, and electrically insulate the positive electrode bus bar 16A, the output bus bar 20 and the negative electrode bus bar 18A. To do.

  Since other wires 26 to 32, insulating substrate 34, cooler 38, and bus bar ASSY 42 have already been described in the first embodiment, description thereof will not be repeated.

  In the above, the positive electrode bus bar 16A, the negative electrode bus bar 18A, and the output bus bar 20 constitute a “first electrode line”, a “second electrode line”, and a “third electrode line”, respectively. The negative conductor substrate 12A and the output conductor substrate 14A constitute a “first conductor substrate”, a “second conductor substrate”, and a “third conductor substrate”, respectively. The power transistors Q31 and Q32 and the diodes D31 and D32 constitute a “first switching circuit”, and the power transistors Q41 and Q42 and the diodes D41 and D42 constitute a “second switching circuit”. Further, each power transistor Q31, Q32, Q41, Q42 constitutes a “switching transistor”, and each diode D31, D32, D41, D42 constitutes a “reflux diode”.

  Also in this U-phase arm, as in the first embodiment, positive electrode bus bar 16A, negative electrode bus bar 18A, and output bus bar 20 are erected on positive electrode conductor substrate 10, negative electrode conductor substrate 12A, and output conductor substrate 14A, respectively. That is, each bus bar is drawn from the corresponding conductor substrate in the normal direction of the substrate. Therefore, positive electrode bus bar 16A, negative electrode bus bar 18A, and output bus bar 20 do not occupy a large area in plan in this semiconductor device.

  Further, in this U-phase arm, an output conductor substrate 14A is disposed adjacent to the positive electrode conductor substrate 10, and further, a negative electrode conductor substrate 12A is disposed so as to be surrounded by the output conductor substrate 14A. The positive electrode conductor board 10, the output conductor board 14A, and the negative electrode conductor board 12A are partially adjacent to each other in that order, and the positive electrode bus bar 16A, the output bus bar 20, and the negative electrode bus bar 18A are interposed through the insulating layers 22A and 22B, respectively. It is set up close.

  Here, since currents in opposite directions flow through the adjacent positive electrode bus bar 16A and output bus bar 20, and output bus bar 20 and negative electrode bus bar 18A, the magnetic fields generated from the bus bars when the current flows through the bus bars are mutually different. It cancels out and cancels out.

  FIG. 6 is a diagram for explaining this, and FIG. 6 is a circuit diagram showing an example of a current flow in the load driving device 100A according to the second embodiment. In FIG. 6, the current output from battery 200 includes the upper arm of U-phase arm 281 of inverter 220, the U-phase coil and V-phase coil of rotating machine M 1, and the lower arm of V-phase arm 282 of inverter 220. The case where the battery 200 is recirculated to the battery 200 is shown representatively. In FIG. 6, description of the converter 210 is omitted.

  Referring to FIG. 6, inverter 220 includes upper arm 281.1 of U-phase arm 281, positive bus bar 16.1 and output bus bar 20.1 erected on arm 281.1, and V-phase arm 282. Lower arm 282.2, and negative electrode bus bar 18.2 and output bus bar 20.2 standing on arm 282.2 are included. The positive electrode bus bar 16.1, the negative electrode bus bar 18.2, and the output bus bar 20.1, 20.2 correspond to the positive electrode bus bar 16A, the negative electrode bus bar 18A, and the output bus bar 20 shown in FIGS. The reference numerals are newly assigned to the arms 281.1 and 282.2.

  The current output from battery 200 flows through positive electrode bus bar 16.1 and is supplied to arm 281.1. Then, the current flows from the arm 281.1 through the output bus bar 20.1 and is supplied to the rotating machine M1, flows through the U-phase coil and the V-phase coil of the rotating machine M1, and then flows through the output bus bar 20.2. 282.2. Then, the current flows from the arm 282.2 through the negative electrode bus bar 18.2 to the battery 200.

  That is, in U-phase arm 281, currents flow in opposite directions in adjacent positive electrode bus bar 16.1 and output bus bar 20.1, so magnetic fields generated from positive electrode bus bar 16.1 and output bus bar 20.1 cancel each other. It will be offset. Further, in V-phase arm 282, currents flow in opposite directions through adjacent output bus bar 20.2 and negative electrode bus bar 18.2, so that magnetic fields generated from output bus bar 20.2 and negative electrode bus bar 18.2 cancel each other. It will be offset. Therefore, the wiring inductance in each bus bar is reduced.

  As described above, according to the second embodiment of the present invention, positive electrode bus bar 16A, negative electrode bus bar 18A, and output bus bar 20 are drawn in the normal direction of positive electrode conductor substrate 10, negative electrode conductor substrate 12A, and output conductor substrate 14A, respectively. Therefore, the positive electrode bus bar 16A, the negative electrode bus bar 18A, and the output bus bar 20 do not occupy a large area in the planar direction of the device, and the mounting area of the load driving device 100A can be reduced.

  Further, according to the second embodiment, the wide positive bus bar 16A, the output bus bar 20 and the negative bus bar 18A are stacked adjacent to each other in the thickness direction in this order via the insulating layers 22A and 22B, and adjacent to each other. Since currents flowing in opposite directions flow through the positive bus bar 16A and the output bus bar 20 and the output bus bar 20 and the negative bus bar 18A, the magnetic field generated from each bus bar is canceled out, and the wiring inductance of each bus bar is reduced.

[Embodiment 3]
The overall configuration of the load driving device 100B according to the third embodiment is the same as the configuration of the load driving device 100 according to the first embodiment shown in FIG.

  FIG. 7 is a plan view showing the structure of the U-phase arm of the inverter according to the third embodiment, and FIG. 8 is a cross-sectional view showing the structure of section VIII-VIII of the U-phase arm shown in FIG. As shown in FIG. 8, a bus bar ASSY 42 is provided on the upper surface of the U-phase arm. However, in FIG. 7, the bus bar ASSY 42 is not shown because the inside of the U-phase arm is shown. . Further, the structure of each other phase arm in the inverter and the arm of the converter is the same as the structure of the U-phase arm shown in FIGS.

  7 and 8, the U-phase arm of the inverter according to the third embodiment includes power transistors Q31, Q32, Q41, and Q42, diodes D31, D32, D41, and D42, a positive conductor substrate 50, and a negative electrode. Conductor substrate 52, output conductor substrate 54, positive electrode bus bar 56, negative electrode bus bar 58, output bus bar 60, insulating layers 62 and 64, wires 66 to 72, insulating substrate 34, bolt 36, and column 37. And a cooler 38.

  In the third embodiment, power transistors Q31 and Q32 and diodes D31 and D32 are mounted on output conductor substrate 54 and electrically connected to output conductor substrate 54. The power transistors Q41 and Q42 and the diodes D41 and D42 are mounted on the negative conductor substrate 52 and are electrically connected to the negative conductor substrate 52.

  The positive conductor substrate 50, the negative conductor substrate 52 and the output conductor substrate 54 are mounted on the insulating substrate 34, and the negative conductor substrate 52 and the output conductor substrate 54 are disposed adjacent to each other and surrounded by the output conductor substrate 54. A positive conductor substrate 50 is provided.

  The positive electrode bus bar 56, the output bus bar 60, and the negative electrode bus bar 58 are wide electrodes, and the insulating layers 62 and 64 are located at positions where parts of the positive electrode conductor substrate 50, the output conductor substrate 54, and the negative electrode conductor substrate 52 are adjacent to each other in that order. Are installed in close proximity to each other.

  The power transistors Q31 and Q32 and the diodes D31 and D32 constituting the upper arm are electrically connected to the positive conductor substrate 50 by the wires 66 and 68, and the power transistors Q41 and Q42 and the diodes D41 and D42 constituting the lower arm. Are electrically connected to the output conductor substrate 54 by wires 70 and 72.

  Since other insulating substrate 34, cooler 38, and bus bar ASSY 42 have already been described in the first embodiment, description thereof will not be repeated.

  In the above description, the positive electrode bus bar 56, the negative electrode bus bar 58, and the output bus bar 60 constitute a “first electrode line”, a “second electrode line”, and a “third electrode line”, respectively, and the positive electrode conductor substrate 50. The negative electrode conductor substrate 52 and the output conductor substrate 54 constitute a “first conductor substrate”, a “second conductor substrate”, and a “third conductor substrate”, respectively.

  Also in the U-phase arm of the inverter according to the third embodiment, positive electrode bus bar 56, negative electrode bus bar 58 and output bus bar 60 are erected on positive electrode conductor substrate 50, negative electrode conductor substrate 52 and output conductor substrate 54, respectively. That is, each bus bar is drawn from the corresponding conductor substrate in the normal direction of the substrate. Therefore, the positive electrode bus bar 56, the negative electrode bus bar 58, and the output bus bar 60 do not occupy a large area in plan in this semiconductor device.

  Similarly to the second embodiment described with reference to FIG. 6, currents in opposite directions flow through the adjacent positive electrode bus bar 56 and output bus bar 60, and output bus bar 60 and negative electrode bus bar 58. When the current flows through the magnetic field, the magnetic fields generated from the bus bars cancel each other and cancel each other. Therefore, the wiring inductance in each bus bar is reduced.

  As described above, according to the third embodiment of the present invention, positive electrode bus bar 56, negative electrode bus bar 58 and output bus bar 60 are drawn in the normal direction of positive electrode conductor substrate 50, negative electrode conductor substrate 52 and output conductor substrate 54, respectively. Therefore, the positive electrode bus bar 56, the negative electrode bus bar 58, and the output bus bar 60 do not occupy a large area in the plane direction of the device, and the mounting area of the load driving device can be reduced.

  Further, according to the third embodiment, the wide positive electrode bus bar 56, the output bus bar 60, and the negative electrode bus bar 58 are stacked adjacent to each other in the thickness direction in this order via the insulating layers 62 and 64, and adjacent to each other. Since currents flowing in opposite directions flow through the positive bus bar 56 and the output bus bar 60 and the output bus bar 60 and the negative bus bar 58, the magnetic fields generated from the bus bars are canceled out, and the wiring inductance of each bus bar is reduced.

  In each of the above-described embodiments, the load driving device is representatively described as an example of the semiconductor device according to the present invention. However, the scope of application of the present invention is not limited to the load driving device. The present invention can be applied to all semiconductor devices.

  The semiconductor device according to the present invention is suitable for, for example, a hybrid vehicle and an electric vehicle that have attracted much attention in recent years. That is, in such a vehicle system, downsizing, high efficiency, reliability, and the like are strongly required. According to this semiconductor device, as described above, it contributes to downsizing by reducing the mounting area of the device. In addition, according to the semiconductor device according to the second and third embodiments, by reducing the wiring inductance, the loss can be reduced, that is, the efficiency can be improved, and the reliability of the device can be improved by reducing the surge voltage during switching. This is because it can be realized.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include meanings equivalent to the scope of claims for patent and all modifications within the scope.

It is a circuit diagram which shows the structure of the principal part of the load drive device shown as an example of the semiconductor device by this invention. It is a top view which shows the structure of the U-phase arm of the inverter shown by FIG. It is sectional drawing which shows the structure of the cross section III-III of the U-phase arm shown by FIG. FIG. 6 is a plan view showing a structure of a U-phase arm of an inverter according to a second embodiment. FIG. 5 is a cross-sectional view illustrating a structure of a cross section VV of the U-phase arm illustrated in FIG. 4. FIG. 6 is a circuit diagram showing an example of a current flow in a load driving device according to a second embodiment. FIG. 6 is a plan view showing a structure of a U-phase arm of an inverter in a third embodiment. It is sectional drawing which shows the structure of the cross section VIII-VIII of the U-phase arm shown by FIG.

Explanation of symbols

  10, 50 Positive conductor board, 12, 12A, 52 Negative conductor board, 14, 14A, 54 Output conductor board, 16, 16A, 16.1, 56 Positive bus bar, 18, 18A, 18.2, 58 Negative bus bar, 20 20, 20.2, 60 Output bus bar, 22, 22A, 22B, 62, 64 Insulating layer, 26-32, 66-72 wire, 34 Insulating substrate, 36 volts, 37 strut, 38 cooler, 40 refrigerant Road, 42 Busbar ASSY, 100, 100A, 100B Load drive device, 200 Battery, 210 Converter, 220 Inverter, 230, 240 Signal generation circuit, 250 Control circuit, 260 Current sensor, 271-278 Driver, 281 U-phase arm, 281 .1 U-phase upper arm, 282 V-phase arm, 282.2 V-phase lower arm, 2 83 W-phase arm, 291, 292 Power line, 293 Ground line, 294 U-phase output line, 295 V-phase output line, 296 W-phase output line, C1, C2 smoothing capacitor, L1 reactor, Q1-Q8, Q31, Q32, Q41, Q42 Power transistor, D1-D8, D31, D32, D41, D42 Diode, M1 Rotating machine.

Claims (11)

Comprising first and second electrode lines for inputting and outputting current to a circuit provided on the substrate;
Each of the first and second electrode lines is a semiconductor device drawn from the substrate in a substantially normal direction of the substrate.   2. The semiconductor device according to claim 1, wherein each of the first and second electrode lines is a wide electrode plate having a width larger than a thickness. The second electrode line inputs and outputs a current to and from the circuit in a direction opposite to the direction of the current flowing through the first electrode line.
The semiconductor device according to claim 2, wherein the first electrode line and the second electrode line are disposed in parallel and close to each other.   The semiconductor device according to claim 3, wherein the first and second electrode lines are stacked in a thickness direction via an insulating layer. A semiconductor device including first and second switching circuits connected in series between first and second power lines and having a third power line connected to each connection portion,
A first electrode line that constitutes the first power line and inputs / outputs a current to / from the first switching circuit provided on the substrate;
A second electrode line that constitutes the second power line and inputs and outputs a current to and from the second switching circuit provided on the substrate;
Comprising the third power line, and a third electrode line for inputting and outputting current to the connection portion;
The semiconductor device, wherein the first to third electrode lines are drawn from the substrate in a substantially normal direction of the substrate. The third electrode line inputs and outputs current to and from the connection part in a direction opposite to the direction of current flowing through the first electrode line.
The second electrode line inputs and outputs current to and from the second switching circuit in a direction opposite to the direction of the current flowing through the third electrode line.
Each of the first to third electrode lines is a wide electrode plate having a width larger than a thickness,
The first to third electrode lines are stacked in the thickness direction through an insulating layer in the order of the first electrode line, the third electrode line, and the second electrode line. The semiconductor device described. Further comprising first to third conductor substrates provided on the substrate and connected to the first to third electrode lines, respectively.
The first and third conductive substrates are disposed adjacent to each other in a planar direction of the substrate;
The second conductive substrate is disposed so as to be surrounded by the third conductive substrate,
In the first to third electrode lines, a part of the first to third conductive substrates is arranged in the order of the first conductive substrate, the third conductive substrate, and the second conductive substrate. The semiconductor device according to claim 5, connected to the semiconductor device.   The first and second switching circuits are mounted on the first and third conductor substrates, respectively, and are electrically connected to the third and second conductor substrates, respectively. The semiconductor device described. Further comprising first to third conductor substrates provided on the substrate and connected to the first to third electrode lines, respectively.
The second and third conductor substrates are disposed adjacent to each other in a planar direction of the substrate;
The first conductor substrate is disposed so as to be surrounded by the third electrode substrate,
In the first to third electrode lines, a part of the first to third conductive substrates is arranged in the order of the first conductive substrate, the third conductive substrate, and the second conductive substrate. The semiconductor device according to claim 5, connected to the semiconductor device.   The first and second switching circuits are mounted on the third and second conductive substrates, respectively, and are electrically connected to the first and third conductive substrates, respectively. The semiconductor device described. Each of the first and second switching circuits includes:
A switching transistor;
A free-wheeling diode provided in parallel with the switching transistor,
The first and second electrode lines are positive and negative power lines, respectively.
The semiconductor device according to claim 5, wherein the third electrode line is connected to an electric load.

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