JP2012008028A - Connector half-insertion detector, connector connection warning method, and connector connection warning program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a connector half-insertion detector, a connector connection warning method, and a connector connection warning program that can precisely determine the transient state of a connection between connector terminals.SOLUTION: An applying means 11b in the testing mode of a first circuit part 11 applies binary logic level voltage to a specific terminal of a first connector 11a alternately multiple times. A signal returned from a second connector 12a that engages with the first connector 11a is checked by a connection quality determination means 11c, and then the quality of a connector connection is determined based on the relationship between the signal and a waveform of the applied voltage.

Description

  The present invention relates to a connector half-insertion detecting device for detecting a half-insertion state in which a plurality of circuits are connected with each other between connectors and the connection between the connectors is insufficient and a problem occurs in the terminal connection. The present invention relates to a connector connection warning method and a connector connection warning program.

  For example, several female connectors for connecting cards are arranged on a motherboard provided in the main body of a computer. A user attaches male connectors attached to a desired card to each of these female connectors one by one, and adds a circuit function of these cards to the apparatus main body.

  By the way, if the connectors are connected incompletely, there is a possibility that, for example, power terminals (pins) are not connected to each other so that power is not supplied to the card side or some signals are not transmitted. In this specification, as a result of incompletely attaching the connectors to each other, a state in which a connection failure occurs in at least some of the terminals constituting the connector is expressed as a “half-insertion state”.

  As a first related technique of the present invention, it has been proposed to send a monitoring signal from a first printed circuit board to a second printed circuit board and examine the logic state of the returned signal (see, for example, Patent Document 1). . Further, as a second related technique of the present invention, it has been proposed to determine a connector mounting state between control boards respectively mounted on a plurality of connectors arranged on a main control board (see, for example, Patent Document 2). ).

  In the second related technique, the main control board is provided with wiring for connecting the specific terminals of a pair of connectors arranged on the main control board. The other specific terminals of the pair of connectors are both grounded. The connector of the first control board mounted on the pair of connectors arranged on the main control board is electrically connected between the terminal contacting the specific terminal and the terminal contacting the grounding terminal. A pattern is printed in advance. The second control board connector attached to the pair of connectors arranged on the main control board is applied to each of the terminal contacting the specific terminal and the terminal contacting the grounding terminal. A power supply and a CPU (Central Processing Unit) for monitoring the application of voltage by these power supplies are arranged.

  As described above, according to the first and second related technologies, whether or not each terminal of the pair of connectors directly connected or the pair of connectors connected via the main control board is connected is determined by the voltage at the time of measurement. The determination is made based on whether the logic level is H (high) level or L (low) level.

Republished patent WO 2007/091332 (paragraphs 0067 to 0071, FIG. 9) JP 2002-372564 A (the 0027th paragraph to the 0038th paragraph, the 0043th paragraph, FIG. 2)

  By the way, it is assumed that the terminals of the male connector are not completely pushed into the female connector and the connection between the connectors is incomplete. In such a case, even if most of the terminals constituting the connector are securely connected to each other, some of the terminals may be in an unstable connection with the opposing terminals. is there.

  In such a case, if the measurement is performed using the first or second related technique, a normal result that there is no uninserted or half-inserted state of the connector at a certain point in time can be obtained. Then, an abnormal result will be obtained if the connector is not inserted or half inserted. For this reason, depending on the connection state of the connector, the measurement result using the first or second related technique may not be reliable.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a connector half-insertion detecting device, a connector connection warning method, and a connector connection warning program that can more accurately determine a transient state of connection between terminals where a connector is half-inserted. It is in.

  In the present invention, (a) a first connector in which a plurality of terminals are arranged, and one or more predetermined terminals among them are held at one potential of a binary logic level via a predetermined resistor. And a predetermined pair terminal paired with each one of the specific terminals in the plurality of terminals described above, in the specific test mode, the above-described one of the two logic levels and the other potential The test mode application means for applying the potential by switching the potential a plurality of times as time elapses, and the first described above from the relationship between the potential appearing at the specific terminal and the potential applied to the pair terminal in the test mode. A first circuit section comprising: a connection quality judgment means for judging quality of connection between terminals of the first connector and the second connector connected to the first connector; Connector The above-described second connector in which a plurality of terminals that are connected in a one-to-one relationship with the plurality of terminals described above are arranged, and each of these terminals makes a one-to-one contact with the plurality of terminals in the first connector described above. And a conduction means for electrically conducting between the two terminals respectively corresponding to the pair terminals described above and paired with the specific terminals of the first connector in the second connector. The connector half-insertion detecting device includes the second circuit unit.

  In the present invention, (a) a predetermined pair that is paired with a specific terminal when a predetermined potential is applied to the specific terminal of the first connector on the board on which a plurality of first connectors are arranged. By monitoring the potential appearing at the terminal for use, a card device in which a second connector in which a conductor is connected between two terminals respectively corresponding to the specific terminal and the paired terminal described above is disposed on the board. A card device that detects that the attachment to the first connector has been started by sending a signal to the specific terminal of the first connector and detecting the signal returned to the pair terminal. A mounting start detection step; and (b) predetermined in this card device mounting start detection step after detecting that the card device starts mounting on the board. When it is not detected that the corresponding second connector has been connected to all of the first connectors before the time of 1 elapses, a warning that the card device is not installed exists. And (c) when it is detected that the corresponding second connector is connected to all of the first connectors before the first time elapses. In this connection state, a signal whose logic level is inverted at a predetermined duty ratio is continuously applied to the specific terminal of the first connector described above for a plurality of periods, and the signal appearing at the pair terminal at this time When the state of the change in the logic level is not the same for a plurality of cycles within a predetermined allowable range, the incomplete connection between the first connector and the second connector described above Half inserted state warning step and the connector connection warning method semi inserted state outputs a warning as is judged as to comprise.

  Furthermore, in the present invention, as a connector connection warning program, (a) when a predetermined potential is applied to the specific terminal of the first connector on the board on which a plurality of first connectors are arranged, the specific terminal By monitoring the potential appearing at a predetermined pair terminal to be paired with, a second connector in which a conductor is connected between the above-mentioned specific terminal and two terminals respectively corresponding to the above-mentioned pair terminal is arranged. When the card device is started to be attached to the first connector of the board, a signal is sent to the specific terminal of the first connector and a signal folded back to the pair terminal is sent. Card device attachment start detection processing detected by detecting, and (b) the card device described in the card device attachment start detection processing is attached to the substrate. When it is not detected that the corresponding second connectors are connected to all of the first connectors until a predetermined first time elapses after the start is detected, Non-installation warning processing for outputting a warning that the card device is not installed as described above, and (c) the above-described first corresponding to all of the first connectors before the first time elapses. When it is detected that two connectors are connected, a signal whose logic level is inverted at a predetermined duty ratio is continuously applied for a plurality of cycles to the specific terminal of the first connector described above in this connected state. At this time, when the state of the change in the logic level of the signal appearing at the pair terminal is not the same for the plurality of cycles within the predetermined allowable range, it is the same as that of the first connector described above. Half inserted state of the incomplete connection state of the second connector is characterized in that to execute a half-inserted condition warning process to output a warning as is determined that.

  As described above, according to the present invention, the voltage of the binary logic level is applied to the terminals while switching a plurality of times in the test mode to detect the connection state between the terminals. Therefore, it is possible to accurately determine whether or not the connector is connected in various environments such as an environment in which vibrations occur and an environment in which temperature changes occur, as well as changes over time.

  In addition, according to the present invention, the time when the connector is started to be mounted is detected, and the connector is not mounted or the half-inserted state is discriminated from this point as a starting point. It is possible to efficiently determine whether the card device is connected or not when it is incorporated.

It is a claim corresponding | compatible figure of the connector half-insertion detection apparatus of this invention. It is a claim corresponding | compatible figure of the connector connection warning method of this invention. It is a claim corresponding | compatible figure of the connector connection warning program of this invention. 1 is a system configuration diagram of a half-insertion detection system for cards according to an embodiment of the present invention. It is a block diagram showing the outline | summary of a structure of the half-insertion detection LSI used in this Embodiment. It is a wave form diagram showing the waveform change of the output signal which the output signal generating part used by this embodiment outputs. It is explanatory drawing which showed the change of the electric potential which appears in a 1st female connector in the state which the terminal corresponding to a 1st male connector is not connected in this Embodiment. It is explanatory drawing which showed the change of the electric potential which appears in a 1st female connector in the state in which the corresponding terminal of the 1st male connector is connected in this Embodiment. It is explanatory drawing which showed the waveform of the input signal to the half-insertion detection LSI when it is determined that the connection of the connector is normally performed and the card is not half-inserted in the present embodiment. It is explanatory drawing which showed an example of the waveform of the input signal to LSI for half-insertion detection in the case of determining with it being a card half-insertion state in this Embodiment. It is the flowchart which showed the 1st step of the control which checks the connection of the connector which starts from the time of mounting of a card | curd in the apparatus side back substrate in this Embodiment. It is a flowchart showing the process which determines the presence or absence of an unmounted card | curd as a 2nd step in this Embodiment. It is a flowchart showing the process which determines whether the card mounted as a process of the 3rd step in this Embodiment is contacting the terminal normally, or is contacting the terminal in the half-insertion state.

  FIG. 1 is a diagram corresponding to the claims of the connector half-insertion detecting device of the present invention. The connector half-insertion detection device 10 of the present invention includes a first circuit unit 11 and a second circuit unit 12. Here, the first circuit unit 11 includes a first connector 11a, a test mode application unit 11b, and a connection quality determination unit 11c. The first connector 11a has a plurality of terminals, and one or more predetermined terminals among them are held at one potential of a binary logic level via a predetermined resistor. The test mode application means 11b is connected to a predetermined pair terminal that is paired with each of the specific terminals in the plurality of terminals described above, and the one of the two logic levels described above in the specific test mode. It is means for applying the potential and the other potential by switching a plurality of times over time. The connection pass / fail judgment means 11c is connected to the first connector 11a and the first connector 11a from the relationship between the potential appearing at the specific terminal and the potential applied to the pair terminal as described above in the test mode. The quality of the connection between the terminals with the second connector 12a is determined. The second circuit unit 12 includes a second connector 12a and conduction means 12b. The second connector 12a includes a plurality of terminals that are connected in a one-to-one relationship with the plurality of terminals of the first connector 11a, and these terminals are the plurality of terminals of the first connector 11a. One-to-one. The conducting means 12b electrically conducts between two terminals respectively corresponding to the above-described pair terminals that are paired with the specific terminals of the first connector 11a in the second connector 12a.

  FIG. 2 is a diagram corresponding to claims of the connector connection warning method of the present invention. The connector connection warning method 20 of the present invention includes a card device attachment start detection step 21, a non-attachment warning step 22, and a half-insertion state warning step 23. Here, in the card device installation start detection step 21, when a predetermined potential is applied to the specific terminal of the first connector on the board on which a plurality of first connectors are arranged, the card device is previously paired with the specific terminal. The card device in which the second connector in which the conductor is connected between the two terminals respectively corresponding to the specific terminal described above and the paired terminal described above is monitored by monitoring the potential appearing at the predetermined pair terminal. Detection of the start of attachment to the first connector on the board is detected by sending a signal to the specific terminal of the first connector and detecting the signal returned to the pair terminal. To do. In the non-installation warning step 22, the above-described first time period elapses after the card device installation start detection step 21 detects that the card device starts to be attached to the board as described above. When it is not detected that the corresponding second connector is connected to all of the connectors, a warning that the card device is not installed is output. In the half-insertion state warning step 23, when it is detected that the corresponding second connectors are connected for all the first connectors before the first time has elapsed, this connection state is detected. Then, a signal whose logic level is inverted at a predetermined duty ratio is continuously applied to the specific terminal of the first connector described above for a plurality of periods, and at this time, the logic level of the signal appearing at the pair terminal is set. When the state of change is not the same for a plurality of cycles within a predetermined allowable range, a warning is given that the half-insertion state as the incomplete connection state between the first connector and the second connector is determined. Output.

  FIG. 3 shows a claim correspondence diagram of the connector connection warning program of the present invention. The connector connection warning program 30 according to the present invention causes the computer to execute a card device attachment start detection process 31, a non-installation warning process 32, and a half-insertion state warning process 33. Here, in the card device installation start detection process 31, when a predetermined potential is applied to a specific terminal of the first connector on the board on which a plurality of first connectors are arranged, a pair with the specific terminal is previously set. The potential appearing at the specified pair terminal is monitored. Then, the card device in which the second connector in which the conductor is connected between the two terminals respectively corresponding to the specific terminal and the pair terminal described above is attached to the first connector of the board described above. This is detected by sending a signal to the specific terminal of the first connector and detecting the signal folded back to the pair terminal as described above. In the non-installation warning process 32, the above-described first time elapses after the card apparatus installation start detection process 31 detects that the card apparatus has been attached to the board as described above. When it is not detected that the corresponding second connector is connected to all of the one connectors, a warning that the card device is not installed is output. In the half-insertion state warning process 33, when it is detected that the corresponding second connectors have been connected for all of the first connectors before the first time has elapsed, this connection state Then, a signal whose logic level is inverted at a predetermined duty ratio is continuously applied to the specific terminal of the first connector described above for a plurality of periods. At this time, when the change in the logic level of the signal appearing at the pair terminal is not the same for the plurality of cycles within a predetermined tolerance, the first connector and the second A warning is output when the half-insertion state as an incomplete connection state of the connector is determined.

  <Embodiment of the Invention>

  Next, an embodiment of the present invention will be described.

FIG. 4 shows a half-insertion detection system for cards according to an embodiment of the present invention. In the half-insertion detection system 100 for a card according to the present embodiment, first to Mth female connectors 102 _{1 to} 102 _M are attached to an apparatus-side rear substrate 101 such as a mother board. However, M is an integer of 1 or more. The first to the female connector 102 ₁ to 102 _M of the M, the male connector 104 ₁ of the first to M attached one each to the first to the card 103 ₁ 10 @ 2 to 10 @ 3 _M of the M -104 _M can be connected.

Of course, it may not be necessary to connect the first to Mth male connectors 104 _{1 to} 104 _M one by one to all of the first to Mth female connectors 102 _{1 to} 102 _M. In addition, for terminals having the same terminal arrangement state among the _first to M-th female connectors 102 _{1 to} 102 _M , the terminals of the first to M-th male connectors 104 _{1 to} 104 _M are arranged. In many cases, any of the same state may be connected.

In addition to the first to Mth female connectors 102 _{1 to} 102 _M , various circuits and devices are mounted on the apparatus-side rear substrate 101. Here, only a circuit and a device for detecting half-insertion of a card are illustrated. In the present embodiment, pull-up resistors (111 ₁₁ ,..., 111 _1K ),..., (111 _M1 ,... Provided corresponding to the _first to Mth female connectors 102 _{1 to} 102 _M are used. 111 _MK ), half-insertion detection LSI (Large Scale Integration) 112, and half-insertion alarm LED (Light Emitting Diode) 113 correspond to these.

For the first male connector 104 ₁ in the first to M-th cards 103 _{1 to} 103 _M , a jumper line 121 _1A is connected between the first terminal P ₁ and the second terminal P ₂ , and the Kth The jumper wire 121 _1B is connected between the −1 terminal P _K-1 and the Kth terminal P _K. The same applies to the _{second to} Mth male connectors 104 ₂ (not shown) to 104 _M. However, K is the number of the terminals P which one connector has, and is an integer of 5 or more.

Thus, for the card 103 _M of the M, the first terminal P ₁ and the jumper wire 121 _KA is connected to the second between the terminals P _2, terminals of the K-1 of the terminal P _K-1 and the K A jumper line 121 _KB is connected between P _K. In this way, jumper wires 121 _1A , 121 _1B ,..., 121 _KA , 121 _KB are connected to both ends of the _first to Mth male connectors 104 _{1 to} 104 _M , respectively. This is easy to detect when the first to Mth male connectors 104 _{1 to} 104 _M are mounted in an inclined state with respect to the first to Mth female connectors 102 _{1 to} 102 _M. It is to do.

The other end of the first terminal P ₁ is connected at one end to the line 131 _11A in the device-side rear first female connector 102 _first substrate 101 side is connected to the signal sending terminal 132 _11A of LSI112 for out semi挿検ing. Further, the other end of the line 131 _11B having one end connected to the second terminal P ₂ is connected to the signal receiving terminal 132 _11B of the half-insertion detecting LSI 112. One end of the pull-up resistor 111 ₁₁ is connected to the line 131 _11B , and the other end of the pull-up resistor 111 ₁₁ is connected to the power supply line 133.

Further, the other end of the line 131 _KA having one end connected to the (K-1) th terminal P _K-1 in the first female connector 102 ₁ is connected to the signal sending terminal 132 _1KA of the half-insertion detecting LSI 112. Yes. Further, the other end of the line 131 _1KB having one end connected to the Kth terminal P _K is connected to the signal receiving terminal 132 _1KB of the half-insertion detecting LSI 112. One end of the pull-up resistor 111 _1K is connected to the line 131 _1KB , and the other end of the pull-up resistor 111 _1K is connected to the power supply line 133.

The same applies hereinafter. Therefore, the other end of the line 131 _M1A , one end of which is connected to the first terminal P ₁ in the _M-th female connector 102 _M on the apparatus-side back substrate 101 side, is connected to the signal transmission terminal 132 _M1A of the half-insertion detection LSI 112. It is connected. Further, the other end of the line 131 _M1B having one end connected to the second terminal P ₂ is connected to the signal receiving terminal 132 _M1B of the half-insertion detecting LSI 112. One end of the pull-up resistor 111 _M1 is connected to the line 131 _M1B , and the other end of the pull-up resistor 111 _M1 is connected to the power supply line 133.

The other end of the line 131 _MKA , one end of which is connected to the (K-1) th terminal P _K-1 of the Mth female connector 102 _M , is connected to the signal sending terminal 132 _MKA of the half-insertion detecting LSI 112. Yes. The other end of the line 131 _MKB having one end connected to the Kth terminal P _K is connected to the signal receiving terminal 132 _MKB of the half-insertion detecting LSI 112. One end of the pull-up resistor 111 _MK is connected to the line 131 _MKB , and the other end of the pull-up resistor 111 _MK is connected to the power supply line 133.

  The card half insertion alarm LED 113 is connected to the LED signal terminal 136 of the half insertion detection LSI 112 by a line 134. The card half-insertion alarm LED 113 is disposed at a position where the lamp in the card half-insertion detection system 100 is easily lit from the outside, and is lit by a current flowing between the card and a ground terminal (not shown).

  FIG. 5 shows an outline of the configuration of the half-insertion detection LSI. The half-insertion detection LSI 112 includes an inter-card interface unit 141, an output signal generation unit 142, and an input signal normality check unit 143.

The inter-card interface unit 141 has an external interface function, and transmits / receives data to / from the _first to Mth cards 103 _{1 to} 103 _M. The output signal generation unit 142 generates test data for checking the mounting normality for the _first to Mth cards 103 _{1 to} 103 _M. The input signal normality check unit 143 checks the normality of data returned from the _first to Mth cards 103 _{1 to} 103 _M via the inter-card interface unit 141. The mounting state determination output by the input signal normality check unit 143 is sent from the LED signal terminal 136 to the card half-insertion alarm LED 113.

FIG. 6 shows a change in the waveform of the output signal output from the output signal generation unit. When the output signal generation unit 142 shown in FIG. 5 is set to a card half-insertion inspection mode, which will be described in detail later, the cards 103 ₁ to 103 ₁ mounted with a rectangular wave having a duty ratio D of 50% on the apparatus-side rear substrate 101. The number Q is continuously output for all 103 _M. Specifically, the lengths of the L (low) level waveform portion 151 and the H (high) level waveform portion 152 are equal to each other, and the length that is alternately switched to repeat the Q period is the length of the output signal. The waveform changes for one unit.

Q is an arbitrary integer of “1” or more. When Q is “1”, a rectangular wave having a duty ratio D of 50% is applied to the _K terminals P _{1 to} P _{K of} one card 103 only once, and Q is In the case of a plurality of “2” or more, this rectangular wave is added “Q” times at once. Therefore, in the latter case, the connection status of each terminal can be determined more accurately.

7 and 8 show the logical relationship between the signal output from the half-insertion detection LSI and the signal returned to the half-insertion detection LSI depending on the connection status of the terminals in the connector. Here, as an example, the relationship between the _first terminal P ₁ and the second terminal P ₂ in the first card 103 ₁ shown in FIG. 4 will be described.

In FIG. 7, it is assumed that the contact between the _first terminals P ₁ or the contact between the second terminals P ₂ in the first female connector 102 ₁ and the first male connector 104 ₁ is completely disconnected. . A case in which the contact between both the first terminals P ₁ and the second terminals P ₂ is completely disconnected at the same time is also included. In such a connection state, a rectangular wave having a duty ratio D of 50% as shown in FIG. 6 is switched from the H level to the L level at the signal transmission terminal 132 _11A of the half-insertion detecting LSI 112 shown in FIG. It is assumed that one cycle is applied.

Such a connection state between the first female connector 102 ₁ and the first male connector 104 ₁ is shown in FIG. 7 by the first terminal P ₁ and the second terminal P ₂ . The result is the same as not conducting (disconnected). Therefore, the pull-up resistor 111 connected to the power supply line 133 is connected to the signal receiving terminal 132 _11B side of the half-insertion detecting LSI 112 regardless of what logic state signal is input to the signal sending terminal 132 _{11A. Eleven} H level signals are input.

Next, as shown in FIG. 8, the contact between the _first terminals P ₁ and the contact between the second terminals P ₂ in the first female connector 102 ₁ and the first male connector 104 ₁ are completely complete. Suppose that In this connection state, it is assumed that a rectangular wave having a duty ratio D of 50% as shown in FIG. 6 is applied to the signal transmission terminal 132 _11A of the half-insertion detecting LSI 112 in such a manner that it switches from H level to L level.

In this case, when an H level signal is applied to the signal transmission terminal 132 _11A in the first half period, the potential on the _second terminal P ₂ side of the pull-up resistor 111 ₁₁ becomes H level in this state. Therefore, no current flows through the pull-up resistor 111 ₁₁ and the signal receiving terminal 132 _11B side is also maintained at the H level.

In the latter half period, an L level signal is applied to the signal transmission terminal 132 _11A . In this state, the potential on the _second terminal P ₂ side of the pull-up resistor 111 ₁₁ becomes L level. Therefore, a current that causes a potential difference between the H level and the L level flows through the pull-up resistor 111 ₁₁ , and the signal receiving terminal 132 _11B side changes to the L level. Thus, in the case of the example shown in FIG. 8, the change in the logic level appears at both the signal transmission terminal 132 _11A and the signal reception terminal 132 _11B and is exactly the same.

FIG. 9 shows a waveform of an input signal to the half-insertion detecting LSI when it is determined that the connector is normally connected and the card is not half-inserted. A total of Q periods for the terminals P _{1 to} P _K of the _first to Mth female connectors 102 _{1 to} 102 _M and the first to Mth male connectors 104 _{1 to} 104 _M shown in FIG. When the H-level duty ratio D in the waveform is expressed by the following equation (1), it is determined that the connector is normally connected.

  48% ≦ D ≦ 52% …… (1)

FIG. 10 shows an example of a waveform of an input signal to the half-insertion detection LSI when it is determined that the card is half-inserted. A total of Q periods for the terminals P _{1 to} P _K of the _first to Mth female connectors 102 _{1 to} 102 _M and the first to Mth male connectors 104 _{1 to} 104 _M shown in FIG. When the waveform is measured, it is assumed that any one or more of the H level duty ratios D is expressed by the following equation (2). In this case, the half-insertion state is detected in the corresponding pair of connectors 102 and 104.

  D <48% or D> 52% …… (2)

In the example shown in FIG. 10, the duty ratio D of the H level at a specific terminal P is 70% for a certain period. Thus, it is determined that the pair of connectors 102 and 104 having terminals having the H-level duty ratio D that does not satisfy the expression (1) (satisfies the expression (2)) is in a half-insertion state. become. In the present embodiment, any _one of all terminals P _{1 to} P _K of the _first to Mth female connectors 102 _{1 to} 102 _M and the first to Mth male connectors 104 _{1 to} 104 _M is (1). When there is a case where the expression is not satisfied, it is determined that there is a half-inserted connector on the apparatus-side rear substrate 101.

  Of course, the criterion for determining whether the connector is in a normal state or in a half-inserted state is not limited to the range of fluctuation values indicated by the equation (1) or (2).

  In FIG. 10, the portion of the H level where the duty ratio D is 70% is caused by the following reasons, for example. In the second half of the H level period in which the duty ratio D is 70% in FIG. 10, the contacts between the terminals become non-contact. Then, even if the period of 50 percent is exceeded, the input signal is maintained at the H level, but it is assumed that the terminals come into contact again when 70 percent of one cycle has elapsed. Then, the input signal changes from the H level to the L level again from this point. In this way, an H level portion with a duty ratio D of 70% is generated.

  On the other hand, in FIG. 10, immediately after the H level portion where the duty ratio D is 70 percent, there is an H level section where the duty ratio D is about 20 percent. Such a waveform appears when, for example, when a signal of L level is received, the terminal is instantaneously contactless, and the terminals of the female connector 102 and the male connector 104 are the same as when the duty ratio D is 70%. Occurs when the contact is unstable.

FIG. 11 shows a first stage of control for checking whether or not the connector connection starting from the time when the mounting of the card is started on the apparatus-side rear substrate is normally performed. This will be described together with FIGS. 4, 5, 7 and 8. FIG. In this first-stage control in the apparatus having the hot-swap apparatus-side back substrate 101, mounting of the first to M-th cards 103 _{1 to} 103 _M is started while the apparatus-side back substrate 101 is energized. Detection is performed at the time.

On the apparatus-side rear substrate 101 side, a CPU (Central Processing Unit) (not shown) executes a control program stored in a memory (not shown), whereby the first to Mth female connectors 102 ₁ to 102 _1- It waits for the mounting work of the _first to M-th male connectors 104 _{1 to} 104 _M to start with respect to 102 _M. In this initial stage, the CPU generates a signal that is at L level over the entire period from the output signal generator 142 shown in FIG. 5 (step S201).

In this state, the parameter m for designating the _first to Mth cards 103 _{1 to} 103 _M is initialized to “1” (step S202). The first terminal P ₁ and the ( _K-1 ) th terminal P _{K-1 of} the m-th card (the parameter m is “1” at this time, so the first card 103 ₁ )). Then, the L level signal generated by the output signal generation unit 142 is transmitted from the signal transmission terminal 132 (here, the signal transmission terminals 132 _11A and 132 _1KA (step S203).

In this state, if the first card 103 ₁ has not yet been attached to the first female connector 102 _1, between the card from the card between the interface unit 141 via the first female connector 102 ₁ Interface There is no signal to be returned to the part 141. Therefore, as described with reference to FIG. 7, the signal levels appearing at the signal receiving terminals 132 _11B and 132 _1KB are all H level.

In this way, if the signal levels appearing at the signal receiving terminals 132 _11B and 132 _1KB are all H levels (step S204: Y), it is determined whether the parameter m is equal to or greater than the total number M of the cards 103 (step S205). . In this example, the parameter m is “1”, and this condition is not satisfied if the total number M of the cards 103 is plural (N). Therefore, in this example, the parameter m is counted up by “1” (step S206). Then, the process returns to step S203.

As described above, it is sequentially checked whether the _first to Mth cards 103 _{1 to} 103 _M are attached to the _first to Mth female connectors 102 _{1 to} 102 _M. It is assumed that all the signal levels appearing at the signal receiving terminals 132 _M1B and 132 _MKB are H level after checking up to the M-th card 103 _M (step S204: Y). In this case, since the parameter m becomes equal to or larger than the total number M of the cards 103 in the next step S205 (Y), the process proceeds to step S202, and the parameter m is initialized to “1” again.

In this way, it is repeatedly checked whether the _first to _M-th cards 103 _{1 to} 103 _M are attached to the _first to M-th female connectors 102 _{1 to} 102 _M , and as time passes, a certain card X It is assumed that the check (where 1 ≦ X ≦ M) is performed. The male connector 104 _X of the X card 103 _X of the X at this point has been mounted on the female connector 102 _X of the X. Then, at least one of the signal levels appearing at the signal receiving terminals 132 _X1B and 132 _XKB is lowered to the L level (step S204: N). This is because an L level signal of at least one of the jumper lines 121 _XA and 121 _XB (not shown) is folded from the Xth male connector 104 _X to the Xth female connector 102 _X , and the signal receiving terminals 132 _X1B and 132 _X are received. _{This is because} the corresponding _XKB is forcibly fixed at the L level. Thereby, the card attachment detection process in the first stage ends (END).

Next, the second stage process will be described. It was detected in the first stage processing that the operation of mounting the _first to Mth cards 103 _{1 to} 103 _M on the apparatus-side rear substrate 101 shown in FIG. 4 has started. For this reason, the process of the second stage that starts immediately after this is the time when the maximum expected time T _MAX from the start to the end of the work for mounting the _first to M-th cards 103 _{1 to} 103 _M has elapsed. Thus, the card 103 that is not yet mounted on the apparatus-side back substrate 101 is detected and not mounted. However, if the mounting is confirmed for all of the _first to M-th cards 103 _{1 to} 103 _M even before the maximum estimated time T _MAX elapses, the processing in the second stage ends at that point, and A three-stage process can be started.

  FIG. 11 shows the flow of processing for determining the presence or absence of an unmounted card as the second stage. This will be described with reference to FIGS. 4, 5, 7 and 8.

First, the above-described CPU starts generation of a signal that is L level over the entire period from the output signal generation unit 142 shown in FIG. 5, and also starts timing of a timer (not shown) (step S221). In this state, the parameter m for designating the _first to Mth cards 103 _{1 to} 103 _M is initialized to “1” (step S222). Then, with respect to the first terminal P ₁ and the (K−1) th terminal P _{K−1 of} the mth card (the parameter m is “1” at this time, the first card 103 ₁ ). The L level signal generated by the output signal generation unit 142 is transmitted from the signal transmission terminal 132 (here, the signal transmission terminals 132 _11A and 132 _1KA ) (step S223).

In this state, if the first card 103 ₁ has not yet been attached to the first female connector 102 _1, between the card from the card between the interface unit 141 via the first female connector 102 ₁ Interface There is no signal to be returned to the part 141. Therefore, as described with reference to FIG. 7, the signal levels appearing at the signal receiving terminals 132 _11B and 132 _1KB are all H level.

As described above, if at least one of the signal levels appearing at the signal receiving terminals 132 _11B and 132 _1KB is not at the L level, that is, if both are at the H level (step S224: N), the time counting by the timer is the maximum expected time T _MAX. If it is before reaching, the arrival is waited (step S225). If at least one of the signal levels appearing at the signal receiving terminals 132 _11B and 132 _1KB attains an L level at a predetermined time before reaching the maximum expected time T _MAX (step S224: Y), the parameter m is set to that of the card 103. It is determined whether the total number is equal to or greater than M (step S226). In this example, the parameter m is “1”, and this condition is not satisfied if the total number M of the cards 103 is plural (N). Therefore, in this example, the parameter m is incremented by “1” (step S227). Then, the process returns to step S223.

As described above, the first to Mth cards 103 _{1 to} 103 _M are attached to the _first to Mth female connectors 102 _{1 to} 102 _M before reaching the maximum expected time T _MAX. Check in order. As a result, it is assumed that at least one of the signal levels appearing at the signal receiving terminals 132 _M1B and 132 _MKB for the M-th card 103 _M is L level before reaching the maximum expected time T _MAX (step S224). : Y). In this case, in the next step S226, it is determined that the parameter m is equal to or greater than the total number M of cards 103 (Y).

As a result, it is confirmed that all of the first to _M-th cards 103 _{1 to} 103 _M are attached to the _first to M-th female connectors 102 _{1 to} 102 _M. Is established (step S228), and the processing of the second stage ends (END). When the flag indicating that the card is not mounted is set, a third stage process described below is performed.

On the other hand, if the elapsed time when the presence or absence of mounting at step S224 in the order are checked for card 103 ₁ 10 @ 2 to 10 @ 3 _M of the first to M reaches the maximum expected time T _MAX (step S225: Y), This means that the time limit has been reached with at least one unmounted card 103 present. Therefore, in this case, a notification that the card is not installed is sent from the input signal normality check unit 143 to the card half-insertion alarm LED 113 (step S229), and the processing of the second stage ends (END). In this case, the second-stage process has been terminated abnormally, so it does not proceed to the third-stage process described below. To proceed to the third stage process, it is necessary to start the second stage process again and set a flag indicating that no card is mounted.

Next, the third stage process will be described. In the process of the third stage, it is assumed that all of the first to Mth cards 103 _{1 to} 103 _M in FIG. 4 are mounted on the _first to Mth female connectors 102 _{1 to} 102 _M. It is determined whether or not there is a half-inserted state. This is also a check as to whether the first to Mth cards 103 _{1 to} 103 _M are mounted with time stability.

FIG. 13 shows a flow of processing for determining whether the card mounted as a third-stage process normally contacts the terminal or contacts the terminal in the half-inserted state. This will be described with reference to FIGS. 4, 5, 7 and 8. Also, it will be shown only the processing for the first card 103 ₁ in order to simplify the description, FIG. 13. The processing in the _{second to} M-th cards 103 ₂ (not shown) to 103 _M is the same as this, and the CPU described above may count up the parameter m in order from “1” and perform the processing.

In the process shown in FIG. 13, first, the parameter q for counting the period Q is set to the initial value “1” (step S241). Then, the output signal generator 142 shown in FIG. 5 generates a test pattern with a duty ratio D shown in FIG. 6 of 50% (step S242). Subsequently, the CPU waits for the time when the rising of the H level is performed in the output signal output from the line 131 _11A having one end connected to the first terminal P ₁ as the first period (q = 1). (Step S243).

When the output signal rises (Y), the duty ratio D is measured by comparing the time during which the output signal is at the H level with a known cycle (step S244). Then, it is checked whether or not the measured duty ratio D is within an allowable range for determining that the connection of the connectors 102 ₁ and 104 ₁ is normal (step S245). Specifically, it is determined whether the duty ratio D satisfies the above-described equation (1).

  If the duty ratio D satisfies the expression (1), that is, if it is within the allowable range (step S245: Y), whether the parameter q at that time has reached the cycle Q that is the final output of the test pattern. Is discriminated (step S246). If the parameter q has not reached the period Q (N), the parameter q is incremented by “1” (step S247), and the process returns to step 243. Then, the duty ratio D is measured by comparing the time during which the output signal is at the H level for the next period with one known period.

  If such a process is repeated and the parameter q reaches the cycle Q at a certain time (step S246: Y), the duty ratio D satisfies the expression (1) in all cycles. Therefore, it is determined that the corresponding terminal P is not in the half-inserted state (step S248), and the processing for the terminal P is ended (END).

  On the other hand, when the duty ratio D does not satisfy the expression (1) in a certain period before the parameter q reaches the period Q (step S245: N), the corresponding terminal P is in a half-inserted state. Is determined (step S249), and the process for the terminal P is terminated (END).

The process for one terminal P of the specific connectors 102 ₁ and 104 _{1 in} the first card 103 ₁ has been described as the third stage process. In the half-insertion detection LSI 112, the terminals P ₁ , P ₂ , P _K-1 , P of the _first to Mth female connectors 102 _{1 to} 102 _M and the first to Mth male connectors 104 _{1 to} 104 _{M When} a situation occurs where the duty ratio D for _K does not satisfy the expression (1), an alarm signal is output from the LED signal terminal 136 shown in FIG.

The lighting of the card half-insertion alarm LED 113 based on step S249 in FIG. 13 and the lighting when a notification that the card is not installed is sent to the card half-insertion alarm LED 113 in step S229 in FIG. It is possible to distinguish the two by changing the lighting state such as the lighting cycle. Similarly, which of the first to Mth cards 103 _{1 to} 103 _M is in the half-inserted state can be distinguished by changing the lighting state of the card half-insertion alarm LED 113. Of course, by replacing the card half-insertion warning LED 113 with a display such as a liquid crystal display, such a warning display can be displayed more easily.

  The embodiment of the present invention described above has the following effects.

  As a first feature, for a specific terminal P, a signal is continuously applied for a certain period to check the quality of the connection. As a result, when any number of terminals P of the connectors 102 and 104 maintain an unstable connection state with time, this can be accurately detected as a half-inserted state.

  As a second feature, a jumper wire 121 is provided on the card 103 and the fitting state of the connectors 102 and 104 is checked by returning a signal on the card 103 side. This eliminates the need for special control on the card 103 side. Also, by checking the duty ratio of the test pattern, it is possible to check with only one signal that does not require a clock. Furthermore, since the fitting state of the pair of terminals P can be checked at a time, the processing can be reduced.

  As a third feature, the function unit for checking the fitting state of the connectors 102 and 104 and the half-insertion state notifying unit are not on the card 103 side but on the apparatus-side back substrate 101 side. Therefore, regardless of the state of the card 103, accurate information can be grasped at a glance at the apparatus main body side.

Further, as shown in the embodiment, between the first terminal P ₁ and the second terminal P ₂ which are the two terminals at both ends of the connectors 102 and 104, and the K−1th terminal P _K−1 . Jumper wires 121 _A and 121 _B can be arranged between the Kth terminals P _K. Thereby, there is also an effect that the half-insertion state caused by the connection in which a gap is generated at one end of the connectors 102 and 104 can be accurately detected.

  <Deformability of invention>

In the above-described embodiment, the description has been made on the assumption that the _first to Mth cards 103 _{1 to} 103 _M are attached to the apparatus-side rear substrate 101 in FIG. 4 in the product manufacturing process. The present invention is applicable without being limited to such a case. For example, the present invention may be applied when checking whether or not a predetermined number of cards are normally attached to the board at a predetermined timing such as when various information processing apparatuses are activated. Moreover, the administrator of the information processing apparatus may be able to check a card attached to the information processing apparatus at a desired timing.

In the embodiment, the half-insertion detecting LSI 112 is arranged on the apparatus-side back substrate 101 on the apparatus main body side, but it may be arranged on the first to M-th cards 103 _{1 to} 103 _M side. In this case, by placing the pattern for folding in place of the first through the female connector 102 jumper line ₁ to 102 _M of the M provided on the device side rear substrate 101 side, a female of the first to M The signals from the connectors 102 _{1 to} 102 _M may be folded back. Thereby, it is possible to detect the half-insertion state similar to the embodiment.

It is also possible to arrange the half-insertion detection LSI 112 on both the apparatus-side back substrate 101 side and the first to Mth cards 103 _{1 to} 103 _M side. In this case, signals are connected one-to-one to the apparatus-side back substrate 101 side and the first to M-th cards 103 _{1 to} 103 _M side, so that a half-insertion state can be detected in both directions. .

Further, in the embodiment, the waveform pattern having the duty ratio D of 50% as shown in FIG. 6 is sent to the _first to Mth female connectors 102 _{1 to} 102 _M , but the present invention is not limited to this. . For example, sending a number of specific pulses within the specified time for the female connector 102 ₁ to 102 _M of the first to M, by counting the number of detected folded pulse, thereby semi-inserted state The presence or absence may be determined.

  Furthermore, in the embodiment, the present invention is applied to a substrate such as a mother board on which two or more cards are mounted. However, the present invention can be similarly applied to a substrate on which only one card is mounted.

  Some or all of the embodiments described above are described as in the following supplementary notes, but are not limited to the following descriptions.

(Appendix 1)
A plurality of terminals, a first connector in which one or more predetermined terminals among them are held at one potential of a binary logic level via a predetermined resistance; and Applied to the predetermined pair terminal paired with each one of the specific terminals by switching the one potential and the other potential of the binary logic level a plurality of times over time in a specific test mode. A test mode application means, and a second connection state between the first connector and the first connector based on the relationship between the potential appearing at the specific terminal and the potential applied to the pair terminal during the test mode. A first circuit unit comprising a connection quality determination means for determining quality of connection between terminals with the connector;
A plurality of terminals connected in a one-to-one relationship with the plurality of terminals of the first connector are arranged, and each of the terminals contacts the plurality of terminals of the first connector in a one-to-one relationship. And a conducting means for electrically conducting between two terminals respectively corresponding to the paired terminals paired with the specific terminal of the first connector in the second connector. A connector half-insertion detecting device comprising: 2 circuit units.

(Appendix 2)
2. The connector half-insertion detecting device according to claim 1, wherein the test mode application means is a repetitive application means for repeatedly applying a signal of a logic level whose logic level is inverted at a predetermined duty ratio for a predetermined period.

(Appendix 3)
The connection quality determination unit determines that the first connector and the second connector are normally connected when it is confirmed over the predetermined period that the logic level is inverted at the predetermined duty ratio. The connector half-insertion detecting device according to Supplementary Note 2, wherein

(Appendix 4)
The connection pass / fail judgment means detects the first level when the logic level is detected to be inverted at a duty ratio outside a predetermined allowable range based on the predetermined duty ratio during the predetermined period at least once. The connector half-insertion detecting device according to appendix 2, wherein the connector and the second connector are determined to be connected in a half-insertion state.

(Appendix 5)
The connection pass / fail judgment means is configured such that when the test mode application means applies any one of the binary logic levels, the potential of the specific terminal is held at the one potential, The connector half-insertion detection device according to appendix 2, wherein it is determined that the second connector is connected in a half-insertion state.

(Appendix 6)
The connector half-insertion detection device according to appendix 1, wherein the first connector has one specific terminal and one pair terminal disposed at both ends thereof.

(Appendix 7)
The connector half-insertion detection device according to appendix 1, wherein a plurality of the first connectors and the second connectors are arranged in each circuit portion.

(Appendix 8)
By monitoring a potential appearing at a predetermined pair terminal that is paired with a specific terminal when a predetermined potential is applied to the specific terminal of the first connector on a board on which a plurality of first connectors are arranged. A card device in which a second connector having a conductor connected between two terminals respectively corresponding to the specific terminal and the pair terminal is started to be attached to the first connector of the board; A card device mounting start detection step for detecting by sending a signal to the specific terminal of the first connector and detecting a signal returned to the pair terminal;
In the card device attachment start detection step, the first corresponding to all of the first connectors from when it is detected that the card device has been attached to the board until a predetermined first time elapses. A non-installation warning step for outputting a warning that the card device is not installed when it is not detected that the connector of 2 is connected;
When it is detected that the corresponding second connector is connected to all of the first connectors before the first time elapses, the specific terminal of the first connector in this connected state A signal whose logic level is inverted at a predetermined duty ratio is continuously applied for a plurality of cycles, and the state of change in the logic level of the signal appearing at the pair terminal at this time is within the predetermined allowable range for the plurality of cycles. And a half-insertion state warning step for outputting a warning when a half-insertion state as an incomplete connection state between the first connector and the second connector is determined when they are not the same. Connector connection warning method.

(Appendix 9)
When the second connectors corresponding to all of the first connectors are connected before the first time has elapsed, the predetermined terminals of the first connectors are connected to the predetermined terminals in this connected state. A signal whose logic level is inverted at a duty ratio is continuously applied for a plurality of cycles, and the state of change in the logic level of the signal appearing at the pair terminal at this time is the same for the plurality of cycles within a predetermined allowable range. 9. The connector connection warning method according to claim 8, further comprising a completion notification step of notifying that the connection of the second connector to the first connector has been normally completed.

(Appendix 10)
On the computer,
By monitoring a potential appearing at a predetermined pair terminal that is paired with a specific terminal when a predetermined potential is applied to the specific terminal of the first connector on a board on which a plurality of first connectors are arranged. A card device in which a second connector having a conductor connected between two terminals respectively corresponding to the specific terminal and the pair terminal is started to be attached to the first connector of the board; A card device mounting start detection process for detecting a signal sent to the specific terminal of the first connector and detecting a signal returned to the pair terminal;
The first corresponding to all of the first connectors until a predetermined first time elapses after the card device installation start detection process detects that the card device has been attached to the board. A non-installation warning process for outputting a warning that the card device is not installed when it is not detected that the two connectors are connected;
When it is detected that the corresponding second connector is connected to all of the first connectors before the first time elapses, the specific terminal of the first connector in this connected state A signal whose logic level is inverted at a predetermined duty ratio is continuously applied for a plurality of cycles, and the state of change in the logic level of the signal appearing at the pair terminal at this time is within the predetermined allowable range for the plurality of cycles. And a half-insertion state warning process for outputting a warning when a half-insertion state as an incomplete connection state between the first connector and the second connector is determined when they are not the same. Connector connection warning program.

(Appendix 11)
When the second connectors corresponding to all of the first connectors are connected before the first time has elapsed, the predetermined terminals of the first connectors are connected to the predetermined terminals in this connected state. A signal whose logic level is inverted by a duty ratio is continuously applied for a plurality of cycles, and the state of the change in the logic level of the signal appearing at the pair terminal at this time is the same for the plurality of cycles within the predetermined allowable range. 11. The connector connection warning program according to claim 10, further comprising a completion notification process for notifying that the connection of the second connector to the first connector has been normally completed.

DESCRIPTION OF SYMBOLS 10 Connector half-insertion detection apparatus 11 1st circuit part 11a 1st connector 11b Test mode application means 11c Connection quality determination means 12 2nd circuit part 12a 2nd connector 12b Conducting means 20 Connector connection warning method 21 Card apparatus Installation start detection step 22 Non-installation warning step 23 Half-insertion state warning step 30 Connector connection warning program 31 Card device installation start detection processing 32 Non-installation warning processing 33 Half-insertion state warning processing 100 Card half-insertion detection system 101 Device side rear substrate 102 Female connector 103 Card 104 Male connector 111 Pull-up resistor 113 Half-insertion alarm LED
121 Jumper Line 131 Line 132 Half Insertion Detection LSI Signal Reception Terminal 133 Power Supply Line 141 Inter-Card Interface Unit 142 Output Signal Generation Unit 143 Input Signal Normality Check Unit P Terminal

Claims (10)

A plurality of terminals, a first connector in which one or more predetermined terminals among them are held at one potential of a binary logic level via a predetermined resistance; and Applied to the predetermined pair terminal paired with each one of the specific terminals by switching the one potential and the other potential of the binary logic level a plurality of times over time in a specific test mode. A test mode application means, and a second connection state between the first connector and the first connector based on the relationship between the potential appearing at the specific terminal and the potential applied to the pair terminal during the test mode. A first circuit unit comprising a connection quality determination means for determining quality of connection between terminals with the connector;
A plurality of terminals connected in a one-to-one relationship with the plurality of terminals of the first connector are arranged, and each of the terminals contacts the plurality of terminals of the first connector in a one-to-one relationship. And a conducting means for electrically conducting between two terminals respectively corresponding to the paired terminals paired with the specific terminal of the first connector in the second connector. A connector half-insertion detecting device comprising: 2 circuit units.   2. The connector half-insertion detecting device according to claim 1, wherein the test mode application means is a repetitive application means for repeatedly applying a logic level signal whose logic level is inverted at a predetermined duty ratio for a predetermined period.   The connection quality determination unit determines that the first connector and the second connector are normally connected when it is confirmed over the predetermined period that the logic level is inverted at the predetermined duty ratio. The connector half-insertion detecting device according to claim 2.   The connection pass / fail judgment means detects the first level when the logic level is detected to be inverted at a duty ratio outside a predetermined allowable range based on the predetermined duty ratio during the predetermined period at least once. The connector half-insertion detecting device according to claim 2, wherein it is determined that the second connector and the second connector are connected in a half-inserted state.   The connection pass / fail judgment means is configured such that when the test mode application means applies any one of the binary logic levels, the potential of the specific terminal is held at the one potential, The connector half-insertion detecting device according to claim 2, wherein it is determined that the second connector is connected in a half-inserted state.   2. The connector half-insertion detecting device according to claim 1, wherein the first connector has the specific terminal and the pair terminal arranged one by one at both ends thereof. By monitoring a potential appearing at a predetermined pair terminal that is paired with a specific terminal when a predetermined potential is applied to the specific terminal of the first connector on a board on which a plurality of first connectors are arranged. A card device in which a second connector having a conductor connected between two terminals respectively corresponding to the specific terminal and the pair terminal is started to be attached to the first connector of the board; A card device mounting start detection step for detecting by sending a signal to the specific terminal of the first connector and detecting a signal returned to the pair terminal;
In the card device attachment start detection step, the first corresponding to all of the first connectors from when it is detected that the card device has been attached to the board until a predetermined first time elapses. A non-installation warning step for outputting a warning that the card device is not installed when it is not detected that the connector of 2 is connected;
When it is detected that the corresponding second connector is connected to all of the first connectors before the first time elapses, the specific terminal of the first connector in this connected state A signal whose logic level is inverted at a predetermined duty ratio is continuously applied for a plurality of cycles, and the state of change in the logic level of the signal appearing at the pair terminal at this time is within the predetermined allowable range for the plurality of cycles. And a half-insertion state warning step for outputting a warning when a half-insertion state as an incomplete connection state between the first connector and the second connector is determined when they are not the same. Connector connection warning method.   When the second connectors corresponding to all of the first connectors are connected before the first time has elapsed, the predetermined terminals of the first connectors are connected to the predetermined terminals in this connected state. A signal whose logic level is inverted at a duty ratio is continuously applied for a plurality of cycles, and the state of change in the logic level of the signal appearing at the pair terminal at this time is the same for the plurality of cycles within a predetermined allowable range. 8. The connector connection warning method according to claim 7, further comprising a completion notification step of notifying that the connection of the second connector to the first connector is normally completed. On the computer,
By monitoring a potential appearing at a predetermined pair terminal that is paired with a specific terminal when a predetermined potential is applied to the specific terminal of the first connector on a board on which a plurality of first connectors are arranged. A card device in which a second connector having a conductor connected between two terminals respectively corresponding to the specific terminal and the pair terminal is started to be attached to the first connector of the board; A card device mounting start detection process for detecting a signal sent to the specific terminal of the first connector and detecting a signal returned to the pair terminal;
The first corresponding to all of the first connectors until a predetermined first time elapses after the card device installation start detection process detects that the card device has been attached to the board. A non-installation warning process for outputting a warning that the card device is not installed when it is not detected that the two connectors are connected;
When it is detected that the corresponding second connector is connected to all of the first connectors before the first time elapses, the specific terminal of the first connector in this connected state A signal whose logic level is inverted at a predetermined duty ratio is continuously applied for a plurality of cycles, and the state of change in the logic level of the signal appearing at the pair terminal at this time is within the predetermined allowable range for the plurality of cycles. And a half-insertion state warning process for outputting a warning when a half-insertion state as an incomplete connection state between the first connector and the second connector is determined when they are not the same. Connector connection warning program.   When the second connectors corresponding to all of the first connectors are connected before the first time has elapsed, the predetermined terminals of the first connectors are connected to the predetermined terminals in this connected state. A signal whose logic level is inverted by a duty ratio is continuously applied for a plurality of cycles, and the state of the change in the logic level of the signal appearing at the pair terminal at this time is the same for the plurality of cycles within the predetermined allowable range. 10. The connector connection warning program according to claim 9, further comprising a completion notification process for notifying that the connection of the second connector to the first connector has been normally completed.

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