JP2012004486A - Nitride semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor device in which a nitride semiconductor layer with excellent crystallinity is formed on a silicon substrate.SOLUTION: A nitride semiconductor device includes a silicon substrate 10 and a selective growth mask layer 20 that contacts the silicon substrate 10 and is made of silicon nitride formed on part of the silicon substrate 10. A nitride semiconductor layer 30 is formed on the silicon substrate 10 where the selective growth mask layer 20 is not formed thereon, so as to contact the silicon substrate 10.

Description

  The present invention relates to a nitride semiconductor device and a manufacturing method thereof, and more particularly, to a nitride semiconductor device in which a nitride semiconductor is formed on a silicon substrate and a manufacturing method thereof.

  Nitride semiconductors are wide band gap semiconductors and have excellent characteristics such as a large dielectric breakdown electric field. A nitride semiconductor also has a characteristic that the saturation drift velocity of electrons is higher than that of a compound semiconductor such as a silicon-based semiconductor or gallium arsenide (GaAs).

Further, when aluminum nitride (AlGaN) and gallium nitride (GaN) are used as the nitride semiconductor constituting the nitride semiconductor device, the heterointerface between AlGaN and GaN having the (0001) plane as a main surface is spontaneously generated. Electric charges are generated by polarization and piezo polarization. Thereby, the sheet carrier concentration at the heterointerface is 1 × 10 ¹³ cm ⁻² or more even in the case of undoped. For this reason, a two-dimensional electron gas (2 DEG: 2 Dimensional Electron Gas) is generated at the heterointerface. By utilizing these two-dimensional electrons, a heterojunction field effect transistor (HFET) having a large current density can be realized.

  Currently, a substrate for growing such a nitride semiconductor crystal is not a substrate made of the same nitride semiconductor as the crystal growth material, but has a lattice mismatch with a nitride semiconductor such as a sapphire substrate, a silicon carbide substrate, or a silicon substrate. Different substrates are used that are different from large crystal growth materials. This is because even when a substrate made of a nitride semiconductor is manufactured, it must be formed by vapor phase growth on a heterogeneous substrate. This is because a large-diameter substrate cannot be obtained. On the other hand, the silicon substrate can mass-produce a large-diameter substrate, which is advantageous in terms of cost.

  However, when a nitride semiconductor is formed on a silicon substrate, it has the following drawbacks.

  First, nitride semiconductors have a larger coefficient of thermal expansion than silicon, and the difference between them is also large. The crystal growth of the nitride semiconductor is generally performed at a high temperature of about 1000 ° C. For this reason, when a nitride semiconductor is deposited on a silicon substrate at a high temperature and then the substrate temperature is lowered to room temperature, tensile stress is applied to the nitride semiconductor due to the difference in thermal expansion coefficient between the nitride semiconductor and the silicon substrate. Is likely to occur. For this reason, there exists a problem that a high density defect generate | occur | produces or a crack generate | occur | produces in the nitride semiconductor formed on the silicon substrate.

  Further, when forming a nitride semiconductor containing gallium (Ga), the raw material tends to form a compound with silicon. For this reason, the nitride semiconductor also has a problem that it is difficult to grow flat on the silicon substrate.

  Furthermore, a nitride semiconductor grown on a different substrate such as a silicon substrate has a problem that the dislocation density becomes very high due to the effect of lattice mismatch with the substrate.

  Conventionally, a technique for forming a high-quality nitride semiconductor by selectively growing a nitride semiconductor has been studied for such a problem. This technique utilizes the property of a nitride semiconductor that it is difficult to grow on a silicon oxide layer, a silicon nitride layer, or an aluminum oxide layer and grows selectively.

  As a conventional technique for selectively growing such a nitride semiconductor, for example, in Patent Document 1, after a nitride semiconductor layer made of GaN is grown as a base crystal film on a heterogeneous substrate of a sapphire substrate, the base crystal film A technique is disclosed in which a selective growth mask is formed so as to partially cover the substrate, and a nitride semiconductor is formed from a growth region that is not covered with the selective growth mask.

  In Patent Document 2, after growing a seed crystal layer made of GaN on a different substrate of a sapphire substrate, a part of the seed crystal layer is removed by etching, and a nitride semiconductor is formed from the remaining portion. The technique of doing is disclosed.

  Patent Document 3 discloses a technique in which a mask layer is formed directly on a silicon substrate, a part of the mask layer is removed to form an opening, and a nitride semiconductor is formed from the opening of the mask. ing.

JP 2000-349338 A Japanese Patent No. 4179317 Japanese Patent No. 3864222

  However, according to the prior art disclosed in Patent Document 1 and Patent Document 2, it is necessary to separately form a nitride semiconductor as a base crystal film or a seed crystal layer before forming the nitride semiconductor. Therefore, there is a problem that the cost is high and the occupation time of the crystal growth apparatus becomes long.

  Further, the prior art disclosed in Patent Document 3 requires a sputtering process or a vapor deposition process when forming a mask layer, and further requires an etching process using a photolithography method when forming an opening in the mask layer. It becomes. In this case, the crystallinity of the base in the opening portion of the mask layer is deteriorated by the sputtering process or the etching process. Since the nitride semiconductor has the property of taking over the crystallinity of the base of the portion where the crystal grows, the nitride semiconductor formed on the base with deteriorated crystallinity also has a problem that the crystallinity deteriorates.

  The present invention has been made to solve such problems, and provides a nitride semiconductor device formed on a silicon substrate and having an excellent crystalline nitride semiconductor layer and a method for manufacturing the nitride semiconductor. The purpose is to provide.

  In order to achieve the above object, an aspect of a nitride semiconductor device according to the present invention includes a silicon substrate, and a selective growth mask layer made of silicon nitride that is in contact with the silicon substrate and is formed on a portion of the silicon substrate. A nitride semiconductor layer is formed on the silicon substrate on which the selective growth mask layer is not formed so as to be in contact with the silicon substrate.

  According to this aspect, the nitride semiconductor layer having excellent crystallinity can be formed by using the selective growth mask layer made of silicon nitride.

  Furthermore, in one aspect of the nitride semiconductor device according to the present invention, it is preferable that the silicon substrate has a recess, and the selective growth mask layer is formed only in the recess.

  Thereby, since a gap can be formed between the selective growth mask layer and the nitride semiconductor layer, the stress generated between the nitride semiconductor layer and the silicon substrate can be relieved.

  Furthermore, in one aspect of the nitride semiconductor device according to the present invention, it is preferable that the nitride semiconductor layer is also formed on the selective growth mask layer.

Thereby, a nitride semiconductor layer having a large area can be formed.
Furthermore, in one aspect of the nitride semiconductor device according to the present invention, the surface of the selective growth mask layer does not exist on the nitride semiconductor layer side than a contact surface where the silicon substrate and the nitride semiconductor layer are in contact with each other. It is preferable.

  As a result, the opening region of the selective growth mask layer is positioned at the highest position when forming the nitride semiconductor layer, so that the nitride is formed when forming the selective growth mask layer or forming the nitride semiconductor layer. Particles, watermarks, and the like that cause semiconductor defects are less likely to remain in the nitride semiconductor layer formation region.

  Furthermore, in one aspect of the nitride semiconductor device according to the present invention, a carbon atom concentration between the selective growth mask layer and the silicon substrate is constant with an interface between the selective growth mask layer and the silicon substrate as a boundary. Preferably there is.

  Thereby, the interface between the selective growth mask layer and the silicon substrate is formed without being exposed.

  Furthermore, in one aspect of the nitride semiconductor device according to the present invention, the selective growth mask layer is preferably formed by nitriding a part of the surface of the silicon substrate.

Thereby, the selective growth mask layer can be easily formed.
Furthermore, in one aspect of the nitride semiconductor device according to the present invention, an active layer made of a nitride semiconductor is preferably formed on the nitride semiconductor layer.

Thereby, a field effect transistor can be constituted.
According to another aspect of the method for manufacturing a nitride semiconductor device according to the present invention, a surface of a silicon substrate is oxidized to form a first layer made of silicon oxide, and the first layer is patterned. Exposing the surface of the silicon substrate; nitriding the exposed surface of the silicon substrate using the patterned first layer as a mask; and forming a second layer made of silicon nitride; Removing the first layer to expose the silicon substrate; and removing the first layer to form a nitride semiconductor layer on the exposed silicon substrate.

  Thereby, the silicon oxide formed by oxidizing the silicon substrate can protect the portion where the nitride semiconductor layer on the silicon substrate is formed until just before the crystal growth of the nitride semiconductor. In other words, the portion where the nitride semiconductor layer is formed on the silicon substrate is not damaged during the formation of the second layer in the step of forming the second layer or during dry etching. Therefore, it is possible to maintain a clean surface without deteriorating the surface of the silicon substrate on which the nitride semiconductor layer is formed until just before crystal growth of the nitride semiconductor. Therefore, a nitride semiconductor layer having excellent crystallinity can be formed.

  Furthermore, by using silicon nitride as the second layer, the second layer can function as a selective growth mask, and a nitride semiconductor can be selectively grown on the silicon substrate, and silicon oxide can be formed by hydrofluoric acid. It can also be selectively removed.

  Furthermore, according to the manufacturing method according to this aspect, the silicon substrate and the nitride semiconductor layer in the portion where the surface of the second layer is exposed by removing the first layer (the opening of the second layer) are It is not present on the nitride semiconductor layer side than the contact surface in contact therewith. As a result, when the nitride semiconductor layer is formed, the opening of the second layer is positioned at the highest position. Therefore, the nitride semiconductor is formed when the second layer is formed or when the nitride semiconductor layer is formed. Particles, watermarks, and the like that are the cause of the defects are less likely to remain in the nitride semiconductor layer formation region.

  Furthermore, in one aspect of the method for manufacturing a nitride semiconductor device according to the present invention, a step of forming a recess in the silicon substrate is formed before the step of forming the second layer, and the second layer is formed. In the step, it is preferable that the second layer is formed only in the concave portion.

  Thereby, since a space | gap can be formed between a 2nd layer and a nitride semiconductor layer, the stress which generate | occur | produces between a nitride semiconductor layer and a silicon substrate can be relieved.

  Furthermore, in one aspect of the method for manufacturing a nitride semiconductor device according to the present invention, in the step of forming the nitride semiconductor layer, the nitride semiconductor layer is preferably formed also on the second layer.

Thereby, a nitride semiconductor layer having a large area can be formed.
Furthermore, in one aspect of the method for manufacturing a nitride semiconductor device according to the present invention, it is preferable that the method further includes a step of forming an active layer made of a nitride semiconductor on the nitride semiconductor layer.

  Thereby, a field effect transistor provided with a nitride semiconductor layer can be manufactured.

  According to the nitride semiconductor device and the manufacturing method thereof according to the present invention, a nitride semiconductor layer having excellent crystallinity can be easily formed on a silicon substrate.

Sectional drawing which shows the structure of the nitride semiconductor device which concerns on the 1st Embodiment of this invention Sectional drawing which showed typically the structure of each process in the manufacturing method of the nitride semiconductor device which concerns on the 1st Embodiment of this invention. The schematic diagram (a) and the cross-sectional SEM photograph (b) which expanded the cross section of the nitride semiconductor device which concerns on the 1st Embodiment of this invention partially Sectional drawing which shows the structure of the nitride semiconductor device which concerns on the 2nd Embodiment of this invention Sectional drawing which shows the structure of the nitride semiconductor device which concerns on the 3rd Embodiment of this invention Sectional drawing which shows the structure of the nitride semiconductor device which concerns on the 4th Embodiment of this invention Sectional drawing which shows the structure of the nitride semiconductor device which concerns on the 5th Embodiment of this invention Sectional drawing which showed typically the structure of each process in the manufacturing method of the nitride semiconductor device which concerns on the 5th Embodiment of this invention.

  Hereinafter, a nitride semiconductor device and a method for manufacturing a nitride semiconductor device according to the present invention will be described based on embodiments with reference to the drawings.

(First embodiment)
First, a nitride semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view showing a configuration of a nitride semiconductor device according to the first embodiment of the present invention.

  As shown in FIG. 1, the nitride semiconductor device 1 according to the first embodiment of the present invention includes a silicon substrate 10, a selective growth mask layer 20, and a nitride semiconductor layer 30.

  As the silicon substrate 10, a silicon substrate having a (111) plane as a main surface can be used. Note that a (0001) plane of a nitride semiconductor is easily grown on the (111) plane of silicon.

  The selective growth mask layer 20 is a mask layer made of silicon nitride (SiN) formed by nitriding a part of the surface of the silicon substrate 10. The selective growth mask layer 20 has an opening formed to expose the silicon substrate 10.

  The nitride semiconductor layer 30 is formed on the silicon substrate 10 on which the selective growth mask layer 20 is not formed, that is, on the silicon substrate 10 in the opening of the selective growth mask layer 20. The nitride semiconductor layer 30 is formed in contact with the silicon substrate 10 in the opening region. The nitride semiconductor layer 30 can be composed of, for example, gallium nitride.

  Next, a method for manufacturing the nitride semiconductor device 1 according to the first embodiment of the present invention will be described with reference to FIG. FIG. 2 is a cross-sectional view of each step in the method for manufacturing a nitride semiconductor device according to the first embodiment of the present invention.

  As shown in FIG. 2A, first, the surface of the silicon substrate 10 is oxidized by annealing the silicon substrate 10 at a temperature of about 1000 ° C. in an atmosphere containing oxygen gas using an oxidation furnace, for example. A silicon oxide mask layer (first layer) 40 is formed on the surface of the silicon substrate 10 (first step).

  Next, as shown in FIG. 2B, a resist mask layer 50 patterned in a predetermined shape is formed on the silicon oxide mask layer 40 by using photolithography (second step). In the region where the resist mask layer 50 is not formed, the silicon oxide mask layer 40 is exposed.

  Next, as shown in FIG. 2C, the silicon oxide mask layer 40 is removed using the resist mask layer 50 as a mask, for example, by etching with dilute hydrofluoric acid (third step). That is, the silicon oxide mask layer 40 exposed in a region where the resist mask layer 50 is not formed (an opening portion of the resist mask layer 50) is removed, thereby providing an opening in the silicon oxide mask layer 40. Thereby, the silicon substrate 10 is exposed in the portion where the silicon oxide mask layer 40 is removed.

  Next, after removing the resist mask layer 50 by a predetermined method, the silicon substrate 10 on which the silicon oxide mask layer 40 is formed is put into an annealing furnace and annealed at a temperature of about 700 ° C. or higher in an ammonia atmosphere, for example. The surface of the silicon substrate 10 is nitrided (fourth step). As a result, as shown in FIG. 4D, the exposed surface of the silicon substrate 10 is nitrided using the silicon oxide mask layer 40 as a mask, and the selective growth mask layer 20 made of silicon nitride is partially formed on the surface of the silicon substrate 10. Can be formed. Note that the selective growth mask layer 20 is not formed on the silicon substrate 10 covered with the silicon oxide mask layer 40, and this portion becomes an opening of the selective growth mask layer 20.

  Next, as shown in FIG. 2E, the silicon oxide mask layer 40 is also removed by cleaning including hydrogen peroxide (for example, RCA cleaning) or cleaning with dilute hydrofluoric acid and also cleaning of the silicon substrate 10 (see FIG. 2E). Fifth step). Thereby, the silicon substrate 10 existing under the silicon oxide mask layer 40 is exposed.

  Next, as shown in FIG. 2F, the silicon substrate 10 whose surface is exposed is put into a crystal growth furnace, and the silicon substrate 10 in the opening portion of the selective growth mask layer 20, that is, the exposed silicon substrate. The nitride semiconductor layer 30 is crystal-grown on the silicon 10 (sixth step).

  As described above, the nitride semiconductor device 1 according to the first embodiment of the present invention can be manufactured.

  Next, a specific example of the nitride semiconductor device 1 according to the first embodiment of the present invention will be described with reference to FIGS. 3 (a) and 3 (b). FIG. 3A is a schematic diagram in which a section of the nitride semiconductor device according to the first embodiment of the present invention is partially enlarged, and FIG. 3B is a section in the section of FIG. It is a SEM photograph. Note that the sample of the nitride semiconductor device 1 shown in FIG. 3B uses MOCVD (Metal Organic Chemical Vapor Deposition) as a crystal growth furnace, and the nitride semiconductor layer 30 has a film thickness. A 50 nm aluminum nitride layer (AlN) 30a and a 2800 nm gallium nitride layer (GaN) 30b were formed. Further, as the silicon substrate 10, a silicon substrate having a (111) plane as a main surface was used. The plane orientation of a GaN-based crystal belonging to the hexagonal system is indicated by the c-plane, a-plane, and m-plane, and the crystal axis directions are indicated by the c-axis, a-axis, and m-axis. The c-plane is the (0001) plane, and the c-axis indicates the normal vector of the c-plane. The a-plane is the (11-20) plane, and the a-axis indicates the normal vector of the a-plane. The m-plane is a (10-10) plane, and the m-axis indicates a normal vector of the m-plane. In general, in crystal growth of nitride semiconductors by MOCVD, it is easier to control crystal growth in the a-plane axis direction than in the m-axis direction. For this reason, in FIGS. 3A and 3B, stripes are formed in a direction rotated 90 degrees around the c-axis. In addition, by doing so, there are advantages that the selective growth can be easily controlled and the m-plane which is a cleavage plane can be used efficiently.

  As shown in FIGS. 3A and 3B, an aluminum nitride layer 30a is formed on the silicon substrate 10 where the selective growth mask layer 20 made of SiN is not formed (the opening of the selective growth mask layer 20). And the nitride semiconductor layer 30 in which the gallium nitride layer 30b is laminated is formed. On the other hand, the aluminum nitride layer 30 a and the gallium nitride layer 30 b are not formed on the selective growth mask layer 20. Thus, it can be seen that selective growth of the nitride semiconductor layer 30 can be realized by the selective growth mask layer 20.

  At this time, an aluminum nitride layer is also deposited on the selective growth mask layer 20 made of SiN depending on the film forming conditions for forming the aluminum nitride layer 30a. In this case, since the aluminum nitride deposited on the selective growth mask layer 20 cannot take over the crystallinity of the silicon substrate 10, it becomes a polycrystalline film. Therefore, when the gallium nitride layer 30b is formed after forming the aluminum nitride layer, gallium nitride cannot grow on the polycrystalline aluminum nitride layer, and the aluminum nitride layer 30a on the opening of the selective growth mask layer 20 is not formed. Then, the gallium nitride layer 30b is selectively grown. In this way, selective growth of the nitride semiconductor layer can be realized.

  In the present embodiment, since the substrate having the (111) plane as the main surface is used as the silicon substrate 10, the (0001) plane nitride semiconductor layer 30 is formed on the (111) plane of the silicon substrate 10. Crystal grows. Further, as shown in FIGS. 3A and 3B, the (10-12) plane is also formed in the gallium nitride layer 30b, but by changing the growth conditions of the gallium nitride layer 30b. The (10-10) plane and (11-20) plane can be stably grown, and the side surfaces of the nitride semiconductor layer 30 such as the gallium nitride layer 30b can be grown vertically.

  When the growth rate of the crystal in the horizontal direction (lateral direction) with respect to the silicon substrate 10 is increased during the growth of the nitride semiconductor layer 30, the mask pattern of the selective growth mask layer 20 is (11 −20) It is desirable that the surface be formed so as to be easily exposed. Specifically, the mask pattern of the selective growth mask layer 20 may be formed in a straight line extending in a direction parallel to the m-axis of the nitride semiconductor layer 30.

  The plane orientations of the (0001) plane nitride semiconductor layer 30 grown on the (111) plane of the silicon substrate 10 are as follows. The (11-20) plane in the (0001) plane nitride semiconductor layer 30 is parallel to the (112) plane of the (111) plane silicon substrate 10 and (10−) in the (0001) plane nitride semiconductor layer 30. 10) The plane is parallel to the (1-10) plane of the silicon substrate 10.

  As described above, according to the nitride semiconductor device 1 according to the first embodiment of the present invention, the silicon nitride layer as the selective growth mask layer 20 is formed by nitriding a part of silicon of the silicon substrate 10. Thereby, the crystallinity of the surface of the silicon substrate 10 which is the base of the nitride semiconductor layer 30 in the opening region of the selective growth mask layer 20 is not deteriorated. Therefore, the nitride semiconductor layer 30 having excellent crystallinity can be formed on the silicon substrate 10 in the opening region of the selective growth mask layer 20.

  Further, according to the method for manufacturing the nitride semiconductor device 1 according to the first embodiment of the present invention, the nitride semiconductor layer 30 is formed on the silicon substrate 10 by using the silicon oxide mask layer 40 to form a nitride semiconductor crystal. Can be protected until just before growth. That is, the formation region of the nitride semiconductor layer 30 on the silicon substrate 10 is not damaged at the time of film formation or etching of various layers in the second to fifth steps after the first step. Therefore, the surface of the silicon substrate 10 that is the formation region of the nitride semiconductor layer 30 can be kept clean without any deterioration until just before crystal growth of the nitride semiconductor layer 30 in the sixth step. Therefore, the nitride semiconductor layer 30 having excellent crystallinity can be formed at a low cost and a short tact time. In addition, according to the manufacturing method according to the present embodiment, there is no step of separately forming a base semiconductor layer only for forming the nitride semiconductor layer 30 as in the prior art.

  Furthermore, according to the manufacturing method according to the present embodiment, since silicon nitride is used as the selective growth mask layer 20, not only the selective growth mask layer 20 functions as a selective growth mask for the nitride semiconductor layer 30, but also the first In step 5, the silicon oxide mask layer 40 can be made to function as a mask for selectively removing with hydrofluoric acid.

  In this embodiment, since the selective growth mask layer 20 is for nitriding a part of the surface of the silicon substrate 10, the selective growth mask layer 20 is formed so as to be embedded in the surface of the silicon substrate 10. Is done. For this reason, the surface of the selective growth mask layer 20 exists only closer to the silicon substrate 10 than the contact surface where the silicon substrate 10 and the nitride semiconductor layer 30 are in contact, and does not exist on the nitride semiconductor layer 30 side. Become. That is, the surface of the selective growth mask layer 20 is on the same plane as the contact surface between the silicon substrate 10 and the nitride semiconductor layer 30 or closer to the silicon substrate 10 than the contact surface.

  As a result, when the nitride semiconductor layer 30 is formed, the opening region of the selective growth mask layer 20 is positioned at the highest position. Therefore, when the selective growth mask layer 20 is formed or when the nitride semiconductor layer 30 is formed. In this case, particles, watermarks, and the like that cause the defects of the nitride semiconductor are less likely to remain in the formation region of the nitride semiconductor layer 30. Therefore, a high quality nitride semiconductor layer 30 with excellent crystallinity can be formed.

  Further, as described above, in this embodiment, the selective growth mask layer 20 nitrides a part of the silicon substrate 10, and therefore the interface between the selective growth mask layer 20 and the silicon substrate 10 may be exposed even once. Absent. Therefore, in the vicinity of the interface between the selective growth mask layer 20 and the silicon substrate 10, impurities such as carbon atoms do not exist other than those originally present inside the silicon substrate 10. Accordingly, when the carbon concentration is continuously measured in the depth direction from the selective growth mask layer 20 toward the silicon substrate 10, the selective growth mask layer 20 and the silicon are separated from each other with the interface between the selective growth mask layer 20 and the silicon substrate 10 as a boundary. The carbon atom concentration between the substrate 10 and the substrate 10 is constant, and the carbon atom concentration in the vicinity of the interface between the selective growth mask layer 20 and the silicon substrate 10 does not change.

  When an excellent crystalline nitride semiconductor layer is grown on a silicon substrate, silicon oxide becomes a selective growth mask layer, so that a natural oxide film on the silicon substrate in the region where the nitride semiconductor layer is formed Should be removed sufficiently. However, according to the manufacturing method according to the present embodiment, the formation region of the nitride semiconductor layer 30 is covered with the silicon oxide mask layer 40 until immediately before the crystal growth of the nitride semiconductor layer 30, and the silicon oxide mask layer 40 is removed immediately before crystal growth of the nitride semiconductor layer 30. Thereby, the surface of the silicon substrate 10 in the region where the nitride semiconductor layer 30 is formed can be kept clean without any deterioration until immediately before the crystal growth of the nitride semiconductor layer 30. Thereby, the nitride semiconductor layer 30 having excellent crystallinity can be selectively crystal-grown.

(Second Embodiment)
Next, a nitride semiconductor device 2 according to a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a cross-sectional view showing a configuration of a nitride semiconductor device according to the second embodiment of the present invention. In FIG. 4, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

  As shown in FIG. 4, the nitride semiconductor device 2 according to the second embodiment of the present invention includes a silicon substrate 10, a selective growth mask layer 20, and a nitride semiconductor layer 31.

  The selective growth mask layer 20 according to the present embodiment is the same as the selective growth mask layer 20 as in the first embodiment, but a plurality of openings for exposing the silicon substrate 10 are formed. That is, there are a plurality of locations where the silicon substrate 10 and the nitride semiconductor layer 31 are in contact.

  Furthermore, the nitride semiconductor layer 31 according to the present embodiment is directly formed not only on the silicon substrate 10 in the opening of the selective growth mask layer 20 but also on the selective growth mask layer 20. That is, in this embodiment, crystal growth of the nitride semiconductor starts from the silicon substrate 10 in the plurality of openings, and the nitride semiconductor is selectively grown in the lateral direction (horizontal direction of the silicon substrate 10) as the crystal growth proceeds. The nitride semiconductor layers 31 are formed by bonding the nitride semiconductors grown in the lateral direction.

  As described above, the nitride semiconductor device 2 according to the present embodiment can achieve the same effects as the nitride semiconductor device 1 according to the first embodiment. Furthermore, according to the present embodiment, the nitride semiconductor device 2 can form the nitride semiconductor layer 31 having a large area while having high quality and excellent crystallinity.

  In the present embodiment, the opening of the selective growth mask layer 20 is preferably formed in a linear shape along a direction parallel to the m-axis of the nitride semiconductor layer 31. Thereby, the crystal growth rate in the a-axis direction of the nitride semiconductor layer 31 can be increased, and the selective growth in the lateral direction can be easily performed. Furthermore, the growth conditions of the nitride semiconductor layer 31 are adjusted so that the crystal growth surface of the nitride semiconductor layer 31 in the initial stage of growth becomes a surface that forms an acute angle with respect to the silicon substrate 10 such as the (11-22) plane. It is preferable. Thereby, threading dislocations extending in the vertical direction from the underlying layer of the silicon substrate 10 can be bent in the horizontal direction with respect to the silicon substrate 10. Thereby, selective growth in the lateral direction of the nitride semiconductor layer 31 can be performed more easily. The threading dislocation is a dislocation that propagates a dislocation defect and penetrates the crystal growth surface.

  The nitride semiconductor device 2 according to this embodiment can be manufactured by the same method as the method for manufacturing the nitride semiconductor device 1 according to the first embodiment.

(Third embodiment)
Next, a nitride semiconductor device 3 according to a third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view showing a configuration of a nitride semiconductor device according to the third embodiment of the present invention.

  As shown in FIG. 5, the nitride semiconductor device 3 according to the third embodiment of the present invention includes a silicon substrate 11, a selective growth mask layer 21, and a nitride semiconductor layer 32.

  Similar to the first embodiment, the silicon substrate 11 according to the present embodiment is a silicon substrate having a (111) plane as a main surface. However, in the present embodiment, unlike the first embodiment, the silicon substrate 11 is a silicon substrate. A recess 11 a is formed on 11. That is, the convex portion 11b is formed on the silicon substrate 11 so as to be sandwiched between the adjacent concave portions 11a.

  The selective growth mask layer 21 according to this embodiment is formed by nitriding a part of the silicon substrate 11 as in the first embodiment. In this embodiment, the selective growth mask layer 21 is the first embodiment. Unlike the form, it is formed only on the surface of the concave portion 11a of the silicon substrate 11, and the selective growth mask layer 21 is not formed on the upper surface of the convex portion 11b. That is, the selective growth mask layer 21 does not exist on the silicon substrate 11 other than the recess 11a.

  A nitride semiconductor layer 32 is formed on the silicon substrate 11 other than the recesses 11a, that is, on the projections 11b so as to be in contact with the silicon substrate 11. The nitride semiconductor layer 32 is not directly formed on the selective growth mask layer 21 in the recess 11 a, but is formed in the lateral direction of the silicon substrate 11 and is separated from the selective growth mask layer 21 via the gap 60. Thus, it is formed even above the selective growth mask layer 21.

  The nitride semiconductor device 3 according to the third embodiment of the present invention configured as described above can be manufactured, for example, according to the method for manufacturing the nitride semiconductor device 1 according to the first embodiment.

  For example, in the third step of the manufacturing method of the first embodiment shown in FIG. 2C, the silicon oxide mask layer 40 is removed by etching with dilute hydrofluoric acid, but RIE (Reactive Ion Etching) is used instead of dilute hydrofluoric acid. After the silicon oxide mask layer 40 is removed by dry etching using an apparatus such as), or in the same process as the silicon oxide mask layer 40 removal process, the silicon substrate in the portion where the silicon oxide mask layer 40 is removed is etched. do it. Thereby, the recessed part 11a can be formed in the silicon substrate 11, and the convex part 11b can be comprised.

  Further, after the recess 11a is formed by dry etching, a process may be added in which the recess 11a is further etched with dilute hydrofluoric acid to remove damage caused by dry etching remaining on the silicon substrate. Thereby, a high quality selective growth mask layer 21 can be formed.

  In addition, the nitride semiconductor device 3 which concerns on this embodiment can be manufactured by performing the process other than this by the same process as 1st Embodiment. However, it is preferable to adjust the growth conditions of the nitride semiconductor layer 32 so that the nitride semiconductor layer 32 is also formed above the selective growth mask layer 20.

  As described above, the nitride semiconductor device 3 according to the third embodiment of the present invention can achieve the same effects as the nitride semiconductor device 1 according to the first embodiment. Furthermore, according to the nitride semiconductor device 3 according to the present embodiment, the surface of the selective growth mask layer 21 is present at a position lower than the contact surface between the silicon substrate 11 and the nitride semiconductor layer 32. A gap 60 exists between the growth mask layer 21 and the nitride semiconductor layer 32. Thereby, the effect that the stress which generate | occur | produces between the nitride semiconductor layer 32 and the silicon substrate 11 can be relieved can also be acquired.

(Fourth embodiment)
Next, a nitride semiconductor device 4 according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view showing a configuration of a nitride semiconductor device according to the fourth embodiment of the present invention. In FIG. 6, the same components as those shown in FIG.

  As shown in FIG. 6, the nitride semiconductor device 4 according to the fourth embodiment of the present invention includes a silicon substrate 11, a selective growth mask layer 21, and a nitride semiconductor layer 33.

  The silicon substrate 11 according to this embodiment is the same silicon substrate 11 as in the third embodiment, but in this embodiment, a plurality of convex portions 11b are formed. That is, there are a plurality of locations where the silicon substrate 11 and the nitride semiconductor layer 33 are in contact.

  Furthermore, the nitride semiconductor layer 33 according to the present embodiment is formed not only on the upper surface of the convex portion 11 b of the silicon substrate 11 but also on the selective growth mask layer 20. That is, in this embodiment, crystal growth of a nitride semiconductor starts from the silicon substrate 11 at the plurality of protrusions 11b, and the nitride semiconductor is selectively grown in the lateral direction (horizontal direction of the silicon substrate 11) as the crystal growth proceeds. Thus, the nitride semiconductor layer 33 is formed by bonding the nitride semiconductors grown in the lateral direction.

  As described above, the nitride semiconductor device 4 according to the present embodiment can achieve the same effects as the nitride semiconductor device 3 according to the third embodiment. Furthermore, the nitride semiconductor device 4 according to the present embodiment can form the nitride semiconductor layer 33 having a large area while having high quality and excellent crystallinity due to the above configuration.

  In particular, in the nitride semiconductor device 4 according to the present embodiment, the gap 60 exists between the selective growth mask layer 21 and the nitride semiconductor layer 33 as in the nitride semiconductor device 3 according to the third embodiment. However, in the present embodiment, the gap 60 is sealed inside the nitride semiconductor layer 33. Therefore, the stress generated inside the nitride semiconductor device 4 can be relaxed without deteriorating the nitride semiconductor layer 33.

  In the present embodiment, the opening of the selective growth mask layer 21 is linear along the direction parallel to the m-axis of the nitride semiconductor layer 33, as in the selective growth mask layer 20 in the second embodiment. It is preferable to form. Thereby, the crystal growth rate in the a-axis direction of the nitride semiconductor layer 33 can be increased, and the selective growth in the lateral direction can be easily performed.

(Fifth embodiment)
Next, a nitride semiconductor device 5 according to a fifth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a cross-sectional view showing a configuration of a nitride semiconductor device according to the fifth embodiment of the present invention. In FIG. 7, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

  As shown in FIG. 7, the nitride semiconductor device 5 according to the fifth embodiment of the present invention is a high electron mobility transistor (HEMT), which includes a silicon substrate 10 and a selective growth mask layer. 20 and a buffer layer 71 that is a nitride semiconductor layer, and a buffer layer 72, an electron transit layer 73, and an electron supply layer 74 are sequentially formed on the buffer layer 71. On the electron supply layer 74, a source electrode 75S, a gate electrode 75G, and a drain electrode 75D are formed.

  The buffer layer 71 is formed in contact with the silicon substrate 10 in a region where the selective growth mask layer 20 is not formed, that is, in an opening portion of the selective growth mask layer 20. Further, the buffer layer 71 is also formed on the selective growth mask layer 20, and the growth of the nitride semiconductor starts from the silicon substrate 10 in the opening portion of the selective growth mask layer 20, as in the second embodiment. As the crystal growth proceeds, a nitride semiconductor is selectively grown in the lateral direction.

In the present embodiment, the buffer layer 71 is made of a nitride semiconductor and may be composed of a plurality of layers. The layer in contact with the silicon substrate 10 of the buffer layer 71 may be a layer made of, for example, Al _x Ga _(1-x) N (0 ≦ x ≦ 1). In this embodiment, aluminum nitride (x = 1) is used as a layer in contact with the silicon substrate 10. The layer that promotes selective growth in the lateral direction may be a layer made of Al _x Ga _(1-x) N (0 ≦ x ≦ 1). In this embodiment, gallium nitride (x = 0) is used as a layer that promotes selective growth in the lateral direction. Thus, in this embodiment, the buffer layer 71 is composed of a plurality of layers made of an aluminum nitride layer and gallium nitride as shown in FIG.

  The buffer layer 72 is a layer for alleviating warpage and cracks of the silicon substrate after the nitride semiconductor is formed. Therefore, the buffer layer 72 is preferably inserted, but may be omitted.

In the present embodiment, the buffer layer 72 may be a single film of Al _x Ga _(1-x) N (0 ≦ x ≦ 1) having a thickness of about 500 nm. In addition, the buffer layer 72 has a superlattice structure composed of Al _x Ga _(1-x) N (0 ≦ x <y) and Al _y Ga _(1-y) N (x <y ≦ 1). Also good. Further, the Al _x Ga _(1-x) N (0 ≦ x ≦ 1) single film and the superlattice structure may be combined. If the buffer layer 72 can be formed thick, the nitride semiconductor on the buffer layer 72 can be highly crystallized and is advantageous for increasing the breakdown voltage of the element. Since a warp or a crack is likely to occur, it is preferable to design the thickness of the buffer layer 72 appropriately.

  The electron transit layer 73 is a layer made of, for example, undoped GaN. In the present embodiment, undoped means that no impurity is intentionally introduced. As the electron transit layer 73, it is desirable that impurities such as carbon atoms trapping carriers are less mixed.

  The electron supply layer 74 is made of a material having a larger band gap than the electron transit layer 73 and generates a two-dimensional electron gas at the interface with the electron transit layer 73. For example, if the electron supply layer 74 is undoped AlGaN and the electron transit layer 73 is undoped GaN as described above, the heterogeneous interface between the electron transit layer 73 and the electron supply layer 74 is 2 due to the influence of spontaneous polarization and piezoelectric polarization. Dimensional electron gas is generated.

  The source electrode 75S and the drain electrode 75D are in ohmic contact with the nitride semiconductor in contact with these electrodes, and are, for example, electrodes having a laminated structure of Ti and Al.

  The gate electrode 75G has a Schottky junction with a layer in contact with the gate electrode 75G, and is, for example, an electrode having a stacked structure of a Ni layer, a Pt layer, and an Au layer.

  Thus, in the nitride semiconductor device 5 according to the fifth embodiment of the present invention, the active layer of the electron transit layer 73 and the electron supply layer 74 is formed on the nitride semiconductor layer (buffer layer 71). By operating the source electrode 75S and the drain electrode 75D, electrons run at high speed in the two-dimensional electron gas generated at the interface between the electron transit layer 73 and the electron supply layer 74, and a drain current flows. Then, by controlling the voltage of the gate electrode 75G, the depletion layer immediately below the gate electrode 75G can be controlled, and the drain current traveling in the secondary electron gas can be controlled.

  As described above, according to the nitride semiconductor device 5 according to the present embodiment, the density of threading dislocations in the active portion of the element is smaller than the density of threading dislocations 80 in the opening portion of the selective growth mask layer 20 due to the above configuration. . Thereby, the crystallinity of the active part of the element can be improved, so that the leakage current of the element can be reduced and a high breakdown voltage can be achieved.

  Next, a method for manufacturing the nitride semiconductor device 5 according to the fifth embodiment of the present invention will be described with reference to FIGS. FIG. 8 is a cross-sectional view showing a configuration of each step in the method for manufacturing the nitride semiconductor device 5 according to the fifth embodiment of the present invention.

  First, as shown in FIG. 8A, a predetermined pattern is selected on the silicon substrate 10 by the same processes (first to fifth processes) as the nitride semiconductor device 1 according to the first embodiment. A growth mask layer 20 is formed. In the present embodiment, the silicon substrate 10 is a substrate having a (111) plane on the surface, and the selective growth mask layer 20 is parallel to the m-axis, that is, the normal line of the (1-10) plane of the silicon substrate. A stripe pattern parallel to

  Next, the silicon substrate 10 on which the selective growth mask layer 20 is formed is put into a crystal growth furnace, and as shown in FIG. 8A, the buffer layer 71 made of a nitride semiconductor layer is in contact with the silicon substrate 10. Crystal growth. The buffer layer 71 is also grown in the horizontal direction with respect to the main surface of the silicon substrate 10 so as to be formed also on the selective growth mask layer 20.

  The crystal growth furnace may be any furnace that can form a nitride semiconductor, and MBE (molecular beam epitaxy), HVPE (hydride vapor phase epitaxy), etc. can be used, but mass productivity is high. It is desirable to use the MOCVD method that facilitates thin film control. In the present embodiment, the case where MOCVD is used will be described below.

After putting the silicon substrate 10 into the crystal growth furnace, annealing is performed at a high temperature of about 1200 ° C. in a mixed gas atmosphere of H ₂ and N ₂ . Next, the temperature is lowered to about 900 ° C. and trimethylaluminum (TMA) and ammonia gas are supplied to form a first buffer layer made of aluminum nitride having a high carbon concentration with a thickness of 20 nm. Next, after a high carbon concentration aluminum nitride film is formed, the growth temperature is raised again to 1100 ° C., and TMA and ammonia gas are supplied in the same manner as described above, so that a second carbon nitride made of low carbon concentration is formed. The buffer layer is formed with a film thickness of 150 nm. Next, in order to promote lateral selective growth, a third buffer layer made of gallium nitride is formed by supplying TMG and ammonia gas. Thereby, the buffer layer 71 having a three-layer structure can be formed.

Next, as shown in FIG. 8B, the buffer layer 72 is formed on the buffer layer 71. In this embodiment, as the buffer layer 72, a buffer layer 72 having a superlattice structure composed of an Al _0.2 Ga _0.8 N layer and an AlN layer is formed with a film thickness of about 500 nm.

  Next, as shown in FIG. 8C, the electron transit layer 73 is formed on the buffer layer 72. In this embodiment, an undoped gallium nitride layer having a thickness of about 2 μm is formed as the electron transit layer 73 at a temperature of about 1050 ° C.

  Next, as shown in FIG. 8D, the electron supply layer 74 is formed on the electron transit layer 73. In this embodiment, as the electron supply layer 74, an undoped aluminum gallium nitride layer having a thickness of about 50 nm is formed at a temperature of about 1100 ° C.

  After the above layers are continuously formed, the silicon substrate 10 on which each layer is formed is taken out from the crystal growth furnace.

  Next, Ti and Al are sequentially formed on the electron supply layer 74 by using an EB (electron beam) vapor deposition apparatus, and unnecessary portions are removed by a lift-off method, thereby forming an ohmic as shown in FIG. A source electrode 75S and a drain electrode 75D as electrodes are formed in a predetermined pattern.

  Next, in the same manner as the source electrode 75S and the drain electrode 75D, Pt and Au are sequentially formed on the electron supply layer 74 using an EB vapor deposition apparatus, and unnecessary portions are removed by a lift-off method. Thus, as shown in FIG. 8F, the gate electrode 75G is formed in a predetermined pattern between the source electrode 75S and the drain electrode 75D.

  As described above, the nitride semiconductor device according to the fifth embodiment of the present invention can be manufactured.

  As described above, the nitride semiconductor device and the manufacturing method thereof according to the present invention have been described based on the embodiments, but the present invention is not limited to the above-described embodiments. For example, it is realized by arbitrarily combining the components and functions in each embodiment without departing from the scope of the present invention, or the form obtained by subjecting each embodiment to various modifications conceived by those skilled in the art. Forms are also included in the present invention.

  The nitride semiconductor device and the manufacturing method thereof according to the present invention are useful for electronic devices including a nitride semiconductor, such as a field effect transistor having a nitride semiconductor layer.

1, 2, 3, 4, 5 Nitride semiconductor device 10, 11 Silicon substrate 11a Recess 11b Protrusion 20, 21 Selective growth mask layer 30, 31, 32, 33: Nitride semiconductor layer 30a Aluminum nitride layer 30b Gallium nitride layer 40 silicon oxide mask layer 50 resist mask layer 60 void 71 buffer layer 72 buffer layer 73 electron transit layer 74 electron supply layer 75S source electrode 75D drain electrode 75G gate electrode 80 threading dislocation

Claims (11)

A silicon substrate;
A selective growth mask layer made of silicon nitride formed on a part of the silicon substrate and in contact with the silicon substrate;
A nitride semiconductor device, wherein a nitride semiconductor layer is formed on the silicon substrate on which the selective growth mask layer is not formed so as to be in contact with the silicon substrate. The silicon substrate has a recess;
The nitride semiconductor device according to claim 1, wherein the selective growth mask layer is formed only in the recess. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor layer is also formed on the selective growth mask layer. 4. The nitride according to claim 1, wherein a surface of the selective growth mask layer does not exist on the nitride semiconductor layer side with respect to a contact surface where the silicon substrate and the nitride semiconductor layer are in contact with each other. Semiconductor device. The nitridation according to claim 1, wherein a carbon atom concentration between the selective growth mask layer and the silicon substrate is constant with an interface between the selective growth mask layer and the silicon substrate as a boundary. Semiconductor device. The nitride semiconductor device according to claim 1, wherein the selective growth mask layer is formed by nitriding a part of a surface of the silicon substrate. The nitride semiconductor device according to claim 1, wherein an active layer made of a nitride semiconductor is formed on the nitride semiconductor layer. Oxidizing the surface of the silicon substrate to form a first layer made of silicon oxide;
Patterning the first layer to expose the surface of the silicon substrate;
Nitriding the exposed surface of the silicon substrate using the patterned first layer as a mask to form a second layer made of silicon nitride;
Removing the first layer to expose the silicon substrate;
Forming a nitride semiconductor layer on the silicon substrate exposed by removing the first layer. A method for manufacturing a nitride semiconductor device. Furthermore, before the step of forming the second layer, including a step of forming a recess in the silicon substrate,
The method for manufacturing a nitride semiconductor device according to claim 8, wherein in the step of forming the second layer, the second layer is formed only in the recess. In the step of forming the nitride semiconductor layer,
The method for manufacturing a nitride semiconductor device according to claim 8, wherein the nitride semiconductor layer is also formed on the second layer. The method for manufacturing a nitride semiconductor device according to claim 8, further comprising a step of forming an active layer made of a nitride semiconductor on the nitride semiconductor layer.