JP2012004151A - Semiconductor device and driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a partial-depletion type transistor formed on an insulation layer, which reduces history effects and realizes high ON/OFF ratio and steep subthreshold characteristics.SOLUTION: The semiconductor device comprises: a partial-depletion type first transistor including a first conductivity type source region, a drain region of the first conductivity type, and a second conductivity type body region which are formed on a semiconductor layer on an insulation layer, a first gate insulation film, and a first gate electrode; and a second transistor including a second conductivity type source region, a second conductivity type drain region and a first conductivity type body region which are formed on a semiconductor layer on an insulation layer, a second gate insulation film, and a second gate electrode. The second conductivity type body region of the first transistor is connected to one of the second conductivity type source region and the second conductivity type drain region of the second transistor.

Description

  The present invention relates to a semiconductor device including a partially depleted transistor formed on an insulating layer, and a driving method thereof.

A semiconductor device having an SOI (Silicon On Insulator) structure in which a thin semiconductor layer is formed on an insulating layer is being developed and put into practical use as a low power semiconductor device for the next generation.
MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor) with SOI structure has features such as a high ON / OFF ratio of drain current, steep subthreshold characteristics, low noise, and low parasitic capacitance. It is used.
Among MISFETs having an SOI structure, a partially depleted (PD) MISFET can be manufactured as easily as a conventional bulk structure MISFET, and thus is widely applied to semiconductor products.

In a partially depleted MISFET, the body region is electrically isolated from other regions by an insulating layer, and the potential (body potential) is floating. For this reason, in the partially depleted MISFET, a phenomenon called a substrate floating effect must be taken into consideration. The substrate floating effect appears in a history effect, etc., in which the body potential and drain current fluctuate due to the history of voltage applied to the gate until then, and the device characteristics become unstable.
Such a phenomenon can be suppressed by a body potential fixing method as shown in Patent Document 1. In Patent Document 1, the body potential is fixed by flowing a leak current from the body region.

JP 2004-119884 A

  However, when the body potential is fixed by the conventional method, the device characteristics are stabilized, but a large parasitic capacitance is generated because the fixed potential portion is connected to the gate capacitance. Therefore, this time, the ON current decreases, and as a result, there arises a problem that the drain current ON / OFF ratio decreases, and there is a possibility that the advantages of SOI cannot be fully utilized.

  The present invention has been made in view of the above technical problems. Some aspects of the present invention relate to reducing the history effect and achieving a high ON current (ON / OFF ratio) in a partially depleted transistor formed on an insulating layer.

In some embodiments of the present invention, a semiconductor device includes a first conductivity type first source region, a first conductivity type first drain region, and a first source region and a first drain region formed in a semiconductor layer. A first body region of a second conductivity type formed between, a first gate insulating film formed on the first body region, a first gate electrode formed on the first gate insulating film, A first depletion type transistor including a second conductivity type second source region, a second conductivity type second drain region formed in a semiconductor layer, and a second source region and a second drain region. A first conductivity type second body region formed therebetween, a second gate insulating film formed on the second body region, and a second gate electrode formed on the second gate insulating film. A semiconductor layer formed on the insulating layer Are, first body region is connected to one of the second source region and second drain region.
According to this aspect, by setting the second transistor to the ON state, the potential of the first body region of the first transistor can be set to a predetermined value from the outside, and the history effect can be reduced. By turning off the second transistor, the potential of the first body region of the first transistor is floated, and a high ON current (ON / OFF ratio) can be realized.

In the above aspect, the first drain region is formed on one side when viewed from the first body region, and the first source region and one of the second source region and the second drain region are formed on the other side. It is desirable.
According to this, the contact area between the first body region and the one of the second source region and the second drain region can be increased, and the effective gate width of the first transistor can be decreased.

In the above-described aspect, it is desirable that the first gate electrode and the second gate electrode are electrically connected.
According to this, the body potential of the first transistor can be set to the predetermined value by turning the second transistor on at the same time that the first transistor is turned off, and the first transistor is turned on. At the same time, by turning off the second transistor, the body potential of the first transistor can be brought into a floating state.

In the above-described aspect, the first source region and the one of the second source region and the second drain region are in contact with each other, and the first source region and the other of the second source region and the second drain region are in contact with each other. Are preferably connected by a conductor.
According to this, forward current is suppressed from flowing in the PN junction formed between the first source region and the one of the second source region and the second drain region.

In the above-described aspect, the second conductivity type third source region, the second conductivity type third drain region, and the third conductivity region formed between the third source region and the third drain region are formed in the semiconductor layer. A partially-depleted third body including a first conductivity type third body region, a third gate insulating film formed on the third body region, and a third gate electrode formed on the third gate insulating film. The transistor, the first conductivity type fourth source region formed in the semiconductor layer, the first conductivity type fourth drain region, and the second conductivity formed between the fourth source region and the fourth drain region. And a fourth transistor including a fourth body region of the mold, a fourth gate insulating film formed on the fourth body region, and a fourth gate electrode formed on the fourth gate insulating film. The third body region includes the fourth source region and the fourth gate region. Is connected to one of the in-region, it is desirable to constitute the inverter by the first transistor and the third transistor.
According to this, it is possible to provide an inverter circuit that reduces the history effect and realizes a high ON current (ON / OFF ratio).

In some aspects of the present invention, a method of driving the above-described semiconductor device includes: a first gate voltage that causes a first transistor to be in an OFF state and a second transistor to be in an ON state; Applying a predetermined voltage to the first body region of the first transistor through the second transistor, and applying a second gate voltage for turning the first transistor on and the second transistor off. Passing a current between the source and the drain of the first transistor while applying the voltage to the first gate electrode and the second gate electrode, respectively.
According to this aspect, when the first transistor is turned off, the potential of the first body region of the first transistor is set to an arbitrary value from the outside by turning the second transistor on, and the history effect is reduced. Can be reduced. When the first transistor is turned on, the second transistor is turned off, thereby floating the potential of the first body region of the first transistor and realizing a high ON current (ON / OFF ratio). Can do.

In the driving method described above, the threshold voltage value of the second transistor is a value between the first gate voltage and the second gate voltage, and the difference between the threshold voltage of the second transistor and the second gate voltage. Is greater than the difference between the threshold voltage of the first transistor and the first gate voltage.
According to this, when the second transistor is turned on, the drain current of the second transistor sufficiently flows, and when the second transistor is turned off, the drain current of the second transistor is set to a value close to zero. be able to.

1 is a schematic plan view showing a semiconductor device according to a first embodiment of the present invention. AA 'line sectional view and BB'-B "line sectional view of FIG. The figure which shows the example of the transfer characteristic of the transistor in 1st Embodiment The plane schematic diagram which shows the semiconductor device which concerns on the 2nd Embodiment of this invention. The figure which shows the example of the transfer characteristic of the transistor in 2nd Embodiment Schematic plan view showing a semiconductor device according to a third embodiment of the present invention. The plane schematic diagram which shows the semiconductor device which concerns on the 4th Embodiment of this invention. Schematic plan view showing a semiconductor device according to a fifth embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail. In addition, this embodiment demonstrated below does not unduly limit the content of this invention described in the claim. Further, not all of the configurations described in the present embodiment are essential as a solution means of the present invention. The same constituent elements are denoted by the same reference numerals, and description thereof is omitted.

<1. First Embodiment>
FIG. 1 is a schematic plan view showing a semiconductor device according to the first embodiment of the present invention. 2A is a cross-sectional view taken along the line AA ′ in FIG. 1, and FIG. 2B is a cross-sectional view taken along the line BB′-B ”in FIG. 1. The semiconductor device 1 shown in FIG. Comprises a first transistor Tr1 and a second transistor Tr2.

As shown in FIG. 2A, the first transistor Tr1 includes an N-type (first conductivity type) source region 11 (first source region) formed in the semiconductor layer 101 on the insulating layer 100, and an N-type transistor. A drain region 12 (first drain region), and a P-type (second conductivity type) body region 13 (first body region) formed between the source region 11 and the drain region 12, This is an N-channel transistor including a gate insulating film 14 (first gate insulating film) formed on the body region 13 and a gate electrode 15 (first gate electrode) formed on the gate insulating film 14. The body region 13 is located in a region immediately below the gate electrode 15 in the semiconductor layer 101.
Contact electrodes 111 and 112 are connected to the source region 11 and the drain region 12, respectively.
The first transistor Tr1 has a partial depletion in which a neutral region that is not depleted remains at the bottom of the body region 13 even during operation (when a voltage higher than a threshold is applied to the gate electrode 15 to turn on the first transistor Tr1). Type transistor.

As shown in FIG. 2B, the second transistor Tr2 includes a P-type (second conductivity type) source region 21 (second source region) formed in the semiconductor layer 101 on the insulating layer 100, and a P-type. A drain region 22 (second drain region), and an N-type (first conductivity type) body region 23 (second body region) formed between the source region 21 and the drain region 22, This is a P-channel transistor including a gate insulating film 24 (second gate insulating film) formed on the body region 23 and a gate electrode 25 (second gate electrode) formed on the gate insulating film 24. The body region 23 is located in a region immediately below the gate electrode 25 in the semiconductor layer 101.
A contact electrode 121 is connected to the source region 21.

The insulating layer 100 is, for example, a silicon oxide (SiO ₂ ) layer, and the semiconductor layer 101 is, for example, a single crystal silicon (Si) layer. The gate insulating films 14 and 24 are, for example, silicon oxide (SiO ₂ ) films, and the gate electrodes 15 and 25 are formed of, for example, metal. An element isolation film 102 is formed around the semiconductor device 1. An interlayer insulating film 103 is formed on the first and second transistors Tr1 and Tr2.

The P-type drain region 22 of the second transistor Tr2 is connected to the P-type body region 13 of the first transistor Tr1.
Accordingly, the source region 21 of the second transistor Tr2 is connected to a predetermined potential, and the second transistor Tr2 is turned on to set the body region 13 of the first transistor Tr1 to the predetermined potential (body contact). can do. Therefore, the history effect in the first transistor Tr1 can be suppressed and stable operation can be realized.
Further, by turning off the second transistor Tr2, the body region 13 of the first transistor Tr1 can be blocked from the predetermined potential and floated (body float). Therefore, the gate capacity of the first transistor Tr1 is suppressed, and a high ON current (ON / OFF ratio) can be obtained.

  The gate electrode 15 of the first transistor Tr1 and the gate electrode 25 of the second transistor Tr2 are electrically connected. Accordingly, the same gate voltage is applied to the first transistor Tr1 and the second transistor Tr2. By sharing the gate voltage applied to the first transistor Tr1 and the second transistor Tr2, the number of signal lines and the number of terminals can be reduced.

  In this configuration, for example, when the gate voltage V1 (first gate voltage) is applied to the gate electrodes 15 and 25 of the first and second transistors Tr1 and Tr2, the N-channel first transistor Tr1 is turned off. At the same time, it is desirable to turn on the P-channel second transistor Tr2. Further, when a gate voltage V2 (second gate voltage) higher than the gate voltage V1 is applied to the gate electrodes 15 and 25 of the first and second transistors Tr1 and Tr2, the N-channel first transistor Tr1. It is desirable to turn off the P-channel second transistor Tr2 at the same time as turning on. Thereby, when the first transistor Tr1 is in the OFF state, the body potential of the first transistor Tr1 is set to the predetermined potential (body contact), and when the first transistor Tr1 is in the ON state, the body potential of the first transistor is floated. (Body float) can be. That is, the body contact and the body float of the first transistor Tr1 can be switched in synchronization with the ON / OFF operation of the first transistor Tr1.

In the MISFET such as the first transistor Tr1, when the drain voltage is 1.1V or more, the impact ionization phenomenon occurs. As a result, the body potential increases, the threshold voltage decreases, and the ON current increases. is there. In the present embodiment, the first transistor Tr1 has an SOI structure formed on the insulating layer. For this reason, if the body potential of the first transistor is floated in synchronism with the ON operation of the first transistor Tr1, the above-described action with an increase in the body potential appears strongly, and a high ON current can be realized.
Here, if the first transistor Tr1 is turned off while the body potential is left floating, the threshold voltage has already decreased, so that an OFF current may flow through the first transistor Tr1. However, in this embodiment, if the body potential of the first transistor is set to the predetermined potential in synchronization with the OFF operation of the first transistor Tr1, the body potential is reset, the threshold voltage is increased again, and the OFF current is increased. Can be reduced.
Thus, by switching between the body contact and the body float of the first transistor Tr1 in synchronization with the ON / OFF operation of the first transistor Tr1, not only a high ON current but also a low OFF current (high ON / OFF ratio) ) And a steep subthreshold characteristic can be realized.

3A and 3B are diagrams illustrating an example of the transfer characteristic of the transistor in the first embodiment. FIG. 3A shows the transfer characteristic of the first transistor Tr1, and FIG. 3B shows the transfer characteristic of the second transistor Tr2. An example is shown.
A high ON / OFF ratio is required for the first transistor Tr1. Therefore, as shown in FIG. 3A, when the gate voltage can be switched between V1 and V2 (V2> V1), the threshold voltage Vth1 of the first transistor Tr1 is set to a value near the gate voltage V1. It is desirable to set (Vth1≈V1).
On the other hand, what is required of the second transistor Tr2 is that the body region of the first transistor Tr1 is connected to a predetermined potential or is in a floating state, rather than an ON / OFF ratio as an electric signal. That is, in the second transistor Tr2, it is required that the drain current sufficiently flows at the gate voltage V1 and that the drain current be as close to 0 as possible at the gate voltage V2. Therefore, as shown in FIG. 3B, it is desirable to set the threshold voltage Vth2 of the second transistor Tr2 to a value between the gate voltage V1 and the gate voltage V2 (V2>Vth2> V1). Furthermore, it is desirable that the absolute value of the difference between the threshold voltage Vth2 of the second transistor Tr2 and the gate voltage V2 is larger than the absolute value of the difference between the threshold voltage Vth1 of the first transistor Tr1 and the gate voltage V1 (| V2−Vth2). |> | V1-Vth1 |).

  Referring again to FIGS. 1 and 2B, the second transistor Tr2 is formed at a position opposite to the drain region 12 of the first transistor Tr1 when viewed from the body region 13 of the first transistor Tr1. The drain region 22 of the second transistor Tr2 is formed so as to be in direct contact with the source region 11 of the first transistor Tr1. The body region 23 and the source region 21 of the second transistor Tr2 are formed at positions opposite to the source region 11 of the first transistor Tr1 when viewed from the drain region 22 of the second transistor Tr2. Accordingly, the contact area between the body region 13 of the first transistor Tr1 and the drain region 22 of the second transistor Tr2 can be increased, and the effective gate width of the first transistor Tr1 can be decreased. Further, according to this configuration, an increase in the area of the gate electrode is suppressed, so that an increase in gate capacitance is suppressed.

  The contact electrode 111 connected to the source region 11 of the first transistor Tr1 and the contact electrode 121 connected to the source region 21 of the second transistor Tr2 are preferably connected by a conductor wiring (not shown). For example, when the source region 11 of the first transistor is connected to the first power supply potential Vss, the source region 21 of the second transistor is also connected to the first power supply potential Vss. The order between the source region 11 of the first transistor and the drain region 22 of the second transistor is between the potential connected to the source region 11 of the first transistor and the potential connected to the source region 21 of the second transistor. This is because if there is a difference exceeding the direction drop voltage, a forward current may flow between the source region 11 of the first transistor and the drain region 22 of the second transistor.

Although the example in which the drain region of the second transistor Tr2 is connected to the body region 13 of the first transistor Tr1 has been described here, the source region of the second transistor Tr2 is connected to the body region 13 of the first transistor Tr1. May be.
In that case, the drain region of the second transistor Tr2 is connected to the predetermined potential. In this case, the source region of the second transistor Tr2 is in contact with the source region 11 of the first transistor Tr1, and the body region 23 and the drain region of the second transistor Tr2 are viewed from the source region of the second transistor Tr2. The first transistor Tr1 is formed at a position opposite to the source region 11. In that case, it is desirable that the contact electrode 111 connected to the source region 11 of the first transistor and the contact electrode connected to the drain region of the second transistor Tr2 are connected by a conductor wiring.

<2. Second Embodiment>
FIG. 4 is a schematic plan view showing a semiconductor device according to the second embodiment of the present invention. The semiconductor device 2 according to the second embodiment includes a third transistor Tr3 and a fourth transistor Tr4. Unlike the N-channel type first transistor Tr1 in the first embodiment, the third transistor Tr3 is a P-channel type. Unlike the N-channel type first transistor Tr1 in the first embodiment, the fourth transistor Tr4 is an N-channel type. Although different from the channel-type second transistor Tr2, the other points are the same as those of the first embodiment, and a duplicate description is omitted.

  In the second embodiment, when a gate voltage V3 (second gate voltage) is applied to the gate electrodes 15 and 25 of the third and fourth transistors Tr3 and Tr4, the P-channel type third transistor Tr3. Can be turned on, and the N-channel fourth transistor Tr4 can be turned off. Further, when a gate voltage V4 (first gate voltage) higher than the gate voltage V3 is applied to the gate electrodes 15 and 25 of the third and fourth transistors Tr3 and Tr4, the P-channel third transistor Tr3. Can be turned OFF, and the N-channel fourth transistor Tr4 can be turned ON. Therefore, the same effect as the first embodiment can be obtained. Thus, the relationship between the first conductivity type and the second conductivity type may be reversed.

FIG. 5 is a diagram illustrating an example of the transfer characteristic of the transistor in the second embodiment. FIG. 5A illustrates the transfer characteristic of the third transistor Tr3, and FIG. 5B illustrates the transfer characteristic of the fourth transistor Tr4. An example is shown.
A high ON / OFF ratio is required for the third transistor Tr3. Therefore, as shown in FIG. 5A, when the gate voltage can be switched between V3 and V4 (V4> V3), the threshold voltage Vth3 of the third transistor Tr3 is set to a value near the gate voltage V4. It is desirable to set (Vth3≈V4).
On the other hand, what is required of the fourth transistor Tr4 is that the body region of the third transistor Tr3 is connected to a predetermined potential or is in a floating state, rather than the ON / OFF ratio as an electric signal. That is, the fourth transistor Tr4 is required to make the drain current as close to 0 as possible at the gate voltage V3 and to allow the drain current to sufficiently flow at the gate voltage V4. Therefore, as shown in FIG. 5B, it is desirable to set the threshold voltage Vth4 of the fourth transistor Tr4 to a value between the gate voltage V3 and the gate voltage V4 (V4>Vth4> V3). Further, it is desirable that the absolute value of the difference between the threshold voltage Vth4 of the fourth transistor Tr4 and the gate voltage V3 is larger than the absolute value of the difference between the threshold voltage Vth3 of the third transistor Tr3 and the gate voltage V4 (| Vth4-V3). |> | Vth3-V4 |).

<3. Third Embodiment>
FIG. 6 is a schematic plan view showing a semiconductor device according to the third embodiment of the present invention. In the semiconductor device 3 according to the third embodiment, the drain region 22 of the second transistor Tr2 is formed at a position sandwiched between the two source regions 11 of the first transistor Tr1, and the body region of the second transistor Tr2 23 and the source region 21 are formed at positions opposite to the body region 13 of the first transistor Tr1 when viewed from the drain region 22 of the second transistor Tr2, and the second transistor Tr2 in the first embodiment. However, the other points are the same as those of the first embodiment, and redundant description is omitted.

In the third embodiment, since the wiring for connecting the gate electrode 15 of the first transistor Tr1 and the gate electrode 25 of the second transistor Tr2 needs to be relatively long, the gate capacity may be slightly increased. However, substantially the same effect as in the first embodiment can be obtained.
The configuration in which the body potential of the P-channel third transistor Tr3 described in the second embodiment is controlled and floated by ON / OFF of the N-channel fourth transistor Tr4 is the same as that of the third embodiment. Even in the case of realizing the same arrangement structure, similar effects can be obtained.

<4. Fourth Embodiment>
FIG. 7 is a schematic plan view showing a semiconductor device according to the fourth embodiment of the present invention. In the semiconductor device 4 according to the fourth embodiment, the gate electrode 15 of the first transistor Tr1 and the gate electrode 25 of the second transistor Tr2 are not electrically connected but separated from each other. Although different from the embodiment, the other points are the same as those of the first embodiment, and redundant description is omitted.

In the fourth embodiment, since different gate voltages can be applied to the gate electrode 15 of the first transistor Tr1 and the gate electrode 25 of the second transistor Tr2, the first transistor Tr1 and the second transistor Tr2 can be controlled independently. In other respects, the same effects as those of the first embodiment can be obtained.
In the configuration in which the body potential of the P-channel third transistor Tr3 described in the second embodiment is controlled and floated by ON / OFF of the N-channel fourth transistor Tr4, the gate of the third transistor Tr3 Even when the electrode 15 and the gate electrode 25 of the fourth transistor Tr4 are separated, the same effect can be obtained.
In the arrangement described in the third embodiment, the same effect can be obtained even when the gate electrode 15 of the first transistor Tr1 and the gate electrode 25 of the second transistor Tr2 are separated.

<5. Fifth Embodiment>
FIG. 8 is a schematic plan view showing a semiconductor device according to the fifth embodiment of the present invention. In the semiconductor device 5 according to the fifth embodiment, the semiconductor device 1 having the first and second transistors Tr1 and Tr2 described in the first embodiment, and the third and fourth described in the second embodiment. An inverter circuit is configured by combining the semiconductor device 2 having the transistors Tr3 and Tr4.

  As shown in FIG. 8, in the semiconductor device 5 according to the fifth embodiment, the gate electrodes (first and second gate electrodes) 15 and 25 of the first and second transistors Tr1 and Tr2, and the third and third The gate electrodes (third and fourth gate electrodes) 15 and 25 of the four transistors Tr3 and Tr4 are connected to a common input terminal IN. The source regions (first and second source regions) 11 and 21 of the first and second transistors Tr1 and Tr2 are connected to the first power supply potential Vss, and the source regions (third regions) of the third and fourth transistors Tr3 and Tr4 are connected. And the fourth source region) 11 and 21 are connected to the second power supply potential Vdd. The drain region (first drain region) 12 of the first transistor Tr1 and the drain region (third drain region) 12 of the third transistor Tr3 are connected to a common output terminal OUT. For example, the gate voltage V1 (for example, V1 = V3) and the gate voltage V2 (for example, V2 = V4) can be selectively applied to the input terminal IN.

In the fifth embodiment, since the semiconductor device 1 described in the first embodiment and the semiconductor device 2 described in the second embodiment are used, the first transistor Tr1 and the third transistor Tr3 operate stably. In addition, a high ON / OFF ratio can be obtained. Accordingly, it is possible to increase the operation speed and reduce the power consumption.
In the fifth embodiment, the example using the semiconductor device described in the first embodiment and the semiconductor device described in the second embodiment has been described. However, the arrangement configuration described in the third embodiment is described. Alternatively, the semiconductor device having the gate electrode structure described in the fourth embodiment may be used.
In addition, by using the above-described semiconductor device, a low power device for a portable device, a personal computer processor, a memory, a logic device that requires high-speed operation, and the like can be created.

DESCRIPTION OF SYMBOLS 1, 2, 3, 4, 5 ... Semiconductor device, 11 ... Source region (first source region), 12 ... Drain region (first drain region), 13 ... Body region (first body region), 14 ... Gate insulation Film (first gate insulating film), 15 ... gate electrode (first gate electrode), 21 ... source region (second source region), 22 ... drain region (second drain region), 23 ... body region (second body) Region), 24 ... gate insulating film (second gate insulating film), 25 ... gate electrode (second gate electrode), 100 ... insulating layer, 101 ... semiconductor layer, 102 ... element isolation film, 103 ... interlayer insulating film, 111 112, 121 ... contact electrode, Tr1 ... first transistor, Tr2 ... second transistor, Tr3 ... third transistor, Tr4 ... fourth transistor, V1 ... gate voltage (first gate voltage) ), V2 ... Gate voltage (second gate voltage), V3 ... Gate voltage (second gate voltage), V4 ... Gate voltage (first gate voltage), Vth1 ... Threshold voltage of the first transistor, Vth2 ... First Threshold voltage of two transistors, Vth3 ... Threshold voltage of third transistor, Vth4 ... Threshold voltage of fourth transistor, IN ... Input terminal, OUT ... Output terminal, Vss ... First power supply potential, Vdd ... Second power supply potential

Claims (7)

A first source region of the first conductivity type formed in the semiconductor layer, a first drain region of the first conductivity type, and a second conductivity type formed between the first source region and the first drain region. A first body region of
A first gate insulating film formed on the first body region;
A first gate electrode formed on the first gate insulating film;
A partially depleted first transistor comprising:
A second source region of a second conductivity type formed in the semiconductor layer, a second drain region of a second conductivity type, and a first conductivity formed between the second source region and the second drain region; A second body region of the mold;
A second gate insulating film formed on the second body region;
A second gate electrode formed on the second gate insulating film;
A second transistor including:
Comprising
The semiconductor layer is formed on an insulating layer;
The first body region is a semiconductor device connected to one of the second source region and the second drain region. In claim 1,
The first drain region is formed on one side as viewed from the first body region, and the first source region and the one of the second source region and the second drain region are formed on the other side. A semiconductor device. In claim 1 or 2,
A semiconductor device in which the first gate electrode and the second gate electrode are electrically connected. In any one of Claims 1 thru | or 3,
The first source region is in contact with the one of the second source region and the second drain region;
A semiconductor device in which the first source region and the other of the second source region and the second drain region are connected by a conductor. In any one of Claims 1 thru | or 4,
A third source region of a second conductivity type formed in the semiconductor layer, a third drain region of a second conductivity type, and a first conductivity formed between the third source region and the third drain region; A third body region of the mold;
A third gate insulating film formed on the third body region;
A third gate electrode formed on the third gate insulating film;
A partially depleted third transistor including
A fourth source region of a first conductivity type formed in the semiconductor layer, a fourth drain region of a first conductivity type, and a second conductivity formed between the fourth source region and the fourth drain region; A fourth body region of the mold;
A fourth gate insulating film formed on the fourth body region;
A fourth gate electrode formed on the fourth gate insulating film;
A fourth transistor including:
Further comprising
The third body region is connected to one of the fourth source region and the fourth drain region;
The semiconductor device which comprises the inverter by the said 1st transistor and the said 3rd transistor. A method for driving a semiconductor device according to any one of claims 1 to 5,
While applying a first gate voltage for turning off the first transistor and turning on the second transistor to the first gate electrode and the second gate electrode, the first transistor is turned on via the second transistor. Applying a predetermined voltage to the first body region of one transistor;
While applying a second gate voltage for turning on the first transistor and turning off the second transistor to the first gate electrode and the second gate electrode, respectively, between the source and drain of the first transistor Passing a current through
A driving method comprising: In claim 6,
The threshold voltage value of the second transistor is a value between the first gate voltage and the second gate voltage, and the difference between the threshold voltage of the second transistor and the second gate voltage is A driving method that is greater than a difference between a threshold voltage of the first transistor and the first gate voltage.

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