JP2011258656A - Bipolar semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bipolar semiconductor element in which control capability by a control electrode can be enhanced.SOLUTION: A gate turnoff thyristor has second and third gate terminals 16 and 17 formed in second and third contact holes 20C and 20D on the end side extending in the row direction along each row R1, R2 on the end side thereof, in addition to a first gate terminal 15 formed in a first contact hole 20B between rows extending in the row direction between two adjoining rows R1 and R2 of mesa type anode-emitter layer 5. Since commutation during turnoff can be born by the first gate terminal 15 between rows and the second and third gate terminals 16 and 17 on the end side, irregular commutation can be minimized.

Description

  The present invention relates to a bipolar semiconductor device such as a gate turn-off thyristor and a bipolar transistor, and more particularly to a bipolar semiconductor device capable of improving the control capability of a control electrode.

  Conventionally, as shown in the sectional view of FIG. 11, a gate turn-off thyristor as a bipolar semiconductor device has a p-type SiC buffer formed on a high impurity concentration n-type SiC cathode emitter layer 601 having a cathode electrode 621 on the lower surface. A layer 602 and a low impurity concentration p-type SiC base layer 603 are formed (see Patent Document 1 (Japanese Patent Laid-Open No. 2009-055063)). An n-type base layer 604 is formed on the p-type base layer 603. A mesa p-type anode emitter layer 605 is formed on the n-type base layer 604. Further, an n-type low-resistance gate region 606 and an n-type gate contact region 607 are formed in the portion of the n-type base layer 604 exposed from the mesa-type anode emitter layer 605 so as to surround the anode emitter layer 605 by ion implantation. Has been. A gate electrode 619 is formed on the n-type gate contact region 607. As shown in the plan view of FIG. 10, an anode terminal 613 is formed on the anode emitter layer 605.

  In this gate turn-off thyristor, a plurality of mesa-type anode emitter layers 605 are formed in two rows in a certain direction along the upper surface of the n-type base layer 604. The anode terminal 613 is formed on the plurality of mesa-type anode emitter layers 605 in each column so as to extend in the column direction. The anode terminal 613 is connected to the anode electrode 612 through a contact hole 620 </ b> A formed in the oxide film 620. A gate terminal 622 extends in the column direction between the two rows of mesa-type anode emitter layers 605 (that is, between the two anode terminals 613). The gate terminal 622 is connected to a gate electrode 619 formed on the gate contact region 607 through a contact hole 620B formed in the oxide film 620.

  In the conventional gate turn-off thyristor, an off-gate voltage is applied between the gate terminal 622 and the anode terminal 613 at the time of turn-off. As a result, the main current is commutated to the gate electrode 619, and the gate turn-off thyristor is turned off.

  The conventional gate turn-off thyristor has one gate terminal 622 for drawing a gate current between the two rows of mesa-type anode emitter layers 605.

  Thus, having only one gate terminal 622 has the following advantages (1) to (3).

   (1) Wiring can be simplified.

   (2) In a gate turn-off thyristor with a fast switching speed, it is possible to suppress uneven wiring lengths during wire bonding and to suppress timing deviations in drawing gate current.

   (3) Overvoltage to the circuit can be suppressed by reducing stray inductance.

  However, when the current to be cut off is increased due to an increase in the size of the element or the like, commutation irregularities occur in the longitudinal direction of the plurality of mesa-type anode emitter layers 605, which may cause destruction of the element. . That is, when only one gate terminal 622 is arranged at the center of the element, the distance from the center part to the end part of the element becomes longer as the element becomes larger, and the timing for drawing the gate current is the center part and the end part of the element. And will be very different. This causes uneven commutation of elements, and if the current to be cut off increases, it may eventually cause element destruction.

  In particular, the gate turn-off thyristor made of SiC has a switching speed about 10 times faster than the gate turn-off thyristor made of Si. Therefore, when the device becomes larger, the gate turn-off thyristor made of SiC has a higher device speed than the gate turn-off thyristor made of SiC. The commutation of the commutation becomes larger.

  More generally, in addition to gate turn-off thyristors, bipolar semiconductor elements such as bipolar transistors are also required to have improved control capability using control electrodes.

JP 2009-055063 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a bipolar semiconductor device that can improve the control capability of a control electrode.

In order to solve the above problems, a bipolar semiconductor device of the present invention includes a first main electrode,
A first semiconductor layer of a first conductivity type formed on the first main electrode;
A plurality of convex second conductive layers formed on the first semiconductor layer and formed along the upper surface of the first semiconductor layer, and arranged in a plurality of rows. Two semiconductor layers;
A second main electrode formed on the convex second semiconductor layer of the second conductivity type arranged in the plurality of rows,
A control electrode formed on the first semiconductor layer;
An insulating layer formed on the control electrode;
A first contact hole formed in the insulating layer so as to extend in a column direction between two adjacent columns of the convex second semiconductor layer and exposing the control electrode;
The one row of the two rows of convex second semiconductor layers is disposed on the opposite side of the first contact hole and extends in the row direction along the one row. A second contact hole formed in the insulating layer and exposing the control electrode;
The other row of the two rows of convex second semiconductor layers is disposed on the opposite side of the first contact hole and extends in the row direction along the other row. A second contact hole formed in the insulating layer and exposing the control electrode;
A first control terminal formed in the first contact hole and electrically connected to the control electrode;
A second control terminal formed in the second contact hole and electrically connected to the control electrode;
And a third control terminal formed in the third contact hole and electrically connected to the control electrode.

  According to the bipolar semiconductor device of the present invention, the second and third contact holes and the first contact hole extend in the column direction on both sides sandwiching the column of the convex second semiconductor layer. is doing. Thereby, the first control terminal formed in the first contact hole between the columns arranged between the columns of the convex second semiconductor layer and the second and third of the end side Control capability can be shared by the second and third control terminals formed in the contact hole, so that uneven control capability can be suppressed, and control capability by the control electrode can be improved.

In one embodiment of the bipolar semiconductor device, the second conductive type convex second semiconductor layers are arranged in three or more rows,
The first contact hole is formed in the insulating layer so as to extend between two adjacent rows of the convex second semiconductor layer in the column direction so as to expose the control electrode. A plurality of insulating layers are formed,
The second contact hole is arranged on the opposite side of the first contact hole with respect to one end row of the three or more convex second semiconductor layers, and the one end row The control electrode is exposed to be formed in the insulating layer so as to extend in the column direction along
The third contact hole is disposed on the opposite side of the first contact hole with respect to the other end row of the three or more convex second semiconductor layers, and the other end row. The control electrode is exposed to be formed in the insulating layer so as to extend in the column direction along
A plurality of first control terminals formed in the plurality of first contact holes and electrically connected to the control electrode;
A second control terminal formed in the second contact hole and electrically connected to the control electrode;
And a third control terminal formed in the third contact hole and electrically connected to the control electrode.

  According to this embodiment, the control capability can be shared by three or more control terminals including the plurality of first control terminals, the second control terminal, and the third control terminal, and uneven control capability can be suppressed. The control ability by the control electrode can be improved.

In one embodiment, the bipolar semiconductor device includes a main electrode terminal formed on the second main electrode,
The dimension of the convex second semiconductor layer in the row direction orthogonal to the column direction is longer than the dimension of the main electrode terminal in the row direction.

  According to this embodiment, since the end of the convex second semiconductor layer in the row direction protrudes from the main electrode terminal in the row direction, the electric characteristics of the convex second semiconductor layer are likely to be unstable. The main electrode terminal is not exposed to the end of the second semiconductor layer in the row direction. Therefore, the withstand voltage between the main electrode terminal and the control electrode can be improved.

In one embodiment of the bipolar semiconductor device, a first conductivity type first emitter layer having a first main electrode formed on one surface;
A first base layer of a second conductivity type formed on the other surface of the first emitter layer;
A first conductivity type second base layer formed on the first base layer as the first conductivity type first semiconductor layer;
A convex second emitter layer as the second conductive type convex second semiconductor layer;
A gate electrode as the control electrode;
A first gate terminal as the first control terminal;
A second gate terminal as the second control terminal;
A third gate terminal as the third control terminal,
It constitutes a gate turn-off thyristor.

  According to the bipolar semiconductor device of this embodiment, the second and third contact holes and the first contact hole extend in the column direction on both sides of the row of the convex second emitter layers. Exist. As a result, the first gate terminal formed in the first contact hole between the columns arranged between the columns by the convex second emitter layer and the second and third of the end side are formed. The second and third gate terminals formed in the contact hole can share the commutation at the time of turn-off, so that irregularity of commutation can be suppressed and the commutation ability can be improved.

In one embodiment of the bipolar semiconductor device, the second conductivity type substrate to be a collector,
A second conductivity type drift layer formed on the second conductivity type substrate;
A first conductivity type base layer formed on the drift layer as the first conductivity type first semiconductor layer;
A convex second conductive type emitter layer as the second conductive type convex second semiconductor layer;
A base electrode as the control electrode;
A first base terminal as the first control terminal;
A second base terminal as the second control terminal;
A third base terminal as the third control terminal,
A bipolar transistor is formed.

  According to the bipolar semiconductor device of this embodiment, the second and third base terminals formed in the second and third contact holes and connected to the base electrode are formed in the first contact hole. The first base terminal connected to the base electrode extends in the column direction on both sides of the row of the convex second conductivity type emitter layers. Thus, the first base terminal formed in the first contact hole between the columns arranged between the columns by the convex second conductivity type emitter layer and the second and second end terminals on the end side are formed. The base current can be shared by the second and third base terminals formed in the three contact holes, so that the uneven base current can be suppressed, and the control capability of the base current can be improved.

In the bipolar semiconductor device of one embodiment,
A first conductivity type substrate to be a collector;
A second conductivity type drift layer formed on the first conductivity type substrate;
A first conductivity type growth layer formed on the drift layer as the first conductivity type first semiconductor layer;
A second conductivity type growth layer as the second conductivity type convex second semiconductor layer formed on the first conductivity type growth layer;
A contact region formed by ion implantation into the first conductive type growth layer through a through hole formed in the second conductive type growth layer;
A gate electrode as the control electrode;
A first gate terminal as the first control terminal;
A second gate terminal as the second control terminal;
A third gate terminal as the third control terminal,
An insulated gate bipolar transistor is formed.

  According to the bipolar semiconductor device of this embodiment, the second and third gate terminals are formed in the second and third contact holes and connected to the gate electrode, and are formed in the first contact hole. The first gate terminal connected to the gate electrode extends in the column direction on both sides of the row of the convex second conductivity type emitter layers. As a result, a channel is formed by the gate electrode between the first gate terminal formed between the columns of the convex second conductivity type emitter layer and the second and third gate terminals on the end side. It is possible to control the unevenness of channel formation and improve the control capability by the gate electrode.

  Moreover, the bipolar semiconductor element of one Embodiment is produced with the wide gap semiconductor.

  According to this embodiment, high-speed operation and high voltage resistance can be realized.

  According to the bipolar semiconductor device of the present invention, the second and third contact holes and the first contact hole extend in the column direction on both sides sandwiching the column of the convex second semiconductor layer. . Thereby, the first control terminal formed in the first contact hole between the columns arranged between the columns of the convex second semiconductor layer and the second and third of the end side Control capability can be shared by the second and third control terminals formed in the contact hole, so that uneven control capability can be suppressed, and control capability by the control electrode can be improved.

It is a top view of the gate turn-off thyristor which is 1st Embodiment of the bipolar semiconductor element of this invention. It is sectional drawing of the said 1st Embodiment. It is a perspective view which shows typically the principal part of the said 1st Embodiment. It is a top view of the modification of the said 1st Embodiment. It is sectional drawing of the said 1st modification. It is a top view of the bipolar transistor which is 2nd Embodiment of the bipolar semiconductor element of this invention. It is sectional drawing of the said 2nd Embodiment. It is a top view of IGBT which is 3rd Embodiment of the bipolar semiconductor element of this invention. It is sectional drawing of the said 3rd Embodiment. It is a top view of the gate turn-off thyristor as a conventional bipolar semiconductor element. It is sectional drawing of the said conventional gate turn-off thyristor.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a plan view of an embodiment of a gate turn-off thyristor (hereinafter referred to as GTO) as a bipolar semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view of the GTO of the above embodiment. A cross section is shown.

As shown in FIG. 2, the GTO of this embodiment has a thickness of about 350 μm and an impurity concentration of about 10 ¹⁹ cm ⁻³ or more with the cathode electrode 11 as the first main electrode connected to the cathode terminal on the lower surface. The cathode emitter layer 1 of an n-type SiC semiconductor as the first conductivity type with a high impurity concentration is provided as the first emitter layer. The cathode emitter layer 1 is an n-type 4H SiC substrate. The 4H type “H” represents a hexagonal crystal, and the 4H type “4” represents a crystal structure in which the atomic stacking has a four-layer period.

On the cathode emitter layer 1, a buffer layer 2 made of a p-type SiC layer having a thickness of about 15 μm and an impurity concentration of about 10 ¹⁷ cm ⁻³ , and an impurity concentration of about 10 ¹⁶ to 10 ¹³ having a thickness of about 75 μm. A p-type SiC semiconductor base layer 3 as a second conductivity type having a low impurity concentration of about cm ⁻³ is formed as a first base layer. A thin n-type base layer 4 having a thickness of about several μm is formed on the p-type base layer 3 as a second base layer. A p-type layer is formed on the entire surface of the n-type base layer 4 by the epitaxial growth method to leave the central region in a later step and serve as the p-type anode emitter layer 5. The buffer layer 2 is not always necessary and may not be formed. Further, an n-type buffer layer may be formed between the n-type cathode emitter layer 1 and the p-type buffer layer 2.

  Next, leaving the region to be the anode emitter layer 5 of the p-type layer as the second emitter layer, the surface of the n-type base layer 4 is exposed and the surface portion of the other region is exposed by reactive ion etching. The mesa type anode emitter layer 5 is formed by etching deep enough to be removed. Ions are implanted into the exposed n-type base layer 4 to sequentially form an n-type low-resistance gate region 6 and an n-type gate contact region 7 so as to surround the mesa-type p-type anode emitter layer 5. Note that the low-resistance gate region 6 is not always necessary and may not be formed.

  The impurity concentration of the n-type low resistance gate region 6 is preferably at least three times the impurity concentration of the n-type base layer 4. The low resistance gate region 6 may be formed up to the vicinity of the upper surface of the base layer 4 in the ion implantation process. The low resistance gate region 6 is formed slightly apart from the junction J between the anode emitter layer 5 and the base layer 4.

  The gate contact region 7 is a low resistance region having a higher impurity concentration than the low resistance gate region 6 and is formed at a position away from the junction J. An anode electrode 12 connected to the anode terminal 13 is formed on the anode emitter layer 5 as a second main electrode. 2, an anode electrode 12 as a second main electrode is formed on the mesa p-type anode emitter layer 5, and a gate electrode 19 is formed on the n-type gate contact region 7. Is formed.

An oxide film 20 as an insulating layer is formed on the gate electrode 19, the n-type SiC base layer 4, the mesa-type p-type anode emitter layer 5, and the anode electrode 12. A contact hole 20A for the anode electrode is formed in the oxide film 20, and an anode terminal 13 is formed so as to be electrically connected to the anode electrode 12 through the contact hole 20A. As the insulating layer, SiO ₂ , SiN or the like can be used.

  As shown in the plan view of FIG. 1 and the schematic perspective view of FIG. 3, in the GTO of this embodiment, the mesa-type anode emitter layer 5 is formed along the upper surface of the n-type base layer 4 with R1, R2 Are arranged in two rows. In the schematic diagram of FIG. 3, the description of the gate electrode 19, the oxide film 20, the anode electrode 12, and the anode terminals 13 and 14 is omitted. The anode electrode 12 is formed on each anode emitter layer 5, and one anode terminal 13 is provided on the anode electrodes 12 on the plurality of mesa p-type anode emitter layers 5 arranged in one row R1. Is formed. An anode electrode 12 is also formed on each mesa type anode emitter layer 5 arranged in the other row R2. One anode terminal 14 is formed across each anode electrode 12 in this row R2. The anode terminal 14 is electrically connected to each anode electrode 12 through a contact hole formed in the oxide film 20.

  In the GTO of this embodiment, as shown in FIG. 1, the first contact hole 20B between the columns extending in the column direction between the two columns R1 and R2 by the mesa-type anode emitter layer 5 is used. Is formed in the oxide film 20, and the gate electrode 19 is exposed in the first contact hole 20B. A first gate terminal 15 is formed so as to be electrically connected to the gate electrode 19 exposed in the first contact hole 20B through the first contact hole 20B.

  The GTO of this embodiment has end-side gate terminals 16 and 17 as second and third control terminals. The gate terminal 16 on the end side extends in the column direction along the column on the end side from the one column R1 by the mesa-type anode emitter layer 5. The end-side gate terminal 16 is formed in the second contact hole 20C formed in the oxide film 20 and exposing the gate electrode 19. Thus, the end-side gate terminal 16 is electrically connected to the gate electrode 19 through the second contact hole 20C.

  The gate terminal 17 on the end side extends in the column direction along the column on the end side with respect to the other column R2 formed by the mesa-type anode emitter layer 5. The end-side gate terminal 17 is formed in the third contact hole 20D formed in the oxide film 20 and exposing the gate electrode 19. Thereby, the gate terminal 17 on the end side is electrically connected to the gate electrode 19 through the third contact hole 20D.

  Although the oxide film 20 is not shown in the plan view of FIG. 1, the outer peripheral edge of the oxide film 20 in FIG. 1 is the same as the outer peripheral edge of the n-type growth layer 4. Further, in the plan view of FIG. 1, only the outer periphery of the N-type gate contact region 7 and the gate electrode 19 is drawn. As can be seen from the cross-sectional view of FIG. 2, the N-type gate contact region 7 and the gate electrode 19 do not extend continuously in the column direction in the regions R1 and R2 shown in the plan view of FIG. In FIG. 1, there is a region that does not exist between two mesa p-type anode emitter layers 5 adjacent in the column direction. On the other hand, the N-type gate contact region 7 and the gate electrode 19 continuously extend outside the regions R1 and R2 shown in the plan view of FIG. That is, although not shown in detail in FIG. 1, the N-type gate contact region 7 and the gate electrode 19 are arranged along the mesa-type p-type anode emitter layers 5 in the regions of the columns R1 and R2 shown in the plan view of FIG. The mesa-type p-type anode emitter layer 5 extends in a ladder shape with an interval without overlapping.

  The operation of the GTO of this embodiment will be described below. In a state where the potential of the anode terminals 13 and 14 is higher than the potential of the cathode electrode 11, the potential of the gate terminals 15, 16 and 17 is made lower than the potential of the anode terminals 13 and 14, and the anode terminals 13 and 14. When a forward bias voltage is applied between the gate terminals 15, 16, and 17, current flows from the anode terminals 13, 14 to the gate terminals 15, 16, 17. In this state, holes are injected from the mesa-type anode emitter layer 5 into the n-type base layer 4 to enter the p-type base layer 3, and electrons are transferred from the n-type cathode emitter layer 1 to the p-type base layer 3. The GTO is turned on and turned on. On the other hand, a reverse bias voltage is applied between the anode terminals 13, 14 and the gate terminals 15, 16, 17, and the electron flow flowing from the cathode electrode 11 to the anode terminals 13, 14 is changed to the gate terminals 15, 16. , 17 the GTO turns off.

  According to the gate turn-off thyristor of this embodiment, only the first gate terminal 15 between the columns extending in the column direction between the mesa-type p-type anode emitter layers 5 of the two adjacent columns R1 and R2. Rather, it has second and third gate terminals 16 and 17 on the end sides extending in the column direction along the respective rows R1 and R2 on the end sides of the respective rows R1 and R2. As a result, the first gate terminal 15 arranged between the column R1 and the column R2 by the mesa anode emitter layer 5 and the second and third gate terminals 16 and 17 on the end side are turned off. The commutation can be shared, the irregularity of the commutation can be suppressed, and the commutation ability can be improved.

  In this embodiment, the dimension of the mesa anode emitter layer 5 in the row direction perpendicular to the column direction is longer than the dimension of the anode terminals 13 and 14 in the row direction. As a result, the end of the mesa anode emitter layer 5 in the row direction protrudes from the anode terminals 13 and 14 in the row direction, and the row of the mesa anode emitter layer 5 is likely to have unstable electrical characteristics. The anode terminals 13 and 14 are not exposed to the end in the direction. Therefore, the withstand voltage between the anode terminals 13 and 14 and the gate electrode 19 can be improved.

  In the above embodiment, as shown in FIG. 1, the mesa-type anode emitter layers 5 arranged in two rows on the n-type base layer 4 are provided. In the oxide film 20, a plurality of first contact holes arranged in a plurality of columns in the row direction and extending in the column direction between the columns of the plurality of columns of the mesa anode emitter layer 5 are formed. A plurality of first gate terminals may be electrically connected to the gate electrode 19 exposed in the plurality of first contact holes. In this case, commutation can be shared by more gate terminals by the second and third gate terminals 16 and 17 and the plurality of first gate terminals, so that non-uniform commutation can be suppressed, and commutation by the gate electrode can be suppressed. Ability can be improved. Further, the mesa anode emitter layers 5 may be arranged in a plurality of rows in the vertical direction in FIG. In the above-described embodiment, a GTO manufactured using an SiC semiconductor has been described. However, the GTO may be manufactured using another wide gap semiconductor, and the present invention can also be applied to a GTO manufactured using another semiconductor such as Si.

  Further, the p-type and n-type conductivity of each layer in the above embodiment are interchanged, and as shown in FIG. 5, a p-type anode emitter layer 51, an n-type buffer layer 52, an n-type base layer 53, and a p-type base. The structure may include a layer 54, a p-type low resistance gate region 56 and a p-type gate contact region 57 formed in the mesa-type n-type cathode emitter layer 55 and the exposed p-type base layer 54. As shown in the sectional view of FIG. 5, a cathode electrode 62 as a second main electrode is formed on the mesa n-type cathode emitter layer 55, and a gate electrode 59 is formed on the p-type gate contact region 57. Is done.

  Further, an oxide film 70 as an insulating layer is formed on the gate electrode 59, the p-type SiC base layer 54, the mesa n-type cathode emitter layer 55, and the cathode electrode 62. A contact hole 70A for the cathode electrode is formed in the oxide film 70, and a cathode terminal 63 is formed so as to be electrically connected to the cathode electrode 62 through the contact hole 70A.

  Further, as shown in the plan view of FIG. 4, the mesa cathode emitter layer 55 is arranged in two rows of R <b> 1 and R <b> 2 along the upper surface of the p-type base layer 54. The cathode electrode 62 is formed on each cathode emitter layer 55, and one cathode terminal 63 is provided on the cathode electrodes 62 on the plurality of mesa p-type cathode emitter layers 55 arranged in one row R1. Is formed. A cathode electrode 62 is also formed on each mesa cathode emitter layer 55 arranged in another row R2. One cathode terminal 64 is formed across each cathode electrode 62 in this row R2. The cathode terminal 64 is electrically connected to each cathode electrode 62 through a contact hole formed in the oxide film 70. In this case, the electrode 61 formed on the lower surface of the p-type anode emitter layer 51 is an anode electrode. Further, as shown in FIG. 4, the gate terminal 65 is formed in the first contact hole 70 </ b> B formed in the oxide film 70. The first contact hole 70B and the gate terminal 65 extend in the column direction between the column R1 and the column R2. In addition, second and third gate terminals 66 and 67 are formed in the second and third contact holes 70C and 70D formed in the oxide film 70. The second and third gate terminals 66 and 67 are formed as described above. The gate electrode 59 is electrically connected. The second contact hole 70C and the first contact hole 70B are located on both sides of the row R1 of the mesa n-type cathode emitter layer 55, and the second contact hole 70C and the first contact hole 70B are located on both sides of the row R2 of the mesa-type n-type cathode emitter layer 55. The third contact hole 70D and the first contact hole 70B are located.

  In this configuration, since the first, second, and third gate terminals 65, 66, and 67 are close to the cathode terminals 63 and 64, the potential of the anode electrode 61 is higher than the potential of the cathode terminals 63 and 64. In this state, when a forward bias voltage is applied between the cathode terminals 63 and 64 and the gate terminals 65, 66 and 67, current flows from the gate terminals 65, 66 and 67 to the cathode terminals 63 and 64. As a result, holes are injected from the p-type anode emitter layer 51 into the n-type base layer 53 and enter the p-type base layer 54, and electrons are injected from the n-type cathode emitter layer 55 into the p-type base layer 54. Is turned on and turned on. On the other hand, a reverse bias voltage is applied between the cathode terminals 63 and 64 and the gate terminals 65, 66 and 67, and current flowing from the anode electrode 61 to the cathode terminals 63 and 64 is commutated to the gate terminals 65, 66 and 67. The GTO turns off. Also in the configuration in this case, the first gate terminal 65 and the second and third gate terminals 66 on the end side between the columns arranged between the column R1 and the column R2 by the mesa cathode emitter layer 55 are used. , 67 can share the commutation at the time of turn-off, and the commutation of the commutation can be suppressed.

(Second embodiment)
FIG. 6 is a plan view of an embodiment of a bipolar transistor as a bipolar semiconductor device of the present invention, and FIG. 7 is a cross-sectional view of the bipolar transistor of the above-described embodiment, showing the AA ′ cross section of FIG.

  As shown in FIG. 7, the bipolar transistor of this embodiment is continuously formed on an n-type 4H SiC substrate 81 in the order of n-type 4H—SiC, p-type 4H—SiC, and n-type 4H—SiC. This is an npn bipolar transistor 80 produced by epitaxial growth.

The n-type 4H-type SiC substrate 81 was prepared by slicing an ingot grown by the modified Rayleigh method so that the off angle θ was 8 degrees, and mirror polishing. The substrate 81 serving as a collector is n-type, has a carrier density of 8 × 10 ¹⁸ cm ⁻³ and a thickness of 400 μm as measured by the Hall effect measurement method. On the C surface (carbon surface) of the substrate 81, a buffer layer 82 of a nitrogen-doped n-type SiC layer and a drift layer 83 are formed by CVD. The buffer layer 82 and the drift layer 83 become an n-type collector layer. The buffer layer 82 is not always necessary and may not be formed.

An aluminum-doped p-type SiC p-type growth layer 84 and a nitrogen-doped n-type SiC layer n-type growth layer 85 were sequentially formed on the drift layer 83 by an epitaxial growth method. The buffer layer 82 has a donor density of 7 × 10 ¹⁷ cm ⁻³ and a film thickness of 10 μm. On the other hand, the drift layer 83 has a donor density of about 5 × 10 ¹⁵ cm ⁻³ and a film thickness of 15 μm. The p-type growth layer 84 to be the p-type base layer has an acceptor density of 2 × 10 ¹⁷ cm ⁻³ and a film thickness of 1 μm. The n-type growth layer 85 to be the n-type emitter layer has a donor density of about 7 × 10 ¹⁷ cm ⁻³ and a film thickness of 0.75 μm.

  Next, a manufacturing process of the npn bipolar transistor 80 will be described.

The n-type 4H-type SiC substrate 81 was prepared by slicing an ingot grown by the modified Rayleigh method so that the off angle θ was 8 degrees, and mirror polishing. The substrate 81 serving as a collector is n-type, has a carrier density of 8 × 10 ¹⁸ cm ⁻³ and a thickness of 400 μm as measured by the Hall effect measurement method. On the C surface of the substrate 81, a buffer layer 82 and a drift layer 83 of a nitrogen-doped n-type SiC layer are formed by CVD.

First, silane (SiH ₄ ) and propane (C ₃ H ₈ ) are used as material gases. Nitrogen (N ₂ ) and trimethylaluminum {Al (CH ₃ ) ₃ } are used as dopant gases. Further, hydrogen (H ₂ ) is used as a carrier gas. The flow rate of each gas is represented by sccm (standard cc per minute) or slm (standard liter minute). The pressure is expressed in kPa (kilo pascal). In the following description, the numerical value in parentheses after the name of each gas represents the flow rate. The temperature of the SiC substrate 81 is kept at 1550 ° C., and the pressure in the processing chamber is kept at 5.6 kPa.

  In the step of forming the buffer layer 82 on the C surface of the substrate 81, silane (30 sccm), propane (12 sccm), nitrogen (30 sccm), and hydrogen (10 slm) are supplied. The processing time is 40 minutes. In the step of forming the drift layer 83, silane (30 sccm), propane (12 sccm), nitrogen (0.2 sccm), and hydrogen (10 slm) are supplied. The processing time is 60 minutes. In the step of forming the P-type bonding layer 84, silane (30 sccm), propane (12 sccm), trimethylaluminum (6 sccm) and hydrogen (10 slm) are supplied. The processing time is 4 minutes. In the step of forming the n-type growth layer 85, silane (30 sccm), propane (12 sccm), nitrogen (30 sccm) and hydrogen (10 slm) are supplied. The processing time is 3 minutes.

  By the above processing, the SiC epitaxial wafer for the npn bipolar transistor of the second embodiment can be obtained. By subjecting this SiC epitaxial wafer to the processing described below, the npn bipolar transistor 80 of this embodiment shown in FIG. 7 is completed.

First, the n-type growth layer 85 is etched by reactive ion etching (RIE) with a width of 10 μm, a depth of 0.75 μm, and a pitch of 23 μm to leave the n-type growth layer 85 serving as an emitter. CF ₄ and O ₂ were used as the etching gas for RIE, and the etching was performed under the conditions of a pressure of 0.05 Torr and a high frequency power of 260 W. As a mask material at this time, a SiO ₂ film (thickness 10 μm) deposited by CVD was used.

Next, in order to perform element isolation in the base region, a mesa structure is formed by reactive ion etching (RIE). CF ₄ and O ₂ were used as the etching gas for RIE, and the etching was performed to a depth of about 1 μm under the conditions of a pressure of 0.05 Torr and high frequency power of 260 W. As a mask material at this time, a SiO ₂ film (thickness 10 μm) deposited by CVD was used. The n-type growth layer 85 having a mesa structure serving as the emitter forms a convex second semiconductor layer of the second conductivity type.

In the present embodiment, a guard ring (not shown) for relaxing the electric field concentration at the base end and a base contact region 87 is formed into a p-type base layer by Al (aluminum) ion implantation in the same process. A growth layer 84 was formed. This p-type growth layer 84 forms a first semiconductor layer of the first conductivity type. The base contact region 87 has a width of 3 μm, a distance from the emitter of 5 μm, and a p-type guard ring (not shown) has a width of 150 μm. Both depths are 0.5 μm. The energy of Al ion implantation when forming a p-type guard ring (not shown) or the base contact region 87 is 40 to 560 keV, and the total dose is 1.0 × 10 ¹³ cm ⁻² . An SiO ₂ film (thickness 5 μm) formed by CVD was used as an ion implantation mask. All the ion implantations were performed at room temperature, and the heat treatment for activating the implanted ions was performed under conditions of a temperature of 1600 ° C. for 5 minutes in an argon gas atmosphere.

  Next, a collector electrode 89 as a first main electrode is formed on the lower surface of the substrate 81. A base electrode 100 serving as a control electrode is formed in the contact region 87 of the p-type growth layer 84 serving as a base. An emitter electrode 104 is formed on the n-type growth layer 85 having a mesa structure as the emitter.

Further, a SiO ₂ film was deposited by CVD to form a total oxide film 90 of 15 μm. A contact hole 90A for the emitter electrode is formed in the oxide film 90, and an emitter terminal 105 is formed so as to be electrically connected to the emitter electrode 104 through the contact hole 90A.

  As shown in the plan view of FIG. 6, in the npn bipolar transistor of the second embodiment, the mesa n-type growth layer (emitter layer) 85 extends along the upper surface of the p-type growth layer (base layer) 84. Are arranged in two rows R61 and R62. The emitter electrode 104 is formed on each mesa n-type growth layer 85, and on the emitter electrode 104 formed on the plurality of mesa n-type growth layers 85 arranged in one row R61. One emitter terminal 105 is formed. An emitter electrode 104 is also formed on each mesa n-type growth layer 85 arranged in another row R62. One emitter terminal 106 is formed across each emitter electrode 104 in this row R62. The emitter terminal 106 is electrically connected to each emitter electrode 104 through a contact hole (not shown) formed in the oxide film 90.

  Further, in the npn bipolar transistor 80 of this embodiment, as shown in FIG. 6, the first between the columns extending in the column direction between the two columns R61 and R62 by the mesa n-type emitter layer 85 is used. The contact hole 90B is formed in the oxide film 90, and the base electrode 100 is exposed in the first contact hole 90B. A first base terminal 103 is formed so as to be electrically connected to the base electrode 100 exposed to the first contact hole 90B through the first contact hole 90B.

  Further, the npn bipolar transistor of this embodiment has second and third base terminals 101 and 102 on the end side as second and third control terminals. The base terminal 101 on the end side extends in the column direction along the column on the end side from the one column R61 by the mesa-type n-type growth layer 85. The base terminal 101 on the end side is formed in the second contact hole 90 </ b> C that is formed in the oxide film 90 and exposes the base electrode 100. Thereby, the base terminal 101 on the end side is electrically connected to the base electrode 100 through the second contact hole 90C.

  Further, the base terminal 102 on the end side extends in the column direction along the column on the end side from the other column R62 by the mesa type n-type growth layer 85. The base terminal 102 on the end side is formed in a third contact hole 90D that is formed in the oxide film 90 and exposes the base electrode 100. Thus, the end-side base terminal 102 is electrically connected to the base electrode 100 through the third contact hole 90D.

  In the plan view of FIG. 6, only the outer peripheral edge of the oxide film 90 and the base electrode 100 is drawn. As can be seen from the sectional view of FIG. 7, the oxide film 90 and the base electrode 100 do not extend continuously in the column direction in the region of the columns R61 and R62 shown in the plan view of FIG. There is a region that does not exist between two mesa n-type growth layers 85 adjacent in the column direction. On the other hand, the oxide film 90 and the base electrode 100 continuously extend outside the regions of the rows R61 and R62 shown in the plan view of FIG. That is, although not shown in detail in FIG. 6, the oxide film 90 extends in a ladder shape along the mesa-type n-type growth layer 85 in the region of the columns R61 and R62 shown in the plan view of FIG. Yes. The base electrode 100 is spaced apart from the mesa n-type growth layer 85 along the mesa n-type growth layer 85 in the region of the columns R61 and R62 shown in the plan view of FIG. It extends in a ladder shape.

  According to the npn bipolar transistor 80 of this embodiment, only the first base terminal 103 between columns extending in the column direction between the mesa-type n-type growth layers 85 of two adjacent columns R61 and R62. Rather, the second and third base terminals 101 and 102 on the end side extending in the column direction along the rows R61 and R62 are provided on the end sides of the rows R61 and R62. As a result, the base current is generated between the first base terminal 103 and the end-side second and third base terminals 101 and 102 arranged between the column R61 and the column R62 by the mesa-type n-type growth layer 85. Thus, the base current unevenness can be suppressed, and the control capability of the base current can be improved.

  In this embodiment, the mesa-type n-type growth layer (emitter layer) 85 has a dimension in the row direction perpendicular to the column direction longer than the dimension in the row direction of the emitter terminals 106 and 105. As a result, the end in the row direction of the mesa n-type growth layer (emitter layer) 85 protrudes from the emitter terminals 106 and 105 in the row direction, and the emitter terminals 106 and 105 have unstable electrical characteristics. The mesa n-type growth layer (emitter layer) 85 in the row direction is not exposed. Therefore, the withstand voltage between the emitter terminals 106 and 105 and the base electrode 100 can be improved.

  In the above embodiment, as shown in FIG. 6, the mesa-type n-type growth layers 85 arranged in two rows on the p-type growth layer 84 are provided. In FIG. 6, a plurality of first contact holes arranged in a plurality of columns of three or more columns in the row direction and extending in the column direction between the columns of the plurality of columns of the mesa type n-type growth layer 85 are formed in the oxide film 90. The plurality of first base terminals may be electrically connected to the base electrode exposed to the plurality of first contact holes. In this case, the base current can be shared by a larger number of base terminals by the second and third base terminals 101 and 102 and the plurality of first gate terminals, so that the uneven base current can be suppressed and the control capability of the base current can be improved. It can be improved. Further, the mesa n-type growth layers 85 may be arranged in a plurality of rows in the vertical direction in FIG. In the above embodiment, an npn bipolar transistor made of a SiC semiconductor has been described. However, the npn bipolar transistor may be made of another wide gap semiconductor, and the present invention can also be applied to a bipolar transistor made of another semiconductor such as Si. .

  In addition, the p-type and n-type conductivity of each layer in the above-described embodiment are interchanged, and the p-type SiC substrate 81, the p-type SiC buffer layer 82, the p-type SiC drift layer 83, the n-type base layer 84, the mesa type An n-type base contact region 87 formed in the p-type emitter layer 85 and the exposed n-type base layer 84 may be provided.

(Third embodiment)
FIG. 8 is a plan view of an embodiment of an IGBT (insulated gate bipolar transistor) as a bipolar semiconductor device of the present invention, and FIG. 9 is a cross-sectional view of the IGBT of the above embodiment. A 'cross section is shown.

  As shown in FIG. 9, the IGBT of this embodiment is formed on a substrate 121 made of n-type 4H-type SiC, with an increase rate of film thickness per hour (h) of 15 μm / h as an example, and p-type 4H-SiC. Three layers were epitaxially grown in the order of a layer, an n-type 4H—SiC layer, and a p-type 4H—SiC layer, and an IGBT 120 was fabricated as described in detail below. In this IGBT 120, the main joint surface of the p layer and the n layer (surface extending in the direction perpendicular to the paper surface in the figure) is a {0001} plane.

  Next, a method for manufacturing the IGBT 120 will be described. That is, the p-type is formed on a substrate using n-type 4H-type SiC having a plane orientation of an off-angle θ of 3.5 degrees from the (000-1) carbon plane at a film formation rate of 15 μm / h. A 4H—SiC layer, an n-type 4H—SiC layer, and a p-type 4H—SiC layer are sequentially formed.

The SiC substrate 121 was fabricated by slicing an ingot grown by the modified Rayleigh method at a surface inclined by 3.5 degrees from the (000-1) carbon surface and mirror polishing. The substrate 121 serving as a collector is n-type, has a thickness of 400 μm, and the carrier density obtained by the Hall effect measurement method is 5 × 10 ¹⁸ cm ⁻³ .

Three layers of an aluminum-doped p-type SiC layer, a nitrogen-doped n-type SiC layer, and an aluminum-doped p-type SiC layer were continuously epitaxially grown on this SiC substrate 121 by the CVD method. This p-type SiC layer becomes the buffer layer 122 and the drift layer 123 of FIG. The buffer layer 122 has an acceptor density of 1 × 10 ¹⁷ cm ⁻³ and a film thickness of 3 μm. The drift layer 123 has an acceptor density of about 5 × 10 ¹⁵ cm ⁻³ and a film thickness of 15 μm. The n-type growth layer 124 as the first conductivity type growth layer formed on the drift layer 123 has a donor density of 2 × 10 ¹⁷ cm ⁻³ and a film thickness of 2 μm. The p-type growth layer 125 formed on the n-type growth layer 124 has an acceptor density of about 1 × 10 ¹⁸ cm ⁻³ and a film thickness of 0.75 μm.

  Next, processing conditions when manufacturing this IGBT 120 will be described.

First, silane (SiH ₄ ) and propane (C ₃ H ₈ ) are used as material gases. Further, nitrogen (N ₂ ) and trimethylaluminum {Al (CH ₃ ) ₃ } are used as dopant gases. Further, hydrogen (H ₂ ) is used as a carrier gas. Here, the flow rate of each gas is represented by sccm (standard cc per minute) or slm (standard liter minute). The pressure is expressed in kPa (kilo pascal). Moreover, in the following description, the numerical value in the parenthesis attached after the name of each gas represents a flow rate.

  The temperature of the substrate 121 is kept at 1550 ° C., and the pressure in the processing chamber is kept at 5.6 kPa. In the step of forming the p-type SiC buffer layer 122 on the C surface of the n-type SiC substrate 121, silane (30 sccm), propane (12 sccm), trimethylaluminum (3 sccm) and hydrogen (10 slm) are supplied. The processing time for this step is 12 minutes. In the step of forming the drift layer 123, silane (30 sccm), propane (12 sccm), trimethylaluminum (0.15 sccm), and hydrogen (10 slm) are supplied. The processing time is 60 minutes.

  In the step of forming the n-type growth layer 124, silane (30 sccm), propane (12 sccm), nitrogen (9 sccm), and hydrogen (10 slm) are supplied. The processing time is 8 minutes. In the step of forming the p-type growth layer 125, silane (30 sccm), propane (12 sccm), trimethylaluminum (30 sccm), and hydrogen (10 slm) are supplied. The processing time is 3 minutes.

  By the above process, the SiC epitaxial wafer for IGBT of this embodiment can be obtained. An IGBT 120 having the structure shown in FIG. 9 is produced from the SiC epitaxial wafer thus produced.

  First, a mesa-type central portion 125A of the second conductivity type p + growth layer 125 is etched by RIE using a photolithographic method to provide a hole 126A, and nitrogen is ion-implanted, thereby forming a contact region 126 serving as a collector. Form. The mesa-type p-type central portion 125A becomes a second conductivity type growth layer as a second conductivity type convex second semiconductor layer.

In order to form the gate region, the p + growth layer 125 and the n + growth layer 124 are etched by RIE to form holes 128A (two in FIG. 9). Next, in order to form a MOS structure on the wall surface of the hole 128A, an SiO ₂ film is deposited by CVD to form an insulating film 127. Ni is deposited on the collector region of the substrate 121 to form a collector terminal 129. An emitter electrode 133 is deposited on the contact region 126. Next, heat treatment is performed to form ohmic junctions. Further, a Mo electrode is formed on the oxide film 127 to form a gate electrode 130 as a control electrode.

In the IGBT 120 of this embodiment, a SiO ₂ film is deposited by CVD to form an oxide film 140 having a total thickness of 3 μm. A contact hole 140A for the emitter electrode is formed in the oxide film 140, and an emitter terminal 141 is formed so as to be electrically connected to the emitter electrode 133 through the contact hole 140A.

  In the IGBT 120 of this embodiment, as shown in the plan view of FIG. 8, the mesa-shaped central portion 125A as the convex second semiconductor layer has two rows R71, R71, R72 is arranged in a row. The emitter electrode 133 is formed on each mesa-type p-type central portion 125A. On the emitter electrode 133 formed on the plurality of mesa-type p-type central portions 125 arranged in one row R71. One emitter terminal 141 is formed to extend in the column direction. An emitter electrode 133 is also formed on each mesa-type p-type central portion 125 arranged in another row R72. One emitter terminal 142 is formed so as to extend in the column direction across each emitter electrode 133 of the column R72. The emitter terminal 142 is electrically connected to each emitter electrode 133 in the row R72 through a contact hole (not shown) formed in the oxide film 140.

  In the IGBT 120 of this embodiment, as shown in FIG. 8, the first contact hole 140B between the columns extending in the column direction between the two rows R71 and R72 by the mesa-shaped central portion 125A is formed. The gate electrode 130 is exposed in the first contact hole 140B formed on the oxide film 140. A first gate terminal 137 is formed so as to be electrically connected to the gate electrode 130 exposed in the first contact hole 140B through the first contact hole 140B.

  Further, the IGBT 120 of this embodiment has end-side gate terminals 135 and 136 as second and third control terminals. The gate terminal 135 on the end side extends in the column direction along the column R72 on the end side from the one column R72 by the mesa-type p-type central portion 125A. The end-side gate terminal 135 is formed in the second contact hole 140 </ b> C that is formed in the oxide film 140 and exposes the gate electrode 130. As a result, the end-side gate terminal 135 is electrically connected to the gate electrode 130 through the second contact hole 140C.

  Further, the end-side gate terminal 136 extends in the column direction along the column R71 on the end side from the other column R71 formed by the mesa-type p-type central portion 125A. The end-side gate terminal 136 is formed in the third contact hole 140D formed in the oxide film 140 and exposing the gate electrode 130. Accordingly, the gate terminal 136 on the end side is electrically connected to the gate electrode 130 through the third contact hole 140D.

  In the plan view of FIG. 8, only the outer peripheral edge of the gate electrode 130 is drawn. As can be seen from the cross-sectional view of FIG. 9, the gate electrode 130 does not continuously extend in the column direction in the region of the columns R71 and R72 shown in the plan view of FIG. There is a region that does not exist between two mesa p-type central portions 125A adjacent in the direction. On the other hand, the mesa p-type central portion 125A continuously extends outside the regions of the rows R71 and R72 shown in the plan view of FIG. That is, although not shown in detail in FIG. 8, the gate electrode 130 is formed on the mesa p-type central portion 125A along the mesa p-type central portion 125A in the region of the columns R71 and R72 shown in the plan view of FIG. It extends in a ladder shape at intervals without overlapping.

  According to the IGBT 120 of this embodiment, not only the first gate terminal 137 between the columns extending in the column direction between the mesa-type p-type central portions 125A of the two adjacent columns R71 and R72, It has second and third gate terminals 135 and 136 on the end side extending in the column direction along the columns R71 and R72 on the end side of the columns R71 and R72. As a result, the gate electric field is generated between the first gate terminal 137 and the second and third gate terminals 135 and 136 on the end side arranged between the column R71 and the column R72 by the mesa-type p-type central portion 125A. Therefore, the channel formation can be shared, the irregularity of the channel formation can be suppressed, and the control ability by the gate electrode 130 can be improved.

  In this embodiment, the dimension of the mesa-shaped central portion 125A in the row direction perpendicular to the column direction is longer than the dimension of the emitter terminals 142 and 141 in the row direction. As a result, the end in the row direction of the mesa-type central portion 125A protrudes from the emitter terminals 142 and 141 in the row direction, and the mesa-type n-type growth layer (emitter layer) whose electrical characteristics tend to become unstable. ) The emitter terminals 142 and 141 are not exposed to the end in the row direction of 85. Therefore, the withstand voltage between the emitter terminals 142 and 141 and the gate electrode 130 can be improved.

  In the above embodiment, as shown in FIG. 8, the mesa-type p-type central portion 125A arranged in two rows on the n-type growth layer 124 is provided. In FIG. 8, a plurality of first contact holes arranged in a plurality of columns in the row direction and extending in the column direction between the columns of the plurality of mesa-type p-type central portions 125A are formed in the oxide film 140. The plurality of first gate terminals may be electrically connected to the gate electrode 130 formed in the step and exposed to the plurality of first contact holes. In this case, the channel formation by the gate electric field can be shared by more gate terminals by the second and third gate terminals 135 and 136 and the plurality of first gate terminals, so that the irregularity of the channel formation can be suppressed. The control ability by can be improved. Further, the mesa-type p-type central portions 125A may be arranged in a plurality of rows in the vertical direction in FIG. Moreover, although the said embodiment demonstrated IGBT produced with the SiC semiconductor, you may produce with other wide gap semiconductors, and this invention is applicable also to IGBT produced with other semiconductors, such as Si.

  Further, the p-type and n-type conductivity of each layer in the above embodiment are interchanged, and the p-type SiC substrate 121, the n-type SiC buffer layer 122, the n-type SiC drift layer 123, the p-type growth layer 124, and the n-type growth. The layer 125 and the mesa-type n-type central portion 125A may be provided.

  The bipolar semiconductor device of the present invention can improve the control capability by the control electrode. For example, it can control a large current and cut off a large current, can be used at a large current, and can improve reliability. Therefore, as an example, it can be applied to a power control device incorporated in a power control device such as an inverter in the home appliance field, the industrial field, a vehicle field such as an electric vehicle, and a power system field such as power transmission. The control current can be improved and the reliability of the apparatus can be improved.

1 n-type SiC cathode emitter layer 2 p-type SiC buffer layer 3 p-type SiC base layer 4 n-type base layer 5 mesa-type p-type anode emitter layer 6 n-type low-resistance gate region 7 n-type gate contact region 11 cathode Electrode (first main electrode)
12 Anode electrode 13, 14 Anode terminal 15, 65 First gate terminal 16, 66 Second gate terminal 17, 67 Third gate terminal 19, 59 Gate electrode 20, 70 Oxide film 20A Contact hole 20B for anode electrode , 70B First contact hole 20C, 70C Second contact hole 20D, 70D Third contact hole 51 p-type anode emitter layer (first emitter layer)
52 n-type buffer layer 53 n-type base layer 54 p-type base layer 55 Mesa-type n-type cathode emitter layer 62 Cathode electrodes 63, 64 Cathode terminal 70A Contact hole for cathode electrode 80 npn bipolar transistor 81 n-type SiC substrate 82 n Type SiC buffer layer 83 n type SiC drift layer 84 p type SiC growth layer (p type base layer)
85 n-type SiC growth layer (n-type emitter layer)
87 p-type contact region 90 oxide film 90A emitter electrode contact hole 90B first contact hole 90C second contact hole 90D third contact hole 100 base electrode 101 second base terminal 102 third base terminal 103 second 1 base terminal 104 emitter electrode 120 IGBT
121 n-type SiC substrate 122 p-type SiC buffer layer 123 p-type SiC drift layer 124 n-type growth layer 125 p-type growth layer 125A Mesa-type p-type central portion 126 contact region (collector)
127 oxide film 128A hole 130 gate electrode 133 emitter electrode 135 second gate terminal 136 third gate terminal 137 first gate terminal 140 oxide film 140A emitter electrode contact hole 140B first contact hole 140C second contact Hole 140D Third contact holes 141, 142 Emitter terminal

Claims (7)

A first main electrode;
A first semiconductor layer of a first conductivity type formed on the first main electrode;
A plurality of convex second conductive layers formed on the first semiconductor layer and formed along the upper surface of the first semiconductor layer, and arranged in a plurality of rows. Two semiconductor layers;
A second main electrode formed on the convex second semiconductor layer of the second conductivity type arranged in the plurality of rows,
A control electrode formed on the first semiconductor layer;
An insulating layer formed on the control electrode;
A first contact hole formed in the insulating layer so as to extend in a column direction between two adjacent columns of the convex second semiconductor layer and exposing the control electrode;
The one row of the two rows of convex second semiconductor layers is disposed on the opposite side of the first contact hole and extends in the row direction along the one row. A second contact hole formed in the insulating layer and exposing the control electrode;
The other row of the two rows of convex second semiconductor layers is disposed on the opposite side of the first contact hole and extends in the row direction along the other row. A third contact hole formed in the insulating layer and exposing the control electrode;
A first control terminal formed in the first contact hole and electrically connected to the control electrode;
A second control terminal formed in the second contact hole and electrically connected to the control electrode;
A bipolar semiconductor device, comprising: a third control terminal formed in the third contact hole and electrically connected to the control electrode. The bipolar semiconductor device according to claim 1, wherein
The convex second semiconductor layers of the second conductivity type are arranged in three or more rows,
The first contact hole is formed in the insulating layer so as to extend between two adjacent rows of the convex second semiconductor layer in the column direction so as to expose the control electrode. A plurality of insulating layers are formed,
The second contact hole is arranged on the opposite side of the first contact hole with respect to one end row of the three or more convex second semiconductor layers, and the one end row The control electrode is exposed to be formed in the insulating layer so as to extend in the column direction along
The third contact hole is disposed on the opposite side of the first contact hole with respect to the other end row of the three or more convex second semiconductor layers, and the other end row. The control electrode is exposed to be formed in the insulating layer so as to extend in the column direction along
A plurality of first control terminals formed in the plurality of first contact holes and electrically connected to the control electrode;
A second control terminal formed in the second contact hole and electrically connected to the control electrode;
A bipolar semiconductor device, comprising: a third control terminal formed in the third contact hole and electrically connected to the control electrode. The bipolar semiconductor device according to claim 1 or 2,
A main electrode terminal formed on the second main electrode;
A bipolar semiconductor element, wherein a dimension of the convex second semiconductor layer in a row direction orthogonal to the column direction is longer than a dimension of the main electrode terminal in the row direction. In the bipolar semiconductor device according to any one of claims 1 to 3,
A first conductivity type first emitter layer having a first main electrode formed on one surface;
A first base layer of a second conductivity type formed on the other surface of the first emitter layer;
A first conductivity type second base layer formed on the first base layer as the first conductivity type first semiconductor layer;
A convex second emitter layer as the second conductive type convex second semiconductor layer;
A gate electrode as the control electrode;
A first gate terminal as the first control terminal;
A second gate terminal as the second control terminal;
A third gate terminal as the third control terminal,
A bipolar semiconductor device comprising a gate turn-off thyristor. In the bipolar semiconductor device according to any one of claims 1 to 3,
A second conductivity type substrate to be a collector;
A second conductivity type drift layer formed on the second conductivity type substrate;
A first conductivity type base layer formed on the drift layer as the first conductivity type first semiconductor layer;
A convex second conductive type emitter layer as the second conductive type convex second semiconductor layer;
A base electrode as the control electrode;
A first base terminal as the first control terminal;
A second base terminal as the second control terminal;
A third base terminal as the third control terminal,
A bipolar semiconductor device comprising a bipolar transistor. In the bipolar semiconductor device according to any one of claims 1 to 3,
A first conductivity type substrate to be a collector;
A second conductivity type drift layer formed on the first conductivity type substrate;
A first conductivity type growth layer formed on the drift layer as the first conductivity type first semiconductor layer;
A second conductivity type growth layer as the second conductivity type convex second semiconductor layer formed on the first conductivity type growth layer;
A contact region formed by ion implantation into the first conductive type growth layer through a through hole formed in the second conductive type growth layer;
A gate electrode as the control electrode;
A first gate terminal as the first control terminal;
A second gate terminal as the second control terminal;
A third gate terminal as the third control terminal,
A bipolar semiconductor device comprising an insulated gate bipolar transistor. The bipolar semiconductor device according to any one of claims 1 to 6,
A bipolar semiconductor device characterized by being made of a wide gap semiconductor.

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