JP2011249828A - Compound semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the increase of the leakage current of a gate electrode and achieve a stable high-voltage operation for a long period.SOLUTION: In a gate electrode 102 formed on a compound semiconductor layer 100 made of GaN, a TiWN layer (0<x<1) 43 formed by carrying out Schottky junction on the compound semiconductor layer 100 made of GaN, and a low-resistance metal layer 42 formed above the TiWN layer 43 and made of one kind of metal chosen from a group consisting of Au, Cu, and Al, are provided.

Description

  The present invention relates to a compound semiconductor device having a high electron mobility transistor (HEMT) structure.

In recent years, a compound semiconductor device having a HEMT structure using a heterojunction of GaN and Al _y Ga _1-y N (0 <y <1) and having a GaN layer as an electron transit layer has been actively developed. Since GaN is a material having features such as a wide band gap, high breakdown electric field strength, and a large saturation electron velocity, it is extremely suitable as a high voltage operation and high output device material. At present, power devices for mobile phone base stations are required to operate at a high voltage of 40 V or higher, and HEMTs using this GaN are promising as the power devices.

JP 2002-359256 A

  In a power device that operates at a high voltage as described above, in order to perform a stable operation for a long time even in a high temperature environment, it is indispensable to suppress an increase in leakage current of the gate electrode. However, in the conventional HEMT, when the operation is performed for a long time in a high temperature environment, the leakage current of the gate electrode is increased, and it is difficult to perform a stable high voltage operation.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a compound semiconductor device that suppresses an increase in leakage current of a gate electrode and realizes stable high-voltage operation over a long period of time. .

The compound semiconductor device of the present invention has a compound semiconductor layer made of GaN and an electrode formed on the compound semiconductor layer made of GaN, and the electrode is a Schottky junction on the compound semiconductor layer made of GaN. A TiWN layer made of Ti _x W _1-x N (0 <x <1), and a single metal selected from the group consisting of Au, Cu and Al, formed above the TiWN layer. And a metal layer.

  According to the present invention, an increase in leakage current of the gate electrode can be suppressed and stable high voltage operation can be realized over a long period of time.

It is a schematic sectional drawing of the compound semiconductor device of a general HEMT structure. It is a schematic sectional drawing of the useless compound semiconductor device explaining the basic point of this invention. It is a schematic sectional drawing of the compound semiconductor device which shows a comparative example. It is a schematic sectional drawing which shows the manufacturing method of the compound semiconductor device of the HEMT structure which concerns on 1st Embodiment in process order. FIG. 5 is a schematic cross-sectional view subsequent to FIG. 4, illustrating a method for manufacturing the HEMT structure compound semiconductor device according to the first embodiment in the order of steps. It is a schematic sectional drawing which shows the manufacturing method of the compound semiconductor device of the HEMT structure which concerns on 2nd Embodiment in process order. It is a schematic sectional drawing which shows the manufacturing method of the compound semiconductor device of the HEMT structure which concerns on 3rd Embodiment in process order.

-Basic outline of the present invention-
In order to provide a compound semiconductor device that suppresses an increase in leakage current of a gate electrode and realizes a stable high voltage operation over a long period of time and a manufacturing method thereof, the inventor has conceived the basic essence of the invention described below .

_{GaN / Al y Ga 1-y} N (0 <y <1) compound semiconductor device of the general HEMT structure with a heterojunction of, as shown in FIG. 1, GaN or _{Al y Ga 1-y N (} 0 On the compound semiconductor layer 100 made of <y <1), a metal having a large work function capable of sufficiently forming the height (potential) of the Schottky barrier with the compound semiconductor layer, for example, the Ni layer 41 is provided, and further Ni A low-resistance metal layer 42 such as Au is provided on the layer 41 to constitute the gate electrode 201 (see, for example, Patent Document 1).

  In this general compound semiconductor device, the problem that the leakage current of the gate electrode 201 increases has been exposed. Therefore, the present inventor pays attention to this point, and the metal in the low-resistance metal layer 42 gradually diffuses into the Ni layer 41 that forms a Schottky junction with the compound semiconductor layer 100 when used in a high temperature environment. Then, it was thought that eventually reaching the interface with the compound semiconductor layer 100 resulted in an increase in the leakage current of the gate electrode 201 as a result of the height of the Schottky barrier being lowered. In view of this, the present inventor has provided a diffusion prevention layer for suppressing metal diffusion of the low resistance metal layer between the compound semiconductor layer and the low resistance metal layer in order to suppress an increase in leakage current of the gate electrode. I thought.

FIG. 2 is a schematic cross-sectional view of a compound semiconductor device for explaining the basic outline of the present invention. Here, in order to explain the basic outline of the invention, only the main part of the compound semiconductor device will be described. As shown in FIG. 2A, the compound semiconductor device according to the present invention includes a compound semiconductor layer 100 on a compound semiconductor layer 100 made of GaN or Al _y Ga _1-y N (0 <y <1). A gate electrode 101 is formed by sequentially stacking a Ni layer 41 forming a Schottky junction, a Ti _x W _1-x N (0 <x <1) layer 43, and a low-resistance metal layer.

The inventor paid attention to the extremely excellent thermal stability of Ti _x W _1-x N and the denseness when a film was formed, and used this as a diffusion prevention layer to form the compound semiconductor layer 100 and the low-resistance metal layer. 42 between them. The Ti _x W _1-x N layer 43 suppresses the diffusion of the metal of the low resistance metal layer 42 into the compound semiconductor layer 100, and the Schottky barrier is stable between the compound semiconductor layer 100 and the Ni layer 41. Can be maintained, and an increase in leakage current of the gate electrode is suppressed.

Further, the inventor of the present invention indicates that Ti _x W _1-x N has a work function capable of forming a sufficient Schottky barrier height with the compound semiconductor layer 100 in performing high voltage operation. As a result, it was considered to apply this to a compound semiconductor device. A schematic cross-sectional view of this compound semiconductor device is shown in FIG.

As shown in FIG. 2B, the compound semiconductor device according to the present invention includes a Ti _x W _1-x N layer 43 and a low resistance on a compound semiconductor layer 100 made of GaN or Al _y Ga _1-y N. A gate electrode 102 is formed by sequentially laminating a metal layer 42. At this time, the Ti _x W _1-x N layer 43 functions as a diffusion preventing layer that suppresses diffusion of the metal of the low-resistance metal layer 42 into the compound semiconductor layer 100 and is Schottky with the compound semiconductor layer 100. The function of forming a bond is also provided. Thereby, even in the gate electrode 102 having the two-layer structure of the Ti _x W _1-x N layer 43 and the low-resistance metal layer 42, a stable Schottky barrier height is maintained between the compound semiconductor layer 100 and the gate electrode 102, An increase in leakage current of the gate electrode can be suppressed.

Further, the present inventor has extremely excellent thermal stability as the above-described Ti _x W _1-x N as a diffusion preventing layer for suppressing the diffusion of the metal of the low resistance metal layer 42 into the compound semiconductor layer 100. It has been found that Pd can be applied. A schematic cross-sectional view of this compound semiconductor device is shown in FIG.

As shown in FIG. 2 (c), the compound semiconductor device according to the present invention has a Ni that forms a Schottky junction with the compound semiconductor layer 100 on the compound semiconductor layer 100 made of GaN or Al _y Ga _1-y N. A gate electrode 103 is formed by sequentially laminating a layer 41, a Pd layer 44, and a low-resistance metal layer 42.

  Since the Pd layer 44 is excellent in thermal stability as described above, the metal from the low resistance metal layer 42 formed on the Pd layer 44 to the compound semiconductor layer 100 even when used in a high temperature environment. Can be prevented from spreading. In the compound semiconductor device shown in FIG. 2C, a Ni layer 41 that can sufficiently form a Schottky barrier with the compound semiconductor layer is provided on the compound semiconductor layer 100. In addition, a Pd layer 44 that suppresses diffusion of the metal of the low-resistance metal layer 42 formed in the uppermost layer into the compound semiconductor layer 100 is provided.

In this regard, similarly to the compound semiconductor device shown in FIG. 2B, a compound semiconductor device in which a Pd layer 44 that is a diffusion prevention layer is formed on the compound semiconductor layer 100 is also conceivable. That is, as shown in FIG. 3A, the Pd layer 44 and the low-resistance metal layer 42 are sequentially stacked on the compound semiconductor layer 100 to form the gate electrode 202. However, in this gate electrode 202, the compound semiconductor layer 100 made of GaN or Al _y Ga _1-y N (0 <y <1) and the Pd layer 44 formed immediately above react with each other, As a result, the height of the Schottky barrier generated between the compound semiconductor layer 100 and the Pd layer 44 is lowered, and an increase in the leakage current of the gate electrode 201 cannot be suppressed.

  Further, for example, as shown in FIG. 3B, it is conceivable to provide a Pt layer 45 as a diffusion preventing layer between the Ni layer 41 and the low resistance metal layer 42. However, the Pt layer 45 is inferior in thermal stability, and Pt of the Pt layer 45 diffuses into the Ni layer 41 in a high temperature environment. Therefore, the Pt layer 45 does not function as a diffusion preventing layer in a high temperature environment.

  As described above, in order to suppress an increase in leakage current of the gate electrode, a request to suppress metal diffusion in the low-resistance metal layer and a sufficient Schottky barrier between the gate electrode and the compound semiconductor layer. The simplest structure that satisfies both of the requirements for maintaining the height of the compound semiconductor device is the compound semiconductor device of the present invention.

-Specific embodiment of the present invention-
Hereinafter, the structure of a compound semiconductor device having a HEMT structure according to embodiments of the present invention will be described together with a manufacturing method thereof.

(First embodiment)
4 and 5 are schematic cross-sectional views illustrating a method of manufacturing a compound semiconductor device having a HEMT structure according to the first embodiment in the order of steps.

First, as shown in FIG. 4A, the i-GaN layer 2, the electron supply layer 3, and the n-GaN layer 4 are sequentially stacked on the SiC substrate 1.
Specifically, an intentionally undoped GaN layer (i-GaN layer) 2 serving as an electron transit layer is formed on the SiC substrate 1 with a film thickness of about 3 μm using the MOVPE method. Subsequently, for example, an intentionally undoped Al _0.25 Ga _0.75 N layer (i-Al _0.25 Ga _0.75 N layer) 31 is formed with a film thickness of about 3 nm on the i-GaN layer 2 using the MOVPE method. Further, an n-Al _0.25 Ga _0.75 N layer 32 doped with Si at a concentration of about 2 × 10 ¹⁸ cm ⁻³ is formed with a film thickness of about 20 nm, and the electron supply layer 3 having these two-layer structures is formed. Subsequently, an n-GaN layer 4 doped with Si to a concentration of about 2 × 10 ¹⁸ cm ⁻³ is formed on the n-Al _0.25 Ga _0.75 N layer 32 by using the MOVPE method. It is formed with a thickness of about 5 nm.

Here, the electron supply layer 3 is composed of an Al _0.25 Ga _0.75 N layer having an Al composition ratio y of 0.25 in Al _y Ga _1-y N. However, the present embodiment is not limited to this. However, the present invention can be applied if the Al composition ratio y is in the range of 0 <y <1.

In the present embodiment, the n-GaN layer 4 is a protective layer provided for the purpose of stabilizing the IV characteristics of the compound semiconductor device and increasing the forward breakdown voltage and the reverse breakdown voltage. In order for this n-GaN layer 4 to function as the above-mentioned protective layer, the doping concentration is desirably 2 × 10 ¹⁷ cm ⁻³ or more.

  Next, as shown in FIG. 4B, the n-GaN layer 4 in the source electrode and drain electrode formation regions is removed, and a source electrode 21 and a rain electrode 22 are formed in the respective formation regions.

Specifically, first, a resist pattern (not shown) that opens only the formation region of the source electrode 21 and the drain electrode 22 is formed on the n-GaN layer 4. Subsequently, the n-GaN layer 4 in the region where the source electrode 21 and the drain electrode 22 are formed by dry etching using, for example, Cl ₂ gas as a chlorine gas or an inert gas, for example, a chlorine gas, using the resist pattern as a mask. Remove. Subsequently, a Ti layer 5 and an Al layer 6 are sequentially deposited on the resist pattern with a film thickness of about 20 nm and 200 nm using the vapor deposition method so as to fill the opening.

  Subsequently, the resist pattern is peeled and removed by a so-called lift-off method, and at the same time, the Ti layer 5 and the Al layer 6 on the resist pattern are removed, leaving the Ti layer 5 and the Al layer 6 following the opening shape. Then, annealing is performed at a temperature of about 550 ° C. to form an ohmic contact between the Ti layer 5 and the n-GaN layer 4, and the source electrode 21 and the drain electrode 22 are formed.

  Here, in this embodiment, the n-GaN layer 4 in the formation region of the source electrode 21 and the drain electrode 22 is removed by dry etching, but the n-GaN layer 4 is not completely removed. In addition, the thickness may be reduced and left.

Next, as shown in FIG. 5A, the gate electrode 23 is formed on the n-GaN layer 4.
Specifically, first, a resist pattern (not shown) is formed on the n-GaN layer 4 and the Al layer 6 so as to open only the formation region of the gate electrode 23 with a width of about 1 μm. Subsequently, the Ni layer 7, the Ti _0.2 W _0.8 N layer 8, the TiW layer 9, and the Au layer 10 are respectively formed on the resist pattern so as to embed the opening by using a vapor deposition method, a sputtering method, a plating method, or the like. The layers are sequentially deposited with a film thickness of about 60 nm, 30 nm, 10 nm, and 300 nm.

Here, in the present embodiment, an example in which Ni is used as a metal material for forming the Schottky junction with the n-GaN layer 4 is shown. However, in the present embodiment, the present invention is not limited to this. Alternatively, Ir can be applied. Moreover, although the example which applied the n-GaN layer 4 was shown as a compound semiconductor layer which forms the gate electrode 23 and a Schottky junction, in this embodiment, it is not restricted to this, For example, the said compound semiconductor layer As, it is also possible to apply Al _y Ga _1-y N of the same type as the electron supply layer 3. In this case, if Al _y Ga _1-y N has an Al composition ratio y in the range of 0 <y <1, it can be applied.

Subsequently, the resist pattern is peeled and removed by a so-called lift-off method, and at the same time, the Ni layer 7, the Ti _0.2 W _0.8 N layer 8, the TiW layer 9 and the Au layer 10 on the resist pattern are removed, and the Ni layer is formed in the opening shape. 7. Gate electrode 23 is formed leaving Ti _0.2 W _0.8 N layer 8, TiW layer 9 and Au layer 10. Here, the TiW layer 9 is provided in consideration of the adhesion between the Ti _0.2 W _0.8 N layer 8 and the Au layer 10.

Here, the Ti _0.2 W _0.8 N layer 8 having a Ti composition ratio x of 0.2 in Ti _x W _1-x N is formed on the gate electrode 23. However, the present invention can be applied if the Ti composition ratio x is in the range of 0 <x <1. At this time, in the case where the Ti composition ratio x is 0, that is, in the case of a WN layer, there arises a disadvantage that the adhesion with the TiW layer 9 formed thereon is deteriorated.

  Next, as shown in FIG. 5B, the SiN film 11 is formed on the entire surface with a film thickness of about 10 nm by using the CVD method, and the electrodes are covered. Thereafter, the formation of contact holes for the interlayer insulating film and each electrode and the formation process of various wiring layers and the like complete the compound semiconductor device having the HEMT structure according to the first embodiment.

According to the HEMT structure compound semiconductor device according to the first embodiment, Ti _0.2 W _0.8 N which is a dense film having extremely excellent thermal stability between the Ni layer 7 and the Au layer 10. Since the layer 8 is provided, it is possible to suppress gold diffusion from the Au layer 10 to the n-GaN layer 4 even under a high temperature environment, and a stable shot between the n-GaN layer 4 and the Ni layer 7. The height of the key barrier can be maintained. As a result, an increase in the leakage current of the gate electrode can be suppressed.

(Second Embodiment)
FIG. 6 is a schematic cross-sectional view showing the method of manufacturing the HEMT structure compound semiconductor device according to the second embodiment in the order of steps.

In this example, first, each process of FIG. 4A and FIG. 4B is performed.
Next, as shown in FIG. 6A, the gate electrode 24 is formed on the n-GaN layer 4.
Specifically, first, using a sputtering method or a plating method, the Ti _0.2 W _0.8 N layer 12 is about 60 nm thick and the TiW layer 13 is about 40 nm thick on the n-GaN layer 4 and the Al layer 6. The Au layer 14 is sequentially deposited with a film thickness of about 300 nm. Subsequently, a resist pattern (not shown) that covers only the formation region of the gate electrode 24 is formed.

Subsequently, the Ti _0.2 W _0.8 N layer 12, the TiW layer 13, and the Au layer 14 other than the formation region of the gate electrode 24 are removed by ion milling or dry etching using the resist pattern as a mask, and the formation region of the gate electrode 24 Only the Ti _0.2 W _0.8 N layer 12, the TiW layer 13 and the Au layer 14 are left. Then, the resist pattern is removed, and the gate electrode 24 is formed.

Here, the Ti _0.2 W _0.8 N layer 12 having a Ti composition ratio x of 0.2 in Ti _x W _1-x N is formed on the gate electrode 24, but this is not the only case in the present embodiment. However, the present invention can be applied if the Ti composition ratio x is in the range of 0 <x <1. At this time, in the case where the Ti composition ratio x is 0, that is, in the case of the WN layer, there arises a disadvantage that the adhesion with the TiW layer 9 formed thereon is deteriorated, and the Ti composition ratio x is 1, That is, in the case of the TiW layer, there is a disadvantage that the work function becomes small and the height of the Schottky barrier formed with the n-GaN layer 4 becomes low.

  Next, as shown in FIG. 6B, a SiN film 15 is formed on the entire surface with a film thickness of about 10 nm by using the CVD method, and covers each electrode. Thereafter, the formation of contact holes for the interlayer insulating film and each electrode and the formation process of various wiring layers, etc., complete the HEMT structure compound semiconductor device according to the second embodiment.

According to the HEMT structure compound semiconductor device according to the second embodiment, gold is prevented from diffusing from the Au layer 14 to the n-GaN layer 4 between the n-GaN layer 4 and the Au layer 14. Since the Ti _0.2 W _0.8 N layer 12 is provided, it is also possible to form a Schottky barrier between the Ti _0.2 W _0.8 N layer 12 and the n-GaN layer 4, and in the first embodiment described above. In addition to the effect, the structure of the gate electrode can be further simplified.

(Third embodiment)
FIG. 7 is a schematic cross-sectional view showing the method of manufacturing the HEMT structure compound semiconductor device according to the third embodiment in the order of steps.

In this example, first, each process of FIG. 4A and FIG. 4B is performed.
Next, as illustrated in FIG. 7A, the gate electrode 25 is formed on the n-GaN layer 4.
Specifically, first, a resist pattern (not shown) is formed on the n-GaN layer 4 and the Al layer 6 so as to open only the formation region of the gate electrode 25 with a width of about 1 μm. Subsequently, the Ni layer 16, the Pd layer 17, and the Au layer 18 are sequentially deposited in a thickness of about 60 nm, 40 nm, and 300 nm on the resist pattern so as to embed the opening by using an evaporation method, a sputtering method, or the like. .

  Subsequently, the resist pattern is peeled and removed by a so-called lift-off method, and at the same time, the Ni layer 16, the Pd layer 17 and the Au layer 18 on the resist pattern are removed, and the Ni layer 16, the Pd layer 17 and the Au layer are formed in the opening shape. The gate electrode 25 is formed leaving 18. Here, in the present embodiment, unnecessary heat treatment is not performed when the gate electrode 25 is formed, and the thickness of the Ni layer 16 on the n-GaN layer 4 is sufficiently thicker than about 10 nm ( Therefore, diffusion of Pd from the Pd layer 17 does not occur at the interface between the n-GaN layer 4 which is a semiconductor layer and the Ni layer 16.

  Next, as shown in FIG. 7B, a SiN film 19 is formed on the entire surface with a film thickness of about 10 nm by using the CVD method to cover the electrodes. Thereafter, the formation of contact holes for the interlayer insulating film and each electrode and the formation process of various wiring layers, etc., complete the HEMT structure compound semiconductor device according to the third embodiment.

  According to the compound semiconductor device having the HEMT structure according to the third embodiment, the Pd layer 17 having extremely excellent thermal stability is provided between the Ni layer 16 and the Au layer 18. , The diffusion of gold from the Au layer 18 to the n-GaN layer 4 can be suppressed, and a stable Schottky barrier height can be maintained between the n-GaN layer 4 and the Ni layer 16. it can. As a result, an increase in the leakage current of the gate electrode can be suppressed.

Various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
A compound semiconductor layer;
An electrode formed by Schottky junction on the compound semiconductor layer,
The electrode is
A TiWN layer made of Ti _x W _1-x N (0 <x <1);
A compound semiconductor device comprising: a low-resistance metal layer formed above the TiWN layer.

(Appendix 2)
The electrode is provided with a metal layer made of one kind of metal selected from the group consisting of Ni, Ti and Ir between the compound semiconductor layer and the TiWN layer. The compound semiconductor device described.

(Appendix 3)
2. The compound semiconductor device according to appendix 1, wherein the TiWN layer is provided immediately above the compound semiconductor layer.

(Appendix 4)
4. The compound semiconductor device according to any one of appendices 1 to 3, wherein the low-resistance metal layer is made of one kind of metal selected from the group consisting of Au, Cu, and Al.

(Appendix 5)
An electron transit layer made of GaN;
An electron supply layer made of Al _y Ga _1-y N (0 <y <1) on the electron transit layer;
Any one of Supplementary notes 1 to 4, wherein the compound semiconductor layer is formed of n-type GaN formed on the electron supply layer and doped at a concentration of 2 × 10 ¹⁷ cm ⁻³ or more. The compound semiconductor device according to item.

(Appendix 6)
A compound semiconductor layer;
An electrode formed on the compound semiconductor layer via a Schottky junction,
The electrode is
A first metal layer made of one kind of metal selected from the group consisting of Ni, Ti and Ir on the compound semiconductor layer;
A second metal layer made of a low resistance metal;
A compound semiconductor device comprising: a third metal layer made of Pd formed between the first metal layer and the second metal layer.

(Appendix 7)
The compound semiconductor device according to appendix 6, wherein the second metal layer is made of one kind of metal selected from the group consisting of Au, Cu, and Al.

(Appendix 8)
An electron transit layer made of GaN;
An electron supply layer made of Al _y Ga _1-y N (0 <y <1) on the electron transit layer;
The compound semiconductor layer according to appendix 6 or 7, wherein the compound semiconductor layer is formed on the electron supply layer and is made of n-type GaN doped with a concentration of 2 × 10 ¹⁷ cm ⁻³ or more. Semiconductor device.

(Appendix 9)
A compound semiconductor layer;
An electrode formed on the compound semiconductor layer via a Schottky junction,
The electrode is
A low resistance metal layer,
A compound semiconductor device comprising: a diffusion prevention layer that is provided between the low-resistance metal layer and the compound semiconductor layer and suppresses metal diffusion of the low-resistance metal layer.

(Appendix 10)
The compound semiconductor device according to appendix 9, wherein the diffusion preventing layer is a TiWN layer or a Pd layer made of Ti _x W _1-x N (0 <x <1).

(Appendix 11)
Forming a compound semiconductor layer above the substrate;
Forming a TiWN layer made of Ti _x W _1-x N (0 <x <1) on the compound semiconductor layer by Schottky junction with the compound semiconductor layer;
Forming a low-resistance metal layer above the TiWN layer. A method of manufacturing a compound semiconductor device, comprising:

(Appendix 12)
Forming a compound semiconductor layer above the substrate;
Forming a metal layer made of one kind of metal selected from the group consisting of Ni, Ti and Ir on the compound semiconductor layer by Schottky junction with the compound semiconductor layer;
Forming a TiWN layer made of Ti _x W _1-x N (0 <x <1) above the metal layer;
Forming a low-resistance metal layer above the TiWN layer. A method of manufacturing a compound semiconductor device, comprising:

(Appendix 13)
Forming a compound semiconductor layer above the substrate;
Forming a metal layer made of one kind of metal selected from the group consisting of Ni, Ti and Ir on the compound semiconductor layer by Schottky junction with the compound semiconductor layer;
Forming a Pd layer above the metal layer;
Forming a low-resistance metal layer above the Pd layer. A method of manufacturing a compound semiconductor device, comprising:

(Appendix 14)
14. The compound semiconductor device according to any one of appendices 11 to 13, wherein the low-resistance metal layer is made of one kind of metal selected from the group consisting of Au, Cu, and Al. Production method.

41 Ni layer 42 Low resistance metal layer 43 Ti _x W _1-x N layer 44 Pd layer 45 Pt layer 100 Compound semiconductor layers 101, 102, 103 Gate electrode

Claims (3)

A compound semiconductor layer made of GaN;
An electrode formed on the compound semiconductor layer made of GaN,
The electrode is
A TiWN layer made of Ti _x W _1-x N (0 <x <1) formed by Schottky junction on the compound semiconductor layer made of GaN;
A compound semiconductor device comprising: a metal layer made of one kind of metal selected from the group consisting of Au, Cu and Al, formed above the TiWN layer. The compound semiconductor layer made of GaN is provided on an electron transit layer made of GaN, and an electron supply layer made of Al _y Ga _1-y N (0 <y <1) on the electron transit layer. The compound semiconductor device according to claim 1, wherein The compound semiconductor device according to claim 1, wherein the compound semiconductor layer made of GaN is made of n-type GaN doped with a concentration of 2 × 10 ¹⁷ cm ⁻³ or more.

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