JP2011244212A - Bit conversion circuit, transfer unit, communication system, bit conversion method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bit conversion circuit, transfer unit, communication system, bit conversion method and program which implement a conversion table of bit conversion in a small gate scale.SOLUTION: According to 8b/10b encoder 11, for example, pattern classification of an encode table used in the case of 8b/10b conversion is performed in accordance with whether the number of '0' and '1' which the data after conversion has is the same, Then, when input data is a D code indicating data, the calculation is carried out by use of the number of input data being the same in the case where the number of '0' and '1' is the same, and otherwise, after conversion of one side polarity is performed according to the encode table, conversion of the other side polarity is performed by an inverter.

Description

  The present invention relates to a bit conversion circuit for performing bit conversion used for high-speed serial transfer, a transfer unit, a communication system, a bit conversion method, and a program.

As communication methods for transmitting and receiving data, there are parallel communication in which a plurality of data signals are simultaneously transmitted through respective communication links, and serial communication in which transmission is performed through a single communication link.
Generally, in the field of computer networks, serial communication is used due to synchronization and cost problems.

One of the serial communication methods for transmitting data at high speed is an 8b / 10b communication method.
The 8b / 10b communication method is a method of converting 8-bit data into 10-bit data and transmitting the data.
FIG. 1 is a diagram showing a part of the 8b / 10b conversion table.
In the 8b / 10b conversion, input data is divided into upper bits and lower bits, and conversion is performed in consideration of run length limitation (RLL) that limits consecutive “0” or “1”. Further, error correction is performed by extending and converting 8-bit input data to 10 bits.
As shown in FIG. 1, 8-bit data corresponding to byte data “00” to “FF” is divided into upper bit “HGF” and lower bit “EDCBA”, and 1 bit “i” and “j” are respectively assigned to each bit. In addition, it is converted into 6-bit 'abcdei' and 4-bit 'fghj'.

The 10-bit data converted by the 8b / 10b conversion is called a symbol, and Dx. It is expressed as y.
6-bit data has 32 bit patterns, and 4-bit data has 8 bit patterns. Therefore, 8-bit data is expressed by any of 256 symbols D00.0 to D31.7.

Each symbol has two types of patterns of + and − obtained by inverting “0” and “1”. These + and-are called running disparity (RD). In FIG. 1, the CurrentRD− column is a column in which the RD polarity is −, and the CurrentRD + column is a column in which the RD polarity is +.
Considering RD polarity +/−, 8-bit input data is converted into 512 symbols by 8b / 10b conversion. These 512 symbols are called D codes.
The 512 D codes are symbols indicating data, but there are 24 symbols called K codes indicating control signals.
Therefore, there are a total of 536 combinations in the 8b / 10b conversion.

As described above, in the 8b / 10b conversion, a conversion table having a total of 536 combinations is used. Therefore, when this conversion table is to be mounted on a semiconductor circuit, a large number of combinational circuits are required. This not only increases the gate scale of the semiconductor circuit, but also limits the operation speed. In order to improve this, it is necessary to add a circuit such as pipeline processing, which further increases the gate scale.
Although the 8b / 10b conversion has been described above, these disadvantages occur similarly in other bit conversions such as the 8b / 14b conversion.

An object of the present invention is to provide a bit conversion circuit in which a conversion table for bit conversion is mounted on a small gate scale.
It is another object of the present invention to provide a transfer unit and a communication system using such a bit conversion circuit.
It is another object of the present invention to provide a bit conversion method and program used in such a bit conversion circuit.
The present invention has found that, for example, regularity is found in a conversion table for converting input data into output data in 8b / 10b conversion, and a circuit with a reduced number of gates is formed by utilizing the regularity. The present invention is based on this finding.

  The bit conversion circuit of the present invention is a bit conversion circuit that generates m-bit output data by converting m-bit input data with reference to a bit conversion table (m and n are positive integers, and n> m), when the input data is converted into D-code output data indicating the data, the output data corresponding to the input data is extracted from the bit conversion table with a symbol having a different number of 0 values and 1 values. The bit conversion is performed with reference to a conversion table of 1 and a second conversion table in which symbols having the same number of 0 values and 1 value are extracted from the bit conversion table.

  The transfer unit according to the present invention generates a m-bit output data by bit-converting the n-bit input data by bit-converting the m-bit input data to generate n-bit output data. A transfer unit having a second bit decoding circuit (m and n are positive integers and n> m), and the bit encoding circuit outputs an input data as an output of a D code indicating the data When converting to data, the output data from the bit conversion table, the first conversion table in which the output data for the input data is extracted from the bit conversion table, the first conversion table that is different from the number of 0 values and the number of 1 values. The bit conversion is performed with reference to the second conversion table in which symbols having the same number of 0 values and 1 values are extracted.

  The communication system according to the present invention generates a m-bit output data by bit-converting the n-bit input data by bit-converting the m-bit input data to generate n-bit output data. A communication system having a plurality of transfer units having a second bit decoding circuit (m and n are positive integers and n> m), and the bit encoding circuit receives input data, When converting into output data of the D code shown, from the bit conversion table, a first conversion table in which the output data for the input data is extracted with symbols having different numbers of 0 values and 1 values, and the bit conversion table. The bit conversion is performed with reference to the second conversion table in which the output data extracts symbols having the same number of 0 values and 1 values.

  The communication method of the present invention is a bit conversion method of a bit conversion circuit that converts n-bit input data to generate n-bit output data (m and n are positive integers and n> m). When the input data is converted into D-code output data indicating the data, a first conversion table in which symbols having different numbers of 0 values and 1 values are extracted from the bit conversion table. The bit conversion is performed with reference to the second conversion table in which the output data is extracted from the bit conversion table by extracting symbols having the same 0-value number and 1-value number.

  The program of the present invention is a program executed by a computer having a bit conversion circuit that converts n-bit input data to generate n-bit output data (m and n are positive integers, and n> m) First, when the input data is converted into D-code output data indicating the data, a first symbol in which the output data corresponding to the input data has different numbers of 0 values and 1 values is extracted from the bit conversion table. A procedure for performing the bit conversion on the computer with reference to a conversion table and a second conversion table in which the output data is extracted from the bit conversion table by extracting symbols having the same number of 0 values and 1 values. Let it run.

The bit conversion method of the present invention is a bit conversion method of an 8b / 10b conversion circuit having a dividing circuit, a 5b / 6b conversion circuit, a 3b / 4b conversion circuit, an RD control circuit, and a synthesis circuit,
A first step in which the dividing circuit divides 8-bit input data into 5-bit data and 3-bit data;
A second step in which the 5b / 6b conversion circuit converts the 5-bit data divided in the first step into 6-bit data by 5b / 6b conversion and outputs the data;
A third step in which the 3b / 4b conversion circuit converts the 3-bit data divided in the first step into 4-bit data by 3b / 4b conversion and outputs the data;
A fourth step in which the RD control circuit determines the polarity of the running disparity (RD) of the next output data based on the polarity of the RD of the current output data;
The synthesis circuit synthesizes the 6-bit data converted in the second step and the 4-bit data converted in the third step to generate 10-bit output data. And the process of
Have
The second step includes
In the 5b / 6b conversion circuit, the output data corresponding to the input data is output data in which the number of 0 values is different from the number of 1 values, or the output data is output data in which the number of 0 values is equal to the number of 1 values. A sixth step of determining whether there is,
In the sixth step, when it is determined that the number of 0 values is different from the number of 1 values, the 5b / 6b conversion circuit outputs the output data having different numbers of 0 values and 1 values. A seventh step of referring to the first conversion table corresponding to the case where the output data of one of the RDs is converted based on the input data;
An eighth step of generating output data of the polarity of the other RD by the inverter based on the output data converted in the seventh step;
A ninth step of determining the polarity of output data to be output according to the polarity of the next output data determined in the fourth step;
In the sixth step, when it is determined that the number of 0 values is equal to the number of 1 values, the second value corresponds to the case where the number of 0 values is equal to the number of 1 values. Referring to the conversion table, a 1-bit extension bit is generated based on the number of zero values and one value of the input data so that the number of zero values and one value of the output data are the same. A tenth step of:
An eleventh step of generating output data by combining the extension bits generated in the tenth step with data having the same value as each value of input data;
Have
The third step includes
In the 3b / 4b conversion circuit, the output data corresponding to the input data is output data in which the number of 0 values is different from the number of 1 values, or the output data is output data in which the number of 0 values is equal to the number of 1 values. A twelfth step of determining whether there is,
In the twelfth step, when it is determined that the number of zero values is different from the number of one values, the 3b / 4b conversion circuit outputs the output data having different numbers of zero values and one values. A thirteenth step of referring to the third conversion table corresponding to the case where the output data of one of the RDs is converted based on the input data;
A fourteenth step of generating output data having the polarity of the other RD by an inverter based on the output data converted in the twelfth step;
A fifteenth step of determining the polarity of output data to be output according to the polarity of the next output data determined in the fourth step;
In the twelfth step, when it is determined that the number of 0 values is equal to the number of 1 values, the fourth value corresponds to the case where the number of 0 values is equal to the number of 1 values. Referring to the conversion table, a 1-bit extension bit is generated based on the number of zero values and one value of the input data so that the number of zero values and one value of the output data are the same. A sixteenth step of
A seventeenth step of generating output data by combining the extension bits generated in the sixteenth step with data having the same value as each value of input data;
Have

  The present invention can implement a conversion table for bit conversion with a small gate scale. Further, the present invention can perform bit conversion at high speed and power saving.

FIG. 1 is a diagram illustrating an example of a part of an 8b / 10b conversion table. FIG. 2 is a diagram illustrating an example of a serial communication unit having an 8b / 10b encoder and an 8b / 10b decoder. FIG. 3 is a diagram illustrating an example of a serial communication system having a plurality of transmission paths using a plurality of 8b / 10b encoders and 10b / 8b decoders. FIG. 4 is a diagram illustrating an example of a block diagram of the 8b / 10b encoder. FIG. 5 is a diagram showing a 5b / 6b conversion table of the present embodiment. FIG. 6 is a diagram showing a 3b / 4b conversion table of the present embodiment. FIG. 7 is a diagram showing a control signal conversion table of the present embodiment. FIG. 8 is a flowchart of the encoding algorithm of the 8b / 10b encoder. FIG. 9 is a flowchart showing an example of 5-bit data conversion processing by the 5b / 6b conversion circuit. FIG. 10 is a flowchart illustrating an example of 3-bit data conversion processing by the 3b / 4b conversion circuit. FIG. 11 is a flowchart illustrating an example of K code conversion processing by the control signal conversion circuit.

Hereinafter, embodiments of the present invention will be described.
First, 8b / 10b conversion, which is one embodiment of bit conversion in the present invention, will be described.

The 8b / 10b conversion is a method for converting 8-bit data into 10-bit data.
The 8b / 10b conversion is used for serial data communication, for example.
Transfer of serial data requires the presence of data and a clock that creates the timing for extracting the data.
The 8b / 10b system is characterized in that the clock is embedded in the serial data so that the data and the clock are transferred through the same wiring. This method is called an embedded clock method.

With serial data, either Low (“0”) or High (“1”) may continue for a long period of time, or the states of “0” and “1” may fluctuate irregularly. is there.
Since the data receiving side regenerates the clock from the toggle of the received data, the clock cannot be taken out from the “0” or “1” state when the state is “long”. Therefore, in the 8b / 10b system, conversion is determined so that the same level does not continue for 6 bits or more for any data.
As a result, about 20% of the bandwidth is lost, but the data and the clock can be simultaneously transmitted through the same wiring. In addition, the bit change of the signal increases, and the occurrence of transfer errors due to noise or the like can be reduced.

Next, a specific example of 8b / 10b conversion will be described with reference to FIG.
Consider 8-bit data 'HGF EDCBA'.
As shown in FIG. 1, in the 8b / 10b conversion, the data block x (decimal notation) of the lower bit 'EDCBA' (5 bits) and the data block y (decimal notation) of the upper bit 'HGF' (3 bits) To separate. Then, the separated data blocks are considered by replacing them with character codes (symbols) called D codes. The D code is Dx. It is expressed as y.
The “EDCBA” block is converted to “abcdei” (6 bits) by performing 5b / 6b conversion.
Similarly, 3b / 4b conversion is performed on the 'HGF' block to convert it to 'fghj' (4 bits).
Then, “abcdei” and “fghj” are combined to obtain 10-bit encoded data.
This bit conversion is performed, for example, using a table illustrated in FIG.

By 8b / 10b conversion, 256 types of 8-bit data are encoded into 256 types of data of 10 bits.
That is, since the bit width is expanded from 8 bits to 10 bits, special codes other than data can be embedded. In this embodiment, a control signal K (K code) is embedded as such a special code. In addition, the bit width is expanded from 8 bits to 10 bits, so that an error correction can be achieved.

By the way, in the 8b / 10b conversion, the number of '0's and'1's in the code string being transmitted is aligned to achieve DC balance, and each data block is set to '0' in order to reduce the loss of information. It has two types of patterns that are inverted from '1'.
These two types of patterns are referred to as a plus code (positive symbol code) and a minus code (negative symbol code). The minus code is a code obtained by inverting each bit of the plus code. These two types of patterns are indicated by a sign + (plus code) /-(minus code).

This +/− is called running disparity (RD). For RD +, RD- is equal to the bit inverted. During data transmission, the number of '0's is suppressed by alternately transmitting RD- if the immediately preceding is RD +, and RD + if the immediately preceding is RD-.
However, if the number of “0” and the number of “1” are the same in the data block, in principle, there is no inversion pattern and the sign (polarity) of RD is continued.
With such a mechanism, it is determined that six or more “0” s or “1” s are not transmitted continuously.

As described above, due to RD, each symbol has two polarities (+ and-).
For this reason, 512 symbols (D codes) are prepared in the 8b / 10b conversion. In addition, 24 control symbols called control signals K (K codes) are prepared.
In the present invention, by finding the regularity of the 8b / 10b conversion table shown in FIG. 1, it is possible to perform 8b / 10b conversion with a smaller conversion table.
Hereinafter, the configuration of the embodiment of the present invention will be described in detail.

FIG. 2 is a diagram illustrating a serial communication unit 100 having an 8b / 10b encoder and an 8b / 10b decoder according to an embodiment of the present invention.
As shown in FIG. 2, the serial communication unit 100 includes a transmission circuit 10, a reception circuit 20, and a serial transmission path 30.
As shown in FIG. 2, an 8-bit data block 'HGF EDCBA' is input to the transmission circuit 10, converted into a 10-bit data block 'abcdei fghj', and transmitted to the reception circuit 20 via the serial transmission path 30. The Then, the receiving circuit 20 decodes the 10-bit data block “abcdei fghj” and outputs an 8-bit output data block “HGF EDCBA”.

The transmission circuit 10 includes an 8b / 10b encoder 11 and a parallel / serial converter 12.
The 8-bit input data is converted into 10-bit data by the 8b / 10b encoder 11 and converted into serial data by the parallel / serial converter 12. The converted data is sequentially transmitted bit by bit through the serial transmission path 30 and received by the receiving circuit 20.
The receiving circuit 20 includes a serial / parallel converter 21 and a 10b / 8b decoder 22.
Serial data transmitted through the serial transmission path 30 is converted into parallel 10-bit data by the serial / parallel converter 21. The 10-bit data is converted into 8-bit data by the 10b / 8b decoder 22 and output as output data.

FIG. 3 is a diagram illustrating an example of a serial communication system 200 having a plurality of transmission paths using a plurality of 8b / 10b encoders and a plurality of 10b / 8b decoders.
As illustrated in FIG. 3, the serial communication system 200 includes a transmission circuit interface 101, a reception circuit interface 201, and serial transmission paths 30-1 to 30-n (n is a positive integer).
The transmission circuit interface 101 includes n 8b / 10b encoders 11-1 to 11-n and parallel / serial converters 12-1 to 12-n.
The reception circuit interface 201 includes n serial / parallel converters 21-1 to 21-n and 10b / 8b decoders 22-1 to 22-n.
The serial transmission lines 30-1 to 30-n perform data transmission between them.

Next, details of the 8b / 10b encoder according to the embodiment of the present invention will be described.
FIG. 4 is a diagram illustrating an example of a block diagram of the 8b / 10b encoder 11 according to the embodiment of the present invention.
The 8b / 10b encoder 11 corresponds to the bit conversion circuit of the present invention.
As shown in FIG. 4, the 8b / 10b encoder 11 includes a dividing circuit 111, a 5b / 6b conversion circuit 112, a 3b / 4b conversion circuit 113, a control signal conversion circuit 114, an RD control circuit 115, a synthesis circuit 116, and a selector / FF. (Flip-flop) 117 is included. The 8b / 10b encoder 11 includes a data input terminal 118, a control signal input terminal 119, a clock signal input terminal 120, and a data output terminal 121 as data input / output terminals.

First, the data flow in the 8b / 10b encoder 11 shown in FIG. 4 will be briefly described.
As shown in FIG. 4, the dividing circuit 111 divides the 8-bit data “HGF EDCBA” input from the data input terminal 118 into a 5-bit “EDCBA” and a 3-bit “HGF”.
The 5-bit data “EDCBA” is input to the 5b / 6b conversion circuit 112, and the 3-bit data “HGF” is input to the 3b / 4b conversion circuit 113. Further, 8-bit data “HGF EDCBA” is input to the control signal conversion circuit 114.

The 5b / 6b conversion circuit 112 converts the input 5-bit data “EDCBA” according to a conversion table to be described later, and generates 6-bit data “abcdei_d” by adding 1 bit. Here, '_d' means data.
Then, the signal currentRD_5b6b indicating the RD polarity (sign) of the current data 'EDCBA' is output to the RD control circuit 115.

On the other hand, the 3b / 4b conversion circuit 113 converts the input 3-bit data 'HGF' according to a conversion table described later, and generates 4-bit data 'fghj_d' by adding 1 bit.
Then, a signal currentRD_3b4b indicating the RD polarity (sign) of the current data 'fghj_d' is output to the RD control circuit 115.

  The synthesizing circuit 116 synthesizes the 6-bit data 'abcdei_d' output from the 5b / 6b conversion circuit 112 and the 4-bit data 'fghj_d' output from the 3b / 4b conversion circuit 113. It is assumed that data is “abcdififghj_d”.

On the other hand, the control signal K input from the control signal input terminal 119 is input to the control signal conversion circuit 114, the RD control circuit 115, and the selector / FF 116.
The control signal conversion circuit 114 performs conversion according to the conversion table described later based on the input 8-bit data “HGF EDCBA” and the control signal K, and generates 10-bit data “abcdefifghj_k”. Here, “_k” means the control signal K.
Then, the signal currentRD_k indicating the RD polarity (sign) of the current data “abcdififj_k” is output to the RD control circuit 115.

  The RD control circuit 115 receives the currentRD_5b6b from the 5b / 6b conversion circuit 112, the currentRD_3b4b from the 3b / 4b conversion circuit 113, and the currentRD_k from the control signal conversion circuit 114, respectively. The RD polarity of the next input data block is determined to be inverted from the current RD polarity. Therefore, the RD control circuit 115 outputs the signal nextRD indicating the polarity obtained by inverting the current RD polarity to the 5b / 6b conversion circuit 112, the 3b / 4b conversion circuit 113, and the control signal conversion circuit 114.

The selector FF (flip-flop) 116 generates 10-bit data “abcdififj_j” based on the input “abcdififj_d” and “abcdififj_k”, and outputs the generated data from the data output terminal 121.
The clock signal CLK input from the clock signal input terminal 120 is input to the RD control circuit 115 and the selector / FF 116. The RD control circuit 115 and the selector FF 116 operate in synchronization with the clock signal CLK.

[5b / 6b conversion table]
Hereinafter, a conversion table for converting the 5-bit data “EDCBA” input in the 5b / 6b conversion circuit 112 will be described.
FIG. 5 is a diagram showing a 5b / 6b conversion table of the present embodiment.
As shown in FIG. 5, the 5b / 6b conversion table used in the 5b / 6b conversion circuit 112 of the present embodiment has two patterns, pattern 1 shown in FIG. 5 (a) and pattern 2 shown in FIG. 5 (b). Divided into tables.
These two tables are a table in the case where the output data after conversion has a bit inversion relationship according to the RD polarity, and the output data after conversion becomes the same output data as the input data regardless of the RD polarity. It is a table when there is.
As described above, when the numbers of “0” and “1” in the output data block are different, there is an inversion pattern of RD− with respect to RD +, but “0” and “1” in the data block exist. When the numbers are equal, there is no inversion pattern.
In other words, the pattern 1 table shown in FIG. 5A is a table in the case where the number of “0” and “1” in the output data block is different, and the pattern 2 shown in FIG. This table is a table when the numbers of “0” and “1” in the output data block are equal.

Hereinafter, a specific example when the 5b / 6b conversion circuit 112 performs the conversion process using the 5b / 6b conversion table shown in FIG. 5 will be described.
As described above, the 5b / 6b conversion circuit 112 performs conversion processing based on the input 5-bit data block 'EDCBA' and nextRD, which is a signal indicating the RD polarity of the output data.

  First, the 5b / 6b conversion circuit 112 refers to the 5b / 6b conversion table shown in FIG. 5 to determine whether the input 5-bit data block 'EDCBA' corresponds to the pattern 1 table or the pattern 2 table. Judge whether it falls under.

When it is determined that the table corresponds to the pattern 1 table shown in FIG. 5A, the 5b / 6b conversion circuit 112 performs conversion of only one of the polarities, and the other polarity is obtained by an inverter.
Then, data having a polarity corresponding to the RD polarity of the next output data indicated by nextRD input from the RD control circuit 115 described above is output as output data.

On the other hand, in the pattern 2 table, as can be seen by referring to FIG. 5B, the input data block 'EDCBA' and the output data block 'edcba' up to the fifth digit have the same output except for exceptions. is there.
For example, D03. In x, the input data block 'EDCBA' = '00011' and the output data block 'abcdei' = '110001'. That is, 'E' = 'e' = 0, 'D' = 'd' = 0, 'C' = 'c' = 0, 'B' = 'b' = 1, 'A' = 'a' = It is 1. In the table of pattern 2 shown in FIG. Except for x, the relationship between input data and output data is all like this.

Therefore, if it is determined that the table corresponds to the pattern 2 table shown in FIG. 5B, the 5b / 6b conversion circuit 112 determines each value except for “i” which is an extension bit of the output data block “abcdei”. The value is the same as that of the input data block 'EDCBA'.
In the pattern 2 table, the extension bit “i” is calculated using the fact that the numbers of “0” and “1” in the output data block must be the same.
For example, D03. In x, the number of “0” in the input data block = the number of “0” in the output data block = 3, and the number of “1” in the input data block = “1” in the output data block. Number = 2. Therefore, the value of the extension bit needs to be “1”.
In this way, conversion is performed when the converted output data is the same output data as the input data regardless of the RD polarity.
However, there is an exception D07. Only x is converted by referring to the conversion table shown in FIG.
Here, D07. x is a symbol having + and-polarities even though the number of output data '0' and '1' is the same. Therefore, an exception is D07. When converting x, the 5b / 6b conversion circuit 112 determines the polarity to be output based on the RD polarity of the next output data notified from the RD control circuit.

As described above, the 5b / 6b conversion circuit 112 has the same output data regardless of the RD polarity when the converted output data has a bit inversion relationship according to the RD polarity. Refer to two different tables.
If the converted output data has a bit inversion relationship according to the RD polarity, the output data of one polarity is generated by referring to the table, and then the output data of another polarity is generated by the inverter .
If the converted output data is the same output data regardless of the RD polarity, the same value as each value of the input data is given to each value of the converted output data, and then “0” and “ Using the fact that the number of 1 'values is the same, the value of the extension bit is calculated.
That is, the 5b / 6b conversion table referred to by the 5b / 6b conversion circuit 112 is a small scale that uses the regularity of the 8b / 10b conversion table shown in FIG. It has become a table.

[3b / 4b conversion table]
Next, a conversion table for converting the 3-bit data “HGF” input in the 3b / 4b conversion circuit 113 will be described.
FIG. 6 is a diagram showing a 3b / 4b conversion table of the present embodiment.
As shown in FIG. 6, the 3b / 4b conversion table used in the 3b / 4b conversion circuit 113 of the present embodiment has two patterns 1 shown in FIG. 6A and 2 shown in FIG. 6B. Divided into tables.
These two tables are similar to the 5b / 6b conversion table described in FIG. 5 when the converted output data has a bit inversion relationship according to the RD polarity and the converted output data has the RD polarity. This is a table when the output data is the same as the input data regardless of the input data.

Hereinafter, a specific example when the 3b / 4b conversion circuit 113 performs the conversion process using the 3b / 4b conversion table shown in FIG. 6 will be described.
As described above, the 3b / 4b conversion circuit 113 performs conversion processing based on the input 3-bit data block 'HGF' and nextRD, which is a signal indicating the RD polarity of the output data.

  First, the 3b / 4b conversion circuit 113 refers to the 3b / 4b conversion table shown in FIG. 6 and determines whether the input 3-bit data block 'HGF' corresponds to the pattern 1 table or the pattern 2 table. Judge whether it falls under.

When it is determined that the table corresponds to the pattern 1 table shown in FIG. 6A, the 3b / 4b conversion circuit 113 performs conversion of only one of the polarities, and the other polarity is obtained by an inverter.
Then, data having a polarity corresponding to the RD polarity of the next output data indicated by nextRD input from the RD control circuit 115 described above is output as output data.

On the other hand, in the pattern 2 table, as can be seen by referring to FIG. 6B, the input data block 'HGF' and the output data block 'hgf' up to the third digit have the same output except for exceptions. is there.
For example, Dx. 1, the input data block 'HGF' = '001' and the output data block 'fghj' = '1001'. That is, 'H' = 'h' = 0, 'G' = 'g' = 0, and 'F' = 'f' = 1. In the pattern 2 table shown in FIG. Except for 3, the relationship between input data and output data is all like this.

Therefore, when it is determined that the table corresponds to the pattern 2 table shown in FIG. 6B, the 3b / 4b conversion circuit 113 sets each value except for “j” which is an extension bit of the output data block “fghj”. The same value as the input data block 'HGF' is used.
In the pattern 2 table, the extension bit “j” is calculated using the fact that the numbers of “0” and “1” in the output data block must be the same.
For example, Dx. 1, the number of “0” in the input data block = the number of “0” in the output data block = 2, and the number of “1” in the input data block = “1” in the output data block. Number = 1. Therefore, the value of the extension bit needs to be “1”.
In this way, conversion is performed when the converted output data is the same output data as the input data regardless of the RD polarity.
However, an exception is Dx. Only 3 is converted by referring to a separate table.
Here, Dx. 3 is a symbol having + and-polarities even though the number of output data '0' and '1' is the same. Therefore, an exception is D.I. When converting 3, the 3b / 4b conversion circuit 113 determines the polarity to be output based on the RD polarity of the next output data notified from the RD control circuit.

As described above, the 3b / 4b conversion circuit 113 uses the case where the output data after conversion has a bit inversion relationship according to the RD polarity according to the input data, and the case where the output data after conversion depends on the RD polarity. First, two different tables are referred to when the output data is the same.
If the converted output data has a bit inversion relationship according to the RD polarity, the output data of one polarity is generated by referring to the table, and then the output data of another polarity is generated by the inverter .
If the converted output data is the same output data regardless of the RD polarity, the same value as each value of the input data is given to each value of the converted output data, and then “0” and “ Using the fact that the number of 1 'values is the same, the value of the extension bit is calculated.
That is, the 3b / 4b conversion table referred to by the 3b / 4b conversion circuit 113 is a small scale using the regularity when the inventor found the regularity of the 8b / 10b conversion table shown in FIG. It has become a table.

[Control signal conversion table]
Next, a conversion table for converting the 8-bit control signal K (K code) 'HGF EDCBA' input in the control signal conversion circuit 114 will be described.
FIG. 7 is a diagram showing a control signal conversion table of the present embodiment.
As the control signal K, there are 24 symbols as described above. As shown in FIG. Indicated as y. There are 24 control signals K, +/- K28.0 to K28.7, K23.7, K27.7, K29.7, and K30.7.

As shown in FIG. 7, in the case of the control signal K, all converted output data has a bit inversion relationship according to the RD polarity. Therefore, an algorithm similar to the algorithm in the case of pattern 1 of the 5b / 6b conversion circuit 112 can be used.
For this reason, the control signal conversion circuit 114 performs only one polarity conversion according to the input data, and the other polarity is obtained by the inverter.
Then, data having a polarity corresponding to the RD polarity of the next output data indicated by nextRD input from the RD control circuit 115 described above is output as output data.

[Encoding algorithm of 8b / 10b encoder 11]
Hereinafter, an example of a specific process of the encoding algorithm of the 8b / 10b encoder 11 will be described.
FIG. 8 is a flowchart of the encoding algorithm of the 8b / 10b encoder 11.

Step ST1:
It is determined whether the input data is a D code or a K code (control signal K).
If the input data is a D code, the process proceeds to step ST2, and if the input data is a K code, the process proceeds to step ST5.
Step ST2:
The dividing circuit 111 divides the input 8-bit data of the D code into a 5-bit data block and a 3-bit data block.
If the block is a 5-bit data block, the process proceeds to step ST3. If the block is a 3-bit data block, the process proceeds to step ST4.

Step ST3:
The divided 5-bit data block proceeds to a 5-bit data conversion process shown in FIG.
Step ST4:
The divided 3-bit data block proceeds to a 3-bit data conversion process shown in FIG.
Step ST5:
The data block of the K code (control signal K) proceeds to a K code conversion process shown in FIG.

[Flowchart of 5-bit data conversion processing]
FIG. 9 is a flowchart illustrating an example of a 5-bit data conversion process by the 5b / 6b conversion circuit 112.
Step ST11:
The 5b / 6b conversion circuit 112 refers to the above-described 5b / 6b conversion table and determines whether the input 5-bit data corresponds to the pattern 1 or the pattern 2. .
As described above, pattern 1 is a table when the output data after conversion has a bit inversion relationship according to the RD polarity, and pattern 2 is the output data after conversion regardless of the RD polarity. This is a table when the output data is the same.
If it is determined that the 5b / 6b conversion circuit 112 is the pattern 1, the process proceeds to step ST12. If it is determined that the pattern 2 is the pattern 2, the process proceeds to step ST13.

Step ST12:
The 5b / 6b conversion circuit 112 refers to the 5b / 6b conversion table of pattern 1 and converts any polarity (+ or-) based on the input 5-bit data block.
Step ST13:
The 5b / 6b conversion circuit 112 generates a 6-bit data block of the other polarity by an inverter based on the converted 6-bit data block of any polarity generated in step ST12.
Step ST14:
The 5b / 6b conversion circuit 112 determines data having polarity according to the RD polarity of the next output data indicated by nextRD input from the RD control circuit 115 as output data.

Step ST15:
The 5b / 6b conversion circuit 112 refers to the 5b / 6b conversion table of pattern 2 and determines whether or not the input 5-bit data block is data corresponding to exception processing.
If it does not correspond to the exception process, the process proceeds to step ST16, and if it corresponds to the exception process (D07.x in the example shown in FIG. 5B), the process proceeds to step ST19.
Step ST16:
The 5b / 6b conversion circuit 112 generates a data block 'abcde' in which each value is the same value as the input data block 'EDCBA'.

Step ST17:
The 5b / 6b conversion circuit 112 calculates the extension bit “i” using the fact that the number of “0” and “1” in the output data block must be the same in the pattern 2 table.
Step ST18:
The 5b / 6b conversion circuit 112 generates an output data block 'abcdei' based on the data block 'abcde' generated in step ST16 and the data block 'i' generated in step ST17.

Step ST19:
The 5b / 6b conversion circuit 112 refers to the 5b / 6b conversion table of pattern 2 and performs exception processing.
Step ST20:
The 5b / 6b conversion circuit 112 outputs the generated output data block.

[Flowchart of 3-bit data conversion processing]
FIG. 10 is a flowchart illustrating an example of 3-bit data conversion processing by the 3b / 4b conversion circuit 113.
Step ST21:
The 3b / 4b conversion circuit 113 determines whether the input 3-bit data corresponds to the pattern 1 or the pattern 2 with reference to the above-described 3b / 4b conversion table. .
As described above, pattern 1 is a table when the output data after conversion has a bit inversion relationship according to the RD polarity, and pattern 2 is the output data after conversion regardless of the RD polarity. This is a table when the output data is the same.
If the 3b / 4b conversion circuit 113 determines that it is the pattern 1, the process proceeds to step ST22. If it is determined that the pattern 2 is the pattern 2, the process proceeds to step ST25.

Step ST22:
The 3b / 4b conversion circuit 113 refers to the 3b / 4b conversion table of pattern 1 and converts any polarity (+ or-) based on the input 3-bit data block.
Step ST23:
The 3b / 4b conversion circuit 113 generates a 4-bit data block of the other polarity by an inverter based on the 4-bit data block after conversion of any polarity generated in step ST22.
Step ST24:
The 3b / 4b conversion circuit 113 determines data having polarity according to the RD polarity of the next output data indicated by nextRD input from the RD control circuit 115 as output data.

Step ST25:
The 3b / 4b conversion circuit 113 refers to the 3b / 4b conversion table of pattern 2 and determines whether or not the input 3-bit data block is data corresponding to exception processing.
If it does not correspond to the exception process, the process proceeds to step ST26, and if it corresponds to the exception process (Dx.P7, Dx.A7 in the example shown in FIG. 6B), the process proceeds to step ST29.
Step ST26:
The 3b / 4b conversion circuit 113 generates a data block 'fgh' in which each value is the same value as the input data block 'HGF'.

Step ST27:
The 3b / 4b conversion circuit 113 calculates the extension bit “j” using the fact that the number of “0” and “1” in the output data block must be the same in the pattern 2 table.
Step ST28:
The 3b / 4b conversion circuit 113 generates an output data block 'fghj' based on the data block 'fgh' generated in step ST26 and the data block 'j' generated in step ST27.

Step ST29:
The 3b / 4b conversion circuit 113 refers to the 3b / 4b conversion table of pattern 2 and performs exception processing.
Step ST30:
The 3b / 4b conversion circuit 113 outputs the generated output data block.

[Flowchart of K code conversion process]
FIG. 11 is a flowchart showing an example of the K code conversion process by the control signal conversion circuit 114.
Step ST51:
The control signal conversion circuit 114 performs conversion of any polarity (+ or −) with reference to the above-described K code conversion table based on the input data block.
Step ST52:
The control signal conversion circuit 114 generates a data block of the other polarity by an inverter based on the data block after conversion of any polarity generated in step ST51.
Step ST53:
The control signal conversion circuit 114 determines data having polarity according to the RD polarity of the next output data indicated by nextRD input from the RD control circuit 115 as output data.
Step ST54:
The control signal conversion circuit 114 outputs the generated output data.

As described above, according to the 8b / 10b encoder 11 of this embodiment, when 8-bit input data is a D code, it is divided into 5-bit data and 3-bit data, and the table is referred to. Perform the following processing.
That is, in the case of 5-bit data and 3-bit data, the number of “0” values and “1” values in the output data after conversion with respect to the input data are different, or the value of “0” in the output data. And whether the number of values of “1” is the same.

When the number of “0” values and “1” values in the output data after conversion with respect to the input data are different, the 5b / 6b conversion circuit 112 causes the 5b / 6b conversion circuit 112 to convert either polarity. The other polarity is obtained by an inverter.
Then, the 5b / 6b conversion circuit 112 outputs, as output data, data having a polarity corresponding to the RD polarity of the next output data indicated by nextRD input from the RD control circuit 115 described above.
When the number of values of “0” and “1” in the output data is the same, the 5b / 6b conversion circuit 112 gives the same value as each value of the input data to each value of the output data after conversion. Then, using the fact that the numbers of “0” and “1” are the same, the value of the extension bit is calculated.
In the case of 3-bit data, the 3b / 4b conversion circuit 113 performs the same processing.

  In the case of the K code (control signal K), the control signal conversion circuit 114 refers to the K code conversion table based on the input data block and converts any polarity (+ or-). I do. Then, the control signal conversion circuit 114 generates a data block of the other polarity by the inverter based on the generated data block after the conversion of one polarity. The control signal conversion circuit 114 determines data having polarity according to the RD polarity of the next output data indicated by nextRD input from the RD control circuit 115 as output data.

According to the 8b / 10b encoder 11 of the present embodiment, as described above, the 8b / 10b conversion is performed depending on whether the number of “0” and “1” included in the converted data matches. The encoding table pattern used for the is divided. When the input data is a D code indicating data, if the number of '0' and '1' is the same, the calculation is made using the same number of input data, otherwise In this method, the conversion process is compressed by converting one polarity according to the encoding table and then converting the other polarity by an inverter.
As described above, the conversion table referred to in the present invention finds the regularity of the 8b / 10b conversion table, and can use the regularity to perform the same conversion with a smaller conversion table. It is configured as follows.
Therefore, in the present invention, when the compressed encoding table is mounted on the hardware, the table is compressed and the combination pattern and the number of operations are reduced, so that the gate scale can be reduced.
Further, since the combination pattern is reduced, the operation speed is increased and the timing control is facilitated. For this reason, the number of flip-flop circuits for timing adjustment can be reduced, so that the power consumption of the entire circuit can be reduced.
Furthermore, in the conversion table used in the 8b / 10b encoder 11, overlapping logic circuits can be reduced, so that the number of logic stages and delay of the entire encoder can be reduced.
Furthermore, the amount of code can be significantly reduced due to software implementation of the 8b / 10b encoder 11.

In addition, this invention is not limited to embodiment mentioned above.
That is, when implementing the present invention, various modifications, combinations, sub-combinations, and alternatives may be made to the components of the above-described embodiments within the technical scope of the present invention or an equivalent scope thereof.
In the above-described embodiment, the 8b / 10b encoder that performs the 8b / 10b conversion and the 5b / 6b conversion table and the 3b / 4b conversion table used in the 8b / 10b encoder have been described. However, the present invention is not limited to this. .
That is, for example, even in a conversion circuit that converts m-bit input data to n-bit output data (m, n is a positive integer, n> m), the input data is divided into upper bits and lower bits, and each is output. Cases are divided according to the number of data “0” and “1” values. In this way, even when m-bit input data is converted to n-bit output data, the same effects as those of the present invention described above can be obtained.

  DESCRIPTION OF SYMBOLS 10 ... Transmission circuit, 100 ... Serial communication unit, 101 ... Transmission circuit interface, 11 ... 8b / 10b encoder, 111 ... Dividing circuit, 112 ... 5b / 6b conversion circuit, 113 ... 3b / 4b conversion circuit, 114 ... Control signal conversion 115, RD control circuit, 116, synthesis circuit, 117, selector FF, 118, data input terminal, 119, control signal input terminal, 120, clock signal input terminal, 121, data output terminal, 12 ... parallel / serial Converter 20: Receiving circuit 201 ... Receiving circuit interface 21 ... Serial / parallel converter 22 ... 10b / 8b decoder 30 ... Serial transmission line 200 ... Serial communication system

Claims (17)

A bit conversion circuit that converts m-bit input data with reference to a bit conversion table to generate n-bit output data (m and n are positive integers and n> m),
A first conversion table obtained by extracting, from the bit conversion table, symbols whose output data is different from the number of 0 values and the number of 1 values when converting input data into D code output data indicating data; A bit conversion circuit that performs the bit conversion with reference to a second conversion table in which symbols having the same number of 0 values and 1 values are extracted from the bit conversion table. The bit conversion circuit according to claim 1, wherein m = 8 and n = 10. A dividing circuit for dividing 8-bit input data into 5-bit data and 3-bit data;
A 5b / 6b conversion circuit that converts the 5-bit data divided by the dividing circuit into 6-bit data by 5b / 6b conversion and outputs the data;
A 3b / 4b conversion circuit that converts the 3-bit data divided by the division circuit into 4-bit data by 3b / 4b conversion and outputs the data;
An RD control circuit that determines the RD polarity of the next output data based on the running disparity (RD) polarity of the current output data;
A synthesis circuit that synthesizes 6-bit data converted by the 5b / 6b conversion circuit and 4-bit data converted by the 3b / 4b conversion circuit to generate 10-bit output data;
The bit conversion circuit according to claim 2, comprising: The bit conversion circuit according to claim 3, further comprising: a control signal conversion circuit that converts an input K code control signal into 10-bit data by 8b / 10b conversion and outputs the data. The 5b / 6b conversion circuit includes a third conversion table in which output data corresponding to input data is output data in which the number of 0 values is different from the number of 1 values, and the output data is the number of 0 values and the number of 1 values. A fourth conversion table in which the output data are equal to each other, and
When conversion is performed with reference to the third conversion table, the output data having the polarity of one of the RDs is converted based on the input data, and then converted by the inverter based on the converted output data. Generating output data of the other RD polarity, and determining the polarity of the output data to be output according to the polarity of the next output data notified by the RD control circuit;
When conversion is performed with reference to the fourth conversion table, the number of 0 values and the number of 1 values in the input data are set so that the number of 0 values and the number of 1 values in the output data are the same. 4. The bit conversion circuit according to claim 3, wherein 1-bit extension bit is generated based on the generated data, and output data is generated by synthesizing with the same value as each value of input data. The 5b / 6b conversion circuit excludes input data and extension bits even when the conversion is performed with reference to the fourth conversion table, even though the number of 0 values and the number of 1 values in the output data are equal. When the output data values are different, as an exception processing, after converting the output data of one of the RD polarities based on the input data, the inverter outputs the other RD based on the converted output data. The bit conversion circuit according to claim 5, wherein output data having a polarity is generated, and a polarity of output data to be output is determined according to a polarity of next output data notified by the RD control circuit. The 3b / 4b conversion circuit includes a fifth conversion table in which output data corresponding to input data is output data in which the number of 0 values is different from the number of 1 values, and the output data is the number of 0 values and the number of 1 values. A sixth conversion table in which the output data are equal to each other, and
When conversion is performed with reference to the fifth conversion table, after conversion of output data having one of the RD polarities based on input data, an inverter is used based on the converted output data. Generating output data of the other RD polarity, and determining the polarity of the output data to be output according to the polarity of the next output data notified by the RD control circuit;
When conversion is performed with reference to the sixth conversion table, the number of 0 values and the number of 1 values in the input data are set so that the number of 0 values and the number of 1 values in the output data are the same. 4. The bit conversion circuit according to claim 3, wherein 1-bit extension bit is generated based on the generated data, and output data is generated by synthesizing with the same value as each value of input data. When the 3b / 4b conversion circuit performs conversion with reference to the sixth conversion table, the 3b / 4b conversion circuit excludes input data and extension bits even though the number of 0 values and the number of 1 values of output data are equal. When the output data values are different, as an exception processing, after converting the output data of one of the RD polarities based on the input data, the inverter outputs the other RD based on the converted output data. The bit conversion circuit according to claim 7, wherein the output data of polarity is generated, and the polarity of output data to be output is determined according to the polarity of the next output data notified by the RD control circuit. A bit encoding circuit that converts m-bit input data to generate n-bit output data, and a second bit decoding circuit that converts n-bit input data to generate m-bit output data (M and n are positive integers and n> m),
When the bit encoding circuit converts input data into D-code output data indicating data, the bit conversion table extracts symbols having different numbers of 0 values and 1 values of output data for the input data. The bit conversion is performed with reference to the first conversion table and the second conversion table in which the output data is extracted from the bit conversion table, the symbol having the same number of 0 values and 1 values. unit. A bit encoding circuit that converts m-bit input data to generate n-bit output data, and a second bit decoding circuit that converts n-bit input data to generate m-bit output data A communication system having a plurality of transfer units including (m and n are positive integers and n> m),
When the bit encoding circuit converts input data into D-code output data indicating data, the bit conversion table extracts symbols having different numbers of 0 values and 1 values of output data for the input data. The bit conversion is performed with reference to the first conversion table and the second conversion table from which the output data is extracted from the bit conversion table, the output data having the same number of 0 values and 1 value. system. A bit conversion method of a bit conversion circuit for generating m-bit output data by bit-converting m-bit input data (m and n are positive integers and n> m),
A first conversion table obtained by extracting, from the bit conversion table, symbols whose output data is different from the number of 0 values and the number of 1 values when converting input data into D code output data indicating data; A bit conversion method for performing the bit conversion by referring to a second conversion table in which symbols having the same number of 0 values and 1 values are extracted from the bit conversion table. A program executed by a computer having a bit conversion circuit for converting m-bit input data to generate n-bit output data (m and n are positive integers and n> m),
A first conversion table obtained by extracting, from the bit conversion table, symbols whose output data is different from the number of 0 values and the number of 1 values when converting input data into D code output data indicating data; A program for causing the computer to execute a procedure for performing the bit conversion with reference to a second conversion table in which the output data is extracted from the bit conversion table as a symbol having the same number of zero values and zero values. . A bit conversion method of an 8b / 10b conversion circuit having a dividing circuit, a 5b / 6b conversion circuit, a 3b / 4b conversion circuit, an RD control circuit, and a synthesis circuit,
A first step in which the dividing circuit divides 8-bit input data into 5-bit data and 3-bit data;
A second step in which the 5b / 6b conversion circuit converts the 5-bit data divided in the first step into 6-bit data by 5b / 6b conversion and outputs the data;
A third step in which the 3b / 4b conversion circuit converts the 3-bit data divided in the first step into 4-bit data by 3b / 4b conversion and outputs the data;
A fourth step in which the RD control circuit determines the polarity of the running disparity (RD) of the next output data based on the polarity of the RD of the current output data;
The synthesis circuit synthesizes the 6-bit data converted in the second step and the 4-bit data converted in the third step to generate 10-bit output data. And the process of
Have
The second step includes
In the 5b / 6b conversion circuit, the output data corresponding to the input data is output data in which the number of 0 values is different from the number of 1 values, or the output data is output data in which the number of 0 values is equal to the number of 1 values. A sixth step of determining whether there is,
In the sixth step, when it is determined that the number of 0 values is different from the number of 1 values, the 5b / 6b conversion circuit outputs the output data having different numbers of 0 values and 1 values. A seventh step of referring to the first conversion table corresponding to the case where the output data of one of the RDs is converted based on the input data;
An eighth step of generating output data of the polarity of the other RD by the inverter based on the output data converted in the seventh step;
A ninth step of determining the polarity of output data to be output according to the polarity of the next output data determined in the fourth step;
In the sixth step, when it is determined that the number of 0 values is equal to the number of 1 values, the second value corresponds to the case where the number of 0 values is equal to the number of 1 values. Referring to the conversion table, a 1-bit extension bit is generated based on the number of zero values and one value of the input data so that the number of zero values and one value of the output data are the same. A tenth step of:
An eleventh step of generating output data by combining the extension bits generated in the tenth step with data having the same value as each value of input data;
Have
The third step includes
In the 3b / 4b conversion circuit, the output data corresponding to the input data is output data in which the number of 0 values is different from the number of 1 values, or the output data is output data in which the number of 0 values is equal to the number of 1 values. A twelfth step of determining whether there is,
In the twelfth step, when it is determined that the number of zero values is different from the number of one values, the 3b / 4b conversion circuit outputs the output data having different numbers of zero values and one values. A thirteenth step of referring to the third conversion table corresponding to the case where the output data of one of the RDs is converted based on the input data;
A fourteenth step of generating output data having the polarity of the other RD by an inverter based on the output data converted in the twelfth step;
A fifteenth step of determining the polarity of output data to be output according to the polarity of the next output data determined in the fourth step;
In the twelfth step, when it is determined that the number of 0 values is equal to the number of 1 values, the fourth value corresponds to the case where the number of 0 values is equal to the number of 1 values. Referring to the conversion table, a 1-bit extension bit is generated based on the number of zero values and one value of the input data so that the number of zero values and one value of the output data are the same. A sixteenth step of
A seventeenth step of generating output data by combining the extension bits generated in the sixteenth step with data having the same value as each value of input data;
A bit conversion method comprising: The bit conversion method according to claim 13, wherein the first conversion table is a conversion table shown in Table 1.

input: Input data
Data byte name: Data byte name
Bits: Input bits
output: Output data
RD =-: The polarity of running disparity is-
RD = +: The polarity of running disparity is + The bit conversion method according to claim 13, wherein the second conversion table is a conversion table shown in Table 2.

input: Input data
Data byte name: Data byte name
Bits: Input bits
output: Output data
RD =-: The polarity of running disparity is-
RD = +: The polarity of running disparity is + The bit conversion method according to claim 13, wherein the third conversion table is a conversion table shown in Table 3.

input: Input data
Data byte name: Data byte name
Bits: Input bits
output: Output data
RD =-: The polarity of running disparity is-
RD = +: The polarity of running disparity is + The bit conversion method according to claim 13, wherein the fourth conversion table is a conversion table shown in Table 4.

input: Input data
Data byte name: Data byte name
Bits: Input bits
output: Output data
RD =-: The polarity of running disparity is-
RD = +: The polarity of running disparity is +

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