US20060139189A1 - Gray code conversion method and apparatus embodying the same - Google Patents
Gray code conversion method and apparatus embodying the same Download PDFInfo
- Publication number
- US20060139189A1 US20060139189A1 US11/020,997 US2099704A US2006139189A1 US 20060139189 A1 US20060139189 A1 US 20060139189A1 US 2099704 A US2099704 A US 2099704A US 2006139189 A1 US2006139189 A1 US 2006139189A1
- Authority
- US
- United States
- Prior art keywords
- binary
- sequence
- decimal
- gray code
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/14—Conversion to or from non-weighted codes
- H03M7/16—Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/02—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
- H03M7/12—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word having two radices, e.g. binary-coded-decimal code
Definitions
- the present invention relates generally to method and system of communicating signals. More particularly, the present invention relates to method and system of communicating signal from one circuit domain to another clock domain using Gray code encoding.
- Electrical signals representing useful information are often communication from one circuit domain to another circuit domain.
- a set of electrical signals representing an address within a storage device is transmitted from a first circuit domain to a second circuit domain.
- each electrical signal is referred to as a bit, and a set of bits is also referred to as a “data word” or “word.”
- the data word can be “wide.” That is, the data word is a set of many bits, or electrical signals.
- a data word having eight bits (eight bits wide) can be used, for example, to address up to 256 unique locations within a storage medium.
- an incrementing sequence of data words is communication from the first circuit domain to the second circuit domain in quick succession, often thousands or millions of words per second.
- the data words are typically encoded in typical decimal based binary data format.
- each data word in decimal binary format
- Gray code binary format is converted to Gray code format before it is transmitted from the first circuit domain.
- the received data word in Gray code binary format
- decimal base binary data format For convenience, a data word in decimal base binary data format is refereed to as a “binary word,” and data word in Gray code binary format is refereed to as a “Gray code word.” Further, a sequence of binary 1 of 21 words is referred to as “decimal-binary sequence” and a sequence of Gray code words is referred to as “Gray code sequence.”
- a decimal-binary sequence has a finite number B of binary words (set of signals). Number B is also referred to as the number of “states” of the decimal-binary sequence. A corresponding Gray code sequence has the same number of states.
- the value of B (the number of states of the decimal-binary sequence) is 2 N .
- TABLE 1 lists a complete decimal-binary sequence of data words having 4 bits of width. That is, for the sample decimal-binary sequence, N is 4, and, thus, B is 2 4 which is 16.
- the sample decimal-binary sequence has 16 states as indicated by State Index 0 to 15.
- the sample decimal-binary sequence of TABLE 1 the corresponding Gray code sequence has a useful property that makes the Gray code value in many applications.
- the useful property is that, in the Gray code sequence, any two successive values differ in only one digit. This property is used in many communication applications to increase examine reliability of transmitted data.
- a conversion look-up table is used to convert each binary word of the decimal-binary sequence to its corresponding Gray code word.
- the conversion look-up table is manually populated. That is, the conversion look-up table is created having an entry for each possible binary word and its corresponding Gray code word. Each entry of the conversion look-up table is manually coded and entered.
- this approach is difficult to perform, time consuming, requires high labor costs, and is error prone.
- a known conversion algorithm is used to convert each binary word (in binary data format) to its corresponding binary word in Gray code format. Typically the conversion is performed on the fly; however, the conversion can be performed to populate a conversion look-up table.
- Several techniques for converting a decimal-binary sequence to Gray code sequence are known in the art. Once known technique for converting a decimal-binary sequence to Gray code sequence using software is reproduced below as a computer program.
- the known conversion techniques are applicable only for decimal-binary sequence s having the number of states N is a power of two. That is, the known conversion techniques are applicable only for a decimal-binary sequence with N states where N is equal to 2 n where n is an integer. For example, N can be 2, 4, 8, 16, 32, etc. Further, the known conversion techniques also require that each successive binary word of the decimal-binary sequence be either incrementing or decrementing by one (1) from the previous binary word within the decimal-binary sequence. That is, the binary word at position i within the sequence is either greater than or less than the binary word at position i-1 by only one.
- a generalized Gray code converter includes a decimal-binary to intermediate-binary converter and an intermediate-binary to Gray code converter.
- the decimal-binary to intermediate-binary converter is operable to convert a sequence of sets of electrical signals encoded in decimal-binary format (decimal-binary sequence) to a sequence of sets of electrical signals encoded in intermediate-binary format (intermediate sequence).
- the intermediate-binary to Gray code converter connected to the decimal-binary to intermediate-binary converter, is operable to convert the intermediate sequence to a sequence of sets of electrical signals encoded in Gray code-binary format (Gray code sequence).
- a generalized Gray code de-converter in a second embodiment of the present invention, includes a Gray code to intermediate-binary converter and an intermediate-binary to decimal-binary converter.
- the Gray code to intermediate-binary converter is operable to convert a sequence of sets of electrical signals encoded in Gray code binary format (Gray code sequence) to a sequence of sets of electrical signals encoded in intermediate-binary format (intermediate sequence).
- the intermediate-binary to decimal-binary converter connected to the Gray code to intermediate-binary converter, is operable to convert the intermediate sequence to a sequence of sets of electrical signals encoded in decimal-binary format (decimal-binary sequence).
- a communication system including a first circuit domain.
- the first circuit domain includes a generalized Gray code converter including a decimal-binary to intermediate-binary converter and an intermediate-binary to Gray code converter.
- the decimal-binary to intermediate-binary converter is operable to convert a sequence of sets of electrical signals encoded in decimal-binary format (decimal-binary sequence) to a sequence of sets of electrical signals encoded in intermediate-binary format (intermediate sequence).
- the intermediate-binary to Gray code converter connected to the decimal-binary to intermediate-binary converter, is operable to convert the intermediate sequence to a sequence of sets of electrical signals encoded in Gray code-binary format (Gray code sequence).
- a method for communicating signals is disclosed. First, a sequence of sets of signals encoded in decimal-binary format (decimal-binary sequence) is converted into a sequence of sets of signals encoded in intermediate-binary format (intermediate sequence). Next, the intermediate sequence is converted into a sequence of sets of electrical signals encoded in Gray code-binary format (Gray code sequence). Then, the Gray code sequence is transmitted.
- FIG. 1 illustrates a communication system according to one embodiment of the present invention
- FIG. 2 is a flow chart illustrating one aspect of the present invention
- FIGS. 3A, 3B , and 4 illustrate various sequences of signals useful for discussing various aspects of the present invention
- FIG. 5 is a flow chart illustrating another aspect of the present invention.
- FIGS. 6 and 7 are more detailed illustrations of portions of the communication system of FIG. 1 .
- references to a structure or a portion being formed on or above another structure or portion without an intervening structure or portion are described herein as being formed “directly on” or “directly above” the other structure or the other portion. Same reference number refers to the same elements throughout this document.
- a generalized Gray code converter includes a decimal-binary to intermediate-binary converter and an intermediate-binary to Gray code converter.
- the decimal-binary to intermediate-binary converter is operable to convert a sequence of sets of electrical signals encoded in decimal-binary format (decimal-binary sequence) to a sequence of sets of electrical signals encoded in intermediate-binary format (intermediate sequence).
- the intermediate-binary to Gray code converter connected to the decimal-binary to intermediate-binary converter, is operable to convert the intermediate sequence to a sequence of sets of electrical signals encoded in Gray code-binary format (Gray code sequence).
- the decimal-binary sequence is converted to the intermediate sequence which is then converted to the Gray code sequence.
- the decimal-binary sequence having any number of states can be converted to a corresponding Gray code sequence. This overcomes the limitation of the prior art techniques and systems discussed above.
- FIG. 1 illustrates a communication system 100 having a first circuit domain 110 and a second circuit domain 150 .
- the first circuit domain 110 and the second circuit domain 150 communicates via a communications means 102 such as a communications bus or via wireless signals.
- a circuit domain is a group of circuits operating together to perform a function.
- the first circuit domain 110 includes circuits operable to transmit a sequence of sets of electrical signals while the second circuit domain 150 includes circuits operable to receive the transmitted signals.
- Often circuits of a circuit domain operate from a common synchronization clock; however, this is not a necessary aspect of the present invention.
- the first circuit domain 110 includes, for example, a register 112 operable to provide a pointer to a sequence of sets of electrical signals encoded in decimal-binary format (decimal-binary sequence).
- the register 112 provides the decimal-binary sequence.
- the first circuit domain 110 includes a generalized Gray code converter 120 .
- the generalized Gray code converter 120 includes a decimal-binary to intermediate-binary converter 130 and an intermediate-binary to Gray code converter 140 .
- the intermediate-binary converter 130 is operable to convert a sequence of sets of electrical signals encoded in decimal-binary format (decimal-binary sequence) to a sequence of sets of electrical signals encoded in intermediate-binary format (intermediate sequence).
- each electrical signal is referred to as a bit.
- a set of bits is also referred to as a “data word” or “word” as well as a set.
- a set of eight bits is often referred to as a byte.
- the intermediate-binary to Gray code converter 140 is connected to the decimal-binary to intermediate-binary converter 130 .
- the intermediate-binary to Gray code converter 140 is operable to convert the intermediate sequence to a sequence of sets of electrical signals encoded in Gray code-binary format (Gray code sequence).
- the Gray code sequence is transmitted from the first circuit domain 110 to the second circuit domain 150 .
- the second circuit domain 150 includes a generalized Gray code de-converter 160 .
- the generalized Gray code de-converter 160 includes a Gray code to intermediate-binary converter 170 and an intermediate-binary to decimal-binary converter 180 .
- the Gray code to intermediate-binary converter 170 is operable to convert the Gray code sequence to the intermediate sequence.
- the intermediate-binary to decimal-binary converter 180 is operable to convert the intermediate sequence to the decimal-binary sequence.
- the decimal-binary sequence is passed onto other components of the second circuit domain 150 such as a register 152 for further processing.
- the generalized Gray code converter 120 is operable to convert a decimal-binary sequence having any number of states.
- TABLE 2 below lists words of a sample decimal-binary sequence having five states (indexed as states 0 through 4) where each word (set of signals) is expressible using three bits (signal lines). That is, for the sample decimal-binary sequence, the number of states, B, is 5 and word width n is 3. Because 5 is not an even number and is not a number that is a power of 2, a prior art Gray code converter cannot be used to convert the sample decimal-binary sequence to Gray code. Often, such sample decimal-binary sequence is repeatedly sent from a first circuit domain to the second circuit domain. TABLE 2 Sample Decimal-Binary State Index sequence 0 000 1 001 2 010 3 011 4 100
- decimal-binary sequence is converted to a sequence of sets of signals encoded in intermediate-binary format (intermediate sequence).
- intermediate sequence is converted to a sequence of sets of electrical signals encoded in Gray code-binary format (Gray code sequence).
- Gray code sequence is transmitted.
- FIG. 3A illustrates various sequences applicable for conversion of the decimal-binary sequence to the intermediate sequence.
- the sample decimal-binary sequence is illustrated as column 310 . This is same as the sample decimal-binary sequence of TABLE 2 above.
- the decimal-binary sequence 310 has five states (states 0 through 4) as indicated by reference numeral 312 .
- Each state of the decimal-binary sequence 310 is represented by a data word (a set of binary signals) having 3 bits as indicated by reference numeral 314 .
- the states of the decimal-binary sequence 310 are also referred to as sets of signals where B represents the number of sets, or states, which, in the present example, is 5.
- Each state, or set, in the present example has n bits, which, in the present example, is 3.
- the decimal-binary sequence 310 is repeatedly communicated from the first circuit domain 110 to the second circuit domain 150 .
- the repetition is indicated by repeated status indexes 313 and 314 , and by an ellipse 315 .
- repeated status indexes 313 and 314 and by an ellipse 315 .
- ellipse 315 only one sequence cycle of the decimal-binary sequence 310 and other sequences are illustrated in the Figures.
- the decimal-binary to intermediate-binary converter 130 doubles the number of states of the decimal-binary sequence 310 resulting in a doubled decimal-binary sequence illustrated as column 320 .
- the number of states of the decimal-binary sequence 310 is doubled by the following steps: first, adding, to each data word of the decimal-binary sequence 310 , another bit (a most significant bit 322 ); then repeating the 3-bit data words of the decimal-binary sequence 310 once for the top half 326 of the doubled decimal-binary sequence 320 with the most significant bit 322 set at 0, then once for the bottom half 328 of the doubled decimal-binary sequence 320 (with the most significant bit 322 set at 1.
- the resulting doubled decimal-binary sequence 320 is a sequence of 4-bit words (indicated by reference number 329 ) and has twice the number of states as the decimal-binary sequence 310 .
- the doubled decimal-binary sequence 320 includes a sequence of data words (set of signals), each word having width of N bits where N is n+1 where n is the number of bits of the words (set of signals) of the decimal-binary sequence 310 .
- the doubled decimal-binary sequence 320 is mapped to a complete-decimal-binary sequence having base N (in the present example, base 4 ).
- the complete-decimal-binary sequence for 4-bit words is listed in TABLE 1 above and also illustrated as column 330 of FIG. 3A .
- the complete-decimal-binary sequence 330 has 16 (or 2 4 ) states (0 through 15).
- the top half 326 of the doubled decimal-binary sequence 320 is mapped to top (first) entries 336 of the complete-decimal-binary sequence 330 as illustrated.
- the bottom half 328 of the doubled decimal-binary sequence 320 is mapped to bottom entries 338 of the complete-decimal-binary sequence 330 as illustrated, resulting in the intermediate sequence illustrated as column 340 .
- the shift constant R 333 has value three (3).
- FIG. 3B An alternative but an equivalent illustration of the mapping technique is illustrated in FIG. 3B .
- the top half 326 of the doubled decimal-binary sequence 320 is identical to top (first) entries 336 of the complete-decimal-binary sequence 330 , no operation is actually performed to accomplish this mapping. That is, for the top half 326 of the doubled decimal-binary sequence 320 , no operation is required to form the intermediate sequence 340 .
- the intermediate sequence 340 is formed by combining the top half 326 of the doubled decimal-binary sequence 320 and the bottom half 328 of the doubled decimal-binary sequence 320 shifted by the shift constant R 333 .
- the shifting can be accomplished by merely adding, in decimal, the value of R (in the present example, R is 3) to each word of the bottom half 328 of the doubled decimal-binary sequence 320 .
- the adding technique is illustrated by the adder 329 .
- This Gray code binary sequence (corresponding to the intermediate sequence 340 ) is illustrated using reference numeral 350 .
- FIG. 4 illustrates the complete-decimal-binary sequence 330 for 4-bit words and the corresponding Gray code sequence 360 listed already as TABLE 1 above.
- the complete-decimal-binary sequence 330 is also illustrated in FIG. 3A as column 330 .
- the Gray code sequence 340 for the intermediate sequence 330 is also a subset of the Gray code sequence 360 for the complete-decimal-binary sequence 330 .
- the Gray code sequence 340 for the intermediate sequence 330 is made up of segments 366 and 368 of the Gray code sequence 360 for the complete-decimal-binary sequence 330 .
- the resulting Gray code sequence 330 still retains the useful property in that any two successive values differ in only one digit. This is because the Gray code sequence 360 (from which the Gray code sequence 330 is derived from) is reflective about its center line 362 (except for its most significant bit 364 ). This is illustrated in FIG. 4 . For the Gray code sequence 360 , not considering its most significant bit 364 , the second half 363 of the Gray codes are identical to but in a reverse order from the first half 361 of the Gray codes. The Gray code sequence 360 is reflective about its center line 362 . This reflective property is known in the art.
- the Gray code sequence 350 is communicated from the first circuit domain 110 (of FIG. 1 ) to the second circuit domain 150 (of FIG. 1 ) where the generalized Gray code de-converter 160 converts the incoming Gray code sequence 350 to the decimal-binary sequence 310 by reversing the operations of the generalized Gray code converter 120 .
- the Gray code sequence 350 is received by the generalized Gray code de-converter 160 .
- Step 402 the Gray code sequence 350 is converted to the intermediate sequence 340 .
- Step 404 the intermediate sequence 340 is converted to the decimal-binary sequence 310 .
- Step 406 the steps outlined in the flowchart 200 of FIG. 2 is performed in a reverse order.
- FIG. 3B illustrates various sequences applicable for conversion of the Gray code sequence 350 to the intermediate sequence 340 then to the decimal-binary sequence 310 .
- the received Gray code sequence 350 is converted to the intermediate sequence 340 using a known Gray code de-conversion technique.
- the intermediate sequence 340 is used to form the doubled decimal-binary sequence 320 by reversing the operation (described above) to form the intermediate sequence 340 from the doubled decimal-binary sequence 320 . That is, the top half 346 of the intermediate sequence 340 forms the top half 326 of the doubled decimal-binary sequence 320 , and a shifted bottom half 348 of the intermediate sequence 340 forms the bottom half 328 of the doubled decimal-binary sequence 320 .
- the shifting is performed by subtracting the shift constant R from the words of the bottom half 348 of the intermediate sequence 340 .
- the top half 326 of the doubled decimal-binary sequence 320 is mapped to the entire decimal-binary sequence 310 .
- the bottom half 328 of the doubled decimal-binary sequence 320 is mapped to the entire decimal-binary sequence 310 . This mapping is performed by removing the most significant bit 322 from the words of the doubled decimal-binary sequence 320 .
- FIG. 6 illustrates one embodiment of the decimal-binary to intermediate-binary converter 130 of FIG. 1 in more detail.
- the decimal-binary to intermediate-binary converter 130 takes, as its input, the decimal-binary sequence 310 .
- a most significant bit generator (MSB Gen) 131 examines the input decimal-binary sequence 310 to generate either a “0” or a “1” as the most significant bit 322 to form, combined with the decimal-binary sequence 310 , the doubled decimal-binary sequence 320 .
- MSB Gen most significant bit generator
- the doubled decimal-binary sequence 320 is introduced to an adding circuit 329 and a first input of a multiplexer 133 .
- the adding circuit 329 adds the shift constant R to the doubled decimal-binary sequence 320 and introduces the shifted values to a second input of the multiplexer 133 .
- the multiplexer uses the MSB generated value to select either from the un-shifted sequence of its first input or the shifted sequence of its second input to produce the intermediate sequence 340 .
- the intermediate sequence 340 is used as an input to the intermediate-binary to Gray code converter 140 to generate the Gray code sequence 350 .
- any known Gray code generating hardware or software that produces a reflective Gray code can be used.
- Gray code sequence 350 is converted to the intermediate sequence 340 .
- any known hardware or software technique may be used.
- binary_code[bit] binary_code[bit+1] ⁇ circumflex over ( ) ⁇ gary_code[bit]; ⁇ where
- FIG. 7 illustrates one embodiment of the intermediate-binary to decimal-binary converter 180 of FIG. 1 in more detail.
- the intermediate-binary to decimal-binary converter 180 takes, as its input, the intermediate binary sequence 340 .
- the intermediate-binary sequence 340 is introduced to a subtracting circuit 329 a and a first input of a multiplexer 183 .
- the subtracting circuit 329 a subtracts the shift constant R from the intermediate-binary sequence 340 and introduces the shifted values to a second input of the multiplexer 183 .
- the multiplexer 183 uses the most significant bit (MSB) of the intermediate-binary sequence 340 to select either from the un-shifted sequence of its first input or the shifted sequence of its second input to produce the doubled decimal-binary sequence 320 .
- MSB most significant bit
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Dc Digital Transmission (AREA)
Abstract
Description
- The present invention relates generally to method and system of communicating signals. More particularly, the present invention relates to method and system of communicating signal from one circuit domain to another clock domain using Gray code encoding.
- Electrical signals representing useful information are often communication from one circuit domain to another circuit domain. For example, a set of electrical signals representing an address within a storage device is transmitted from a first circuit domain to a second circuit domain. For convenience, each electrical signal is referred to as a bit, and a set of bits is also referred to as a “data word” or “word.” For some applications, the data word can be “wide.” That is, the data word is a set of many bits, or electrical signals. For example, a data word having eight bits (eight bits wide) can be used, for example, to address up to 256 unique locations within a storage medium.
- In practice, an incrementing sequence of data words is communication from the first circuit domain to the second circuit domain in quick succession, often thousands or millions of words per second. The data words are typically encoded in typical decimal based binary data format.
- To improve reliability and speed of the communication of the data words from the first circuit domain to the second circuit domain, each data word (in decimal binary format) is converted to Gray code format before it is transmitted from the first circuit domain. At the second circuit domain, the received data word (in Gray code binary format) is converted back to decimal binary data format before it is further processed or used. For convenience, a data word in decimal base binary data format is refereed to as a “binary word,” and data word in Gray code binary format is refereed to as a “Gray code word.” Further, a sequence of binary 1 of 21 words is referred to as “decimal-binary sequence” and a sequence of Gray code words is referred to as “Gray code sequence.” A decimal-binary sequence has a finite number B of binary words (set of signals). Number B is also referred to as the number of “states” of the decimal-binary sequence. A corresponding Gray code sequence has the same number of states.
- In complete sequence of a decimal-binary sequence having binary words with width N, the value of B (the number of states of the decimal-binary sequence) is 2N. For example, TABLE 1 below lists a complete decimal-binary sequence of data words having 4 bits of width. That is, for the sample decimal-binary sequence, N is 4, and, thus, B is 24 which is 16. The sample decimal-binary sequence has 16 states as indicated by
State Index 0 to 15.TABLE 1 Corresponding Decimal-Binary Gray code State Index sequence sequence 0 0000 0000 1 0001 0001 2 0010 0011 3 0011 0010 4 0100 0110 5 0101 0111 6 0110 0101 7 0111 0100 8 1000 1100 9 1001 1101 10 1010 1111 11 1011 1110 12 1100 1010 13 1101 1011 14 1110 1001 15 1111 1000 - Note that, the sample decimal-binary sequence of TABLE 1, the corresponding Gray code sequence has a useful property that makes the Gray code value in many applications. The useful property is that, in the Gray code sequence, any two successive values differ in only one digit. This property is used in many communication applications to increase examine reliability of transmitted data.
- There are two basic approaches for converting a decimal-binary sequence to a corresponding Gray code sequence. In the first approach, a conversion look-up table is used to convert each binary word of the decimal-binary sequence to its corresponding Gray code word. To implement this technique, the conversion look-up table is manually populated. That is, the conversion look-up table is created having an entry for each possible binary word and its corresponding Gray code word. Each entry of the conversion look-up table is manually coded and entered. For a large decimal-binary sequence (requiring a table having hundreds, thousands, or even more entries), this approach is difficult to perform, time consuming, requires high labor costs, and is error prone.
- In the second approach, a known conversion algorithm is used to convert each binary word (in binary data format) to its corresponding binary word in Gray code format. Typically the conversion is performed on the fly; however, the conversion can be performed to populate a conversion look-up table. Several techniques for converting a decimal-binary sequence to Gray code sequence are known in the art. Once known technique for converting a decimal-binary sequence to Gray code sequence using software is reproduced below as a computer program.
- The known conversion techniques are applicable only for decimal-binary sequence s having the number of states N is a power of two. That is, the known conversion techniques are applicable only for a decimal-binary sequence with N states where N is equal to 2n where n is an integer. For example, N can be 2, 4, 8, 16, 32, etc. Further, the known conversion techniques also require that each successive binary word of the decimal-binary sequence be either incrementing or decrementing by one (1) from the previous binary word within the decimal-binary sequence. That is, the binary word at position i within the sequence is either greater than or less than the binary word at position i-1 by only one.
- For a decimal-binary sequence having a number of states N that is not a power of two, known algorithms are not applicable, and a conversion look-up table needs to be manually coded. However, as already discussed, manual population of conversion look-up tables are often difficult to perform, time consuming, requires high labor costs, and is error prone.
- Accordingly, there remains a need for improved method and system for converting decimal-binary sequence of signals to Gray code sequence of signals.
- The need is met by the present invention. In a first embodiment of the present invention, a generalized Gray code converter includes a decimal-binary to intermediate-binary converter and an intermediate-binary to Gray code converter. The decimal-binary to intermediate-binary converter is operable to convert a sequence of sets of electrical signals encoded in decimal-binary format (decimal-binary sequence) to a sequence of sets of electrical signals encoded in intermediate-binary format (intermediate sequence). The intermediate-binary to Gray code converter, connected to the decimal-binary to intermediate-binary converter, is operable to convert the intermediate sequence to a sequence of sets of electrical signals encoded in Gray code-binary format (Gray code sequence).
- In a second embodiment of the present invention, a generalized Gray code de-converter includes a Gray code to intermediate-binary converter and an intermediate-binary to decimal-binary converter. The Gray code to intermediate-binary converter is operable to convert a sequence of sets of electrical signals encoded in Gray code binary format (Gray code sequence) to a sequence of sets of electrical signals encoded in intermediate-binary format (intermediate sequence). The intermediate-binary to decimal-binary converter, connected to the Gray code to intermediate-binary converter, is operable to convert the intermediate sequence to a sequence of sets of electrical signals encoded in decimal-binary format (decimal-binary sequence).
- In a third embodiment of the present invention, a communication system including a first circuit domain is disclosed. The first circuit domain includes a generalized Gray code converter including a decimal-binary to intermediate-binary converter and an intermediate-binary to Gray code converter. The decimal-binary to intermediate-binary converter is operable to convert a sequence of sets of electrical signals encoded in decimal-binary format (decimal-binary sequence) to a sequence of sets of electrical signals encoded in intermediate-binary format (intermediate sequence). The intermediate-binary to Gray code converter, connected to the decimal-binary to intermediate-binary converter, is operable to convert the intermediate sequence to a sequence of sets of electrical signals encoded in Gray code-binary format (Gray code sequence).
- In a fourth embodiment of the present invention, a method for communicating signals is disclosed. First, a sequence of sets of signals encoded in decimal-binary format (decimal-binary sequence) is converted into a sequence of sets of signals encoded in intermediate-binary format (intermediate sequence). Next, the intermediate sequence is converted into a sequence of sets of electrical signals encoded in Gray code-binary format (Gray code sequence). Then, the Gray code sequence is transmitted.
- Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
-
FIG. 1 illustrates a communication system according to one embodiment of the present invention; -
FIG. 2 is a flow chart illustrating one aspect of the present invention; -
FIGS. 3A, 3B , and 4 illustrate various sequences of signals useful for discussing various aspects of the present invention; -
FIG. 5 is a flow chart illustrating another aspect of the present invention; and -
FIGS. 6 and 7 are more detailed illustrations of portions of the communication system ofFIG. 1 . - The present invention will now be described with reference to the Figures which illustrate various embodiments of the present invention. In the Figures, some sizes of structures or portions may be exaggerated and not to scale relative to sizes of other structures or portions for illustrative purposes and, thus, are provided to illustrate the general structures of the present invention. Furthermore, various aspects of the present invention are described with reference to a structure or a portion positioned “on” or “above” relative to other structures, portions, or both. Relative terms and phrases such as, for example, “on” or “above” are used herein to describe one structure's or portion's relationship to another structure or portion as illustrated in the Figures. It will be understood that such relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, rotated, or both, the structure or the portion described as “on” or “above” other structures or portions would now be oriented “below,” “under,” “left of,” “right of,” “in front of,” or “behind” the other structures or portions. References to a structure or a portion being formed “on” or “above” another structure or portion contemplate that additional structures or portions may intervene. References to a structure or a portion being formed on or above another structure or portion without an intervening structure or portion are described herein as being formed “directly on” or “directly above” the other structure or the other portion. Same reference number refers to the same elements throughout this document.
- As shown in the Figures for the purposes of illustration, embodiments of the present invention are exemplified by a generalized Gray code converter includes a decimal-binary to intermediate-binary converter and an intermediate-binary to Gray code converter. The decimal-binary to intermediate-binary converter is operable to convert a sequence of sets of electrical signals encoded in decimal-binary format (decimal-binary sequence) to a sequence of sets of electrical signals encoded in intermediate-binary format (intermediate sequence). The intermediate-binary to Gray code converter, connected to the decimal-binary to intermediate-binary converter, is operable to convert the intermediate sequence to a sequence of sets of electrical signals encoded in Gray code-binary format (Gray code sequence).
- In the present invention the decimal-binary sequence is converted to the intermediate sequence which is then converted to the Gray code sequence. Utilizing inventive conversion techniques, the decimal-binary sequence having any number of states (not limited to a number matching a power of 2) can be converted to a corresponding Gray code sequence. This overcomes the limitation of the prior art techniques and systems discussed above.
- Communication System
-
FIG. 1 illustrates acommunication system 100 having afirst circuit domain 110 and asecond circuit domain 150. Referring toFIG. 1 , thefirst circuit domain 110 and thesecond circuit domain 150 communicates via a communications means 102 such as a communications bus or via wireless signals. A circuit domain is a group of circuits operating together to perform a function. In the present embodiment, thefirst circuit domain 110 includes circuits operable to transmit a sequence of sets of electrical signals while thesecond circuit domain 150 includes circuits operable to receive the transmitted signals. Often circuits of a circuit domain operate from a common synchronization clock; however, this is not a necessary aspect of the present invention. - In the illustrated embodiment, the
first circuit domain 110 includes, for example, aregister 112 operable to provide a pointer to a sequence of sets of electrical signals encoded in decimal-binary format (decimal-binary sequence). Alternatively, theregister 112 provides the decimal-binary sequence. - The
first circuit domain 110 includes a generalizedGray code converter 120. The generalizedGray code converter 120 includes a decimal-binary to intermediate-binary converter 130 and an intermediate-binary toGray code converter 140. The intermediate-binary converter 130 is operable to convert a sequence of sets of electrical signals encoded in decimal-binary format (decimal-binary sequence) to a sequence of sets of electrical signals encoded in intermediate-binary format (intermediate sequence). For convenience, each electrical signal is referred to as a bit. A set of bits is also referred to as a “data word” or “word” as well as a set. For example, a set of eight bits is often referred to as a byte. - The intermediate-binary to
Gray code converter 140 is connected to the decimal-binary to intermediate-binary converter 130. The intermediate-binary toGray code converter 140 is operable to convert the intermediate sequence to a sequence of sets of electrical signals encoded in Gray code-binary format (Gray code sequence). - The Gray code sequence is transmitted from the
first circuit domain 110 to thesecond circuit domain 150. - The
second circuit domain 150 includes a generalizedGray code de-converter 160. The generalizedGray code de-converter 160 includes a Gray code to intermediate-binary converter 170 and an intermediate-binary to decimal-binary converter 180. The Gray code to intermediate-binary converter 170 is operable to convert the Gray code sequence to the intermediate sequence. The intermediate-binary to decimal-binary converter 180 is operable to convert the intermediate sequence to the decimal-binary sequence. The decimal-binary sequence is passed onto other components of thesecond circuit domain 150 such as aregister 152 for further processing. - Operations
- Sample Decimal-Binary Sequence
- As already stated, the generalized
Gray code converter 120, unlike the prior art Gray code converters, is operable to convert a decimal-binary sequence having any number of states. For example, TABLE 2 below lists words of a sample decimal-binary sequence having five states (indexed asstates 0 through 4) where each word (set of signals) is expressible using three bits (signal lines). That is, for the sample decimal-binary sequence, the number of states, B, is 5 and word width n is 3. Because 5 is not an even number and is not a number that is a power of 2, a prior art Gray code converter cannot be used to convert the sample decimal-binary sequence to Gray code. Often, such sample decimal-binary sequence is repeatedly sent from a first circuit domain to the second circuit domain.TABLE 2 Sample Decimal-Binary State Index sequence 0 000 1 001 2 010 3 011 4 100 - Operations of the generalized
Gray code converter 120 can be explained utilizingflowchart 200 ofFIG. 2 . For example, assume the sample decimal-binary sequence of TABLE 2 is the sequence of sets of signals for communication from thefirst circuit domain 110 to thesecond circuit domain 150. - First, the decimal-binary sequence is converted to a sequence of sets of signals encoded in intermediate-binary format (intermediate sequence).
Step 202. Next, the intermediate sequence is converted to a sequence of sets of electrical signals encoded in Gray code-binary format (Gray code sequence).Step 204. Then, the Gray code sequence is transmitted. Step 206. - Doubling the Decimal-Binary Sequence
-
FIG. 3A illustrates various sequences applicable for conversion of the decimal-binary sequence to the intermediate sequence. Referring toFIGS. 1 and 3 A, the sample decimal-binary sequence is illustrated ascolumn 310. This is same as the sample decimal-binary sequence of TABLE 2 above. As illustrated, the decimal-binary sequence 310 has five states (states 0 through 4) as indicated byreference numeral 312. Each state of the decimal-binary sequence 310 is represented by a data word (a set of binary signals) having 3 bits as indicated byreference numeral 314. The states of the decimal-binary sequence 310 are also referred to as sets of signals where B represents the number of sets, or states, which, in the present example, is 5. Each state, or set, in the present example, has n bits, which, in the present example, is 3. - In the illustrated embodiment, the decimal-
binary sequence 310 is repeatedly communicated from thefirst circuit domain 110 to thesecond circuit domain 150. The repetition is indicated by repeatedstatus indexes ellipse 315. However, to avoid clutter and possible confusion, only one sequence cycle of the decimal-binary sequence 310 and other sequences are illustrated in the Figures. - The decimal-binary to intermediate-
binary converter 130 doubles the number of states of the decimal-binary sequence 310 resulting in a doubled decimal-binary sequence illustrated ascolumn 320. The number of states of the decimal-binary sequence 310 is doubled by the following steps: first, adding, to each data word of the decimal-binary sequence 310, another bit (a most significant bit 322); then repeating the 3-bit data words of the decimal-binary sequence 310 once for thetop half 326 of the doubled decimal-binary sequence 320 with the mostsignificant bit 322 set at 0, then once for thebottom half 328 of the doubled decimal-binary sequence 320 (with the mostsignificant bit 322 set at 1. - Mapping to Intermediate Sequence
- The resulting doubled decimal-
binary sequence 320 is a sequence of 4-bit words (indicated by reference number 329) and has twice the number of states as the decimal-binary sequence 310. The doubled decimal-binary sequence 320 includes a sequence of data words (set of signals), each word having width of N bits where N is n+1 where n is the number of bits of the words (set of signals) of the decimal-binary sequence 310. - Then, the doubled decimal-
binary sequence 320 is mapped to a complete-decimal-binary sequence having base N (in the present example, base 4). The complete-decimal-binary sequence for 4-bit words is listed in TABLE 1 above and also illustrated ascolumn 330 ofFIG. 3A . In the present example, the complete-decimal-binary sequence 330 has 16 (or 24) states (0 through 15). - The
top half 326 of the doubled decimal-binary sequence 320 is mapped to top (first)entries 336 of the complete-decimal-binary sequence 330 as illustrated. Thebottom half 328 of the doubled decimal-binary sequence 320 is mapped tobottom entries 338 of the complete-decimal-binary sequence 330 as illustrated, resulting in the intermediate sequence illustrated ascolumn 340. - The mapping of the
bottom half 328 of the doubled decimal-binary sequence 320 to thebottom entries 338 of the complete-decimal-binary sequence 330 is equivalent to mapping of thebottom half 328 of the doubled decimal-binary sequence 320 to the complete-decimal-binary sequence 330 beginning at itscenter reflection line 332 plus a shifting constant 333 (designated R) where the shiftconstant R 333 is determined as follows:
R=(2N−2B)/2
where -
- N is the number of bits in a word (or set) of the doubled decimal-binary sequence (in the present example, N=4); and
- B is the number of states of the decimal-binary sequence (in the present example, B=5).
- Thus, in the present example, the shift
constant R 333 has value three (3). - Equivalent Technique to form the Intermediate Sequence
- An alternative but an equivalent illustration of the mapping technique is illustrated in
FIG. 3B . Referring toFIGS. 3A and 3B , since thetop half 326 of the doubled decimal-binary sequence 320 is identical to top (first)entries 336 of the complete-decimal-binary sequence 330, no operation is actually performed to accomplish this mapping. That is, for thetop half 326 of the doubled decimal-binary sequence 320, no operation is required to form theintermediate sequence 340. - Accordingly, the
intermediate sequence 340 is formed by combining thetop half 326 of the doubled decimal-binary sequence 320 and thebottom half 328 of the doubled decimal-binary sequence 320 shifted by the shiftconstant R 333. The shifting can be accomplished by merely adding, in decimal, the value of R (in the present example, R is 3) to each word of thebottom half 328 of the doubled decimal-binary sequence 320. The adding technique is illustrated by theadder 329. - Intermediate Sequence to Gray code Sequence
- Then the
intermediate sequence 340 is converted to its corresponding Gray code binary sequence using a known Gray conversion technique. This Gray code binary sequence (corresponding to the intermediate sequence 340) is illustrated usingreference numeral 350. -
FIG. 4 illustrates the complete-decimal-binary sequence 330 for 4-bit words and the correspondingGray code sequence 360 listed already as TABLE 1 above. The complete-decimal-binary sequence 330 is also illustrated inFIG. 3A ascolumn 330. Referring toFIGS. 3A and 4 , since theintermediate sequence 340 is a subset of the complete-decimal-binary sequence 330, theGray code sequence 340 for theintermediate sequence 330 is also a subset of theGray code sequence 360 for the complete-decimal-binary sequence 330. In particular theGray code sequence 340 for theintermediate sequence 330 is made up ofsegments Gray code sequence 360 for the complete-decimal-binary sequence 330. - The resulting
Gray code sequence 330 still retains the useful property in that any two successive values differ in only one digit. This is because the Gray code sequence 360 (from which theGray code sequence 330 is derived from) is reflective about its center line 362 (except for its most significant bit 364). This is illustrated inFIG. 4 . For theGray code sequence 360, not considering its mostsignificant bit 364, thesecond half 363 of the Gray codes are identical to but in a reverse order from thefirst half 361 of the Gray codes. TheGray code sequence 360 is reflective about itscenter line 362. This reflective property is known in the art. - Gray Code Sequence to Intermediate Sequence
- Referring again to
FIGS. 1 and 3 A, theGray code sequence 350 is communicated from the first circuit domain 110 (ofFIG. 1 ) to the second circuit domain 150 (ofFIG. 1 ) where the generalizedGray code de-converter 160 converts the incomingGray code sequence 350 to the decimal-binary sequence 310 by reversing the operations of the generalizedGray code converter 120. - Operations of the generalized
Gray code de-converter 160 can be explained utilizingflowchart 400 ofFIG. 5 along with various sequences illustrated inFIG. 3A and discussed above. Referring toFIGS. 3A and 5 , theGray code sequence 350 is received by the generalizedGray code de-converter 160.Step 402. Next, theGray code sequence 350 is converted to theintermediate sequence 340.Step 404. Then, theintermediate sequence 340 is converted to the decimal-binary sequence 310.Step 406. In short, to convert theGray code sequence 350 to the decimal-binary sequence 310, the steps outlined in theflowchart 200 ofFIG. 2 is performed in a reverse order. -
FIG. 3B illustrates various sequences applicable for conversion of theGray code sequence 350 to theintermediate sequence 340 then to the decimal-binary sequence 310. - Gray Code Sequence to Intermediate Sequence
- Referring to
FIGS. 1 and 3 B, the receivedGray code sequence 350 is converted to theintermediate sequence 340 using a known Gray code de-conversion technique. - Intermediate Sequence to Decimal-binary Sequence
- The
intermediate sequence 340 is used to form the doubled decimal-binary sequence 320 by reversing the operation (described above) to form theintermediate sequence 340 from the doubled decimal-binary sequence 320. That is, thetop half 346 of theintermediate sequence 340 forms thetop half 326 of the doubled decimal-binary sequence 320, and a shiftedbottom half 348 of theintermediate sequence 340 forms thebottom half 328 of the doubled decimal-binary sequence 320. Here, the shifting is performed by subtracting the shift constant R from the words of thebottom half 348 of theintermediate sequence 340. - Then, the
top half 326 of the doubled decimal-binary sequence 320 is mapped to the entire decimal-binary sequence 310. Also, thebottom half 328 of the doubled decimal-binary sequence 320 is mapped to the entire decimal-binary sequence 310. This mapping is performed by removing the mostsignificant bit 322 from the words of the doubled decimal-binary sequence 320. - Hardware and Code—Coding
-
FIG. 6 illustrates one embodiment of the decimal-binary to intermediate-binary converter 130 ofFIG. 1 in more detail. Referring toFIGS. 3B and 6 , the decimal-binary to intermediate-binary converter 130 takes, as its input, the decimal-binary sequence 310. A most significant bit generator (MSB Gen) 131 examines the input decimal-binary sequence 310 to generate either a “0” or a “1” as the mostsignificant bit 322 to form, combined with the decimal-binary sequence 310, the doubled decimal-binary sequence 320. - The doubled decimal-
binary sequence 320 is introduced to an addingcircuit 329 and a first input of amultiplexer 133. The addingcircuit 329 adds the shift constant R to the doubled decimal-binary sequence 320 and introduces the shifted values to a second input of themultiplexer 133. The multiplexer uses the MSB generated value to select either from the un-shifted sequence of its first input or the shifted sequence of its second input to produce theintermediate sequence 340. - Then, the
intermediate sequence 340 is used as an input to the intermediate-binary toGray code converter 140 to generate theGray code sequence 350. For the intermediate-binary toGray code converter 140, any known Gray code generating hardware or software that produces a reflective Gray code can be used. For example, the following is a computer program code in C programming language that generates theGray code sequence 350 from the intermediate sequence 340:for(bit=0; bit<N−1; ++bit) { gray_code[bit] = binary_code[bit] {circumflex over ( )} binary_code[bit+1]; } gray_code[N−1] = binary_code[N−1];
where -
- N is the number of bits (width) of the words of the
intermediate sequence 340; - bit is an index that references a specific bit (signal) within the word. That is, if a 4-bit word (e.g., 1011) is considered as an array of bits, then bit 3 is 1,
bit 2 is 0,bit 1 is 1 andbit 0 is 1; - binary_code is an array that contains the bits of one word in the
intermediate sequence 340; and - gray_code is an array that contains the bits of one word in the Gray code sequence.
Hardware and Code—deCoding
- N is the number of bits (width) of the words of the
- Also known in the art is the reverse operation of converting the
Gray code sequence 350 to theintermediate sequence 340. For this operation, any known hardware or software technique may be used. For example, the following is a computer program code in C programming language that generates theintermediate sequence 340 from the Gray code sequence 350:binary_code[N−1] = gray_code[N−1]; for(bit=N−2; bit>=0; −−bit) { binary_code[bit] = binary_code[bit+1] {circumflex over ( )} gary_code[bit]; }
where -
- N is the number of bits (width) of the words of the
intermediate sequence 340; - bit is an index that references a specific bit (signal) within the word. That is, if a 4-bit word (e.g., 1011) is considered as an array of bits, then bit 3 is 1,
bit 2 is 0,bit 1 is 1 andbit 0 is 1; - binary_code is an array that contains the bits of one word in the
intermediate sequence 340; and - gray_code is an array that contains the bits of one word in the Gray code sequence.
- N is the number of bits (width) of the words of the
- The
intermediate sequence 340 is then converted to thebinary sequence 310.FIG. 7 illustrates one embodiment of the intermediate-binary to decimal-binary converter 180 ofFIG. 1 in more detail. Referring toFIGS. 3B and 7 , the intermediate-binary to decimal-binary converter 180 takes, as its input, the intermediatebinary sequence 340. The intermediate-binary sequence 340 is introduced to asubtracting circuit 329 a and a first input of amultiplexer 183. The subtractingcircuit 329 a subtracts the shift constant R from the intermediate-binary sequence 340 and introduces the shifted values to a second input of themultiplexer 183. Themultiplexer 183 uses the most significant bit (MSB) of the intermediate-binary sequence 340 to select either from the un-shifted sequence of its first input or the shifted sequence of its second input to produce the doubled decimal-binary sequence 320. - Then, the
MSB bit 322 of the doubled decimal-binary sequence 320 is eliminated resulting in the decimal-binary sequence 310. - From the foregoing, it will be apparent that the present invention is novel and offers advantages over the current art. Although specific embodiments of the invention are described and illustrated above, the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated. For example, differing configurations, sizes, or materials may be used but still fall within the scope of the present invention. Further, the present invention is disclosed for application to electrical signals; however, the present invention encompasses optical signals and any and all other types of signals in the magneto-electric spectrum. The invention is limited by the claims that follow.
Claims (18)
R=(2N−2B)/2
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/020,997 US7071855B1 (en) | 2004-12-23 | 2004-12-23 | Gray code conversion method and apparatus embodying the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/020,997 US7071855B1 (en) | 2004-12-23 | 2004-12-23 | Gray code conversion method and apparatus embodying the same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20060139189A1 true US20060139189A1 (en) | 2006-06-29 |
US7071855B1 US7071855B1 (en) | 2006-07-04 |
Family
ID=36610792
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/020,997 Active US7071855B1 (en) | 2004-12-23 | 2004-12-23 | Gray code conversion method and apparatus embodying the same |
Country Status (1)
Country | Link |
---|---|
US (1) | US7071855B1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070208905A1 (en) * | 2006-03-06 | 2007-09-06 | Ramot At Tel-Aviv University Ltd. | Multi-bit-per-cell flash memory device with non-bijective mapping |
US20110093652A1 (en) * | 2006-03-06 | 2011-04-21 | Sandisk Il Ltd. | Multi-bit-per-cell flash memory device with non-bijective mapping |
US10103912B1 (en) * | 2016-04-22 | 2018-10-16 | Ervin A Paw | Phased information pulse method and apparatus |
US20190214072A1 (en) * | 2018-01-11 | 2019-07-11 | Micron Technology, Inc. | Apparatuses and methods for maintaining a duty cycle error counter |
CN113110278A (en) * | 2021-04-13 | 2021-07-13 | 珠海格力智能装备有限公司 | Information interaction method and device, storage medium and processor |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7518535B1 (en) * | 2007-12-12 | 2009-04-14 | International Business Machines Corporation | Generating a Gray code sequence for any even length using an intermediate binary sequence |
KR101811615B1 (en) * | 2012-04-24 | 2017-12-27 | 삼성전자주식회사 | Binary-to-gray converting circuit and gray code counter including the same |
US8966416B2 (en) | 2013-03-07 | 2015-02-24 | Cadence Design Systems, Inc. | Finite-state machine encoding during design synthesis |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6703950B2 (en) * | 2001-09-13 | 2004-03-09 | Pmc Sierra, Ltd. | Gray code sequences |
US6809666B1 (en) * | 2000-05-09 | 2004-10-26 | Pixim, Inc. | Circuit and method for gray code to binary conversion |
US6836525B1 (en) * | 2003-07-21 | 2004-12-28 | Realtek Semiconductor Corp. | Method for establishing a gray code and related counter circuit |
-
2004
- 2004-12-23 US US11/020,997 patent/US7071855B1/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6809666B1 (en) * | 2000-05-09 | 2004-10-26 | Pixim, Inc. | Circuit and method for gray code to binary conversion |
US6703950B2 (en) * | 2001-09-13 | 2004-03-09 | Pmc Sierra, Ltd. | Gray code sequences |
US6836525B1 (en) * | 2003-07-21 | 2004-12-28 | Realtek Semiconductor Corp. | Method for establishing a gray code and related counter circuit |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070208905A1 (en) * | 2006-03-06 | 2007-09-06 | Ramot At Tel-Aviv University Ltd. | Multi-bit-per-cell flash memory device with non-bijective mapping |
US7388781B2 (en) * | 2006-03-06 | 2008-06-17 | Sandisk Il Ltd. | Multi-bit-per-cell flash memory device with non-bijective mapping |
US20110093652A1 (en) * | 2006-03-06 | 2011-04-21 | Sandisk Il Ltd. | Multi-bit-per-cell flash memory device with non-bijective mapping |
US8804423B2 (en) | 2006-03-06 | 2014-08-12 | Ramot At Tel-Aviv University Ltd. | Multi-bit-per-cell flash memory device with non-bijective mapping |
US8848442B2 (en) | 2006-03-06 | 2014-09-30 | Sandisk Il Ltd. | Multi-bit-per-cell flash memory device with non-bijective mapping |
US10103912B1 (en) * | 2016-04-22 | 2018-10-16 | Ervin A Paw | Phased information pulse method and apparatus |
US20190214072A1 (en) * | 2018-01-11 | 2019-07-11 | Micron Technology, Inc. | Apparatuses and methods for maintaining a duty cycle error counter |
US10438648B2 (en) * | 2018-01-11 | 2019-10-08 | Micron Technology, Inc. | Apparatuses and methods for maintaining a duty cycle error counter |
US10770130B2 (en) * | 2018-01-11 | 2020-09-08 | Micron Technology, Inc. | Apparatuses and methods for maintaining a duty cycle error counter |
CN113110278A (en) * | 2021-04-13 | 2021-07-13 | 珠海格力智能装备有限公司 | Information interaction method and device, storage medium and processor |
Also Published As
Publication number | Publication date |
---|---|
US7071855B1 (en) | 2006-07-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0098153B1 (en) | Digital data code conversion circuit for variable-word-length data code | |
US5382955A (en) | Error tolerant thermometer-to-binary encoder | |
GB2183971A (en) | Data transmission system | |
EP0463216B1 (en) | Signal conversion circuit | |
US4691319A (en) | Method and system for detecting a predetermined number of unidirectional errors | |
US7071855B1 (en) | Gray code conversion method and apparatus embodying the same | |
US4646327A (en) | Waveform shaping apparatus | |
US5034742A (en) | Message compression encoder and encoding method for a communication channel | |
US7933354B2 (en) | Encoding and decoding architecture and method for pipelining encoded data or pipelining with a look-ahead strategy | |
KR100327856B1 (en) | Circuit and method for arbitrarily shifting M series | |
US7916048B2 (en) | Encoding a gray code sequence for an odd length sequence | |
EP0470793B1 (en) | Digital signal orthogonal transformer apparatus | |
US5920496A (en) | High speed correlator using up/down counter | |
US6041086A (en) | Signal decoding for either Manhattan or Hamming metric based Viterbi decoders | |
JP2001069181A (en) | Digital data transmitting method and device to carry out the same | |
KR980013161A (en) | Error Correction Code Generation Circuit and Modulation Device Using the Same (ERROR-CORRECTING CODE) | |
JPH0583229A (en) | Digital communication equipment | |
US7812636B2 (en) | Method and device for generating pseudo-random binary data | |
KR100434364B1 (en) | Serial adder | |
JPS5899028A (en) | Code converter | |
GB2149162A (en) | Fixed point to floating point conversion | |
JP3168514B2 (en) | Counter | |
JP3876067B2 (en) | Data signal path connection method and signal path connector | |
SU1736008A1 (en) | Device for decoding nordstrome-robinson code in discrete channel | |
JPH09153821A (en) | Serial-parallel converting system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: AGILENT TECHNOLOGIES, INC., COLORADO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SADOWSKY, JONATHAN B.;REEL/FRAME:016005/0590 Effective date: 20041215 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.,SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AGILENT TECHNOLOGIES, INC.;REEL/FRAME:017206/0666 Effective date: 20051201 Owner name: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD., SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AGILENT TECHNOLOGIES, INC.;REEL/FRAME:017206/0666 Effective date: 20051201 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT, NEW YORK Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:032851/0001 Effective date: 20140506 Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:032851/0001 Effective date: 20140506 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., SINGAPORE Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037689/0001 Effective date: 20160201 Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037689/0001 Effective date: 20160201 |
|
AS | Assignment |
Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH CAROLINA Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001 Effective date: 20160201 Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001 Effective date: 20160201 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNOR:AGILENT TECHNOLOGIES, INC.;REEL/FRAME:038632/0662 Effective date: 20051201 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., SINGAPORE Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001 Effective date: 20170119 Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001 Effective date: 20170119 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553) Year of fee payment: 12 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITE Free format text: MERGER;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:047196/0097 Effective date: 20180509 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITE Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:048555/0510 Effective date: 20180905 |
|
AS | Assignment |
Owner name: BROADCOM INTERNATIONAL PTE. LTD., SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED;REEL/FRAME:053771/0901 Effective date: 20200826 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED, SINGAPORE Free format text: MERGER;ASSIGNORS:AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED;BROADCOM INTERNATIONAL PTE. LTD.;REEL/FRAME:062952/0850 Effective date: 20230202 |