JP2011243908A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method that can surely suppress characteristic deterioration caused by processing dispersion of gate length.SOLUTION: A correlation between a shift amount from each of design values of a gate length and an offset side wall length and a dosage of a source/drain extension region to set transistor characteristics as design values is determined in advance. After the gate length and the offset side wall length are actually measured, on the basis of the shift amounts of the actual measurement values of the gate length and the offset side wall length from the design values thereof and the predetermined correlation, the dosage of the source/drain extension region is adjusted so that the shift amounts of the transistor characteristics from the design values are within a predetermined range.

Description

  The present invention relates to a method of manufacturing a semiconductor device including a MISFET (Metal Insulator Semiconductor Field Effect Transistor), and more particularly, to a method of manufacturing a semiconductor device including a MISFET having an offset sidewall structure and a source / drain extension structure after the 90 nm generation. About.

  In recent years, as semiconductor devices have been miniaturized, the influence of dimensional variations on circuit characteristics has become relatively large. In particular, since the variation in the gate length of the MISFET has a great influence on the characteristics of the MISFET, very strict dimension control is required in the gate electrode processing step. On the other hand, in order to obtain higher dimensional accuracy, an immersion exposure machine that introduces an exposure machine with a shorter wavelength or actively uses water having a higher refractive index than air in the optical waveguide region between the lens and the wafer. However, these introductions are a major factor in increasing costs.

  In view of this, a feed-forward technique has been proposed that compensates for the difference in gate length finish (deviation from the design value) in a post-process that has a great influence on the characteristics of the MISFET, thereby reducing variations in the characteristics of the MISFET.

  For example, Patent Document 1 preliminarily formulates the relationship between the amount of deviation from the design value of the finished dimension of the gate length and the dose amount of the source / drain extension region necessary to match the characteristics of the MISFET with the design value. A method for correcting the implantation dose amount in the source / drain extension region forming process, which is a subsequent process, based on the deviation amount between the actual measurement value and the design value of the finished dimension of the gate length and the formulated relationship is disclosed. Has been. In this method, even if the gate length varies, the MISFET characteristic variation can be reduced by adjusting the dose amount of the source / drain extension region and keeping the effective channel length within a predetermined range.

JP 2001-308317 A

  However, when a MISFET of the 90 nm generation or later is formed by the conventional semiconductor device manufacturing method using the above-described feedforward technology, there are problems such as failure to obtain desired transistor characteristics and deterioration of leakage characteristics. Arise.

  In view of the above, an object of the present invention is to provide a method of manufacturing a semiconductor device that can reliably suppress characteristic deterioration due to processing variations in gate length.

  In order to achieve the above object, even if the feedforward technique disclosed in Patent Document 1 is applied to the formation of a MISFET of the 90 nm generation or later, the reason why the characteristic deterioration due to the processing variation of the gate length cannot be suppressed is as follows. As a result of various studies by the inventors of the present application, the following findings were obtained.

When miniaturization of MISFET progresses after 90nm generation,
(1) It becomes difficult to scale the overlap amount between the gate electrode and the source / drain extension region, and (2) When the source / drain extension region is shallowly joined, the vicinity of the surface of the source / drain extension region is obtained. The overlap capacitance between the gate electrode and the source / drain extension region is not reduced due to factors such as higher concentration and less depletion at the surface of the source / drain extension region. It becomes. As a result, problems such as increase in leakage current such as GIDL (Gate Induced Drain Leakage) and deterioration of circuit characteristics occur.

  Therefore, an offset sidewall spacer is formed on the side surface of the gate electrode, and then impurity implantation is performed using the gate electrode and the offset sidewall spacer as a mask to form a source / drain extension region. The overlap amount (that is, overlap capacitance) with the source / drain extension region is optimized by adjusting the spacer length. Thereby, it is possible to improve circuit characteristics while suppressing leakage current such as GIDL.

  However, when the feedforward technology disclosed in Patent Document 1 is applied to the formation of the MISFET having the offset sidewall structure and the source / drain extension structure as described above, the source / Although the dose amount of the drain / extension region is adjusted, the variation in the spacer length of the offset sidewall spacer (hereinafter referred to as the offset sidewall length) is not taken into consideration. I can't.

Further, when the deviation direction from the design value of the gate length is opposite to the deviation direction from the design value of the offset sidewall length, the following problem occurs.
(1) When the gate length is shorter than the design value and the offset sidewall length is longer than the design value Since the gate length is shorter than the design value, the dose amount of the source / drain extension region tends to be relatively small. In this case, the overlap length between the gate electrode and the source / drain extension region is reduced due to the offset sidewall length being longer than the design value. The extension region does not overlap (becomes an offset transistor).
(2) When the gate length is longer than the design value and the offset sidewall length is shorter than the design value Since the gate length is longer than the design value, the dose amount of the source / drain extension region is relatively increased. In this case, the overlap length between the gate electrode and the source / drain extension region becomes large due to the fact that the offset sidewall length is shorter than the design value. In the worst case, the overlap length is excessive. Become. When the overlap length between the gate electrode and the source / drain extension region becomes excessive, a leakage current such as GIDL increases and circuit characteristics deteriorate.

  Based on the above knowledge, the inventors of the present invention can suppress the deterioration of characteristics due to processing variations in the gate length and offset sidewall length in the MISFET having the offset sidewall structure and the source / drain extension structure as follows. Invented the invention.

  That is, the method of manufacturing a semiconductor device according to the present invention includes a gate electrode formed on a semiconductor substrate, an offset sidewall spacer formed on a side surface of the gate electrode, and the gate electrode on a surface portion of the semiconductor substrate. A method of manufacturing a semiconductor device including a transistor having source / drain extension regions formed on both sides of the gate electrode, wherein a deviation amount from a design value of a gate length of the gate electrode and The correlation between the offset amount from the design value of the spacer length of the offset sidewall spacer and the dose amount of the impurity implanted into the source / drain extension region in order to set the transistor characteristics to the design value is obtained. Step (a), and after forming the gate electrode, the gate length of the gate electrode A step (b) of measuring, a step (c) of measuring a spacer length of the offset sidewall spacer after forming the offset sidewall spacer, and a gate length of the gate electrode measured in the step (b) Based on the amount of deviation from the design value, the amount of deviation from the design value of the spacer length of the offset sidewall spacer actually measured in the step (c), and the correlation obtained in the step (a), And a step (d) of adjusting a dose amount of the impurity implanted into the source / drain extension region so that a deviation amount from a design value of the characteristics of the transistor falls within a predetermined range.

  According to the semiconductor device manufacturing method of the present invention, the amount of deviation from the design value of the gate length and the offset sidewall length, and the amount of dose of the source / drain extension region for setting the transistor characteristics to the design value In advance, and after measuring the gate length and offset sidewall length, based on the amount of deviation from the design value of each measured value of the gate length and offset sidewall length, and the correlation, The dose of the source / drain extension region is adjusted so that the deviation from the design value of the transistor characteristics falls within a predetermined range. That is, since the dose amount of the source / drain extension region can be adjusted in consideration of not only the variation in gate length but also the variation in offset sidewall length, in the MISFET having the offset sidewall structure and the source / drain extension structure, Degradation of transistor characteristics due to variations in processing of the gate length and offset sidewall length can be suppressed.

  In addition, according to the method of manufacturing a semiconductor device according to the present invention, the dose of the source / drain extension region can be adjusted in consideration of variations in both the gate length and the offset sidewall length. Even when the offset sidewall length is shorter than the design value, the overlap between the gate electrode and the source / drain extension region can be prevented, and the gate length is longer than the design value and the offset sidewall length is Even when the design value is shorter than the designed value, it is possible to prevent the gate electrode from being excessively overlapped with the source / drain extension region. Accordingly, it is possible to improve the chip characteristics by preventing the deterioration of the leak characteristics and the circuit characteristics.

  In the method of manufacturing a semiconductor device according to the present invention, in the step (c), the gate length of the gate electrode including the offset sidewall spacer is measured, and the actual value measured in the step (b) is measured. A step of calculating half the value obtained by subtracting the gate length of the gate electrode as the spacer length of the offset sidewall spacer may be included. In this way, the offset sidewall length can be easily calculated.

  In the method for manufacturing a semiconductor device according to the present invention, the characteristics of the transistor may be a threshold voltage or a saturation current of the gate electrode.

  In the method of manufacturing a semiconductor device according to the present invention, in the step (d), the impurity implanted into the source / drain extension region may be formed such that the gate electrode and the source / drain extension region overlap. A step of adjusting the dose may be included. By doing so, it is possible to avoid a situation where the gate electrode and the source / drain extension region do not overlap (become an offset transistor).

  In the method of manufacturing a semiconductor device according to the present invention, in the step (d), the smaller the gate length of the gate electrode actually measured in the step (b), the smaller the impurity implanted into the source / drain extension region. A step of reducing the dose may be included. In this way, variation in transistor characteristics can be reduced by keeping the effective channel length within a predetermined range. In this case, in the step (d), when the spacer length of the offset sidewall spacer measured in the step (c) is larger than a design value, the gate of the gate electrode measured in the step (b) is measured. When the length is smaller than a predetermined value, a step of suppressing the reduction of the dose of the impurity implanted into the source / drain extension region may be included. For example, when the gate length of the gate electrode actually measured in the step (b) becomes smaller than a predetermined value, the dose of the impurity implanted into the source / drain extension region may be constant. . In this way, it is possible to prevent insufficient overlap between the gate electrode and the source / drain extension region (worst case, the gate electrode does not overlap with the source / drain extension region), thus preventing deterioration of transistor characteristics. it can. When the present invention is carried out at the wafer level, the overlap length between the gate electrode and the source / drain extension region is set to 0.degree. It is preferably about 5 nm or more.

  In the method of manufacturing a semiconductor device according to the present invention, in the step (d), the larger the gate length of the gate electrode actually measured in the step (b), the larger the impurity implanted into the source / drain extension region. A step of increasing the dose may be included. In this way, variation in transistor characteristics can be reduced by keeping the effective channel length within a predetermined range. In this case, in the step (d), when the spacer length of the offset sidewall spacer measured in the step (c) is smaller than a design value, the gate of the gate electrode measured in the step (b) is measured. When the length becomes larger than a predetermined value, a step of suppressing an increase in the dose of the impurity implanted into the source / drain extension region may be included. For example, when the gate length of the gate electrode actually measured in the step (b) becomes larger than a predetermined value, the dose of the impurity implanted into the source / drain extension region may be made constant. . In this way, excessive overlap between the gate electrode and the source / drain extension region can be prevented, so that deterioration of leak characteristics and circuit characteristics can be prevented. In order to reliably prevent the occurrence of leakage current such as GIDL due to excessive overlap between the gate electrode and the source / drain extension region, that is, reduction in effective channel length, the overlap length of both is about 5 nm. The following is preferable.

  According to the present invention, since the dose amount of the source / drain extension region can be adjusted in consideration of not only the variation in gate length but also the variation in offset sidewall length, the offset sidewall structure and the source / drain extension structure are provided. In the MISFET, it is possible to suppress deterioration of transistor characteristics due to processing variations in the gate length and offset sidewall length.

FIGS. 1A to 1G are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps. FIG. 2 is a flowchart showing a method of compensating for manufacturing variation by feed-forward control with respect to the dose amount of extension implantation in the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIGS. 3A to 3E illustrate an example of a technique for compensating for the deviation between the gate length and the offset sidewall length in the semiconductor device manufacturing method according to the first embodiment of the present invention by the dose amount of the extension implantation. It is a figure to do. FIG. 4 is a diagram for explaining an example of a technique for compensating for the deviation of the gate length and the offset sidewall length by the dose amount of the extension implantation in the semiconductor device manufacturing method according to the modification of the first embodiment of the present invention. .

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
Hereinafter, the semiconductor device manufacturing method according to the first embodiment of the present invention will be described with reference to FIGS. 1A to 1G, FIG. 2, and FIGS. 3A to 3E with specific examples. While explaining. FIGS. 1A to 1G are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps. FIG. 2 is a flowchart showing a method of compensating for manufacturing variation by feed-forward control with respect to the dose amount of extension implantation in the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIGS. 3A to 3E illustrate an example of a technique for compensating for the deviation between the gate length and the offset sidewall length in the semiconductor device manufacturing method according to the first embodiment of the present invention by the dose amount of the extension implantation. It is a figure to do.

First, as shown in FIG. 1A, a one-conductivity-type substrate (hereinafter referred to as a semiconductor substrate) 1 having a semiconductor region such as a silicon region is formed by, for example, a buried trench isolation (STI) method. An element isolation region 2 in which an insulating film is buried in a trench is selectively formed on the upper portion. As a result, the region surrounded by the element isolation region 2 in the semiconductor substrate 1 becomes the active region 3. Thereafter, although not shown, a P-type well and a P-type punch-through stopper are formed by ion-implanting P-type impurities into the semiconductor substrate 1. Here, the implantation conditions for the P-type well are, for example, that the implanted ion species is B (boron), the implantation energy is 200 keV, the implantation dose is 1 × 10 ¹³ cm ⁻² , and the implantation conditions for the P-type punch-through stopper are For example, the implanted ion species is B, the implantation energy is 100 keV, and the implantation dose is 1 × 10 ¹³ cm ⁻² . Thereafter, a channel region 4 of the N-type MISFET is formed on the active region 3 by ion-implanting P-type impurities into the semiconductor substrate 1. Here, the implantation conditions of the channel region 4 are, for example, that the implanted ion species is B, the implantation energy is 30 keV, and the implantation dose is 2 × 10 ¹² cm ⁻² .

  Thereafter, as shown in FIG. 1A, after a gate insulating film 5 made of, for example, a silicon oxide film having a thickness of 2 nm is formed on the semiconductor substrate 1, a gate made of, for example, polysilicon is formed on the gate insulating film 5. An electrode film 6 is deposited.

  Next, after forming a resist pattern (not shown) having a gate pattern shape on the gate electrode film 6, the gate electrode film 6 and the gate insulating film 5 are sequentially patterned by dry etching using the resist pattern as a mask. Then, as shown in FIG. 1B, a gate electrode 6A is formed on the active region 3 via a gate insulating film 5.

  Here, as step S1 in FIG. 2, the gate length Lg of the gate electrode 6A is measured using, for example, a length measuring SEM (scanning electron microscope). At this time, the pattern to be measured may be an actual circuit pattern, a pattern dedicated to length measurement, or a TEG (test element group) pattern for electrical characteristic monitoring. . Also, when using length measurement-specific patterns, TEG patterns, etc., if the correlation (difference, ratio, etc.) between the measured values of these patterns and the representative values of the actual circuit pattern is clear, The dimensions of the TEG pattern or the like may be different from the dimensions of the actual circuit pattern.

  Next, after depositing, for example, a silicon nitride film (SiN film) having a thickness of about 5 nm on the semiconductor substrate 1 including the gate electrode 6A, the SiN film is etched back, whereby FIG. ), An offset sidewall spacer 7 is formed on the side surface of the gate electrode 6A.

  Here, as step S2 in FIG. 2, the gate length Lgs of the gate electrode 6A including the offset sidewall spacer 7 is measured using, for example, a length measuring SEM. At this time, the pattern to be measured is the same pattern as that used in step S1.

  Subsequently, as step S3 in FIG. 2, the spacer length (hereinafter referred to as offset sidewall length) Ls of the offset sidewall spacer 7 is calculated using, for example, the calculation formula Ls = (Lgs−Lg) / 2. Here, Lg is the gate length Lg measured in step S1, and Lgs is the gate length Lgs measured in step S2.

  Subsequently, as step S4 in FIG. 2, based on the deviation amount ΔLg from the design value of the gate length Lg measured in step S1 and the deviation amount ΔLs from the design value of the offset sidewall length Ls obtained in step S3. Then, the dose amount of the extension injection is corrected. Specifically, before starting the manufacture of the semiconductor device, a deviation amount ΔLg from the design value of the gate length Lg and a deviation amount ΔLs from the design value of the offset sidewall length Ls, and transistor characteristics (for example, threshold voltage) Is set to the design value, a correlation with the dose amount of the impurity implanted into the source / drain extension region (that is, the dose amount of extension implantation) Dext is obtained, and the measured ΔLg and By applying ΔLs, the dose amount Dext is adjusted so that the deviation amount from the design value of the transistor characteristics falls within a predetermined range (for example, variation in threshold voltage is within 20 mV).

  3A shows the sensitivity of the threshold voltage Vt with respect to ΔLg, FIG. 3B shows the sensitivity of the threshold voltage Vt with respect to ΔLs, and FIG. 3C shows the correction of the dose amount Dext. The sensitivity of the threshold voltage Vt with respect to the amount (extension dose correction amount) ΔDext is shown, and FIG. 3D shows the sensitivity of the threshold voltage Vt with respect to ΔLg and ΔLs. FIG. 3E shows the relationship between ΔLg and ΔLs and the extension dose correction amount ΔDext for setting the threshold voltage Vt to the design value. Here, for example, based on the relationships shown in FIGS. 3A to 3D, the relationship shown in FIG. 3E can be obtained.

3A to 3E, as an example, the design value of the gate length Lg is 40 nm, the design value of the offset sidewall length Ls is 5 nm, and the doses (Lg and Ls are designed). If the value is as it is, the dose amount for setting the threshold voltage as the design value is 1 × 10 ¹⁵ / cm ² , the implantation type is arsenic (As), the implantation energy is 2 keV, and the implantation angle (normal to the substrate main surface) (Tilt angle with respect to direction) was obtained under the condition of 0 °. Further, in order to obtain the relationships shown in FIGS. 3A to 3E, for example, TEG patterns having various gate lengths and offset sidewall lengths may be used. In this case, if the correlation (difference, ratio, etc.) between the measured value of the TEG pattern and the representative value of the actual circuit pattern is clear, the dimension of the TEG pattern may be different from the dimension of the actual circuit pattern.

Next, as shown in FIG. 1D, using the gate electrode 6A and the offset sidewall spacer 7 as a mask, the extension dose correction amount obtained based on, for example, the relationship shown in FIG. An N-type source / drain extension region 10 is formed by implanting, for example, As ions as an n-type impurity into the active region 3 using a dose amount Dext adjusted by ΔDext. Here, the dose amount Dext before adjustment is, for example, 1 × 10 ¹⁵ / cm ² , and the implantation energy is, for example, 2 keV.

Before forming the source / drain extension region 10, a pocket region (not shown) may be formed by implanting boron (B) ions, for example. In this case, the implantation dose is, for example, 1 × 10 ¹³ / cm ² , and the implantation energy is, for example, 10 keV.

  Next, an insulating film made of, for example, a 50 nm-thickness silicon oxide film is deposited on the entire surface of the semiconductor substrate 1 by, eg, CVD (chemical vapor deposition), and then the insulating film is etched by anisotropic etching. By performing the back, sidewall spacers 11 are formed on the side surfaces of the gate electrode 6A with the offset sidewall spacers 7 interposed therebetween, as shown in FIG.

Next, as shown in FIG. 1F, for example, As ions are implanted into the active region 3 as an n-type impurity by using the gate electrode 6A, the offset side wall spacer 7 and the side wall spacer 11 as a mask. Source / drain regions 12 are formed. Here, the implantation dose is, for example, 5 × 10 ¹⁵ / cm ² , and the implantation energy is, for example, 10 keV. Thereafter, a spike RTA (rapid thermal annealing) process is performed on the semiconductor substrate 1 at a temperature of, for example, 1050 ° C., thereby activating the impurities implanted in the source / drain extension region 10 and the source / drain region 12. Make it.

  Next, a silicide metal film (not shown) made of, for example, a nickel (Ni) film having a thickness of 10 nm is deposited on the entire surface of the semiconductor substrate 1 by, eg, sputtering. Thereafter, for example, in a nitrogen atmosphere, the semiconductor substrate 1 is subjected to a first RTA treatment at a temperature of 320 ° C., for example, and silicon contained in the upper portions of the source / drain regions 12 and the gate electrode 6A and the silicide It reacts with nickel contained in the metal film. Thereafter, the unreacted metal for silicide remaining on the element isolation region 2 and the sidewall spacers 11 and the like by immersing the semiconductor substrate 1 in an etching solution made of, for example, a mixture of sulfuric acid and hydrogen peroxide. Remove the membrane. Thereafter, the second RTA process is performed on the semiconductor substrate 1 at a temperature (for example, 550 ° C.) higher than the temperature of the first RTA process. Thereby, as shown in FIG. 1G, a silicide film 13 made of a nickel silicide film (NiSi film) is formed on each of the source / drain regions 12 and the gate electrode 6A.

  According to the first embodiment described above, the shift amounts ΔLg and ΔLs from the respective design values of the gate length Lg and the offset sidewall length Ls, and the source / drain region for setting the transistor characteristics to the design values. A correlation with the dose amount Dext of the extension region 10 is obtained in advance, and after actually measuring the gate length Lg and the offset sidewall length Ls, the measured values of the gate length Lg and the offset sidewall length Ls from the design values. Based on the shift amounts ΔLg and ΔLs and the correlation, the dose amount of the source / drain extension region 10 is adjusted so that the shift amount from the design value of the transistor characteristics falls within a predetermined range. That is, since the dose amount of the source / drain extension region 10 can be adjusted in consideration of not only the variation in the gate length Lg but also the variation in the offset sidewall length Ls, the offset sidewall structure and the source / drain extension structure are provided. In the MISFET, it is possible to suppress deterioration of transistor characteristics due to processing variations of the gate length Lg and the offset sidewall length Ls.

  In the first embodiment, the threshold voltage Vt is targeted as the transistor characteristics, and the dose amount of the source / drain extension region 10 is adjusted. Instead, the transistor characteristics such as saturation current are targeted. As an alternative, the dose amount of the source / drain extension region 10 may be adjusted.

  In the first embodiment, the offset sidewall length Ls is obtained using the difference between the gate length Lgs of the gate electrode 6A including the offset sidewall spacer 7 and the gate length Lg of the gate electrode 6A. Instead of this, the offset sidewall length Ls may be obtained by other methods such as directly measuring the offset sidewall length Ls.

  In the first embodiment, the adjustment of the dose of the source / drain extension region 10 is preferably performed so that the gate electrode 6A and the source / drain extension region 10 overlap. In this way, it is possible to avoid a situation in which the gate electrode 6A and the source / drain extension region 10 do not overlap (become an offset transistor).

  In the first embodiment, the adjustment of the dose amount of the source / drain extension region 10 is performed so that the dose amount decreases as the measured gate length Lg of the gate electrode 6A decreases. The gate electrode 6A is preferably performed so that the dose amount increases as the gate length Lg of the gate electrode 6A increases. In this way, variation in transistor characteristics can be reduced by keeping the effective channel length within a predetermined range.

(Modification of the first embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to a modification of the first embodiment of the present invention, specifically, a modification of feed forward control with respect to a dose amount of extension implantation will be described with reference to FIG. . FIG. 4 is a diagram for explaining an example of a technique for compensating for the deviation between the gate length and the offset sidewall length in the present modification by the dose amount of the extension implantation.

In the first embodiment, for example, as shown in FIG. 3E, the dose amount Dext of the extension implantation monotonously increases or decreases as the deviation amount ΔLg from the design value of the gate length Lg increases or decreases. Adjustments are made as follows. However, when such adjustment is performed, the following problem occurs when the deviation direction from the design value of the gate length Lg is opposite to the deviation direction from the design value of the offset sidewall length Ls.
(1) When the gate length Lg is shorter than the design value and the offset sidewall length Ls is longer than the design value Since the gate length Lg is shorter than the design value, the dose amount of the source / drain extension region 10 is relatively In this case, the overlap length between the gate electrode 6A and the source / drain extension region 10 is reduced due to the offset sidewall length Ls being longer than the design value. The gate electrode 6A and the source / drain extension region 10 do not overlap (becomes an offset transistor and circuit characteristics deteriorate).
(2) When the gate length Lg is longer than the design value and the offset sidewall length Ls is shorter than the design value Since the gate length Lg is longer than the design value, the dose amount of the source / drain extension region 10 is relatively In such a case, the overlap length between the gate electrode 6A and the source / drain extension region 10 is increased due to the fact that the offset sidewall length Ls is shorter than the design value. The overlap length becomes excessive. If the overlap length between the gate electrode 6A and the source / drain extension region 10 becomes excessive, a leakage current such as GIDL increases and circuit characteristics deteriorate.

  In order to solve the above-mentioned problem (1), in this modification, as shown in FIG. 4, when the measured value of the offset sidewall length Ls is larger than the design value (when ΔLs> 0), the gate When the length Lg is smaller than a predetermined value (the one-dot chain line region on the left side in FIG. 4 (ΔLg <0)), the reduction of the extension injection dose is suppressed. Specifically, when the measured value of the offset sidewall length Ls is larger than the design value, the extension implantation dose is made constant when the gate length becomes smaller than a predetermined value. In this way, it is possible to prevent insufficient overlap between the gate electrode 6A and the source / drain extension region 10 (worst case, the gate electrode 6A and the source / drain extension region 10 do not overlap). Can be prevented. Although this modification avoids deterioration of characteristics due to insufficient overlap between the gate electrode 6A and the source / drain extension region 10, there is a possibility that slight deterioration of other characteristics such as threshold voltage may occur. Therefore, it is preferable to set the predetermined value in consideration of a trade-off between these characteristics. In addition, when the present modification is implemented at the wafer level, the overlap length between the gate electrode 6A and the source / drain extension region 10 is reliably set in consideration of variations in the wafer. It is preferable to secure about 0.5 nm or more.

  Further, in order to solve the above-mentioned problem (2), in this modification, as shown in FIG. 4, when the measured value of the offset sidewall length Ls is smaller than the design value (when ΔLs <0). When the gate length Lg is larger than the predetermined value (the one-dot chain line region on the right side in FIG. 4 (ΔLg> 0)), an increase in the dose amount of extension injection is suppressed. Specifically, when the measured value of the offset sidewall length Ls is smaller than the design value, when the gate length becomes larger than a predetermined value, the dose amount of extension implantation is made constant. In this way, excessive overlap between the gate electrode 6A and the source / drain extension region 10 can be prevented, so that deterioration of leak characteristics and circuit characteristics can be prevented. Although this modification avoids characteristic deterioration due to excessive overlap between the gate electrode 6A and the source / drain extension region 10, there is a possibility that slight deterioration may occur in other characteristics such as a threshold voltage. Therefore, it is preferable to set the predetermined value in consideration of a trade-off between these characteristics. In order to reliably prevent the occurrence of leakage current such as GIDL due to excessive overlap between the gate electrode 6A and the source / drain extension region 10, that is, reduction of the effective channel length, the overlap length between the two is set. It is preferable to set it to about 5 nm or less.

  In this modification, when the measured value of the offset sidewall length Ls is larger than the design value, the dose amount of the extension implantation is made constant when the gate length is smaller than the predetermined value. Instead, the reduction rate of ΔDext with respect to ΔLg may be relatively small.

  Further, in this modification, when the measured value of the offset sidewall length Ls is smaller than the design value, the dose amount of the extension implantation is made constant when the gate length becomes larger than the predetermined value. Instead, the increase rate of ΔDex with respect to ΔLg may be relatively small.

  Further, in the above-described embodiment or its modification, the deviation of the gate length and the offset sidewall length is compensated by the dose amount of the extension implantation. However, the present invention is not limited to this, and the deviation of the gate length and the offset sidewall length is compensated by the extension implantation. May be compensated by any one or a combination of two or more of the dose, implantation angle, and acceleration energy (including all combinations). Further, in place of or in addition to compensating for the deviation of the gate length and the offset sidewall length by the dose amount of the extension implantation or the like, any one of the dose amount, implantation angle and acceleration energy in the pocket implantation or Two or more combinations (including all combinations) may be compensated.

  Further, in the above-described embodiment or the modification thereof, the characteristic deterioration of the N-type MISFET due to the deviation of the gate length and the offset sidewall length is prevented, but a similar method is used instead of or in addition to this. Accordingly, the characteristic deterioration of the P-type MISFET due to the deviation of the gate length and the offset sidewall length may be prevented. In this case, the measurement of the gate length and the offset sidewall length may be performed for each of the N-type MISFET and the P-type MISFET, or a measured value for one of the MISFETs may be used as a representative value.

  In the above-described embodiment or its modification, the polysilicon film / silicon oxide film structure is used as the gate structure of the MISFET. However, the gate structure is not particularly limited. For example, the metal film / high− A k (high dielectric constant) film structure may be used.

  In the above-described embodiment or its modification, a single-layer silicon nitride film is used as the offset sidewall spacer 7. However, the structure of the offset sidewall spacer 7 is not particularly limited, and the offset sidewall spacer 7 is not limited. 7 may be, for example, a single layer silicon oxide film or a laminated film composed of a silicon oxide film and a silicon nitride film. Further, although a single layer silicon oxide film is used as the sidewall spacer 11, the structure of the sidewall spacer 11 is not particularly limited, and the sidewall spacer 11 may be, for example, a single layer silicon nitride film or Alternatively, a laminated film including a silicon oxide film and a silicon nitride film may be used.

  The present invention relates to a method of manufacturing a semiconductor device including a MISFET, and particularly to a MISFET having an offset sidewall structure and a source / drain extension structure after the 90 nm generation, and characteristics resulting from processing variations in gate length and offset sidewall length. Since the deterioration can be suppressed, it is useful for improving the performance of the semiconductor device and reducing the manufacturing cost.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 3 Active region 4 Channel region 5 Gate insulating film 6 Gate electrode film 6A Gate electrode 7 Offset sidewall spacer 10 Source / drain extension region 11 Side wall spacer 12 Source / drain region 13 Silicide film Lg Gate Gate length of electrode Lgs Gate length of gate electrode including offset sidewall spacer Ls Offset sidewall length

Claims (10)

A gate electrode formed on a semiconductor substrate; an offset sidewall spacer formed on a side surface of the gate electrode; and source / drain extension regions formed on both sides of the gate electrode on a surface portion of the semiconductor substrate; A method of manufacturing a semiconductor device including a transistor having
In order to set the amount of deviation from the design value of the gate length of the gate electrode, the amount of deviation from the design value of the spacer length of the offset sidewall spacer, and the characteristics of the transistor to the design value before manufacturing the semiconductor device. (A) obtaining a correlation with a dose amount of impurities implanted into the source / drain extension region;
(B) measuring the gate length of the gate electrode after forming the gate electrode;
(C) measuring the spacer length of the offset sidewall spacer after forming the offset sidewall spacer;
The amount of deviation from the design value of the gate length of the gate electrode measured in the step (b), the amount of deviation from the design value of the spacer length of the offset sidewall spacer measured in the step (c), and Based on the correlation obtained in the step (a), the dose of the impurity implanted into the source / drain extension region is set so that the deviation from the design value of the transistor characteristics falls within a predetermined range. And a step (d) of adjusting the semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
In the step (c), the gate length of the gate electrode including the offset sidewall spacer is measured, and half the value obtained by subtracting the gate length of the gate electrode measured in the step (b) from the measured value. Including a step of calculating as a spacer length of the offset sidewall spacer. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method of manufacturing a semiconductor device, wherein the characteristic of the transistor is a threshold voltage of the gate electrode. In the manufacturing method of the semiconductor device of any one of Claims 1-3,
The step (d) includes a step of adjusting a dose amount of impurities implanted into the source / drain extension region so that the gate electrode and the source / drain extension region overlap each other. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device given in any 1 paragraph of Claims 1-4,
The step (d) includes a step of reducing the dose of the impurity implanted into the source / drain extension region as the gate length of the gate electrode actually measured in the step (b) is smaller. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 5,
In the step (d), when the spacer length of the offset sidewall spacer measured in the step (c) is larger than a design value, the gate length of the gate electrode measured in the step (b) is predetermined. A method of manufacturing a semiconductor device, comprising a step of suppressing a reduction in dose of impurities implanted into the source / drain extension region when the value is smaller than the value. In the manufacturing method of the semiconductor device according to claim 5 or 6,
The step (d) includes a step of adjusting a dose amount of impurities implanted into the source / drain extension region so that the gate electrode and the source / drain extension region overlap each other by 0.5 nm or more. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device given in any 1 paragraph of Claims 1-4,
The step (d) includes a step of increasing the dose of the impurity implanted into the source / drain extension region as the gate length of the gate electrode actually measured in the step (b) increases. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 8,
In the step (d), when the spacer length of the offset sidewall spacer measured in the step (c) is smaller than a design value, the gate length of the gate electrode measured in the step (b) is predetermined. A method of manufacturing a semiconductor device, comprising the step of suppressing an increase in the dose of impurities implanted into the source / drain extension region when the value exceeds the value. In the manufacturing method of the semiconductor device according to claim 8 or 9,
The step (d) includes a step of adjusting a dose amount of impurities implanted into the source / drain extension region so that the gate electrode and the source / drain extension region overlap each other by 5 nm or less. A method of manufacturing a semiconductor device.

Images