JP2011238744A - Semiconductor light-emitting element and light-emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element used for, for example, flip-chip mounting, with less defective contact of an electrode with respect to a wiring board.SOLUTION: A semiconductor light-emitting element 1 of the present invention comprises an n-type semiconductor layer 140 including a Group III nitride semiconductor having a first conductivity type, a light-emitting layer 150 stacked on one plane of the n-type semiconductor layer 140 so as to partially expose the one plane and emitting light by electrical conduction, a p-type semiconductor layer 160 including a Group III nitride semiconductor having a second conductivity type different from the first conductivity type and stacked on the light-emitting layer 150, a first electrode 170 stacked on the p-type semiconductor layer 160 and including a metal reflection layer 172 for reflecting light emitted from the light-emitting layer 150, and a second electrode 180 extending from an exposure part of the one plane of the n-type semiconductor layer 140 and protruding to be higher than the first electrode.

Description

  The present invention relates to a semiconductor light emitting device including a group III nitride semiconductor.

  A semiconductor light emitting device using a group III nitride semiconductor such as GaN is usually configured by forming a group III nitride semiconductor layer including a light emitting layer on a substrate such as sapphire. Here, the light emitting layer is sandwiched between a p-type semiconductor layer whose conductivity is controlled to be p-type and an n-type semiconductor layer whose conductivity is controlled to be n-type. Then, light is emitted from the light emitting layer by energizing the p-type semiconductor layer and the n-type semiconductor layer. Here, a p-electrode is formed on the p-type semiconductor layer, and an n-electrode is formed on the surface of the n-type semiconductor layer. In order to form an n-electrode on the surface of the n-type semiconductor layer, it is usually necessary to etch from the p-type semiconductor layer up to the n-type contact layer of the n-type semiconductor layer. As a result, on the p-type semiconductor layer A step is created between the p-electrode formation position and the n-electrode formation position on the n-type semiconductor layer. Even if the p electrode and the n electrode are formed of the same electrode material, a step corresponding to the etching depth from the p-type semiconductor layer to the n-type contact layer is generally generated. As a result, when the n electrode and the p electrode of this light emitting element are wire bonded and mounted on the wiring board, the position of each electrode must be aligned and the process becomes complicated. there were. Furthermore, since the n electrode and the p electrode are not located on the same plane, flip chip mounting is difficult.

  On the other hand, as a conventional technique described in the publication, there is a method for manufacturing a semiconductor light emitting device that does not have a step and has a simple wafer process by forming an n electrode and a p electrode on the same plane (Patent Document 1). reference).

JP-A-10-294491

  However, when a semiconductor light emitting device in which the p-side electrode and the n-side electrode are formed on the same plane is mounted on a wiring board by flip chip, the contact failure of the n-side electrode with respect to the wiring board occurs. There is.

  An object of the present invention is to reduce the occurrence of contact failure of an electrode with respect to a wiring board in a semiconductor light emitting device used, for example, in flip chip mounting.

A semiconductor light emitting device to which the present invention is applied includes a first semiconductor layer composed of a group III nitride semiconductor having a first conductivity type, and a part of the one surface on one surface of the first semiconductor layer. A light emitting layer that is stacked so as to be exposed and emits light when energized; and a second semiconductor layer that is formed of a group III nitride semiconductor having a second conductivity type different from the first conductivity type and is stacked on the light emitting layer; A first electrode including a reflective layer that is laminated on the second semiconductor layer and has a reflectivity for light emitted from the light emitting layer, and extends from an exposed portion of the one surface of the first semiconductor layer, A second electrode protruding from the first electrode.
In such a semiconductor light emitting device, the first electrode further includes a transparent conductive layer stacked on the second semiconductor layer.

In addition, a light emitting device to which the present invention is applied includes a first semiconductor layer formed of a group III nitride semiconductor having a first conductivity type, and a part of the one surface on one surface of the first semiconductor layer. A second light emitting layer which is laminated to expose the light emitting layer and which is made of a group III nitride semiconductor having a second conductivity type different from the first conductivity type, and is laminated on the light emitting layer. A first electrode stacked on the second semiconductor layer, a second electrode extending from an exposed portion of the one surface of the first semiconductor layer, and protruding from the first electrode, and the first electrode A first connection portion provided at an end opposite to the second semiconductor layer side, and a second connection portion provided at an end opposite to the exposed portion side of the second electrode; The wiring board electrically connected with the said 1st connection part and the said 2nd connection part is included.
In such a light emitting device, the wiring board is provided substantially in parallel with the first semiconductor layer.
In the light emitting device, the first electrode further includes a transparent conductive layer stacked on the second semiconductor layer.

  According to the present invention, for example, in a semiconductor light emitting device used in flip chip mounting, it is possible to reduce the occurrence of electrode contact failure with respect to a wiring board.

It is an example of the cross-sectional schematic diagram of a semiconductor light-emitting device. It is an example of the cross-sectional schematic diagram of the laminated semiconductor layer which comprises a semiconductor light-emitting device. It is a figure which shows an example of the light-emitting device which flip-chip mounted the semiconductor light-emitting element on the board | substrate. It is a table which shows the experimental result in the Example of this invention.

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
FIG. 1 shows an example of a schematic cross-sectional view of a semiconductor light-emitting element (light-emitting diode) 1 to which the present embodiment is applied, and FIG. 2 shows an example of a schematic cross-sectional view of a laminated semiconductor layer 100 constituting the semiconductor light-emitting element 1. Is shown.

<Semiconductor light emitting device>
As shown in FIG. 1, the semiconductor light emitting device 1 includes a substrate 110, an intermediate layer 120 stacked on the substrate 110, and a base layer 130 stacked on the intermediate layer 120. Further, the semiconductor light emitting device 1 includes an n-type semiconductor layer 140 stacked on the base layer 130, a light-emitting layer 150 stacked on the n-type semiconductor layer 140, and a p-type semiconductor layer stacked on the light-emitting layer 150. 160. In the following description, the n-type semiconductor layer 140, the light emitting layer 150, and the p-type semiconductor layer 160 are collectively referred to as a laminated semiconductor layer 100 as necessary. In addition, the stacked semiconductor layer 100 may include the intermediate layer 120 and the base layer 130.

  Further, in the semiconductor light emitting device 1, the first electrode 170 formed on the upper surface 160c of the p-type semiconductor layer 160 and a part of the stacked p-type semiconductor layer 160, light-emitting layer 150, and n-type semiconductor layer 140 are cut out. And a second electrode 180 formed on the exposed surface 140c of the semiconductor layer 140 of the n-type semiconductor layer 140. Here, the semiconductor layer exposed surface 140c is formed so as to expose the periphery of the n-type semiconductor layer 140 over the entire circumference. As a result, in this semiconductor light emitting device 1, the substrate 110, the intermediate layer 120, the foundation layer 130, and the n-type semiconductor layer 140 are partially p-type with respect to the side wall surface of the n-type semiconductor layer 140 (on the foundation layer 130 side with respect to the semiconductor layer exposed surface 140c). Side wall surfaces of the semiconductor layer 160, the light emitting layer 150, and a part of the n-type semiconductor layer 140 (on the light emitting layer 150 side with respect to the semiconductor layer exposed surface 140c) are positioned more inside.

Furthermore, the semiconductor light emitting device 1 includes the first electrode 170 and the second electrode 180, the p-type semiconductor layer 160, the light emitting layer 150, and a part of the n-type semiconductor layer 140 (on the light emitting layer 150 side from the semiconductor layer exposed surface 140c). ) Is further provided. However, the protective layer 190 is formed so as to cover the entire sidewall surface of the p-type semiconductor layer 160, the light-emitting layer 150, and a part of the n-type semiconductor layer 140 (on the light-emitting layer 150 side with respect to the semiconductor layer exposed surface 140c). On the other hand, each of the first electrode 170 and the second electrode 180 is formed so as to expose a part of the upper surface in FIG.
As described above, the semiconductor light emitting device 1 according to the present embodiment has a structure in which the first electrode 170 and the second electrode 180 are formed on one surface side opposite to the substrate 110.

  In the semiconductor light emitting device 1, the first electrode 170 is a positive electrode and the second electrode 180 is a negative electrode, and the stacked semiconductor layer 100 (more specifically, the p-type semiconductor layer 160, the light-emitting layer 150, and the n-type semiconductor is interposed therebetween. The light emitting layer 150 emits light by passing a current through the layer 140).

Next, each component of the semiconductor light emitting element 1 will be described in more detail.
<Board>
The substrate 110 is not particularly limited as long as a group III nitride semiconductor crystal is epitaxially grown on the surface, and various substrates can be selected and used. However, since the semiconductor light emitting element 1 of the present embodiment is flip-chip mounted so as to extract light from the substrate 110 side, as described later, it has a light transmittance with respect to the light emitted from the light emitting layer 150. It is preferable. Therefore, for example, sapphire, zinc oxide, magnesium oxide, zirconium oxide, magnesium aluminum oxide, gallium oxide, indium oxide, lithium gallium oxide, lithium aluminum oxide, neodymium gallium oxide, lanthanum strontium aluminum tantalum, strontium titanium oxide, titanium oxide, etc. A substrate 110 made of can be used.
Further, among the above materials, it is particularly preferable to use sapphire whose C surface is a main surface as the substrate 110. When sapphire is used as the substrate 110, an intermediate layer 120 (buffer layer) is preferably formed on the C surface of sapphire.
Further, the surface of the substrate 110 where the laminated semiconductor layer 100 is not formed is preferably subjected to a surface roughening process in order to suppress warpage of the substrate 110.

<Laminated semiconductor layer>
The laminated semiconductor layer 100 as an example of the group III nitride semiconductor layer is a layer made of, for example, a group III nitride semiconductor, and as shown in FIG. 1, an n-type semiconductor layer 140, a light emitting layer are formed on the substrate 110. The layers 150 and p-type semiconductor layer 160 are stacked in this order.
As shown in FIG. 2, each of the n-type semiconductor layer 140, the light emitting layer 150, and the p-type semiconductor layer 160 may be composed of a plurality of semiconductor layers. Here, the n-type semiconductor layer 140 conducts electricity in the first conductivity type using electrons as carriers, and the p-type semiconductor layer 160 serves as the second conductivity type that uses holes as carriers. Conducts electricity.
Note that although the stacked semiconductor layer 100 can be formed with good crystallinity when formed by the MOCVD method, a semiconductor layer having crystallinity superior to that of the MOCVD method can be formed by optimizing the conditions also by the sputtering method. . Hereinafter, description will be made sequentially.

<Intermediate layer>
The intermediate layer 120 formed on the substrate 100 is preferably made of polycrystalline Al _x Ga _1-x N (0 ≦ x ≦ 1), and single crystal Al _x Ga _1-x N (0 ≦ x ≦ 1). ) Is more preferable.
As described above, the intermediate layer 120 can be, for example, made of polycrystalline Al _x Ga _1-x N (0 ≦ x ≦ 1) and having a thickness of 0.01 to 0.5 μm. If the thickness of the intermediate layer 120 is less than 0.01 μm, the intermediate layer 120 may not sufficiently obtain an effect of relaxing the difference in lattice constant between the substrate 110 and the base layer 130. In addition, when the thickness of the intermediate layer 120 exceeds 0.5 μm, the film forming process time of the intermediate layer 120 becomes longer and the productivity may be lowered, although the function as the intermediate layer 120 is not changed. There is.

  The intermediate layer 120 alleviates the difference in lattice constant between the substrate 110 and the base layer 130. In particular, when the substrate 110 is made of sapphire having a C plane as a main surface, the (0001) plane (C plane) of the substrate 110 is used. ) To facilitate the formation of a c-axis oriented single crystal layer on top. Therefore, by forming the intermediate layer 120, the base layer 130 with better crystallinity can be stacked thereon. In the present invention, it is preferable to form the intermediate layer 120, but it is not always necessary.

<Underlayer>
As the underlayer 130, Al _x Ga _y In _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) can be used, but Al _x Ga _1-x N It is preferable to use (0 ≦ x <1) because the base layer 130 with good crystallinity can be formed.
The film thickness of the underlayer 130 is preferably 0.1 μm or more, more preferably 0.5 μm or more, and most preferably 1 μm or more. An Al _x Ga _1-x N layer with good crystallinity is more easily obtained when the thickness is increased.
In order to improve the crystallinity of the underlayer 130, it is desirable that the underlayer 130 is not doped with impurities. However, when p-type or n-type conductivity is required, acceptor impurities or donor impurities can be added.

<N-type semiconductor layer>
As shown in FIG. 2, for example, an n-type semiconductor layer 140 as an example of a first semiconductor layer having a first conductivity type (n-type) using electrons as carriers includes an n-contact layer 140a and an n-cladding layer 140b. It has. Note that the above-described base layer 130 may be included in the n-type semiconductor layer 140.
The n contact layer 140 a is a layer for providing the second electrode 180. The n contact layer 140a is preferably composed of an Al _x Ga _1-x N layer (0 ≦ x <1, preferably 0 ≦ x ≦ 0.5, more preferably 0 ≦ x ≦ 0.1). .

The n-contact layer 140a is preferably doped with an n-type impurity, and the n-type impurity is preferably 1 × 10 ¹⁷ to 1 × 10 ²⁰ / cm ³ , preferably 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm. ^When it is contained at a concentration of ³ , it is preferable in that good ohmic contact with the second electrode 180 can be maintained. Although it does not specifically limit as an n-type impurity, For example, Si, Ge, Sn, etc. are mentioned, Preferably Si and Ge are mentioned.

  The thickness of the n contact layer 140a is preferably 0.5 to 5 μm, and more preferably set to a range of 1 to 3 μm. When the thickness of the n-contact layer 140a is in the above range, the crystallinity of the semiconductor is maintained well.

The n-cladding layer 140b is a layer that performs carrier injection and carrier confinement into the light-emitting layer 150, and is configured as a layer including a superlattice structure in this embodiment.
More specifically, the n-clad layer 140b is made of a group III nitride semiconductor, and the n-side first layer 141 having a film thickness of 100 nm (10 nm) or less and the n-side first layer 141 have a composition. It has a structure in which n-side second layers 142 made of different group III nitride semiconductors and having a thickness of 100 nm (10 nm) or less are alternately stacked. The n-clad layer 140b has a structure in which one n-side second layer 142 is sandwiched between two n-side first layers 141. The side in contact with the n-contact layer 140a and the side in contact with the light-emitting layer 150 are Each is an n-side first layer 141.

In the present embodiment, the n-side first layer 141 is made of GaInN, and the n-side second layer 142 is made of GaN. Here, when the n clad layer 140 b is formed including GaInN, it is desirable that GaInN constituting the n-side first layer 141 is larger than the GaInN band gap of the light emitting layer 150. Here, the In composition of the GaInN layer is desirably in the range of 0.5 to 3%. Instead of the configuration described above, the n-side first layer 141 may be made of AlGaN and the n-side second layer 142 may be made of GaN.
In this specification, AlGaN, GaN, and GaInN may be described in a form in which the composition ratio of each element is omitted.

The total film thickness of the n-clad layer 140b is not particularly limited, but is preferably 5 nm to 500 nm, and more preferably 5 nm to 100 nm. The n-type impurity concentration of the n-clad layer 140b is preferably 1.5 × 10 ^{17 to} 1.5 × 10 ²⁰ / cm ³ , more preferably 1.5 × 10 ^{18 to} 1.5 × 10 ¹⁹ / cm ³ . . An n-type impurity concentration in this range is preferable in terms of maintaining good crystallinity and reducing the operating voltage of the light emitting element.

<Light emitting layer>
As the light emitting layer 150 stacked on the n-type semiconductor layer 140, a single quantum well structure, a multiple quantum well structure, or the like can be employed. In the present embodiment, as shown in FIG. 2, the light emitting layer 150 has a multiple quantum well structure in which barrier layers 150a and well layers 150b are alternately stacked. The light emitting layer 150 is a barrier layer 150a on the side in contact with the n-cladding layer 140b and the side in contact with the p-cladding layer 160a (described later).

Here, as the well layer 150b, a group III nitride semiconductor layer made of Ga _1-y In _y N (0 <y <0.4) is usually used. The film thickness of the well layer 150b can be set to a film thickness that provides a quantum effect, for example, 1 to 10 nm, and preferably 2 to 6 nm, from the viewpoint of light emission output.
As the barrier layer 150a, Al _z Ga _1-z N (0 ≦ z <0.3) having a larger band gap energy than the well layer 150b is used. The well layer 150b and the barrier layer 150a may or may not be doped with impurities by design.
In the present embodiment, the light emitting layer 150 outputs blue light (emission wavelength λ = about 400 nm to 465 nm).

<P-type semiconductor layer>
As shown in FIG. 2, for example, a p-type semiconductor layer 160 as an example of a second semiconductor layer having a second conductivity type (p-type) using holes as carriers is generally composed of a p-cladding layer 160 a and a p-contact. It is composed of the layer 160b. However, the p contact layer 160b can also serve as the p clad layer 160a.

The p-cladding layer 160a is a layer that performs confinement of carriers in the light emitting layer 150 and injection of carriers. The p-cladding layer 160a is not particularly limited as long as it has a composition larger than the band gap energy of the light-emitting layer 150 and can confine carriers in the light-emitting layer 150, but is preferably Al _x Ga _1-x N. (0 <x ≦ 0.4).

It is preferable that the p-cladding layer 160a is made of such AlGaN from the viewpoint of confining carriers in the light-emitting layer 150. The film thickness of the p-cladding layer 160a is not particularly limited, but is preferably 1 to 400 nm, more preferably 5 to 100 nm.
The p-type impurity concentration in the p-cladding layer 160a is preferably 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , more preferably 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ . When the p-type impurity concentration is in the above range, a good p-type crystal can be obtained without reducing the crystallinity.
Further, the p-cladding layer 160a may have a superlattice structure similar to the above-described n-cladding layer 140b. In this case, AlGaN and GaN having different structures or different compositions of AlGaN and other AlGaN having different composition ratios. It is preferable that this is an alternate structure.

The p contact layer 160 b is a layer for providing the first electrode 170. The p contact layer 160b is preferably Al _x Ga _1-x N (0 ≦ x ≦ 0.4). When the Al composition is in the above range, it is preferable in that good crystallinity and good ohmic contact with the first electrode 170 can be maintained.
When p-type impurities are contained at a concentration of 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , preferably 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ , good ohmic contact is maintained, cracks It is preferable in terms of prevention of generation and maintaining good crystallinity. Although it does not specifically limit as a p-type impurity, For example, Preferably Mg is mentioned.
The thickness of the p contact layer 160b is not particularly limited, but is preferably 0.01 to 0.5 μm, and more preferably 0.05 to 0.2 μm. When the film thickness of the p-contact layer 160b is within this range, it is preferable in terms of light emission output.

<First electrode>
Next, the configuration of the first electrode 170 will be described in detail.
The first electrode 170 is preferably a first conductive layer 171 stacked on the upper surface 160c of the p-type semiconductor layer 160, a metal reflective layer 172 stacked on the first conductive layer 171 and a stack thereon. The first bonding layer 174 is provided so as to cover the first bonding layer 174 except for the exposed portion of the first bonding layer 174 described above, and a protective layer 190 is provided on the surface opposite to the first bonding layer 174. And a first adhesion layer 175 to be laminated.
Note that the first diffusion preventing layer 173 may be provided between the metal reflective layer 172 and the first bonding layer 174. Here, FIG. 1 illustrates a case where the first diffusion prevention layer 173 is provided as a preferable example.

<First conductive layer>
As shown in FIG. 1, the first conductive layer 171 is preferably stacked on the p-type semiconductor layer 160. The first conductive layer 171 (see FIG. 1) is a peripheral portion of the upper surface 160c of the p-type semiconductor layer 160 that is partially removed by means such as etching in order to form the second electrode 180 when viewed in plan. It is formed to cover almost the entire surface except for. The central portion of the first conductive layer 171 has a constant film thickness and is substantially flat with respect to the upper surface 160c. On the other hand, the end portion of the first conductive layer 171 is p-type because the film thickness is gradually reduced. The semiconductor layer 160 is formed to be inclined with respect to the upper surface 160c. However, the first conductive layer 171 is not limited to such a shape, and may be formed in a lattice shape or a tree shape with a gap, or may have a rectangular cross section. .

  As the first conductive layer 171 as an example of the transparent conductive layer, it is preferable to use a layer having an ohmic contact with the p-type semiconductor layer 160 and having a low contact resistance with the p-type semiconductor layer 160. Moreover, in this semiconductor light emitting element 1, since the light from the light emitting layer 150 is taken out to the substrate 110 side through the metal reflecting layer 172, it is preferable to use the first conductive layer 171 having excellent light transmittance. . Furthermore, in order to uniformly diffuse the current over the entire surface of the p-type semiconductor layer 160, it is preferable to use the first conductive layer 171 having excellent conductivity and a small resistance distribution. In the present embodiment, the thickness of the first conductive layer 171 is set to 5 nm (50 mm). Note that the thickness of the first conductive layer 171 can be selected from a range of 2 nm to 500 nm. Here, if the thickness of the first conductive layer 171 is less than 2 nm, it may be difficult to make ohmic contact with the p-type semiconductor layer 160. If the thickness of the first conductive layer 171 is greater than 500 nm, In some cases, the light emission from the light emitting layer 150 and the light transmittance of the reflected light from the metal reflective layer 172 are not preferable.

An example of the first conductive layer 171 is a transparent conductive layer. For example, in this embodiment, as the first conductive layer 171, an oxide conductive material that has high light transmittance with respect to light having a wavelength emitted from the light-emitting layer 150 is used. In particular, a part of the oxide containing In is preferable in that both light transmittance and conductivity are superior to other transparent conductive films. As the conductive oxide containing In, for example, ITO (indium tin oxide (In ₂ O ₃ —SnO ₂ )), IZO (indium zinc oxide (In ₂ O ₃ —ZnO)), IGO (indium gallium oxide (In ₂ O ₃ —Ga ₂ O ₃ )), ICO (indium cerium oxide (In ₂ O ₃ —CeO ₂ )) and the like. In addition, for example, a dopant such as fluorine may be added. For example, an oxide containing no In, for example, a conductive material such as SnO ₂ , ZnO ₂ , or TiO ₂ doped with carriers may be used.
The first conductive layer 171 can be formed by providing these materials by conventional means well known in the art. In addition, after the first conductive layer 171 is formed, thermal annealing may be performed for the purpose of making the first conductive layer 171 transparent and further reducing resistance.

In the present embodiment, the first conductive layer 171 may have a crystallized structure, and in particular, a light-transmitting material including an In ₂ O ₃ crystal having a hexagonal crystal structure or a bixbite structure (for example, ITO, IZO, etc.) can be preferably used.
For example, in the case where IZO containing In ₂ O ₃ crystal having a hexagonal crystal structure is used as the first conductive layer 171, it can be processed into a specific shape using an amorphous IZO film having excellent etching properties, and then heat treatment is performed. By transferring the structure from an amorphous state to a structure including a crystal by, for example, an electrode having a light-transmitting property better than that of an amorphous IZO film.

In addition, as the IZO film used for the first conductive layer 171, it is preferable to use a composition having the lowest specific resistance.
For example, the ZnO concentration in IZO is preferably 1 to 20% by mass, more preferably 5 to 15% by mass, and particularly preferably 10% by mass.

Heat treatment of the IZO film used for the first conductive layer 171 is desirably performed in an atmosphere containing no O _2, as the atmosphere containing no O _2, or an inert gas atmosphere such as N ₂ atmosphere, or such as N ₂ A mixed gas atmosphere of an inert gas and H ₂ can be given, and it is desirable to use an N ₂ atmosphere or a mixed gas atmosphere of N ₂ and H ₂ . When the heat treatment of the IZO film is performed in an N ₂ atmosphere or a mixed gas atmosphere of N ₂ and H ₂ , for example, the IZO film is crystallized into a film containing In ₂ O ₃ crystal having a hexagonal structure, It is possible to effectively reduce the sheet resistance of the IZO film.
Further, the heat treatment temperature of the IZO film is preferably 500 ° C. to 1000 ° C. When heat treatment is performed at a temperature lower than 500 ° C., the IZO film may not be sufficiently crystallized, and the light transmittance of the IZO film may not be sufficiently high. When heat treatment is performed at a temperature exceeding 1000 ° C., the IZO film is crystallized, but the light transmittance of the IZO film may not be sufficiently high. In addition, when heat treatment is performed at a temperature exceeding 1000 ° C., the semiconductor layer under the IZO film may be deteriorated.

In particular, as described above, an IZO film crystallized by heat treatment is very effective in the embodiment of the present invention because it has better adhesion to the p-type semiconductor layer 160 than an amorphous IZO film. Further, IZO film crystallized by heat treatment, as compared with the IZO film in an amorphous state, since the resistance value is lowered, at the time of constructing a semiconductor light emitting element 1, also preferred because it reduces the forward voltage V _F.

<Metal reflective layer>
As shown in FIG. 1, a metal reflective layer 172 is stacked on the first conductive layer 171.
The metal reflective layer 172 (see FIG. 1) is formed so as to cover the entire area of the first conductive layer 171 when viewed in plan. The central portion of the metal reflective layer 172 has a constant film thickness and is substantially flat. On the other hand, the end of the metal reflective layer 172 gradually decreases in thickness so that the upper surface 160c of the p-type semiconductor layer 160 is formed. It is inclined with respect to. Further, the metal reflection layer 172 is formed on the first conductive layer 171 and is not formed on the p-type semiconductor layer 160. That is, the p-type semiconductor layer 160 and the metal reflective layer 172 are configured not to contact directly.

The metal reflection layer 172 is made of Ag (silver). The reason why silver is used as the metal reflection layer 172 is that it has high light reflectivity with respect to light having a wavelength in a blue to green region emitted from the light emitting layer 150. As will be described later, the metal reflective layer 172 also has a function of supplying power to the p-type semiconductor layer 160 via the first conductive layer 171, so that the resistance value is low and the first conductive layer is also provided. This is because the contact resistance with 171 needs to be kept low. In this embodiment, the thickness of the metal reflection layer 172 is set to 150 nm (1500 mm). The thickness of the metal reflective layer 172 can be preferably selected from a range of 50 nm or more. Here, when the thickness of the metal reflective layer 172 is less than 50 nm, it may be undesirable in that the performance of reflecting light from the light emitting layer 150 is lowered.
In this embodiment, single Ag is used as the metal reflective layer 172, but an alloy containing Ag may be used.

<First diffusion prevention layer>
As shown in FIG. 1, a first diffusion prevention layer 173 is preferably laminated on the metal reflection layer 172. The first diffusion preventing layer 173 is provided to suppress diffusion of the metal (in this example, Ag (silver)) that constitutes the metal reflective layer 172 in a contact state.
The first diffusion prevention layer 173 is formed so as to cover the entire region of the metal reflection layer 172 when viewed in plan. The central portion of the first diffusion prevention layer 173 has a constant film thickness and is formed almost flat, while the end portion side of the first diffusion prevention layer 173 is gradually reduced in thickness so that the p-type semiconductor is formed. The layer 160 is formed to be inclined with respect to the upper surface 160c. The first diffusion prevention layer 173 is formed on the metal reflection layer 172 and is not formed on the p-type semiconductor layer 160. That is, the p-type semiconductor layer 160 and the first diffusion prevention layer 173 are configured not to contact directly.

  As the first diffusion preventing layer 173, it is preferable to use a layer having an ohmic contact with the metal reflective layer 172 and having a low contact resistance with the metal reflective layer 172. However, as will be described later, the first diffusion prevention layer 173 basically does not require a function of transmitting light from the light emitting layer 150, and therefore has a light transmission property unlike the first conductive layer 171. There is no need. Note that, from the viewpoint of increasing the light extraction efficiency from the light emitting layer 150 as described later, it is desirable to use a material that absorbs less light emitted from the light emitting layer 150 as the first diffusion preventing layer 173. Further, as will be described later, the first diffusion prevention layer 173 has a function of supplying power to the p-type semiconductor layer 160 through the metal reflection layer 172 and the first conductive layer 171, and thus has excellent conductivity. It is preferable to use one having a low resistance distribution.

  In the present embodiment, the thickness of the first diffusion preventing layer 173 is set to 50 nm (500 mm). In the present embodiment, if the thickness of the first diffusion preventing layer 173 is 50 nm or more, it is preferable in that the migration of Ag (silver) constituting the metal reflective layer 172 is easily suppressed. On the other hand, if the thickness of the first diffusion prevention layer 173 is less than 50 nm, it is not preferable in terms of preventing migration of Ag (silver) to the first bonding layer 174 formed on the first diffusion prevention layer 173. Further, if the thickness of the first diffusion preventing layer 173 is thicker than 5000 nm, it is not preferable from the viewpoint of increasing the cost of the material. In the present embodiment, each thickness is set such that the thickness of the first conductive layer 171 is thinner than the thickness of the first diffusion prevention layer 173.

  In the present embodiment, IZO is used as the first diffusion prevention layer 173 in the same manner as the first conductive layer 171. However, since the heat treatment is not performed on the IZO constituting the first diffusion prevention layer 173, it remains in an amorphous state.

As the first diffusion preventing layer 173, ITO, IGO, ICO or the like can be used in addition to IZO. Further, for example, a conductive material such as SnO ₂ , ZnO ₂ , or TiO ₂ doped with carriers may be used. Furthermore, a metal material such as Ni (nickel) or Ti (titanium) may be used.

<First bonding layer>
As shown in FIG. 1, a first bonding layer 174 is laminated on the upper surface and side surfaces of the first diffusion prevention layer 173 so as to cover the first diffusion prevention layer 173.
The first bonding layer 174 is formed so as to cover the entire region of the first diffusion preventing layer 173 when viewed in plan. The central portion of the first bonding layer 174 has a constant thickness and is formed almost flat, while the end portion of the first bonding layer 174 is gradually reduced in thickness so that the p-type semiconductor layer 160 is formed. The upper surface 160c is inclined.

  The first bonding layer 174 includes at least one metal layer and is formed so that the innermost layer is in contact with the first diffusion prevention layer 173 and the like. Further, Au (gold) is generally used for the outermost metal layer that is the outermost layer. In this embodiment, a single layer film of Au (gold) is used as the first bonding layer 174, but for example, a Ni (nickel) layer as a first layer formed in contact with the first diffusion prevention layer 173 A structure having a Pt (platinum) layer as a second layer formed outside the Ni layer and an Au (gold) layer as a third layer formed outside and outside the Pt layer May be adopted. In the present embodiment, the entire thickness of the first bonding layer 174 is set to 300 nm (3000 mm). The total thickness of the first bonding layer 174 can be used without limitation as long as it has a function as a pad electrode in flip-chip mounting, but preferably 50 nm (500 mm) or more. It is set to 8000 nm (80000 mm).

  In the case where the first bonding layer 174 is composed of a plurality of metal layers, the material constituting the first layer in contact with the first diffusion prevention layer 173 includes Ta (tantalum) in addition to the above-described Ni (nickel), Ti (titanium), NiTi (nickel titanium) alloy, and nitrides thereof can be used.

<First adhesion layer>
As shown in FIG. 1, a first adhesion layer 175 is preferably laminated on the upper surface and side surfaces of the first bonding layer 174 so as to cover the first bonding layer 174.
The first adhesion layer 175 is formed so as to cover a region excluding the exposed portion of the first bonding layer 174 when seen in a plan view. The central portion of the first adhesion layer 175 has a constant thickness and is substantially flat, while the end portion of the first adhesion layer 175 is inclined with respect to the upper surface 160c of the p-type semiconductor layer 160. Is formed. The end portion on the side surface side of the first adhesion layer 175 is provided so as to be in contact with the upper surface 160 c of the p-type semiconductor layer 160.

  The first adhesion layer 175 is provided to improve the physical adhesion between the first bonding layer 174 made of Au (gold) and the protective layer 190. In the present embodiment, the first adhesion layer 175 is made of Ta (tantalum). However, as the first adhesion layer 175, for example, Ti (titanium) or Ni (nickel) can be used in addition to Ta (tantalum). In the present embodiment, the thickness of the first adhesion layer 175 is set to 10 nm (100 mm). The thickness of the first adhesion layer 175 is preferably 5 nm to 400 nm, more preferably 5 nm to 300 nm, and still more preferably 7 nm to 100 nm. If the thickness of the first adhesion layer 175 is less than 5 nm, the bonding strength of the first adhesion layer 175 is not preferable.

<Second electrode>
Next, the configuration of the second electrode 180 will be described in detail.
The second electrode 180 is preferably a second conductive layer 181 stacked on the semiconductor layer exposed surface 140c of the n-type semiconductor layer 140, a second bonding layer 183 stacked on the second conductive layer 181; A second adhesive layer 184 is provided so as to cover the second bonding layer 183 except for the exposed portion of the second bonding layer 183 described above, and a protective layer 190 is laminated on the surface opposite to the second bonding layer 183. have.
A second diffusion prevention layer 182 may be provided between the second conductive layer 181 and the second bonding layer 183. Here, FIG. 1 illustrates a case where the second diffusion prevention layer 182 is provided as a preferred example.

<Second conductive layer>
As shown in FIG. 1, a second conductive layer 181 is preferably stacked on the n-type semiconductor layer 140.
The second conductive layer 181 (see FIG. 1) has a circular outer shape when seen in a plan view. The central portion of the second conductive layer 181 has a constant thickness and is substantially flat with respect to the exposed surface 140c of the semiconductor layer, while the end portion of the second conductive layer 181 has a gradually decreasing thickness. The n-type semiconductor layer 140 is formed to be inclined with respect to the semiconductor layer exposed surface 140c. However, the second conductive layer 181 is not limited to such a shape, and may be formed in a lattice shape or a tree shape with a gap, or may have a rectangular cross section. Further, it may have an outer shape other than a circular shape.

The second conductive layer 181 is preferably made of an ohmic contact with the n-type semiconductor layer 140 and having a low contact resistance with the n-type semiconductor layer 140.
In this embodiment, Al (aluminum) is used for the second conductive layer 181. Al (aluminum) constituting the second conductive layer 181 has a wavelength in the blue to green region emitted from the light emitting layer 150, similar to Ag (silver) constituting the metal reflective layer 172 of the first electrode 170 described above. It has high light reflectivity with respect to light, and this also functions as a metal reflection layer. In the present embodiment, the thickness of the second conductive layer 181 is set to 100 nm (1000 mm). Note that the thickness of the second conductive layer 181 can be selected from a range of 50 nm to 1000 nm. Here, if the thickness of the second conductive layer 181 is less than 50 nm, the light extraction efficiency is reduced due to light transmission, and if the thickness of the second conductive layer 181 is greater than 100 nm. In some cases, the film is not preferable in terms of reliability, for example, the resist is heated and the resist residue is likely to be generated due to the long film formation time.

<Second diffusion prevention layer>
As shown in FIG. 1, the second diffusion prevention layer 182 is preferably laminated on the second conductive layer 181. The second diffusion prevention layer 182 is provided to suppress the diffusion of the metal (in this example, Al (aluminum)) constituting the second conductive layer 181 in contact.
The second diffusion prevention layer 182 is formed so as to cover the entire region of the second conductive layer 181 when viewed in plan. The central portion of the second diffusion barrier layer 182 has a constant film thickness and is formed almost flat, while the end portion of the second diffusion barrier layer 182 is gradually reduced in thickness so that the n-type semiconductor layer is formed. The semiconductor layer 140 is formed to be inclined with respect to the exposed surface 140c of the semiconductor layer. Further, the second diffusion prevention layer 182 is formed on the second conductive layer 181 and is not formed on the n-type semiconductor layer 140. That is, the n-type semiconductor layer 140 and the second diffusion prevention layer 182 are configured not to contact directly.

  In the present embodiment, the thickness of the second diffusion prevention layer 182 is set to 100 nm (1000 mm). In the present embodiment, it is preferable that the thickness of the second diffusion prevention layer 182 is 50 nm or more because migration of Al (aluminum) constituting the second conductive layer 181 is easily suppressed. On the other hand, if the thickness of the second diffusion prevention layer 182 is less than 50 nm, it is not preferable in terms of preventing migration of Al (aluminum) to the second bonding layer 183 formed on the second diffusion prevention layer 182. Further, if the thickness of the second diffusion prevention layer 182 is thicker than 5000 nm, it is not preferable from the viewpoint of increasing the cost of the material.

In the present embodiment, Pt (platinum) is used as the second diffusion preventing layer 182.
The second diffusion prevention layer 182 may be made of a metal material such as Rh (rhodium) or W (tungsten) in addition to Pt (platinum).

<Second bonding layer>
As shown in FIG. 1, a second bonding layer 183 is laminated on the second diffusion prevention layer 182.
As shown in FIG. 2, the second bonding layer 183 is formed so as to cover the entire region of the second diffusion preventing layer 182. The central portion of the second bonding layer 183 has a constant thickness and is substantially flat, while the end portion of the first bonding layer 174 has a thickness that is gradually reduced. The semiconductor layer is formed to be inclined with respect to the exposed surface 140c.

  Similar to the first bonding layer 174 of the first electrode 170 described above, the second bonding layer 183 includes at least one metal layer and is formed so that the innermost layer is in contact with the first diffusion prevention layer 173 and the like. The Further, Au (gold) is generally used for the outermost metal layer that is the outermost layer. In the present embodiment, the second bonding layer 183 is formed of the same Au (gold) single layer film as the first bonding layer 174. In the present embodiment, the total thickness of the second bonding layer 183 is set to 1000 nm (10000 mm). The total thickness of the second bonding layer 183 is also preferably set to 50 nm (500 mm) to 8000 nm (80000 mm). Note that, as described with respect to the first diffusion preventing layer 173, the second bonding layer 183 may have a stacked structure of a plurality of metal layers.

<Second adhesion layer>
As shown in FIG. 1, the second adhesion layer 184 is preferably laminated on the second bonding layer 183.
The second adhesion layer 184 is formed so as to cover a region excluding the exposed portion of the second bonding layer 183 when viewed in plan. The central portion of the second adhesion layer 184 has a constant film thickness and is substantially flat, while the end portion side of the second adhesion layer 184 is opposite the semiconductor layer exposed surface 140c of the n-type semiconductor layer 140. Inclined. The end portion on the side surface side of the second adhesion layer 184 is provided so as to be in contact with the semiconductor layer exposed surface 140 c of the n-type semiconductor layer 140.

  Similar to the first adhesion layer 175 of the first electrode 170 described above, the second adhesion layer 184 improves the physical adhesion between the second bonding layer 183 made of Au (gold) and the protective layer 190. It is provided for. In the present embodiment, the second adhesion layer 184 is made of Ta (tantalum), like the first adhesion layer 175. However, for example, Ti (titanium) or Ni (nickel) can be used as the second adhesion layer 184 in addition to Ta (tantalum). In the present embodiment, the thickness of the second adhesion layer 184 is set to 10 nm (100 mm). The thickness of the second adhesion layer 184 is preferably 5 nm to 400 nm, more preferably 5 nm to 300 nm, and even more preferably 7 nm to 100 nm. If the thickness of the second adhesion layer 184 is less than 5 nm, it is not preferable because the bonding strength of the second adhesion layer 184 decreases.

<Protective layer>
As shown in FIG. 1, the protective layer 190 covers the first electrode 170 and the second electrode 180. More specifically, the protective layer 190 is a first adhesion layer that is a surface of the first electrode layer 170 opposite to the substrate 110 except for a part of the first electrode 170 and a part of the second electrode 180. The upper surface 175c and the second adhesion layer upper surface 184c, which is the surface of the second electrode layer 180 opposite to the substrate 110, are covered.
Furthermore, the protective layer 190 is laminated so as to cover a part of the p-type semiconductor layer 160, the light-emitting layer 150, and the n-type semiconductor layer 140 (the light-emitting layer 150 side with respect to the semiconductor layer exposed surface 140c). The protective layer 190 has a function of preventing water and the like from entering the light emitting layer 150, the first electrode 170, and the second electrode 180 from the outside and protecting them. In the present embodiment, the protective layer 190 is made of SiO ₂ (silicon oxide).

<Relationship between first electrode and second electrode>
Here, looking at the relationship between the first electrode 170 and the second electrode 180, the end of the second electrode 180 and the end opposite to the substrate 110 is the end of the first electrode 170. Compared with the end opposite to the substrate 110, it protrudes. When the protruding portion of the end of the second electrode 180 is a step compared to the end of the first electrode 170, the height of the step is preferably more than 10 nm in the present invention, and more than 100 nm. More preferably. Moreover, it is preferable that this level | step difference is 3 micrometers or less.
In the present invention, more specifically, when the second adhesion layer upper surface 184 c of the second electrode 180 and the first adhesion layer upper surface 175 c of the first electrode layer 170 are compared with each other in the positional relationship with the substrate 110, The adhesion layer upper surface 184 c is disposed at a position farther from the substrate 110. In other words, when considering the height from the substrate 110, the height of the second electrode 180 is higher than the height of the first electrode 170.
Furthermore, in the present invention, the second solder 22 (also referred to as Au plating bump) provided on the second adhesion layer upper surface 184c of the second electrode 180 and the first adhesion layer upper surface 175c of the first electrode 170 are provided. Alternatively, when the first solder 21 (also referred to as Au plating bump) provided on the first bonding layer 174 is compared with the substrate 110, the second solder 22 is farther from the substrate 110. Placed in position. That is, the semiconductor light emitting device has a configuration in which the height of the second electrode 180 including the second solder 22 is higher than the height of the first electrode 170 including the first solder 21. Also good.
In this case, the first electrode 170 and the second electrode 180 of the semiconductor light emitting element 1 are provided with solder (also referred to as Au plating bumps), and the semiconductor light emitting element 1 is used to further pass Au, tin, and solder. It may be mounted on a wiring board.

Next, a method for using the semiconductor light emitting device 1 shown in FIG. 1 will be described.
FIG. 3 is a diagram illustrating an example of a configuration of a light emitting device in which the semiconductor light emitting element 1 illustrated in FIG. 1 is mounted on the wiring substrate 10.
A positive electrode 11 and a negative electrode 12 are formed on one surface of the wiring substrate 10.
Then, the first electrode 170 (specifically, the first bonding layer 174) is applied to the positive electrode 11 in a state where the top and bottom of the semiconductor light emitting element 1 shown in FIG. A second electrode 180 (specifically, the second bonding layer 183) is electrically connected to the electrode 12 using the first solder 21 and the second solder 22, and is mechanically fixed thereto. Such a connection method of the semiconductor light emitting element 1 to the wiring substrate 10 is generally called flip chip connection. In the flip-chip connection, the substrate 110 of the semiconductor light emitting element 1 is placed at a position farther from the light emitting layer 150 when viewed from the wiring substrate 10.

  As described above, when the heights of the first electrode 170 and the second electrode 180 from the substrate 110 are compared, the second electrode 180 is higher than the first electrode 170. However, by adjusting the first solder 21 and the second solder 22, the substrate 110 of the semiconductor light emitting element 1 and the wiring substrate 10 can be installed substantially in parallel. As shown in FIG. 3, the length of the second solder 22 on the second electrode 180 side is the length on the first electrode 170 side with respect to the length in the height direction with respect to the substrate 110 of the semiconductor light emitting element 1. By making it shorter than the length of the first solder 21. Here, “substantially parallel” includes parallel.

Then, considering the height from the substrate 110, the height of the second electrode 180 is higher than the height of the first electrode 170, so that the occurrence of electrical contact failure can be reduced.
This will be specifically described. First, for example, consider a case where the height of the first electrode 170 is higher than the height of the second electrode 180. As shown in FIG. 1, since the area of the first electrode 170 is larger than that of the second electrode 180, only the first electrode 170 comes into contact with the wiring board 10 side when being fixed to the wiring board 10. Thus, it is conceivable that the second electrode 180 is fixed without contacting the wiring substrate 10 side. In this case, the possibility that the second electrode 180 causes an electrical contact failure with the wiring board 10 side is increased. On the other hand, when the height of the second electrode 180 is higher than the height of the first electrode 170, the second electrode 180 is more reliably brought into contact with the wiring substrate 10 side and fixed. Therefore, the occurrence of contact failure between the second electrode 180 and the wiring board 10 can be reduced.
Here, in this technical field, in order to improve the light extraction efficiency, it is desired to further reduce the area of the second electrode 180. On the other hand, the reduction in the area of the second electrode 180 makes it more difficult to establish conduction between the second electrode 180 and the n-type semiconductor layer 140. From such a technical background, the above-described configuration that reduces the occurrence of contact failure between the second electrode 180 and the substrate 110 and ensures conduction is particularly effective.

Further, considering the height from the substrate 110, the following effects can be obtained by making the height of the second electrode 180 higher than the height of the first electrode 170. For example, even if the semiconductor light emitting device 1 is manufactured so that the height of the second electrode 180 is the same as that of the first electrode 170, the second electrode 180 may be higher due to manufacturing variations or vice versa. In some cases, the second electrode 180 is lower. When such a semiconductor light emitting element 1 is fixed to the wiring substrate 10, the second electrode 180 is also fixed when inclined to the first electrode 170 side (the first electrode 170 side is fixed closer to the wiring substrate 10). In some cases, the second electrode 180 is fixed while being inclined (the second electrode 180 side is fixed closer to the wiring board 10). That is, the semiconductor light emitting element 1 may be tilted in both directions on the first electrode 170 side and the second electrode 180 side.
However, when the semiconductor light emitting device 1 is manufactured so that the height of the second electrode 180 is higher than the height of the first electrode 170 in terms of the height from the substrate 110, the semiconductor light emitting device 1 is disposed on the first electrode 170 side. The possibility of being tilted and being fixed increases. Therefore, it becomes easier to control the light emitted from the semiconductor light emitting element 1.

Now, the light emitting operation of the light emitting device will be described with reference to FIG.
When a current from the positive electrode 11 to the negative electrode 12 is passed through the semiconductor light emitting device 1 via the positive electrode 11 and the negative electrode 12 of the wiring substrate 10, the semiconductor light emitting device 1 has the first electrode 170 to the p-type semiconductor layer 160. Current flowing toward the second electrode 180 flows through the light emitting layer 150 and the n-type semiconductor layer 140, and blue light is output from the light emitting layer 150. At this time, in the first electrode 170, current flows through the first bonding layer 174, the first diffusion prevention layer 173, the metal reflection layer 172, and the first conductive layer 171, and the p-type semiconductor layer 160 has a top surface. The current in a uniform state is supplied on the surface 160c.

  Of the light output from the light emitting layer 150, the light traveling toward the substrate 110 passes through the n-type semiconductor layer 140, the base layer 130, the intermediate layer 120, and the substrate 110, and is shown in the arrow direction shown in FIG. It is emitted to the outside.

  On the other hand, the light emitted from the light emitting layer 150 toward the first electrode 170 side reaches the metal reflection layer 172 via the p-type semiconductor layer 160 and the first conductive layer 171 and is reflected by the metal reflection layer 172. Is done. Then, the light reflected by the metal reflection layer 172 passes through the first conductive layer 171, the p-type semiconductor layer 160, the light emitting layer 150, the n-type semiconductor layer 140, the base layer 130, the intermediate layer 120, and the substrate 110, and FIG. Is emitted to the outside of the semiconductor light emitting element 1.

  Here, in the present embodiment, by providing the metal reflective layer 172 on the first electrode 170, the extraction efficiency of light output from the semiconductor light emitting element 1 can be improved. In addition, since the metal reflection layer 172 functions both as an electrode and a mirror, the configuration of the semiconductor light emitting element 1 can be simplified.

Next, although the Example of this invention is described using FIG. 4, this invention is not limited to an Example. Here, FIG. 4 is a table showing experimental results in the embodiments of the present invention, and shows the defect rate in each embodiment. In addition, each column in the row | line | column of the 1st electrode and 2nd electrode in FIG. 4 shows the material and thickness of each layer.
Example 1
<Fabrication of semiconductor light emitting device>
As a specific example of the present embodiment, a semiconductor light emitting device 1 made of a gallium nitride compound semiconductor was manufactured as follows. First, an underlayer 130 made of undoped GaN (gallium nitride) having a thickness of 5 μm was formed on a substrate 110 made of sapphire via an intermediate layer 120 (buffer layer) made of AlN (aluminum nitride). Next, after forming a Si-doped n-type GaN contact layer having a thickness of 2 μm and an n-type In _0.1 Ga _0.9 N cladding layer having a thickness of 250 nm, a Si-doped GaN barrier layer having a thickness of 16 nm and a thickness of 2 A light emitting layer 150 having a multiple quantum well structure in which a .5 nm In _0.2 Ga _0.8 N well layer was stacked five times and a barrier layer was finally provided was formed.
Further, a 10 nm thick Mg (magnesium) doped p-type Al _0.07 Ga _0.93 N cladding layer and a 150 nm thick Mg-doped p-type GaN contact layer were formed in this order to produce a semiconductor wafer.
The gallium nitride-based compound semiconductor layer was stacked by MOCVD under normal conditions well known in the technical field. However, the intermediate layer made of AlN was formed by sputtering under normal conditions well known in the art.

Next, in order to fabricate the 350 μm square semiconductor light emitting device 1, a substantially square opening having a side length of 320 μm (in the schematic cross-sectional view of the semiconductor light emitting device 1 in FIG. 1, the first conductive layer 171 is formed). A first mask having a shape of an opening that can be formed was formed. As the resist, AZ5200NJ (product name: manufactured by AZ Electronic Materials Co., Ltd.) was used.
Next, with the first mask, the first conductive layer 171 made of IZO having a thickness of 5 nm, the metal reflective layer 172 made of Ag having a thickness of 150 nm, and the IZO having a thickness of 50 nm are formed by sputtering. A first diffusion preventing layer 173 and a first bonding layer 174 made of Au (gold) having a thickness of 300 nm were formed.
Next, the first mask was removed using a resist stripping solution.

Next, a second mask having a substantially square opening with a side length of 330 μm was formed. As the resist, AZ5200NJ was used.
With the second mask provided, a first adhesion layer 175 made of Ta (tantalum) having a thickness of 10 nm was formed by sputtering. Thereafter, the second mask was removed using a resist stripping solution.

  Next, a mask having a region where the second electrode 180 of the 350 μm-square light emitting element is formed is formed using a photolithography technique, and the p-type semiconductor layer 160, the light emitting layer 150, and the n-clad are formed by a known method. The layer 140b and a part of the n contact layer 140a were etched to expose the n-type GaN contact layer in a desired region where the second electrode 180 was to be formed. A third mask having an opening with a desired size of the second electrode 180 was formed on the exposed surface 140c of the semiconductor layer in accordance with a known mask forming process. As the resist, the same AZ5200NJ as described above was used. With the mask, the second conductive layer 181 made of Al with a thickness of 100 nm, the second diffusion prevention layer 182 made of Pt (platinum) with a thickness of 100 nm, and the first conductive layer made of Au with a thickness of 1000 nm by sputtering. Two bonding layers 183 were sequentially formed. Subsequently, the third mask was removed using a resist stripping solution.

Next, a fourth mask having an opening shape wider than that of the third mask was formed. As the resist, AZ5200NJ was used.
With the mask provided, a second adhesion layer 184 made of Ta having a thickness of 10 nm was formed by sputtering. Thereafter, the fourth mask was removed using a resist stripping solution.

Next, the surface of the first electrode 170, the surface of the second electrode 180, the p-type semiconductor layer 160, and the like are protected with a protective layer 190 made of SiO ₂ with a thickness of 250 nm using a photolithography mask process and a known sputtering method. did. Next, in order to form an exposed surface for bonding on the first electrode 170 and the second electrode 180, a desired region is etched, and the protective layer 190, the first adhesion layer 175, and the second adhesion layer 184 in the region are formed. The first bonding layer 174 and the second bonding layer 183 were exposed by removing.
In this way, the semiconductor light emitting device 1 was manufactured in which the length of the second electrode 180 extended from the exposed surface of the n-type GaN contact layer was higher than that of the first electrode 170.

<Measurement of Height of First Electrode 170 and Second Electrode 180>
The height of the first electrode 170 (p electrode) is from the surface of the protective layer 190 covering the exposed surface of the n-type contact layer formed between the first electrode 170 and the second electrode 180 (n electrode). The distance to the surface of the protective layer 190 covering the one electrode 170 was measured using a contact-type measuring instrument. The height of the second electrode 180 is such that the protective layer 190 that covers the second electrode 180 from the surface of the protective layer 190 that covers the exposed surface of the n contact layer 140 a formed between the first electrode 170 and the second electrode 180. The distance to the surface of was measured using a contact-type measuring instrument.

The difference in height between the first electrode 170 and the second electrode 180 was obtained as a value obtained by subtracting the height of the second electrode 180 from the height of the first electrode 170 in one chip of the semiconductor light emitting device 1. When the difference in height represents minus, the height of the second electrode 180 is higher than that of the first electrode 170.
Five light emitting element chip patterns were arbitrarily selected from one wafer, and the heights of the first electrode 170 and the second electrode 180 were measured. This measurement was performed on 10 wafers. When the difference in height between the first electrode 170 and the second electrode 180 in total 50 points was determined, the average value was − (minus) 10 nm.

<Evaluation of contact failure rate after mounting>
Subsequently, the back surface of 10 wafers was polished, thinned to a predetermined thickness, and divided into 350 μm square sizes to manufacture 510,000 semiconductor light-emitting element 1 chips for mounting. These chips were mounted on a substrate under normal conditions well known in the art.
Evaluation of the contact failure rate after mounting at this time was in accordance with the following method. A 20 mA forward drive voltage was measured with a prober for each chip before mounting, and then the 20 mA forward drive voltage was measured again after mounting the chip on a substrate. The contact failure rate after mounting was determined with the drive voltage before and after mounting as 0.01 V or less as acceptable and the other chips as unacceptable. The electrode structure and evaluation results in Example 1 are shown in FIG. The number of contact failures after mounting was 5, and the mounting failure rate was 0.001%.

(Example 2)
The first conductive layer 171 in the first electrode 170 is 5 nm thick ITO, the first diffusion prevention layer 173 is 50 nm thick ITO, the first adhesion layer 175 is 10 nm thick Ti, and the second electrode 180 A wafer in which the chip of the semiconductor light emitting element 1 was formed was manufactured in the same manner as in Example 1 except that the second bonding layer 183 was Au having a thickness of 1700 nm and the second adhesion layer 184 was Ti having a thickness of 10 nm. . Then, in the same manner as in Example 1, the difference in height between the first electrode 170 and the second electrode 180 in total of 50 points was obtained for 10 wafers. As a result, the average value of the height difference between the first electrode 170 and the second electrode 180 was −721 nm.
Next, the contact failure rate after mounting was determined in the same manner as in Example 1. Ten wafers were each thinned to a predetermined thickness and divided into 350 μm square sizes to produce 528,800 chips. Furthermore, when these chips were mounted on a substrate and evaluated in the same manner as in Example 1, the number of contact failures after mounting was 0. The electrode structure and evaluation results in Example 2 are shown in FIG.

(Example 3)
The first diffusion prevention layer 173 in the first electrode 170 is made of Ti having a thickness of 50 nm, the second diffusion prevention layer 182 in the second electrode 180 is made of Rh having a thickness of 100 nm, and the second bonding layer 183 is made of Au having a thickness of 2200 nm. A wafer on which a chip of the semiconductor light emitting element 1 was formed was manufactured in the same manner as in Example 1 except that. Then, in the same manner as in Example 1, the difference in height between the first electrode 170 and the second electrode 180 in total of 50 points was obtained for 10 wafers. As a result, the average difference in height between the first electrode 170 and the second electrode 180 was −1235 nm.
Next, the contact failure rate after mounting was determined in the same manner as in Example 1. Ten wafers were each thinned to a predetermined thickness and divided into 350 μm square sizes to produce 502,300 semiconductor light-emitting element 1 chips for mounting. Furthermore, when these chips were mounted on a substrate and evaluated in the same manner as in Example 1, the number of contact failures after mounting was 0. The electrode structure and evaluation results in Example 3 are shown in FIG.

(Comparative Example 1)
A wafer on which the semiconductor light emitting element 1 was formed was manufactured in the same manner as in Example 1 except that the second bonding layer 183 in the second electrode 180 was changed to Au having a thickness of 300 nm. Then, in the same manner as in Example 1, the difference in height between the first electrode 170 and the second electrode 180 in total of 50 points was obtained for 10 substrate wafers. As a result, the average difference in height between the first electrode 170 and the second electrode 180 was +698 nm.
Next, the contact failure rate after mounting was determined in the same manner as in Example 1. Ten wafers were each thinned to a predetermined thickness and divided into 350 μm square sizes to produce 499,600 semiconductor light-emitting element 1 chips for mounting. Further, when these chips were mounted on a substrate and evaluated in the same manner as in Example 1, the number of contact failures after mounting was as large as 32. Moreover, the mounting defect rate was as high as 0.006%. The electrode structure and evaluation results in Comparative Example 1 are shown in FIG.

  As shown in FIG. 4, in comparison with Examples 1 to 3 and Comparative Example 1, in Examples 1 to 3 in which the length of the second electrode 180 protrudes from the first electrode 170 and is higher, Compared to Example 1, the number of contact failures after mounting was extremely low, and it was found that the configuration was suitable for mounting on a substrate.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor light-emitting device, 10 ... Wiring board, 100 ... Laminated semiconductor layer, 110 ... Substrate, 120 ... Intermediate layer, 130 ... Underlayer, 140 ... N-type semiconductor layer, 140c ... Exposed surface of semiconductor layer, 141 ... N side first 1 layer, 142 ... n-side second layer, 150 ... light emitting layer, 160 ... p-type semiconductor layer, 160c ... upper surface, 170 ... first electrode, 171 ... first conductive layer, 172 ... metal reflection layer, 173 ... first Diffusion prevention layer, 174 ... first bonding layer, 175 ... first adhesion layer, 175c ... first adhesion layer upper surface 180 ... second electrode, 181 ... second conductive layer, 182 ... second diffusion prevention layer, 183 ... second Bonding layer, 184 ... second adhesion layer, 184c ... second adhesion layer upper surface, 190 ... protective layer

Claims (5)

A first semiconductor layer composed of a group III nitride semiconductor having a first conductivity type;
A light emitting layer that is laminated on one surface of the first semiconductor layer so as to expose a part of the one surface, and emits light when energized;
A second semiconductor layer composed of a Group III nitride semiconductor having a second conductivity type different from the first conductivity type, and stacked on the light emitting layer;
A first electrode comprising a reflective layer stacked on the second semiconductor layer and having reflectivity for light emitted from the light emitting layer;
A semiconductor light emitting element comprising: a second electrode extending from an exposed portion of the one surface of the first semiconductor layer and protruding beyond the first electrode.   The semiconductor light emitting device according to claim 1, wherein the first electrode further includes a transparent conductive layer stacked on the second semiconductor layer. A first semiconductor layer composed of a group III nitride semiconductor having a first conductivity type;
A light emitting layer that is laminated on one surface of the first semiconductor layer so as to expose a part of the one surface, and emits light when energized;
A second semiconductor layer composed of a Group III nitride semiconductor having a second conductivity type different from the first conductivity type, and stacked on the light emitting layer;
A first electrode stacked on the second semiconductor layer;
A second electrode extending from an exposed portion of the one surface of the first semiconductor layer and projecting from the first electrode;
A first connection portion provided at an end of the first electrode opposite to the second semiconductor layer side;
A second connection portion provided at an end of the second electrode opposite to the exposed portion side;
A light emitting device comprising: a wiring board electrically connected to the first connection part and the second connection part.   The light emitting device according to claim 3, wherein the wiring board is provided substantially parallel to the first semiconductor layer.   The light emitting device according to claim 3, wherein the first electrode further includes a transparent conductive layer laminated on the second semiconductor layer.

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