JP2011234275A - Gate driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gate driving circuit that operates without being affected by bad influence even when a voltage of a power source connected to a gate of a level-shift high-voltage transistor is high or low.SOLUTION: A gate driving circuit has: a level-shift high-voltage transistor whose gate voltage waveform is controlled by a pulse signal; a resistance that connects a gate of the level-shift high-voltage transistor with a power source; a high-voltage circuit that is connected with a drain of the level-shift high-voltage transistor and outputs a gate driving signal depending on a drain current of the level-shift high-voltage transistor; a current mirror circuit that is connected with a source and the gate of the level-shift high-voltage transistor and configured so as to increase the current flowing in the resistance when the drain current increases; and resistance adjustment means that reduces a resistance value of the resistance when a power source voltage of the power source is low and maintains the resistance value of the resistance when the power source voltage of the power source is high.

Description

  The present invention relates to a gate drive circuit that drives switching elements such as MOSFETs and IGBTs.

  The gate drive circuit is a circuit that transmits a gate drive signal to the gate of a switching element (hereinafter referred to as IGBT) such as an IGBT. A low potential input signal is supplied to the gate drive circuit from a CPU or the like. The gate drive circuit includes a level shift high voltage transistor for converting the input signal into a high potential signal.

  The gate of the level shift high voltage transistor is generally connected to the high voltage side of the power supply through the transistor. A high voltage circuit is connected to the drain of the level shift high voltage transistor. The on / off of this transistor is switched by the aforementioned input signal. As a result, a drain current reflecting the input signal flows through the level shift high voltage transistor. In response to the drain current, the high voltage circuit transmits a gate drive signal to the gate of the IGBT.

JP 2009-54639 A

  The power supply connected to the gate of the level shift high voltage transistor is not dedicated to the gate drive circuit and may be shared with other circuits. Therefore, for the sake of design, it is preferable that the gate drive circuit operates without any harmful effects even when connected to a power supply having a low power supply voltage or to a power supply having a high power supply voltage.

  However, when the voltage of the power source connected to the gate of the level shift high voltage transistor is low, the level shift high voltage transistor is delayed in turn-on and the ability to transmit the input signal to the IGBT gate may be insufficient. In this case, the delay time of the input signal increases. On the other hand, when the voltage of the power supply is high, an excessive drain current flows through the level shift high voltage transistor, and the loss may increase. In addition, this increase in loss may promote deterioration of the level shift high voltage transistor.

  The present invention has been made to solve the above-described problems, and provides a gate driving circuit that operates without adverse effects even when the voltage of a power supply connected to the gate of a level shift high voltage transistor is high or low. The purpose is to do.

  A gate drive circuit according to a first aspect of the present invention includes a level shift high voltage transistor whose gate voltage waveform is controlled by a pulse signal, a resistor connecting the gate of the level shift high voltage transistor and a power source, and a drain of the level shift high voltage transistor And a high voltage circuit that outputs a gate drive signal according to the drain current of the level shift high voltage transistor, and a current that flows through the resistor when the drain current increases. A current mirror circuit configured to increase the resistance, and a resistance adjustment that reduces the resistance value of the resistor when the power supply voltage of the power supply is low and maintains the resistance value of the resistor when the power supply voltage of the power supply is high Means.

  A gate drive circuit according to a second aspect of the invention includes a level shift high voltage transistor whose gate voltage waveform is controlled by a pulse signal, a resistor connecting the gate of the level shift high voltage transistor and a power source, and a drain of the level shift high voltage transistor. And a high voltage circuit that outputs a gate drive signal according to the drain current of the level shift high voltage transistor, and a current that flows through the resistor when the drain current increases. A current mirror circuit configured to increase the current, and the current mirror circuit has a plurality of paths through which current flows through the resistor, and at least one path of the plurality of paths If the power supply voltage of the power supply is low, the power supply is cut off. If the power supply voltage of the power supply is high, the current control is turned on. It means, comprising the.

  According to the present invention, it is possible to provide a gate driving circuit that operates without adverse effects even when the voltage of the power supply connected to the gate of the level shift high voltage transistor is high or low.

1 is a circuit diagram of a gate drive circuit and its peripherals according to a first embodiment of the present invention. It is a gate drive circuit of a comparative example, and its peripheral circuit diagram. It is a timing chart which shows operation | movement of the gate drive circuit of a comparative example. 3 is a timing chart showing an operation of the gate drive circuit according to the first embodiment of the present invention. It is a circuit diagram which shows the modification of the gate drive circuit which concerns on Embodiment 1 of this invention. It is a timing chart which shows operation | movement of the gate drive circuit of a modification. It is a circuit diagram which shows the modification of the gate drive circuit which concerns on Embodiment 1 of this invention. It is a circuit diagram which shows the modification of the gate drive circuit which concerns on Embodiment 1 of this invention. FIG. 5 is a circuit diagram of a gate drive circuit and its peripherals according to a second embodiment of the present invention. 6 is a timing chart for explaining the operation of the gate drive circuit according to the second embodiment of the present invention. It is a circuit diagram which shows the modification of the gate drive circuit which concerns on Embodiment 2 of this invention. It is a timing chart explaining operation | movement of the gate drive circuit of a modification. It is a circuit diagram which shows the modification of the gate drive circuit which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the modification of the gate drive circuit which concerns on Embodiment 2 of this invention.

Embodiment 1 FIG.
First, a first embodiment of the present invention will be described with reference to FIG. In addition, the same code | symbol may be attached | subjected to the same or corresponding component, and description of description may be abbreviate | omitted. The same applies to other embodiments.

  FIG. 1 is a circuit diagram of a gate driving circuit and its peripherals according to Embodiment 1 of the present invention. The gate driving circuit 10 includes terminals for connection with the outside, that is, an input terminal 12, an input signal terminal 14, a high voltage terminal 16, an output terminal 18, and a virtual ground terminal 20. The input terminal 12 is connected to the high voltage side of the power source 22. The input signal terminal 14 is connected to, for example, a CPU. The high voltage terminal 16 is connected to the high voltage side of the floating power supply 24. The output terminal 18 is connected to the gate of the IGBT 26. The virtual ground terminal 20 is connected to the midpoint of the IGBTs 26 and 28 connected in a totem pole connection.

  Next, the configuration of the gate drive circuit 10 will be described. The input terminal 12 is connected to the source of a PMOS transistor 30 (hereinafter referred to as PMOS 30). One end of a resistor 32 is connected to the drain of the PMOS 30. One end of a resistor 34 is connected to the other end of the resistor 32. The other end of the resistor 34 is connected to the drain of an NMOS transistor 36 (hereinafter referred to as NMOS 36). The source of the NMOS 36 is grounded.

  A switch 38 is connected in parallel to the resistor 32. Thus, since the resistor 32 and the switch 38 are connected in parallel, the resistor 32 can be disconnected. Further, a comparator 40 with hysteresis is connected to the switch 38 in order to control the switch 38. The inputs of the comparator 40 with hysteresis are a threshold voltage Vt and a voltage Vdet. The voltage Vdet is a voltage at the other end of the resistor 42 having one end connected to the power supply 22. Since Vdet is a voltage at a portion where only the resistor 42 is interposed between the power supply 22 and the power supply 22, it accurately reflects the voltage VCC of the power supply 22 (hereinafter referred to as VCC).

  A pulse generation circuit 44 is connected to the gates of the PMOS 30 and the NMOS 36. The pulse generation circuit 44 is a circuit that converts a low-potential input signal input to the input signal terminal 14 into a pulse signal and applies it to the gates of the PMOS 30 and the NMOS 36. The pulse generation circuit 44 includes an input circuit 46. The input signal terminal 14 is connected to the input circuit 46. The input circuit 46 is a circuit that shapes the waveform of the input signal from the input signal terminal 14. A one-shot pulse generation circuit 48 is connected to the input circuit 46. The one-shot pulse generation circuit 48 is a circuit that generates a pulse signal corresponding to the shaped waveform. An inverter 50 is connected to the one-shot pulse generation circuit 48. The inverter 50 transmits a pulse signal. The output of the inverter 50 is connected to the gate of the PMOS 30 and the gate of the NMOS 36.

  The gate of the level shift high voltage transistor 52 is connected between the drain of the NMOS 36 and the resistor 34. The level shift high voltage transistor 52 is a transistor that performs level shift of the pulse signal generated by the pulse generation circuit 44. The gate of the level shift high voltage transistor 52 and the power supply 22 are connected via a PMOS 30, a resistor 32, and a resistor 34. This connection is controlled by turning on and off the PMOS 30 reflecting the pulse signal. Therefore, the voltage waveform applied to the gate of the level shift high voltage transistor 52 reflects the pulse signal.

  A current mirror circuit 54 is connected to the source and gate of the level shift high voltage transistor 52. The current mirror circuit 54 includes NPN transistors 56, 58 and 60. The NPN transistor 56 has an emitter grounded, a collector connected to the power source 22 via the resistor 42, and a base connected to the base of the NPN transistor 60. The NPN transistor 58 has an emitter grounded, a collector connected to the gate of the level shift high voltage transistor 52, and a base connected to the base of the NPN transistor 60. The NPN transistor 60 has an emitter grounded, and a collector and a base connected to the source of the level shift high voltage transistor 52.

  A high voltage circuit 62 is connected to the drain of the level shift high voltage transistor 52. The high voltage circuit 62 is a circuit for outputting a gate drive signal from the output terminal 18 in accordance with switching of the level shift high voltage transistor 52. The high voltage circuit 62 includes a level shift resistor 64. One end of the level shift resistor 64 is connected to the high voltage side of the floating power supply 24 via the high voltage terminal 16, and the other end is connected to the drain of the level shift high voltage transistor 52. One end of an inverter 66 is connected between the drain of the level shift high voltage transistor 52 and the level shift resistor 64. The other end of the inverter 66 is connected to the output terminal 18.

  A clamp diode 68 is connected between the virtual ground terminal 20 and the drain of the level shift high voltage transistor 52 so that an excessive voltage is not applied to the level shift resistor 64.

  Prior to describing the operation of the gate drive circuit 10 according to the first embodiment of the present invention, a comparative example will be described in order to facilitate understanding of the present invention. FIG. 2 is a circuit diagram of a gate drive circuit of the comparative example and its periphery. In the gate driving circuit 200, the gate of the level shift high voltage transistor 52 is connected to the power supply 22 through the PMOS 30 and the resistor 34. The current mirror circuit 202 includes NPN transistors 58 and 60.

  The operation of the gate drive circuit 200 will be described with reference to FIG. 3 together with FIG. FIG. 3 is a timing chart showing the operation of the gate drive circuit 200 of the comparative example. The left side of FIG. 3 is a timing chart when the gate drive circuit 200 is connected to the power supply 22 having a low VCC. On the other hand, what is shown on the right side of FIG. 3 is a timing chart when the gate drive circuit 200 is connected to the power supply 22 having a high VCC.

  First, a case where VCC shown on the left side of FIG. 3 is low will be described. When the pulse signal generated by the pulse generation circuit 44 is transmitted to the PMOS 30 and the PMOS 30 is turned on, Vgs (referred to as the gate voltage of the level shift high voltage transistor 52, hereinafter the same) increases. Then, the drain current I1 (see the broken arrow in FIG. 2) flows through the level shift high voltage transistor 52. I1 is a current flowing from the floating power supply 24 through the high voltage terminal 16 and the level shift resistor 64 to the drain of the level shift high voltage transistor 52.

  This I1 also flows into the NPN transistor 60. At this time, a corresponding current I2 (see the broken-line arrow in FIG. 2) also flows through the NPN transistor 58 that forms the current mirror circuit 202 together with the NPN transistor 60. A potential difference ΔV is generated across the resistor 34 due to I2. ΔV can be calculated by the product of the resistance value of the resistor 34 and I2. Then, the increase in Vgs is suppressed by the amount of ΔV generated. Therefore, the transmission capability (signal transmission capability) of the input signal to the output terminal 18 is insufficient, and the transmission delay time increases.

  Next, the case where VCC shown on the right side of FIG. 3 is high will be described. Even when VCC is high, an increase in Vgs is suppressed by ΔV as described above. However, when VCC is high, ΔV becomes insufficient, and Vgs is not sufficiently suppressed. When Vgs rises without being sufficiently suppressed, I1 becomes excessive and power loss increases. Further, it is conceivable that the level shift high voltage transistor 52 deteriorates due to an excessive current flowing through the level shift high voltage transistor 52.

  Next, the operation of the gate drive circuit 10 according to the first embodiment of the present invention will be described. The operation of the gate drive circuit 10 will be described with reference to FIG. 4 together with FIG. FIG. 4 is a timing chart showing the operation of the gate drive circuit 10 according to the first embodiment of the present invention.

  First, the case where VCC shown on the left side of FIG. 4 is low will be described. The pulse signal generated by the pulse generation circuit 44 turns on the PMOS 30 and turns off the NMOS 36. Then, Vgs rises, the level shift high voltage transistor 52 is turned on, and I1 flows through the high voltage circuit 62. The operation in the high voltage circuit 62 is the same as that in the comparative example.

  I1 also flows into the NPN transistor 60. Therefore, a current corresponding to I1 also flows through the NPN transistors 56 and 58 constituting the current mirror circuit 54. At this time, I2 flows through the NPN transistor 58. Further, the current I3 (see the broken line arrow in FIG. 1) flows through the NPN transistor 56. I3 is a current flowing from the power source 22 to the NPN transistor 56 via the resistor 42.

  Then, a potential difference ΔV42 occurs between both ends of the resistor 42 due to I3. ΔV42 is obtained by the product of the resistance value of the resistor 42 and I3. The voltage obtained by subtracting ΔV42 from VCC becomes the input Vdet of the comparator 40 with hysteresis. While I3 is low, ΔV42 is low, so Vdet is larger than Vt. In this state, the hysteresis-equipped comparator 40 controls the switch 38 so as to maintain the switch 38 in the OFF state (the period during which Vdet is increased but the switch 38 is in the OFF state is referred to as period 1).

  In period 1, I 2 flows from the power supply 22 to the NPN transistor 58 via the PMOS 30, the resistor 32, and the resistor 34. Due to I2, a potential difference ΔV3234 is generated between both ends of the resistor 32 and the resistor 34. Then, a voltage obtained by subtracting ΔV3234 from VCC is applied to the gate of the level shift high voltage transistor 52 as Vgs.

  Thereafter, when Vgs continues to rise and ΔV42 increases, Vdet decreases to Vt accordingly. This is because Vt is set so that Vdet reaches the threshold voltage Vt when VCC is low. When Vdet reaches Vt, the comparator 40 with hysteresis controls the switch 38 so as to turn on the switch 38 (the period during which the switch 38 is on is referred to as period 2).

  In period 2, I2 flows not through the resistor 32 but through the lower-resistance switch 38. That is, I2 flows from the power supply 22 to the NPN transistor 58 via the PMOS 30, the switch 38, and the resistor 34. In period 1, a potential difference Δ 3234 is generated between both ends of the resistor 32 and the resistor 34, but in the period 2, the resistor 32 is disconnected, and thus only the potential difference Δ 34 is generated at both ends of the resistor 34. Therefore, in the period 2, the effect of suppressing Vgs is small, and Vgs and I1 are higher than those in the period 1.

  In this manner, when VCC is low, sufficient Vgs can be supplied to the gate of the level shift high voltage transistor 52 by reducing the resistance value of the path of I2. Therefore, when VCC is low, it is possible to prevent the signal transmission capability to the high voltage circuit 62 from being insufficient and the transmission delay time from increasing.

  Next, a case where VCC shown on the right side of FIG. 4 is high will be described. Even when VCC is high, I3 flows and a voltage ΔV42 is generated across the resistor 42. However, because VCC is high, Vdet does not drop as much as Vt is reached. Therefore, the comparator with hysteresis 40 controls the switch 38 so as to maintain the switch 38 in the OFF state.

  Since the switch 38 is maintained in the OFF state, when I2 flows, a potential difference Δ3234 is generated between both ends of the resistor 32 and the resistor 34. Therefore, since the rise of Vgs can be suppressed by the two resistors (resistor 32 and resistor 34), it is possible to prevent the power loss from increasing due to excessive Vgs (and I1).

  As described above, the gate drive circuit 10 according to the first embodiment of the present invention includes resistance adjusting means (resistor 32, switch 38, and hysteresis) for adjusting the resistance value between the gate of the level shift high-voltage transistor 52 and the power supply 22. It is characterized in that it has a comparator 40). With this feature, it is possible to provide a gate drive circuit that operates without adverse effects even when the voltage of the power supply connected to the gate of the level shift high voltage transistor is high or low.

  A modification of the first embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a circuit diagram showing a modification of the gate drive circuit 10 according to the first embodiment of the present invention. The gate drive circuit 70 is characterized by having two resistors. That is, the resistor 72 is connected between the resistor 34 and the drain of the NMOS 36. A switch 74 is connected to the resistor 72 so as to be in parallel with the resistor 72. The switch 74 is controlled to be turned on and off by the output of the comparator with hysteresis 76. Here, the threshold value of the comparator 40 with hysteresis is Vt, and the threshold value of the comparator 76 with hysteresis is Vta. Vta is set to be smaller than Vt.

  FIG. 6 is a timing chart showing the operation of the gate drive circuit 70 according to the modification. When VCC is low and Vgs rises, Vdet first reaches Vt. As a result, the switch 38 is turned on and the resistor 32 is disconnected. I2 at this time flows to the NPN transistor 58 via the power supply 22, the PMOS 30, the switch 38, the resistor 34, and the resistor 72 (referred to as a first I2).

  As Vgs further increases, Vdet reaches Vta. As a result, the switch 74 is turned on and the resistor 72 is disconnected. I2 at this time flows to the NPN transistor 58 via the power supply 22, the PMOS 30, the switch 38, the resistor 34, and the switch 74 (referred to as a second I2). In this case, since the resistance of the path of the current I2 is only the resistance 34, a sufficient Vgs can be applied to the level shift high voltage transistor 52 although VCC is low.

  On the other hand, when VCC is high, Vdet does not decrease to Vt or Vta. Therefore, both the switches 38 and 74 are kept off. I2 at this time flows to the NPN transistor 58 via the power supply 22, the PMOS 30, the resistor 32, the resistor 34, and the resistor 72 (referred to as a third I2). In the path I2, a potential difference is generated between both ends of the resistor 32, the resistor 34, and the resistor 72, so that Vgs can be suppressed.

  Thus, I2 can take three values according to VCC (first I2, second I2, and third I2). Since Vgs also changes in accordance with the value of each I2, the optimum Vgs is applied to the gate of the level shift high-voltage transistor 52 from the three types of Vgs. Therefore, highly accurate Vgs control is possible, and the reliability of the gate drive circuit 70 can be improved. In order to control Vgs with high accuracy in this way, the resistance adjusting means may be further increased.

  With reference to FIGS. 7 and 8, another modification of the first embodiment of the present invention will be described. 7 and 8 are circuit diagrams showing modifications of the gate drive circuit 10 according to the first embodiment of the present invention. The gate drive circuit 80 is characterized in that the input of the comparator 40 with hysteresis is grounded via a resistor 82. Thereby, the configuration can be simplified while obtaining the same effect as the gate drive circuit 10 of the first embodiment of the present invention. The gate drive circuit 90 shown in FIG. 8 is the same simplified as described above when there are a plurality of comparators with hysteresis. In this case, the configuration can be simplified while obtaining the same effect as the gate drive circuit 70 of FIG.

  Although the output terminal 18 of the gate drive circuit 10 of the present invention is connected to the gate of the IGBT 26, it can also be connected to the gate of the IGBT 28.

Embodiment 2. FIG.
The second embodiment of the present invention will be described with reference to FIGS. FIG. 9 is a circuit diagram of the gate driving circuit 100 and its peripherals according to the second embodiment of the present invention. The gate drive circuit 100 is characterized in that Vgs is adjusted by adjusting the amount of current flowing in the current mirror circuit.

  The gate drive circuit 100 has an NPN transistor 102. The NPN transistor 102 forms a current mirror circuit 106 together with the NPN transistors 56, 58 and 60. The emitter of the NPN transistor 102 is grounded. The base of the NPN transistor 102 is connected to the base of the NPN transistor 60. The collector of the NPN transistor 102 is connected to one end of the switch 104. The other end of the switch 104 is connected to the gate of the level shift high voltage transistor 52. The switch 104 is controlled to be turned on and off by the output of the comparator 40 with hysteresis.

  FIG. 10 is a timing chart for explaining the operation of the gate drive circuit 100 according to the second embodiment of the present invention. First, a case where VCC shown on the left side of FIG. 10 is low will be described. When VCC is low, when Vgs rises gently, the switch 104 is on. At this time, a current flows through the NPN transistors 58 and 102. The current flowing through the NPN transistor 58 is I2, and flows through the path as described above. The current I4 flows through the NPN transistor 102. I4 flows via the power supply 22, the PMOS 30, the resistor 34, and the NPN transistor 102.

  As Vgs further rises, current I1 rises and current I3 also rises. As a result, ΔV42 increases and Vdet decreases. When Vdet reaches the threshold voltage Vt, the comparator with hysteresis 40 controls the switch 104 so that the switch 104 is turned off. I4 becomes 0 when the switch 104 is turned off. Then, the potential difference ΔV34 between both ends of the resistor 34 is lowered by the amount that the current I4 does not flow. Therefore, Vgs can be increased.

  On the other hand, when VCC shown on the right side of FIG. 10 is high, Vdet does not reach the threshold voltage Vt, and the switch 104 is kept on. Therefore, the current I4 continues to flow. At this time, the potential difference ΔV34 at both ends of the resistor 34 is a value obtained by multiplying the sum of I2 and I4 by the resistance value of the resistor 34. In this case, since Δ34 becomes larger than when only I2 flows, Vgs can be reduced.

  As described above, the gate driving circuit 100 adjusts the current between the gate of the level shift high-voltage transistor 52 and the power source 22 as described above according to VCC (NPN transistor 102, switch 104, and with hysteresis). It is characterized by having a comparator 40). According to the configuration of the gate drive circuit 100, the same effect as that of the gate drive circuit 10 according to the first embodiment of the present invention can be obtained by a simple method of increasing the number of NPN transistors constituting the current mirror circuit 106.

  A modification of the second embodiment of the present invention will be described with reference to FIGS. FIG. 11 is a circuit diagram showing a modification of the gate drive circuit according to Embodiment 2 of the present invention. The gate drive circuit 110 is configured to include the two current adjusting means. Specifically, the gate drive circuit 110 is obtained by adding an NPN transistor 112, a switch 114, and a comparator 118 with hysteresis to the configuration of FIG. The NPN transistor 112 corresponds to the NPN transistor 102, the switch 114 corresponds to the switch 104, and the comparator 118 with hysteresis corresponds to the comparator 40 with hysteresis. Here, the threshold voltage Vta of the comparator 118 with hysteresis is set to be smaller than the threshold voltage Vt of the comparator 40 with hysteresis.

  FIG. 12 is a timing chart showing the operation of the gate drive circuit 110 according to the modification of the second embodiment of the present invention. First, a case where VCC is low will be described. When VCC is low and Vgs is rising slowly, switches 104 and 114 are in the on state. At this time, a current I5 flows through the NPN transistor 112 in addition to the currents I2 and I4 described above. I5 is a current flowing through the power source 22, the PMOS 30, the resistor 34, the switch 114, and the NPN transistor 112.

  Thereafter, as Vgs rises, Vdet reaches the threshold voltage Vt, and the comparator 40 with hysteresis turns off the switch 104. When the switch 104 is turned off, I4 becomes zero. Therefore, Vgs can be raised.

  Thereafter, when Vgs further increases, Vdet reaches the threshold voltage Vta, and the comparator 118 with hysteresis turns off the switch 114. When the switch 114 is turned off, I5 is also zero. Therefore, Vgs can be further increased.

  On the other hand, when VCC shown on the right side of FIG. 12 is high, Vdet does not reach the threshold voltage Vt or Vta, and the switches 104 and 114 remain on. Therefore, the currents I4 and I5 described above continue to flow. Therefore, Vgs can be reduced.

  According to the configuration of the gate drive circuit 110, the number of paths of the current flowing through the resistor 34 can be changed in three ways according to VCC. Specifically, there are three cases: I2, I4 and I5 flow, I2 and I5 flow, and I2 flow. Therefore, the value of Vgs can be adjusted with high accuracy according to VCC.

  With reference to FIGS. 13 and 14, another modification of the second embodiment of the present invention will be described. 13 and 14 are circuit diagrams showing modifications of the gate drive circuit 100 according to Embodiment 2 of the present invention. The gate drive circuit 130 is characterized in that the input of the comparator 40 with hysteresis is grounded through a resistor 132. Thereby, the configuration can be simplified while obtaining the same effect as the gate drive circuit 100 of the second embodiment of the present invention. The gate drive circuit 140 shown in FIG. 14 is the same simplified as described above when there are a plurality of comparators with hysteresis. In this case, the configuration can be simplified while obtaining the same effect as the gate drive circuit 110 of FIG.

  10 gate drive circuit, 22 power supply, 30 PMOS transistor, 32 resistor, 34 resistor, 38 switch, 40 comparator with hysteresis, 54 current mirror circuit, 62 high voltage circuit

Claims (6)

A level shift high voltage transistor in which the waveform of the gate voltage is controlled by a pulse signal;
A resistor connecting a gate and a power source of the level shift high voltage transistor;
A high voltage circuit connected to a drain of the level shift high voltage transistor and outputting a gate drive signal in accordance with a drain current of the level shift high voltage transistor;
A current mirror circuit connected to the source and gate of the level shift high voltage transistor and configured to increase the current flowing through the resistor when the drain current increases;
A gate drive comprising: resistance adjusting means for reducing a resistance value of the resistor when the power supply voltage of the power supply is low and maintaining a resistance value of the resistor when the power supply voltage of the power supply is high. circuit. The resistance adjusting means is
A switch connected in parallel to the resistor;
A comparator with hysteresis connected to the switch to control on / off of the switch,
2. The gate drive circuit according to claim 1, wherein an input of the comparator with hysteresis is connected to the power supply through a resistor.   3. The gate drive circuit according to claim 1, further comprising a plurality of the resistance adjusting means. A level shift high voltage transistor in which the waveform of the gate voltage is controlled by a pulse signal;
A resistor connecting a gate and a power source of the level shift high voltage transistor;
A high voltage circuit connected to a drain of the level shift high voltage transistor and outputting a gate drive signal in accordance with a drain current of the level shift high voltage transistor;
A current mirror circuit connected to the source and gate of the level shift high voltage transistor and configured to increase the current flowing through the resistor when the drain current increases;
The current mirror circuit has a plurality of paths through which current flows through the resistor,
A gate drive comprising: current adjusting means for cutting off at least one of the plurality of paths when the power supply voltage of the power supply is low and turning on when the power supply voltage of the power supply is high. circuit. The current adjusting means includes
A switch connected in series to at least one of the plurality of paths;
A comparator with hysteresis connected to the switch to control on / off of the switch,
The gate drive circuit according to claim 4, wherein an input of the comparator with hysteresis is connected to the power supply via a resistor.   6. The gate drive circuit according to claim 4, wherein a plurality of the current adjusting means are provided.

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