JP2011233670A - Manufacturing method of super junction semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a super junction semiconductor device having a super junction structure including parallel pn layers, that can be manufactured at low cost with improved production efficiency by reducing thermal diffusion time and the number of steps needed for making the parallel pn layers serving as drift layers successive impurity diffusion regions.SOLUTION: A manufacturing method of a super junction semiconductor device comprises a first step of growing an epitaxial layer 3 on a high-concentration semiconductor substrate 1 with a first conductivity type, a second step of implanting ions of an impurity element with the first conductivity type whose diffusion coefficient is higher than that of boron and implanting boron ions twice or more at different acceleration voltages, a third step of increasing the thickness of the epitaxial layer to a predetermined layer thickness by repeating the first and second steps, and a fourth step of forming parallel pn layers 10 in which impurities are successive in a direction perpendicular to a main plane of the substrate and which are mutually adjacent in a direction parallel to the main plane.

Description

  The present invention relates to a power semiconductor device. More particularly, the present invention relates to a method of manufacturing a super junction (sometimes abbreviated as super junction: SJ) semiconductor device. In the following description, a semiconductor device having a superjunction structure including a parallel pn layer in the drift layer is referred to as a superjunction semiconductor device.

A semiconductor device that breaks the conventional characteristic limit using the super junction structure, specifically, an SJ-MOSFET as shown in the cross-sectional views of FIGS. As a method of forming the parallel pn layer in the drift layer, an epitaxial layer is grown in several times on n ⁺ Si-Substrate (indicated as n ⁺ Si-Sub Wafer in FIGS. 3 and 4), and each growth stage Before the step, a p-type ion implantation region and an n-type ion implantation region (hereinafter abbreviated as p-type region and n-type region) are formed by patterning and ion implantation. With this process as one step, the above process is repeated while pattern alignment, and the epitaxial layer including the p-type region and the n-type region is stacked in the direction perpendicular to the main surface of the substrate. After the thickness of the epitaxial layer including the p-type region and the n-type region reaches the thickness required for the design withstand voltage, the p-type region and the n-type region that are still separated from each other at each step are subjected to high-temperature heat treatment. In general, a manufacturing method in which a parallel pn layer formed into a continuous impurity diffusion region by a diffusion process is formed as a drift layer. This manufacturing method is hereinafter referred to as a multi-stage epi method.

FIG. 2 is a cross-sectional view showing a main manufacturing process of an SJ-semiconductor substrate (also referred to as a wafer) for manufacturing this SJ-MOSFET by the multi-stage epi method. On an n-type Sub wafer (synonymous with n ⁺ Si-Substrate) 51 (FIG. 2A), an n ⁺ -type epitaxial having a medium concentration (about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ ) called a buffer layer. The layer 52 is grown to a thickness of about 20 μm (FIG. 2B). Next, phosphorus ion (P ⁺ ) implantation indicated by an arrow is performed on the entire surface to form an n-type ion implantation region 54a (FIG. 2 (c)), and then a pattern to be an ion implantation mask 56 is formed with a resist. Then, boron ions (B ⁺ ) indicated by arrows are implanted to form a p-type ion implantation region 55a (FIG. 2D). After removing the resist mask 56, a 7 μm thick non-doped epitaxial layer 53 is grown (FIG. 2E). In the case of a 600V class SJ-MOSFET wafer, if the process from the entire surface phosphorus ion implantation to the 7 μm growth of the non-doped epitaxial layer 53 is taken as one step and this process is repeated about 6 times, the thickness required for the breakdown voltage as a drift layer (FIG. 2 (f)). Then, when epitaxial growth of a cap layer (not shown) having a thickness of several μm and thermal diffusion treatment at about 1100 ° C. are performed, the separated phosphorus and boron ion implantation regions 54a and 55a are formed on the main surface of the substrate. The parallel pn layer 57 is an impurity diffusion region which is continuous in the vertical direction and adjacent to the parallel direction. Since the impurity diffusion region of phosphorus is sometimes referred to as an n column 54 and the impurity diffusion region of boron is sometimes referred to as a p column 55, the parallel pn layer 57 is sometimes referred to as an SJ column (FIG. 2 (g)).

Conventionally, as described above, phosphorus is used as an n-type impurity and boron is used as a p-type impurity. When the thermal diffusion treatment temperature is 1100 ° C., the diffusion coefficient of phosphorus into the Si crystal is 1.07 × 10 ⁻¹³ cm ² / sec, so that the depth is 3.5 μm corresponding to half of the epitaxial layer thickness of 7 μm. By thermally diffusing phosphorus ion-implanted in each direction, phosphorus spreads over the entire thickness of the epitaxial layer 53 of 7 μm. The time required for this is about 5.5 hours. On the other hand, since the diffusion coefficient of boron at 1100 ° C. is 2.5 × 10 ⁻¹³ cm ² / sec, similarly, the time required to expand boron to the entire thickness of the epitaxial layer 53 is 2.4 hours. . Since phosphorus and boron are subjected to simultaneous thermal diffusion treatment in order to shorten the process and improve efficiency, the diffusion time required for phosphorus has determined the time of the thermal diffusion treatment process.

  As a publicly known document relating to such a technique, there is a description relating to implanting selenium having a large diffusion coefficient with respect to a silicon single crystal as an n-type dopant at the peripheral edge of a high voltage semiconductor element (Patent Document 1).

Japanese Patent No. 3842893

  However, as described above, in the manufacture of the SJ-MOSFET by the multi-stage epi method, as a parallel pn layer serving as a drift layer, epitaxial growth, patterning, and ion implantation are performed in one step in order to ensure a necessary thickness for a required breakdown voltage. This process needs to be repeated many times. As a result, it is a problem to be solved that the manufacturing cost must be increased. In addition, since it takes a long time for thermal diffusion to make each pn ion implantation region arranged separately from each other into a parallel pn layer which is a continuous impurity diffusion region, there is a problem that production efficiency is lowered. is there.

  The present invention has been made in view of the above-described points, and improves the production efficiency by reducing the number of processes and the thermal diffusion time necessary for making the parallel pn layer serving as the drift layer a continuous impurity diffusion region. Another object of the present invention is to provide a method of manufacturing a superjunction semiconductor device having a superjunction structure including a parallel pn layer that can be manufactured at low cost.

  In order to achieve the object of the present invention, in the present invention, a first step of growing an epitaxial layer on a high-concentration first conductivity type semiconductor substrate, and a diffusion coefficient into a silicon crystal in the epitaxial layer is a second step. A second conductivity type ion implantation layer is selectively formed by forming an ion implantation layer of a first conductivity type impurity element larger than the conductivity type impurity element and ion implantation of the second conductivity type impurity element at least twice by different acceleration voltages. A second step of forming, a third step of repeating the first and second steps one or more times to make the epitaxial layer have a predetermined lamination thickness, and ion-implanted impurities by impurity diffusion at a thermal diffusion temperature, In the direction perpendicular to the main surface of the semiconductor substrate, the impurity continues in the epitaxial layer, and in the direction parallel to the main surface, the first conductivity type region and the second adjacent to each other. A method for manufacturing a superjunction semiconductor device having a fourth step of the drift layer to form a parallel pn layer made of conductive type region.

  In the second step, it is preferable that the second conductivity type impurity element is boron and the first conductivity type impurity element having a diffusion coefficient into the silicon crystal larger than boron is selenium or sulfur. In the second step, it is also preferable to provide an impurity concentration gradient in the second conductivity type region by ion-implanting boron by combining a plurality of doses together with different acceleration voltages. Furthermore, in the second step, it is also preferable that boron ion implantation is performed seven times with different acceleration voltages. It is also preferable that the superjunction semiconductor device is a superjunction MOSFET.

  According to the present invention, a parallel pn layer that can be manufactured at a low cost by improving the production efficiency by reducing the number of processes and the thermal diffusion time required to make the parallel pn layer serving as the drift layer into a continuous impurity diffusion region. A method for manufacturing a superjunction semiconductor device having a superjunction structure can be provided.

It is sectional drawing of the wafer which shows the main manufacturing processes of the SJ-wafer which uses selenium as an n-type impurity concerning this invention. It is sectional drawing of the wafer which shows the main manufacturing processes of the conventional SJ-wafer. It is typical sectional drawing of the peripheral pressure | voltage resistant structure part of SJ-MOSFET. It is a typical sectional view of an element active part of SJ-MOSFET. It is the impurity depth and density | concentration profile (the 1) figure after boron ion implantation in multiple times by changing acceleration voltage. It is the impurity depth and density | concentration profile (the 2) figure after boron ion implantation in multiple times by changing acceleration voltage and dose amount. It is a relationship diagram of the acceleration voltage of boron ion implantation and the range (Rp).

  Embodiments of a method for manufacturing a superjunction semiconductor device according to the present invention will be described below in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.

Conventionally, as described with reference to FIG. 2, phosphorus ions (P ⁺ ) are used as n-type impurities, and boron ions (B ⁺ ) are used as p-type impurities. When the thermal diffusion treatment temperature is 1100 ° C., the diffusion coefficient of phosphorus into the Si crystal is 1.07 × 10 ⁻¹³ cm ² / sec, and the diffusion coefficient of boron is 2.5 × 10 ⁻¹³ cm ² / sec. Therefore, the time of the thermal diffusion treatment process is determined by the diffusion time required for phosphorus because the simultaneous thermal diffusion treatment is performed in order to shorten and improve the efficiency of the phosphorus and boron processes.

FIG. 1 shows a main semiconductor process of an SJ-wafer when selenium ions (Se ⁺ ) are applied as n-type impurities, which is a feature of the present invention. Similar to FIG. 2 described above, n ^{+ having} a medium concentration (about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ ) called a buffer layer is formed on the n-type Sub wafer 1 shown in FIG. The type epitaxial layer 2 is grown by about 20 μm (FIG. 1B). After epitaxial growth, ion implantation of the entire surface of selenium is performed as an n-type impurity (FIG. 1C), and boron as a p-type impurity is selectively ion-implanted using a resist mask to form n-type and p-type ion implantation regions 4a and 5a, respectively. (FIG. 1D), and thermal diffusion treatment for further diffusing impurities is performed. However, in this case, if the thermal diffusion treatment is performed as it is, selenium has a three-digit diffusion coefficient higher than that of phosphorus or boron, so that the epitaxial layer 3 having a thickness of about 10 μm at 1100 ° C. diffuses and spreads within a few minutes. Further, when several tens of minutes of thermal diffusion treatment is applied at 1100 ° C., diffusion of boron is only about 1 μm, but diffusion of selenium also proceeds in the lateral direction, and selenium diffuses under the selective ion implantation region of boron. Therefore, there arises a problem that the p column 5 which is an impurity region of boron cannot be formed.

  Therefore, in the present invention, when selenium is applied as an n-type impurity, for a single selenium ion implantation, boron continuously changes the acceleration voltage and performs multiple times of ion implantation with different depths. There is a feature in applying together. For example, as shown in FIG. 5, when the thickness of the epitaxial layer 3 is 10 μm, the acceleration voltage at the time of boron ion implantation for the first time (range Rp1) is 8 MeV, the second time (range Rp2) is 6.5 MeV, and the third time. (Range Rp3) is 5 MeV, 4th (Range Rp4) is 3.5 MeV, 5th (Range Rp5) is 2 MeV, 6th (Range Rp6) is 800 KeV, 7th (Range Rp7) is 200 KeV Seven boron ion implantations are continuously performed to form p-type ion implantation regions 5a having different depths. Since the boron ion-implanted in this way has already entered the entire region of the p column 5 at each stage without thermal diffusion, it is not necessary to further diffuse the boron further, and an activity of several minutes at 1100 ° C. An effective p column 5 can be formed only by the conversion process. On the other hand, since selenium having a diffusion coefficient higher than that of boron is used for the n column 4, if the epitaxial layer thickness is, for example, about 10 μm, the n column 4 is diffused all over the n column 4 by thermal diffusion treatment at 1100 ° C. for several minutes. Further, by adding heat treatment, the concentration of selenium in the vicinity of the interface and the center of the epitaxial layer into which impurities are introduced becomes uniform, and a flat n column 4 having no concentration gradient can be formed. In this way, by using selenium as the n-type impurity for the one-step epitaxial layer 3 and boron by applying an ion implantation technique by a plurality of times, when the epitaxial layer 3 thickness of the drift layer per layer is 10 μm, By repeating the epitaxial growth four times and the ion implantation, it is possible to form the parallel pn layer 10 having a thickness of 40 μm equivalent to the case where the epitaxial growth is performed six times by the above-described conventional method (FIGS. 1E and 1F). ). In the above description, as a method of forming the p column 5 by multiple times of boron ion implantation, the ion implantation is performed by selecting the acceleration voltage from 200 KeV to 8 MeV in order seven times, so that a sufficient depth can be obtained without thermal diffusion. However, the method is not limited to seven times, and the number of times can be reduced. For example, the effects of the present invention can be obtained by ion implantation with different acceleration voltages two or more times depending on characteristics such as withstand voltage.

  On the other hand, in the conventional method, when a parallel pn layer 57 thickness of 40 μm is obtained using phosphorus, it is necessary to repeat the epitaxial growth and ion implantation six times as shown in FIG. The number of times of ion implantation can be reduced by 6, and the number of times of patterning can be reduced by 3. Further, since the thermal diffusion treatment for forming the columns 54 and 55 is 1100 ° C. several tens of minutes from the conventional 1100 ° C. and 5.5 hours, it is possible to greatly shorten the time by about 5 hours.

  Furthermore, the present invention is also effective for improving the avalanche resistance of the SJ-MOSFET. In the description of Japanese Patent No. 4304433, if the n-type impurity concentration is constant in the depth direction and the p-type impurity concentration is a parallel pn layer having an impurity concentration gradient in the depth direction, the avalanche resistance is improved. is there. In the conventional manufacturing method, it is possible to provide a concentration gradient in the p column by changing the ion implantation dose every time the epitaxial layer is formed. The impurity concentration in the epitaxial layer is thin at the center, and the impurity concentration near the epitaxial layer interface is high. In order to flatten the impurity concentration in one epitaxial layer, which is the ideal n-type impurity concentration, it seems better to make the impurity diffusion time longer, but as mentioned above, there are several ways to increase the diffusion time. There is a problem. Further, as in the method for forming the p column 5 of the parallel pn layer 10 described in the above-described embodiment of the present invention, the ion implantation depth is changed linearly with respect to the depth direction in the single epitaxial layer 3. The method of enabling the impurity concentration gradient is not possible with the conventional method in which impurities must be introduced by ion implantation under the same conditions for each epitaxial layer 3. In order to obtain an arbitrary linear impurity concentration gradient by the conventional method, it is necessary to further reduce the thickness of one epitaxial layer and greatly increase the number of ion implantations. There is a problem that costs increase.

In the case of the present invention, for example, as shown in FIG. 6, the first boron ion implantation (Rp1) at the time of forming the p column is an acceleration voltage of 8 MeV, a dose amount of 1 × 10 ¹¹ cm ⁻² , and a subsequent Rp2 of 6.5 MeV. 1.5 × 10 ¹¹ cm ⁻² , the next Rp3 is 2 × 10 ¹¹ cm ^{−2 at} 5 MeV, the next Rp4 is 2.5 × 10 ¹¹ cm ⁻² at 3.5 MeV, and the next Rp5 is 3 × at 2 MeV. 10 ¹¹ cm ⁻² , the next Rp6 is 3.5 × 10 ¹¹ cm ⁻² at 800 KeV, the next Rp7 is 200 KeV and 4 × 10 ¹¹ cm ⁻² , and the dose on the surface side is increased in order. . Since the introduced boron is in the whole of the p-column 5 to be formed, it is not necessary to thermally diffuse boron, and the p-column 5 having a linear concentration gradient only by an activation process at about 1100 ° C. for several minutes can be obtained. Can be formed. Further, the impurity concentration gradient can be arbitrarily controlled by changing the dose amount.

  On the other hand, since the n column 4 uses selenium having a high diffusion coefficient, for example, if the thickness of the epitaxial layer 3 is about 10 μm, the n column 4 is sufficiently diffused by a thermal diffusion treatment at 1100 ° C. for several minutes. Further, by adding heat treatment, the concentration of selenium becomes uniform in the vicinity of the interface of the epitaxial layer 3 into which impurities are introduced and in the central portion, and a flat n column 4 having no concentration gradient can be formed. Of course, the acceleration voltage, the dose amount, and the thermal diffusion treatment conditions for a plurality of times of boron ion implantation performed in one epitaxial layer 3 are calculated by simulation, and optimum conditions are applied to obtain a desired concentration gradient. . FIG. 7 shows a relationship diagram between the acceleration voltage and the range (Rp) used in such boron ion implantation.

After that, as shown in FIGS. 3 and 4 and the like, as shown in FIGS. If the guard ring 7, the field insulating film 8, the n ⁻ region 9, etc. are formed in the electrode 17 and the peripheral breakdown voltage structure 200, a super junction MOSFET can be formed.

  According to the present invention, as described above, it is possible to manufacture SJ-MOSFET wafers having the same specifications and performance by greatly reducing the number of steps compared to the conventional method of forming an n column using phosphorus impurities. It becomes possible to provide an SJ-MOSFET at a low cost. In addition, the loss of SJ-MOSFET decreases as the pitch of the SJ-column is reduced to about 2 μm. However, according to the present invention, the heat diffusion processing time for forming the conventional SJ-column can be greatly shortened. Since the lateral diffusion of impurities can be suppressed, the above-mentioned pattern of about 2 μm can be easily miniaturized and the performance can be improved.

  The thickness of the epitaxial layer 3 grown at one time in the multi-stage epi method is determined by the opening size by patterning for selectively introducing the p-type impurity, the diffusion coefficient of the impurity to be introduced, and the thermal diffusion processing time. From the viewpoint of the characteristics of the SJ-MOSFET, when the pitch dimension of the SJ-column is about 10 μm, the widths of the finished substrate surfaces of the p column 5 and the n column 4 are each about 5 μm. For example, if the opening size by patterning for the p column 5 is 1 μm, boron is directly ion-implanted into this opening, and the impurity diffusion region is expanded by 2 μm on one side by thermal diffusion treatment to make the width 5 μm. In general, the distance spread by thermal diffusion in the horizontal direction parallel to the main surface of the substrate is about 2/3 of the vertical diffusion depth perpendicular to the main surface of the substrate. Therefore, when the thermal diffusion is performed by 2 μm in the horizontal direction, the impurities are thermally diffused by 3 μm in the vertical direction. In the case of the multi-stage epi method, since the impurities are diffused in both the upper and lower epitaxial layers 3, the vertical diffusion depth is 6 μm, which is the maximum value of the thickness of one epitaxial layer. Similarly, when the opening dimension by patterning for the p column 5 is 0.1 μm, the diffusion length (width) required in the horizontal direction is about 2.5 μm, and the vertical diffusion depth is 3.8 μm. Become. Therefore, the maximum one-time epitaxial layer 3 thickness is about 7.6 μm. Thus, the one where the opening width is narrower can increase the thickness of the epitaxial layer 3 once.

  If the thickness of one epitaxial layer 3 is too large with respect to the diffusion depth and the p-type impurity diffusion layers are not connected in the vertical direction, the p-type impurity diffusion layer will be in an electrically floating state. Problems such as transient on-resistance increase due to residual charge occur. Similarly, if the n-type impurity diffusion layers adjacent in the vertical direction are not connected to each other, there is a problem that the on-resistance is increased because a high resistance region is partially formed. In order to prevent these problems, it would be better to further increase the diffusion time. However, in actuality, the p-type impurity diffusion layer is excessively spread laterally, the width of the n-type impurity diffusion layer is narrowed, and the on-resistance is increased. Further, the dopants of the p column 5 and the n column 4 are mixed with each other, and the effective doping concentration is lowered and the on-resistance is raised. Therefore, the thickness of one epitaxial layer 3 cannot be increased unnecessarily. Next, regarding the diffusion coefficient of the n-type impurity introduced into the epitaxial layer 3 and the impurity introduced by the p-type impurity, the diffusion coefficient of phosphorus, which is an n-type impurity, is about half of that of boron, which is a p-impurity. The thickness of the epitaxial layer 3 was determined by the depth. That is, in order to connect the adjacent impurity diffusion layers of phosphorus separated in the vertical direction to form a continuous layer of phosphorus, it is necessary to reduce the thickness of the epitaxial layer 3 once. Therefore, by applying an n-type impurity element having a diffusion coefficient of at least boron or more, the n-type impurity diffusion layers adjacent in the vertical direction can be easily connected even under the same thermal diffusion treatment conditions. it can. As a result, the epitaxial layer 3 can be made thicker and the number of repeated steps can be reduced, so that the production efficiency is improved. Furthermore, it is possible to significantly shorten the thermal diffusion time for making each p ion implantation region 5a and n ion implantation region 4a a continuous impurity diffusion region (p column 5, n column 4). In the above-described embodiments, selenium is used as the n-type impurity element having a diffusion coefficient higher than that of boron. However, ion implantation using not only selenium but also sulfur or the like may be used.

In addition, although the said Example demonstrated using the non-doped epitaxial layer 3, you may make it form each layer using a low impurity concentration n-type epitaxial layer.
According to the embodiments of the present invention described above, the thermal diffusion time and the number of epitaxial growths can be reduced and the production efficiency can be improved, so that a superjunction semiconductor device capable of forming a parallel pn layer can be manufactured at low cost. can do.

1 n-type Sub wafer 2 n ⁺ -type epitaxial layer 3 non-doped epitaxial layer 4 n column 4a n-type ion implantation region 5 p column 5a p-type ion implantation region 6 resist mask 7 guard ring 8 field insulating film 10 parallel pn layer 13 p base Region 14 n ⁺ source region 15 gate insulating film 16 gate electrode 17 emitter electrode 100 element active part 200 peripheral breakdown voltage structure part

Claims (5)

A first step of growing an epitaxial layer on a high-concentration first-conductivity-type semiconductor substrate; and an ion-implanted layer of a first-conductivity-type element having a diffusion coefficient into a silicon crystal larger than that of a second-conductivity-type impurity element in the epitaxial layer A second step of selectively forming a second conductivity type ion implantation layer by ion implantation of the second conductivity type impurity element twice or more with different acceleration voltages, and the first and second steps as 1 The third step of repeatedly forming the epitaxial layer to a predetermined stack thickness by repeating the process more than once, and impurity diffusion of the ion-implanted impurity by thermal diffusion temperature causes the impurity to be in the direction perpendicular to the main surface of the semiconductor substrate. A parallel pn layer composed of a first conductivity type region and a second conductivity type region, which are respectively continuous in the layer and parallel to the main surface, is formed as a drift layer. Method for manufacturing a superjunction semiconductor device characterized by having a fourth step. The said 2nd conductivity type impurity element is said boron in said 2nd process, The 1st conductivity type impurity element whose diffusion coefficient to a silicon crystal is larger than boron is selenium or sulfur, The said 2nd process is characterized by the above-mentioned. A method of manufacturing a superjunction semiconductor device. 3. The superjunction semiconductor device according to claim 2, wherein in the second step, an impurity concentration gradient is provided in the second conductivity type region by ion-implanting boron by combining a plurality of dose amounts together with different acceleration voltages. Manufacturing method. 4. The method of manufacturing a superjunction semiconductor device according to claim 3, wherein in the second step, boron ion implantation is performed seven times with different acceleration voltages. The method of manufacturing a superjunction semiconductor device according to any one of claims 1 to 4, wherein the superjunction semiconductor device is a superjunction MOSFET.

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