JP2011233624A - Semiconductor element and electronic apparatus including the semiconductor element - Google Patents

Semiconductor element and electronic apparatus including the semiconductor element Download PDF

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JP2011233624A
JP2011233624A JP2010101001A JP2010101001A JP2011233624A JP 2011233624 A JP2011233624 A JP 2011233624A JP 2010101001 A JP2010101001 A JP 2010101001A JP 2010101001 A JP2010101001 A JP 2010101001A JP 2011233624 A JP2011233624 A JP 2011233624A
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liquid crystal
semiconductor element
bump electrode
conductive particles
acf
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Naoya Hirata
直也 平田
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item

Abstract

PROBLEM TO BE SOLVED: To prevent an occurrence of electrical short-circuit due to conductive particles between adjacent bump electrodes when a semiconductor element such as a liquid crystal driving IC is subjected to thermocompression using an ACF on a substrate.SOLUTION: A recessed/projecting part 31 is formed on a side face of a bump electrode 7 of a liquid crystal driving IC 6, so that physical resistance in flowing is resulted in a thermosetting resin in an ACF 9. Accordingly, fluidity of the resin around the bump electrode 7 is prevented, a pressure around the side face of the bump electrode 7 is increased as compared with a case where the recessed/projecting part 31 is not formed, conductive particles 10 around the side face of the bump electrode 7 are pushed to a central space between the bumps, and thereby, an occurrence of electrical short-circuit between adjacent bumps can be suppressed.

Description

本発明は、半導体素子及び該半導体素子を備える電子機器に関するものである。   The present invention relates to a semiconductor element and an electronic apparatus including the semiconductor element.

液晶表示装置をはじめとするフラットパネルディスプレイは広く一般的に使われるようになっている。液晶表示装置は、例えばガラス基板間に液晶材料が保持された液晶パネルがこのガラス基板上に搭載された液晶駆動用ＩＣと電気的に接続されて構成される（ＣＯＧ方式：Ｃｈiｐ Ｏｎ Ｇｌａｓｓ）。ＣＯＧ方式では、例えばガラス基板上に形成された端子と液晶駆動用ＩＣに形成されたバンプ電極との間に異方性導電膜（ＡＣＦ：Ａｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕcｔｉｖｅ Ｆｉｌｍ）を介在させて熱圧着することで実装が行われている。ここで、ＡＣＦは熱硬化性樹脂中に導電性粒子を分散されてなるが、導電性粒子が端子とバンプ電極間に挟まれることにより、端子とバンプ電極との間を電気的に接続する一方で、液晶パネルと液晶駆動用ICとの間の空間に充填された熱硬化性樹脂が硬化することにより、両者間の接続状態が保持される。   Flat panel displays such as liquid crystal display devices are widely used. The liquid crystal display device is configured, for example, by electrically connecting a liquid crystal panel in which a liquid crystal material is held between glass substrates to a liquid crystal driving IC mounted on the glass substrate (COG method: Chip On Glass). In the COG method, for example, an anisotropic conductive film (ACF) is interposed between a terminal formed on a glass substrate and a bump electrode formed on a liquid crystal driving IC to perform thermocompression bonding. Has been done. Here, the ACF is formed by dispersing conductive particles in a thermosetting resin, and the conductive particles are sandwiched between the terminals and the bump electrodes to electrically connect the terminals and the bump electrodes. Thus, the thermosetting resin filled in the space between the liquid crystal panel and the liquid crystal driving IC is cured, so that the connection state between the two is maintained.

液晶駆動用ICを液晶パネルに熱圧着した際、液晶パネルと液晶駆動用ICとの間の空間に収まりきらない熱硬化性樹脂は液晶パネルと液晶駆動用ICの間の空間の外に排出されるため、液晶駆動用ICの中心部から外に向かって熱硬化性樹脂の流れが生じる。熱圧着の完了後は、熱硬化性樹脂が硬化するため上記のような樹脂の流れはなくなるが、この際、異なるバンプ電極間に導電性粒子が連なることにより、電気的な短絡が生じるという問題がある。   When the liquid crystal drive IC is thermocompression bonded to the liquid crystal panel, the thermosetting resin that does not fit in the space between the liquid crystal panel and the liquid crystal drive IC is discharged outside the space between the liquid crystal panel and the liquid crystal drive IC. Therefore, a thermosetting resin flows from the center of the liquid crystal driving IC to the outside. After completion of thermocompression bonding, the thermosetting resin cures and the resin flow as described above disappears. However, at this time, the conductive particles are connected between different bump electrodes, which causes an electrical short circuit. There is.

近年、表示画像の高精細化の要求から、ガラス基板に搭載される液晶駆動用ICの出力ピン数は急速に増加している。また駆動ICの製造コストの削減を図るため駆動ICの外形はシュリンクされており、ピン数の増加と相まってバンプの狭ピッチ化はいっそう進んでいる。狭ピッチ化が進むと、バンプ電極間のスペースは狭くなるため、隣接するバンプ電極間に導電性粒子が連なり、バンプ電極間の電気的短絡が生じるという問題が起こりやすくなる。   In recent years, the number of output pins of a liquid crystal driving IC mounted on a glass substrate is rapidly increasing due to a demand for higher definition of a display image. In addition, the outline of the driver IC has been shrunk in order to reduce the manufacturing cost of the driver IC, and the pitch of the bumps has been further reduced along with the increase in the number of pins. As the pitch becomes narrower, the space between the bump electrodes becomes narrower, so that conductive particles are connected between the adjacent bump electrodes, which easily causes an electrical short circuit between the bump electrodes.

このような電気的短絡を抑制するために、液晶駆動用ICのバンプにくさび型溝や段付き溝を設けて導電性粒子を捕捉することによりバンプ間ギャップ部に存在する導電性粒子の総体数を減少させることにより電気的短絡を抑制するという技術が知られている。（特許文献１参照）   In order to suppress such an electrical short circuit, the total number of conductive particles present in the gap portion between the bumps by capturing the conductive particles by providing wedge-shaped grooves or stepped grooves on the bumps of the liquid crystal driving IC. A technique is known that suppresses an electrical short circuit by reducing. (See Patent Document 1)

特開２００８−１３５４６８号公報（図１、図９）JP 2008-135468 A (FIGS. 1 and 9)

今後ピッチの微細化が進んでいく中においても、熱圧着の際に端子とバンプ電極間に挟まれる導電性粒子の個数を確保しようとすると、ＡＣＦ中の導電性粒子の個数を増加させる必要が生じる。しかし、上記の先行技術においても、液晶駆動用ICのバンプにくさび型溝や段付き溝を設けて導電性粒子を捕捉できる個数は限られているため、電気的短絡の防止に対しての効果が薄れてくるという課題が生じてしまう。   As the pitch becomes finer in the future, it is necessary to increase the number of conductive particles in the ACF in order to secure the number of conductive particles sandwiched between the terminal and the bump electrode during thermocompression bonding. Arise. However, even in the prior art described above, the number of conductive particles that can be captured by providing wedge-shaped grooves or stepped grooves on the bumps of the liquid crystal driving IC is limited, which is effective in preventing electrical short circuits. The problem arises that fades.

本発明は以上のような課題を解決するためになされたものであり、基板上にＡＣＦを用いて液晶駆動用ICのような半導体素子あるいは他の基板を熱圧着する際に、隣接するバンプ電極間における導電性粒子による電気的な短絡を防止することを目的とする。   The present invention has been made in order to solve the above-described problems. When a semiconductor element such as a liquid crystal driving IC or another substrate is thermocompression-bonded using ACF on the substrate, adjacent bump electrodes are provided. It aims at preventing the electrical short circuit by the electroconductive particle in between.

本発明においては、半導体素子に形成されるバンプ電極の側面に、凹凸部を設けることを特徴とする。   The present invention is characterized in that an uneven portion is provided on a side surface of a bump electrode formed in a semiconductor element.

本発明に係る半導体素子においては、液晶駆動用ICのバンプ電極側面に凹凸部を設けることにより、ＡＣＦ中の熱硬化性樹脂にとっては流動する際の物理的な抵抗となるため、バンプ電極近傍の樹脂の流動性が妨げられ、凹凸部がない場合に比べて、バンプ電極側面近傍の圧力が高くなり、バンプ側面近傍の導電性粒子はバンプ間中央のスペースに追いやられ、隣接バンプ間での電気的短絡を低減することができる。これにより、バンプのピッチが狭くなっても、電気的短絡を低減することができるので、この半導体素子を備えた電子機器においても、短絡不良を抑制することができる。   In the semiconductor element according to the present invention, by providing an uneven portion on the side surface of the bump electrode of the liquid crystal driving IC, the thermosetting resin in the ACF becomes a physical resistance at the time of flow. The flow of the resin is hindered and the pressure in the vicinity of the bump electrode side becomes higher than in the case where there is no uneven part, and the conductive particles in the vicinity of the bump side are driven to the central space between the bumps. The short circuit can be reduced. Thereby, even when the pitch of the bumps is narrowed, the electrical short circuit can be reduced. Therefore, even in an electronic device including this semiconductor element, it is possible to suppress a short circuit failure.

本発明に係る半導体素子を備えた表示装置の概略構成を示す正面図である。It is a front view which shows schematic structure of the display apparatus provided with the semiconductor element which concerns on this invention. 図１の表示装置の周辺領域における主要部拡大図である。It is a principal part enlarged view in the peripheral region of the display apparatus of FIG. 図２のＡ−Ａ方向における断面図である。It is sectional drawing in the AA direction of FIG. 本発明の実施形態１に係る半導体素子である液晶駆動用ICの実装面の概略図である。It is the schematic of the mounting surface of IC for liquid crystal drive which is a semiconductor element which concerns on Embodiment 1 of this invention. 本発明の実施形態１に係る半導体素子のバンプ電極部とその近傍の導電性粒子を示した図である。It is the figure which showed the bump electrode part of the semiconductor element which concerns on Embodiment 1 of this invention, and the electroconductive particle of the vicinity. 本発明の実施形態１に係る半導体そしのバンプ電極部の凹凸部を示した図である。It is the figure which showed the uneven | corrugated | grooved part of the bump electrode part of the semiconductor which concerns on Embodiment 1 of this invention. 本発明に係る半導体素子を備えた表示装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the display apparatus provided with the semiconductor element which concerns on this invention.

本発明に係る半導体素子を説明するために、一例として当該半導体素子を備えた表示装置を用いて説明を行う。ここで、図１は、表示装置の概略構成を示す正面図、図２は図１の表示装置の周辺領域における主要部拡大図、図３は図２のＡ−Ａ方向における断面図である。   In order to describe the semiconductor element according to the present invention, description will be made using a display device including the semiconductor element as an example. Here, FIG. 1 is a front view showing a schematic configuration of the display device, FIG. 2 is an enlarged view of a main part in a peripheral region of the display device of FIG. 1, and FIG. 3 is a cross-sectional view in the AA direction of FIG.

図１において、本発明に係る表示装置２０は、ガラス等の透明な基板である第１の絶縁性基板１と、この第１の絶縁性基板１と対向するように配置される第２の絶縁性基板２を備えている。また、第１の絶縁性基板１上の表示領域３には複数のゲート線およびソース線によりマトリクス状に形成された複数の画素と、該画素の交差部付近に形成されたスイッチング素子とを備えている。第２の絶縁性基板２は、第１の絶縁性基板１の表示領域３上に形成された複数の画素と対向する位置にＲＧＢのカラーフィルタをマトリクス状に形成し、２枚の基板間に封入した液晶に外部から信号を入力することで表示を行う（図示せず）。また、外部からの電源、信号は、制御基板１１からフレキシブル基板（Ｆｌｅｘｉｂｌｅ Ｐｒｉｎｔｅｄ Ｃｉｒｃｕｉｔ：ＦＰＣ） ８を介して液晶駆動用IC ６に送られる。   In FIG. 1, a display device 20 according to the present invention includes a first insulating substrate 1 that is a transparent substrate such as glass, and a second insulating member that is disposed so as to face the first insulating substrate 1. A conductive substrate 2 is provided. The display region 3 on the first insulating substrate 1 includes a plurality of pixels formed in a matrix by a plurality of gate lines and source lines, and a switching element formed near the intersection of the pixels. ing. The second insulating substrate 2 is formed by forming RGB color filters in a matrix in positions facing the plurality of pixels formed on the display region 3 of the first insulating substrate 1, and between the two substrates. Display is performed by inputting an external signal to the sealed liquid crystal (not shown). In addition, an external power source and signal are sent from the control board 11 to the liquid crystal driving IC 6 via a flexible printed circuit (FPC) 8.

図２に示すように、第１の絶縁性基板１上の表示領域３の外側である周辺領域４には、上述の液晶駆動用IC ６を介して外部から入力される電源、信号を複数のゲート線およびソース線に入力するための入出力端子５が形成されている。   As shown in FIG. 2, the peripheral region 4 outside the display region 3 on the first insulating substrate 1 is supplied with a plurality of power supplies and signals inputted from the outside via the liquid crystal driving IC 6 described above. Input / output terminals 5 for inputting to the gate lines and the source lines are formed.

さらに、図３に示すように、液晶駆動用IC ６と入出力端子５との接続は、液晶駆動用IC ６に形成されたＡｕなどのバンプ電極７を第１の絶縁性基板１にＡＣＦ ９を用いて直接実装することで行われる。なお、図３にて、１５とあるのは、入出力端子５を被覆するＩＴＯ膜等の透明導電膜を指し、１２と１３と１４とあるのは、各種絶縁膜に対応するのであるが、詳細については製造方法とともに後で説明する。   Further, as shown in FIG. 3, the connection between the liquid crystal driving IC 6 and the input / output terminal 5 is performed by connecting a bump electrode 7 such as Au formed on the liquid crystal driving IC 6 to the first insulating substrate 1 with an ACF 9. It is done by implementing directly using. In FIG. 3, 15 indicates a transparent conductive film such as an ITO film covering the input / output terminal 5, and 12, 13, and 14 correspond to various insulating films. Details will be described later together with the manufacturing method.

再度、図３に示すように、ＡＣＦ ９においてはエポキシなどの絶縁性樹脂中にＮｉ／Ａｕめっきで覆われたプラスチック粒子や、Ｎｉ粒子などの導電性粒子１０が分散されており、この導電性粒子１０がバンプ電極７と入出力端子５との間で捕捉されることにより、液晶駆動用IC ６と入出力端子５との間に電気的導通をえることができる。   Again, as shown in FIG. 3, in ACF 9, plastic particles covered with Ni / Au plating and conductive particles 10 such as Ni particles are dispersed in an insulating resin such as epoxy. By capturing the particles 10 between the bump electrodes 7 and the input / output terminals 5, electrical conduction can be established between the liquid crystal driving IC 6 and the input / output terminals 5.

さらに、液晶駆動用IC ６を第１の絶縁性基板１の周辺領域４に接続する方法について説明を行う。   Further, a method for connecting the liquid crystal driving IC 6 to the peripheral region 4 of the first insulating substrate 1 will be described.

図２および図３に示すように、まず、第１の絶縁性基板１上の周辺領域４において、液晶駆動用ICの配置領域 ６ａより若干はみ出すようにＡＣＦ ９を貼付する。   As shown in FIGS. 2 and 3, first, the ACF 9 is pasted in the peripheral region 4 on the first insulating substrate 1 so as to slightly protrude from the arrangement region 6a of the liquid crystal driving IC.

次に液晶駆動用IC ６のバンプ電極７と入出力端子５の接続部５ａとを精度良く配置させた後、加熱加圧ツールを用いて熱圧着し、ＡＣＦ ９を硬化させることで接続させる。このときの圧着条件は、例えば、ＡＣＦ ９の到達温度１７０〜２００℃、時間５〜１０秒、圧力３０〜１００ＭＰａとする。   Next, after the bump electrode 7 of the liquid crystal driving IC 6 and the connection portion 5a of the input / output terminal 5 are arranged with high accuracy, they are thermocompression-bonded using a heating and pressing tool, and the ACF 9 is cured to be connected. The pressure bonding conditions at this time are, for example, an ultimate temperature of ACF 9 of 170 to 200 ° C., a time of 5 to 10 seconds, and a pressure of 30 to 100 MPa.

この条件で熱圧着すると、液晶駆動用IC ６のＡｕバンプ７と入出力端子５間に存在する導電性粒子１０は扁平してバンプ電極７と入出力端子５の方向（上下方向）のみ導通を有する。また、捕捉された導電性粒子１０の周囲には絶縁性のエポキシ樹脂が存在するために絶縁が保たれる。   When thermocompression bonding is performed under these conditions, the conductive particles 10 existing between the Au bumps 7 and the input / output terminals 5 of the liquid crystal driving IC 6 are flattened so as to conduct only in the direction of the bump electrodes 7 and the input / output terminals 5 (vertical direction). Have. Further, since insulating epoxy resin is present around the captured conductive particles 10, insulation is maintained.

次に、本発明に係る半導体素子について、図３〜図６を用いて説明を行う。ここで、図４は、液晶駆動用ICの実装面を上面側から見た状況を示したものであり、図５は図４の中のバンプ電極とその近傍の導電性粒子をより詳細に示した図である。図６は、図５の中のバンプ電極の凹凸部をより詳細に示した図である。   Next, the semiconductor element according to the present invention will be described with reference to FIGS. Here, FIG. 4 shows a situation when the mounting surface of the liquid crystal driving IC is viewed from the upper surface side, and FIG. 5 shows the bump electrodes in FIG. 4 and the conductive particles in the vicinity thereof in more detail. It is a figure. FIG. 6 is a diagram showing the bumps and depressions of the bump electrode in FIG. 5 in more detail.

図３において、第１の絶縁性基板１上には入出力端子５が形成されており、一方で液晶駆動用IC ６にはバンプ電極７が複数個形成されている。本発明においては、バンプ電極７の側面には凹凸部３１が形成されている。液晶駆動用IC ６は、バンプ電極７と液晶パネル入出力端子５とが互いに接続するような形で、表示装置２０の第１の絶縁性基板１上に実装されるが、その際にバンプ電極７と液晶パネル入出力端子５との間には、前述のとおり、導電性粒子１０が捕捉される。   In FIG. 3, an input / output terminal 5 is formed on the first insulating substrate 1, while a plurality of bump electrodes 7 are formed on the liquid crystal driving IC 6. In the present invention, an uneven portion 31 is formed on the side surface of the bump electrode 7. The liquid crystal driving IC 6 is mounted on the first insulating substrate 1 of the display device 20 such that the bump electrode 7 and the liquid crystal panel input / output terminal 5 are connected to each other. As described above, the conductive particles 10 are captured between the liquid crystal panel 7 and the liquid crystal panel input / output terminal 5.

ここで、図４において、液晶駆動用IC ６を液晶パネル入出力端子５に熱圧着する際に生じるＡＣＦ ９中の熱硬化性樹脂の流れ方向が矢印で示されている。熱圧着において、ＡＣＦ ９中の熱硬化性樹脂は液晶駆動用IC ６の中心からICの外に向かって、排出される。したがって、ＡＣＦ ９中の熱硬化性樹脂においても、液晶駆動用IC ６の中心からICの外に向かっての流れが発生する。   Here, in FIG. 4, the flow direction of the thermosetting resin in the ACF 9 generated when the liquid crystal driving IC 6 is thermocompression bonded to the liquid crystal panel input / output terminal 5 is indicated by arrows. In thermocompression bonding, the thermosetting resin in the ACF 9 is discharged from the center of the liquid crystal driving IC 6 toward the outside of the IC. Accordingly, the thermosetting resin in the ACF 9 also flows from the center of the liquid crystal driving IC 6 toward the outside of the IC.

ここで、本発明においては図５に示すとおりバンプ電極７の側面に凹凸部３１が備えられているため、熱圧着に際しては、バンプ電極７の近傍領域３２におけるＡＣＦ９ 中の熱硬化性樹脂の流動性が抑えられる。そのため、バンプ電極７の側面に凹凸部３１がない従来の構造と比べると、ＡＣＦ ９中の熱硬化性樹脂のバンプ電極７の近傍領域３２における局所的な圧力はより高くなることになる。したがって、導電性粒子１０は、隣接するバンプ電極７間の中央領域３３に向かって追いやられる。   Here, in the present invention, as shown in FIG. 5, the bump electrode 7 is provided with the concavo-convex portion 31 on the side surface. Therefore, during thermocompression bonding, the flow of the thermosetting resin in the ACF 9 in the vicinity region 32 of the bump electrode 7. Sex is suppressed. Therefore, the local pressure in the vicinity region 32 of the thermosetting resin in the ACF 9 in the vicinity of the bump electrode 7 becomes higher as compared with the conventional structure in which the bump electrode 7 has no uneven portion 31 on the side surface. Accordingly, the conductive particles 10 are driven toward the central region 33 between the adjacent bump electrodes 7.

以上述べたＡＣＦ ９中の熱硬化性樹脂の流れは、熱圧着が終了しＡＣＦ ９中の熱硬化性樹脂が硬化すると収まり、導電性粒子１０もＡＣＦ ９中の熱硬化性樹脂が硬化した時の位置で固定される。結果として、バンプ電極７の側面に接触する導電性粒子１０が存在しなくなり、異なるバンプ電極間において導電性粒子１０が連なることによって生じる電気的短絡を防ぐことができる。   The flow of the thermosetting resin in the ACF 9 described above is settled when the thermocompression bonding is completed and the thermosetting resin in the ACF 9 is cured, and the conductive particles 10 are also cured when the thermosetting resin in the ACF 9 is cured. It is fixed at the position. As a result, the conductive particles 10 that contact the side surfaces of the bump electrodes 7 do not exist, and an electrical short circuit caused by the conductive particles 10 continuing between different bump electrodes can be prevented.

図６において、バンプ電極７の側面に形成される凹凸部３１の深さＤやピッチＷは適宜決めてよいが、本実施の形態においては、導電性粒子１０の直径は通常3〜5μm程であり、樹脂の流れに十分な抵抗を与えるためには凹凸部３１のピッチＷや、凹凸の深さＤについては１μm以上が良い。また、バンプ電極７の大きさは通常、短辺15μm〜50μm×長辺80μm〜150μm程度であるため、凹凸部３１のピッチＷと凹凸の深さＤは、バンプ面積の減少を防ぐために５μm以下がよい。   In FIG. 6, the depth D and the pitch W of the concavo-convex portion 31 formed on the side surface of the bump electrode 7 may be determined as appropriate, but in the present embodiment, the diameter of the conductive particles 10 is usually about 3 to 5 μm. In order to give sufficient resistance to the flow of resin, the pitch W of the uneven portions 31 and the depth D of the uneven portions are preferably 1 μm or more. In addition, since the size of the bump electrode 7 is usually about 15 μm to 50 μm on the short side × 80 μm to 150 μm on the long side, the pitch W of the concavo-convex portion 31 and the depth D of the concavo-convex are 5 μm or less to prevent a decrease in the bump area. Is good.

なお、一般的には、凹凸部３１の凹凸の深さＤ、ピッチＷは共に導電性粒子１０の直径よりも小さくすると、凹凸部３１の凹み部分への導電性粒子１０の入り込みを防ぐことができ、導電性粒子１０の凹み部分への入り込みによる樹脂の流れに対する抵抗の低下を防ぐことができる。   In general, if both the depth D and the pitch W of the concavo-convex portion 31 are smaller than the diameter of the conductive particles 10, the conductive particles 10 can be prevented from entering the recessed portions of the concavo-convex portion 31. It is possible to prevent a decrease in resistance to the flow of the resin due to the conductive particles 10 entering the recessed portions.

また、凹凸部３１は図３に示すようにノコギリ歯状でもよいが、パルス波のような溝が形成されていても良い。円弧状の形状でも良い。また、ピッチや深さを連続的に一方向に変化させることにより、導電性粒子１０の移動を微妙に制御してもよい。さらに、一部のバンプ電極７の側面部のみに凹凸部３１を形成し、他のバンプ電極７の側面には形成しなくても良い。以上の形態を適宜組み合わせてもよい。凹凸部３１を有するバンプ電極７と有しないバンプ電極７とを混在させることにより、導電性粒子１０の移動する分布をより細かく制御することが可能となる。   Moreover, although the uneven | corrugated | grooved part 31 may be a sawtooth shape as shown in FIG. 3, the groove | channel like a pulse wave may be formed. An arc shape may be used. Further, the movement of the conductive particles 10 may be delicately controlled by continuously changing the pitch and depth in one direction. Furthermore, the concavo-convex portion 31 may be formed only on the side surface portion of some of the bump electrodes 7 and may not be formed on the side surfaces of other bump electrodes 7. You may combine the above forms suitably. By mixing the bump electrode 7 having the concavo-convex portion 31 and the bump electrode 7 not having the concavo-convex portion 31, it is possible to more finely control the distribution of the conductive particles 10 moving.

次に、表示装置２０の製造方法について、図７を参照して詳細に説明を行なう。図７（ａ）〜（ｅ）は、本発明にかかる第１の絶縁性基板１に入出力端子５を備える表示装置２０において、表示領域３および周辺領域４についての製造工程を説明するための断面図である。   Next, a method for manufacturing the display device 20 will be described in detail with reference to FIG. 7A to 7E are diagrams for explaining a manufacturing process for the display region 3 and the peripheral region 4 in the display device 20 including the input / output terminal 5 on the first insulating substrate 1 according to the present invention. It is sectional drawing.

図７（ａ）において、ガラスなどの第１の絶縁性基板１上にスパッタリング、写真製版などを用いて、周辺領域にゲート線側の全ての入出力端子５、および表示領域にゲート電極（ゲート線）２１を２００〜３００ｎｍの厚さで形成する。配線材料としては、アルミニウム、アルミニウム合金、クロム、モリブデン、チタン等が用いられる。   In FIG. 7A, all the input / output terminals 5 on the gate line side are formed in the peripheral region and the gate electrode (gate) is formed in the display region using sputtering, photoengraving or the like on the first insulating substrate 1 such as glass. Line) 21 is formed with a thickness of 200 to 300 nm. As the wiring material, aluminum, aluminum alloy, chromium, molybdenum, titanium, or the like is used.

次に図７（ｂ）において、プラズマＣＶＤ法を用い、全面にＳｉＮやＳｉＯ２等の材料からなるゲート絶縁膜１２を形成する。   Next, in FIG. 7B, a gate insulating film 12 made of a material such as SiN or SiO 2 is formed on the entire surface by plasma CVD.

次に図７（ｃ）において、表示領域の各画素を駆動するためのスイッチング素子として、ゲート電極２１、ゲート絶縁膜１２上にａ−Ｓｉ（非晶質シリコン）からなるチャネル層２２、コンタクト層２３と、導電膜からなるソース電極２４、ドレイン電極２５とをプラズマＣＶＤ法あるいはスパッタリング法と、写真製版法により形成する。次にプラズマＣＶＤ等の成膜方法を用いて、表示領域、周辺領域ともにＳｉＮ等からなるパッシベーション膜１３を形成する。このパッシベーション膜１３は、ソース電極２４から延在するソース線の周辺領域の入出力端子（図示せず）において、ソース線材料の表面が露出して配線間で腐食が発生することを防止する。   Next, in FIG. 7C, as a switching element for driving each pixel in the display region, a gate electrode 21, a channel layer 22 made of a-Si (amorphous silicon) on the gate insulating film 12, and a contact layer 23, and a source electrode 24 and a drain electrode 25 made of a conductive film are formed by plasma CVD or sputtering, and photolithography. Next, a passivation film 13 made of SiN or the like is formed in both the display region and the peripheral region by using a film forming method such as plasma CVD. The passivation film 13 prevents the surface of the source line material from being exposed and corroding between the wirings at the input / output terminals (not shown) in the peripheral region of the source line extending from the source electrode 24.

次に図７（ｄ）に示すように、全面にアクリル樹脂等で構成される有機膜１４を塗布等の方法により形成する。   Next, as shown in FIG. 7D, an organic film 14 made of acrylic resin or the like is formed on the entire surface by a method such as coating.

次に図７（ｅ）に示すように、表示領域および周辺領域のうち、電気的接続を行う必要のある領域における絶縁膜１２、パッシベーション膜１３および有機膜１４をドライエッチングで除去する。図７（ｅ）では、入出力端子５の接続部５ａやドレイン電極２５の一部を露出させるように加工する形態を示した。   Next, as shown in FIG. 7E, the insulating film 12, the passivation film 13 and the organic film 14 in the display area and the peripheral area where electrical connection is required are removed by dry etching. FIG. 7E shows a form in which the connection portion 5a of the input / output terminal 5 and the drain electrode 25 are partially exposed.

最後に、入出力端子５上のバンプ電極７との接続部５ａおよび表示領域に０.１μｍの厚さのＩＴＯ等からなる透明導電膜１５をスパッタリング等の成膜方法により成膜する。成膜した後に透明導電膜１５をパターニングする。図７（ｅ）の周辺領域においては、入出力端子５の接続部５ａを被覆するようにパターニングされ、図７（ｅ）の表示領域においては画素電極としてパターニングされる。   Finally, a transparent conductive film 15 made of ITO or the like having a thickness of 0.1 μm is formed on the connection portion 5a of the bump electrode 7 on the input / output terminal 5 and the display region by a film forming method such as sputtering. After the film formation, the transparent conductive film 15 is patterned. In the peripheral region of FIG. 7E, patterning is performed so as to cover the connection portion 5a of the input / output terminal 5, and in the display region of FIG. 7E, patterning is performed as a pixel electrode.

後は、本発明に係る半導体素子である液晶駆動用IC ６を実装すれば、図３に示したような構造を備えた電子機器である液晶表示装置を得ることができる。また、本発明に係る半導体素子を適用できる電子機器は、液晶表示装置に限定されない。ＥＬディスプレイ、プラズマディスプレイ、電子ペーパー、プロジェクションモニター等の表示装置や、それ以外の電子機器においても、導電性粒子を含むＡＣＦ ９中の熱硬化性樹脂を用いた熱圧着により半導体素子を実装する電子機器に広く適用することができる。   After that, if the liquid crystal driving IC 6 which is a semiconductor element according to the present invention is mounted, a liquid crystal display device which is an electronic device having the structure shown in FIG. 3 can be obtained. Further, an electronic device to which the semiconductor element according to the present invention can be applied is not limited to a liquid crystal display device. Electronics for mounting semiconductor elements by thermocompression bonding using thermosetting resin in ACF 9 containing conductive particles in display devices such as EL displays, plasma displays, electronic paper, projection monitors, and other electronic devices. Can be widely applied to equipment.

１ 第１の絶縁性基板、２ 第２の絶縁性基板、 ３ 表示領域、 ４ 周辺領域、
５ 入出力端子、 ６ 液晶駆動用IC、 ７ バンプ電極、 ８ フレキシブル基板、
９ ＡＣＦ、 １０ 導電性粒子、１１ 制御基板、
１２ 絶縁膜、 １３ パッシベーション膜、 １４ 有機膜、１５ 透明導電膜、
６ａ 液晶駆動用ICの配置領域、２０ 表示装置
３１ 凹凸部、３２ バンプ電極の近傍領域、３３ 隣接バンプ間の中央領域 1 first insulating substrate, 2 second insulating substrate, 3 display area, 4 peripheral area,
5 I / O terminals, 6 Liquid crystal drive ICs, 7 Bump electrodes, 8 Flexible substrates,
9 ACF, 10 conductive particles, 11 control substrate,
12 insulating film, 13 passivation film, 14 organic film, 15 transparent conductive film,
6a Liquid crystal drive IC placement area, 20 Display device 31 Concavity and convexity, 32 Area near bump electrode, 33 Center area between adjacent bumps

Claims (4)

複数のバンプ電極を有し、
前記バンプ電極のうち少なくとも一つの側面部には、凹凸部が設けられていることを特徴とする半導体素子。 Having a plurality of bump electrodes,
A semiconductor element, wherein at least one side surface portion of the bump electrode is provided with an uneven portion. 複数のバンプ電極を有し、
前記バンプ電極のうち少なくとも一つの側面部には、凹凸部が設けられていることを特徴とする半導体素子と、
入出力端子とを備えた電子機器であって、
前記半導体素子はＡＣＦを用いて前記電子機器に実装されており、
前記凹凸部が設けられている前記バンプ電極と、前記入出力端子とは、前記ＡＣＦ中に添加された導電性粒子を介して接続されていることを特徴とする電子機器。 Having a plurality of bump electrodes,
At least one side surface portion of the bump electrode is provided with a concavo-convex portion, and a semiconductor element,
An electronic device having an input / output terminal,
The semiconductor element is mounted on the electronic device using an ACF,
The electronic apparatus, wherein the bump electrode provided with the concavo-convex portion and the input / output terminal are connected via conductive particles added to the ACF. 前記凹凸部の深さあるいはピッチの少なくとも一方が、前記導電性粒子の直径以下の大きさであることを特徴とする請求項２に記載の電子機器。 The electronic device according to claim 2, wherein at least one of a depth or a pitch of the concavo-convex portion is a size equal to or smaller than a diameter of the conductive particles. 前記凹凸部の深さあるいはピッチの少なくとも一方が、１μｍよりも大きいことを特徴とする請求項３に記載の電子機器。 The electronic apparatus according to claim 3, wherein at least one of a depth or a pitch of the uneven portion is larger than 1 μm.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015179831A (en) * 2014-02-27 2015-10-08 デクセリアルズ株式会社 Connection body, manufacturing method of the same, and inspection method of the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015179831A (en) * 2014-02-27 2015-10-08 デクセリアルズ株式会社 Connection body, manufacturing method of the same, and inspection method of the same

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