JP2008053547A - Display device, and manufacturing method therefor - Google Patents

Display device, and manufacturing method therefor Download PDF

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JP2008053547A
JP2008053547A JP2006229555A JP2006229555A JP2008053547A JP 2008053547 A JP2008053547 A JP 2008053547A JP 2006229555 A JP2006229555 A JP 2006229555A JP 2006229555 A JP2006229555 A JP 2006229555A JP 2008053547 A JP2008053547 A JP 2008053547A
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film
bumps
input
region
driver lsi
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Hitoshi Morishita
均 森下
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Mitsubishi Electric Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

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  • Liquid Crystal (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device where a plurality of conductive particles can be captured on Au bumps, even when an Au bump area is made to be small for miniaturization and multiple output of a driver LSI. <P>SOLUTION: In a driver LSI arranged region 6a, a film wall 15 is formed of a film member so as to surround the plurality of Au bumps 7. A region is such that the film wall 15 is not formed and which is located inside the film wall 15 and is set to be a recess 15a. Via the ACF 9 stuck to the recess 15a, an input/output terminal 5 and the Au bumps 7 are connected directly to an insulating substrate. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は表示装置等の画素を形成した絶縁性基板上の周囲に形成された入出力端子に、異方性導電膜を用いてドライバーLSIを直接実装するCOG工法を採用した表示装置および該表示装置の製造方法に関するものである。   The present invention relates to a display device employing a COG method in which a driver LSI is directly mounted on an input / output terminal formed around an insulating substrate on which pixels such as a display device are formed using an anisotropic conductive film, and the display The present invention relates to a device manufacturing method.

近年、液晶表示装置の安価な製造工法としてCOG(Chip On Glass 以下、COGと称する)工法の採用が進んでいる。これはAuバンプを形成したドライバーLSIをガラス等の絶縁性基板の周囲に形成された入出力端子上に異方性導電膜(Anisotropic Conductive Film 以下、ACFと称する)を用いて直接搭載する工法である。この工法を採用する場合、ドライバーLSIを駆動するための電源線および信号線に接続する入出力端子列は、ドライバーLSIに設けられたAuバンプとACFを介して接続される必要がある。   In recent years, a COG (Chip On Glass, hereinafter referred to as COG) method has been adopted as an inexpensive manufacturing method for liquid crystal display devices. This is a method of mounting a driver LSI with Au bumps directly on an input / output terminal formed around an insulating substrate such as glass using an anisotropic conductive film (hereinafter referred to as ACF). is there. When this method is employed, the input / output terminal array connected to the power supply line and signal line for driving the driver LSI needs to be connected to the Au bump provided on the driver LSI via the ACF.

また、AuバンプはドライバーLSI内に多数設ける必要があるため、そのバンプの面積は非常に小さなものにならざるを得ないが、ドライバーLSIの小型化や多出力の目的でAuバンプ面積を小さくした場合、Auバンプ上に複数個捕捉される必要があるACF中の導電粒子が、捕捉されずに線欠陥などの表示不良を引き起こす品質不良がしばしば発生していた。   In addition, since it is necessary to provide a large number of Au bumps in the driver LSI, the area of the bumps must be very small, but the Au bump area has been reduced for the purpose of downsizing the driver LSI and increasing the number of outputs. In some cases, a plurality of conductive particles in the ACF that need to be captured on the Au bump often fail to be captured and cause a display defect such as a line defect.

このような問題を改善する方法として、特許文献1に示すように、プリント基板4側の電極5の周囲に電極5より厚い絶縁性部材であるレジスト8を配置して、電極5部のみに凹部を形成し、半導体部品1のバンプ2とこの凹部とでACF6を挟み込むことでACF6溶融時の流動性を阻害し、導電粒子7の捕捉性を向上させることが開示されている。   As a method for solving such a problem, as shown in Patent Document 1, a resist 8 that is an insulating member thicker than the electrode 5 is disposed around the electrode 5 on the printed circuit board 4 side, and a recess is formed only in the electrode 5 portion. It is disclosed that the ACF 6 is sandwiched between the bumps 2 of the semiconductor component 1 and the recesses to inhibit the fluidity when the ACF 6 is melted, thereby improving the trapping property of the conductive particles 7.

しかしながら、この構造では、レジスト8とACF6が直接接する構造となり、ACF6硬化後に密着力低下による界面剥離が生じやすい。また、半導体部品と異なり、液晶等を用いる表示装置の入出力端子は微小であるため、このような方法を用いてACF6の仮圧着を行うと凹部に気泡が残存し、ACF6硬化後もこの残存気泡による信頼性の低下を招くという問題があった。   However, in this structure, the resist 8 and the ACF 6 are in direct contact with each other, and interface peeling due to a decrease in adhesion tends to occur after the ACF 6 is cured. Also, unlike semiconductor components, the input / output terminals of a display device using liquid crystal or the like are very small. Therefore, when ACF6 is temporarily bonded using such a method, bubbles remain in the recesses and remain even after ACF6 is cured. There was a problem that reliability was lowered due to air bubbles.

また、特許文献2には、ACF自体を改善する方法として、ACFを2層の構造に分けパネル側入出力端子に接する層のみに導電粒子を混入させることが開示されている。   Patent Document 2 discloses a method of improving the ACF itself by dividing the ACF into a two-layer structure and mixing conductive particles only in the layer in contact with the panel side input / output terminal.

しかしながら、この工法を採用してもドライバーLSIのAuバンプと入出力端子により、ACF中の導電粒子が捕捉されるまでにドライバーLSIの外側へ流れ出すACFが多いため、Auバンプ面積が小さい場合は導電粒子の捕捉がなされないという問題があった。   However, even if this method is used, the ACF flows out of the driver LSI until the conductive particles in the ACF are captured by the driver LSI Au bumps and input / output terminals. There was a problem that particles were not captured.

特開平11−16949号公報(第2−3頁、第1図、第2図)Japanese Patent Laid-Open No. 11-16949 (page 2-3, FIGS. 1 and 2) 特開2005−333119号公報(第17−20頁、第1図、第2図)JP 2005-333119 A (pages 17-20, FIGS. 1 and 2)

本発明は、上述のような課題を解決するためになされたもので、ドライバーLSIの小型化や多出力のためにAuバンプ面積を小さくした場合であっても、導電粒子がAuバンプ上に複数個捕捉されることができる表示装置を提供することを目的とする。   The present invention has been made to solve the above-described problems, and even when the Au bump area is reduced for downsizing of the driver LSI or multiple outputs, a plurality of conductive particles are formed on the Au bump. It is an object to provide a display device that can be captured individually.

本発明の表示装置は、絶縁性基板上の表示領域に形成された複数の画素から延在され、周辺領域に形成される複数の入出力端子と、入出力端子に外部からの信号を入力し、画素を駆動させるための複数のバンプを有するドライバーLSIと、周辺領域のドライバーLSI配置領域において、複数のバンプを取り囲むように膜壁部が設けられ、複数のバンプは、膜壁部の内側に貼付された異方性導電膜によって、前記複数の入出力端子と接続されることを特徴とする。   The display device of the present invention extends from a plurality of pixels formed in a display region on an insulating substrate, inputs a plurality of input / output terminals formed in a peripheral region, and inputs an external signal to the input / output terminals. In the driver LSI having a plurality of bumps for driving the pixel and the driver LSI arrangement region in the peripheral region, a film wall portion is provided so as to surround the plurality of bumps, and the plurality of bumps are provided inside the film wall portion. The plurality of input / output terminals are connected to each other by an attached anisotropic conductive film.

また、本発明の表示装置の製造方法は、絶縁性基板上の表示領域に形成された複数の画素から延在され、周辺領域に形成される複数の入出力端子と、入出力端子に外部からの信号を入力し、画素を駆動させるための複数のバンプを有するドライバーLSIとを備えた表示装置の製造方法において、絶縁性基板の周辺領域に入出力端子を形成する工程と、絶縁性基板の全面に絶縁膜を形成する工程と、画素を駆動するためのスイッチング素子形成後に、前記絶縁性基板の全面にパッシベーション膜と、有機膜とを順次積層する工程と、周辺領域のドライバーLSI配置領域において、複数のバンプを取り囲むように積層した絶縁膜、パッシベーション膜、有機膜を除去して、膜壁部を形成する工程と、複数のバンプを前記膜壁部の内部に貼付された異方性導電膜によって、複数の入出力端子と接続させる工程、とを含むことを特徴とする。   The display device manufacturing method of the present invention extends from a plurality of pixels formed in a display region on an insulating substrate, and includes a plurality of input / output terminals formed in a peripheral region, and the input / output terminals from the outside. And a driver LSI having a plurality of bumps for driving the pixels, a process for forming input / output terminals in the peripheral region of the insulating substrate, In a step of forming an insulating film on the entire surface, a step of sequentially depositing a passivation film and an organic film on the entire surface of the insulating substrate after forming a switching element for driving a pixel, and a driver LSI arrangement region in a peripheral region Removing the insulating film, the passivation film, and the organic film laminated so as to surround the plurality of bumps to form a film wall portion, and attaching the plurality of bumps to the inside of the film wall portion. The anisotropic conductive film, the step of connecting a plurality of input and output terminals, characterized in that it comprises a city.

本発明の表示装置は、絶縁性基板上の周辺領域のドライバーLSI配置領域において、前記複数のバンプを取り囲むように膜部材による膜壁部を設けたので、膜壁部の内部に貼付された異方性導電膜が膜壁部の最上部に乗り上げてドライバーLSI配置領域から外部へ流れ出る量が減少するとともに、異方性導電膜が流れ出る速度(流速)が落ちるため、ドライバーLSIの圧着時に異方性導電膜に存在する導電粒子が外部へ流れ出る量が減少し、バンプと入出力端子間を導通させるための導電粒子がドライバーLSI配置領域内に十分に確保されることにより、バンプと入出力端子間の導通不良を防止できる。   In the display device of the present invention, since the film wall portion is provided by the film member so as to surround the plurality of bumps in the driver LSI arrangement region in the peripheral region on the insulating substrate, the difference adhered to the inside of the film wall portion is provided. Since the amount of the anisotropic conductive film climbs on top of the film wall and flows out of the driver LSI placement area decreases, the anisotropic conductive film flows at a lower speed (flow velocity). The amount of conductive particles existing in the conductive conductive film is reduced to the outside, and the bumps and the input / output terminals are secured in the driver LSI placement area by sufficiently securing the conductive particles between the bumps and the input / output terminals. It is possible to prevent poor conduction between them.

本発明の表示装置の製造方法は、表示領域に膜部材を形成する工程と同工程で膜壁部を形成したので、膜壁部の形成工程を簡略化することができる。   In the manufacturing method of the display device of the present invention, the film wall portion is formed in the same process as the process of forming the film member in the display region, so that the film wall portion forming process can be simplified.

以下、本発明の表示装置の構成および製造方法についての実施の形態を図面に基づいて説明する。なお、各図において同一の符号を用いたものは、実質的に同様の構成を示す。
実施の形態1.
図1は、本発明に係る表示装置の概略構成を示す正面図、図2は図1の表示装置の周辺領域における主要部拡大図、図3は図2のA−A方向における断面図である。
Embodiments of the configuration and manufacturing method of a display device according to the present invention will be described below with reference to the drawings. In addition, what uses the same code | symbol in each figure shows the substantially same structure.
Embodiment 1 FIG.
1 is a front view showing a schematic configuration of a display device according to the present invention, FIG. 2 is an enlarged view of a main part in a peripheral region of the display device of FIG. 1, and FIG. 3 is a cross-sectional view in the AA direction of FIG. .

図1において、本発明に係る表示装置20は、ガラス等の透明な基板である第1の絶縁性基板1と、この第1の絶縁性基板1と対向するように配置される第2の絶縁性基板2を備えている。また、第1の絶縁性基板1上の表示領域3には複数のゲート線およびソース線によりマトリクス状に形成された複数の画素と、該画素の交差部付近に形成されたスイッチング素子とを備えている。第2の絶縁性基板2は、第1の絶縁性基板1の表示領域3上に形成された複数の画素と対向する位置にRGBのカラーフィルタをマトリクス状に形成し、2枚の基板間に封入した液晶に信号を入力することで表示を行う(図示せず)。図2に示すように、第1の絶縁性基板1上の表示領域3の外側である周辺領域4には外部からの電源、信号を複数のゲート線およびソース線に入力するための入出力端子5が形成されている。   In FIG. 1, a display device 20 according to the present invention includes a first insulating substrate 1 that is a transparent substrate such as glass, and a second insulating member that is disposed so as to face the first insulating substrate 1. A conductive substrate 2 is provided. The display region 3 on the first insulating substrate 1 includes a plurality of pixels formed in a matrix by a plurality of gate lines and source lines, and a switching element formed near the intersection of the pixels. ing. The second insulating substrate 2 is formed by forming RGB color filters in a matrix in positions facing the plurality of pixels formed on the display region 3 of the first insulating substrate 1, and between the two substrates. Display is performed by inputting a signal to the sealed liquid crystal (not shown). As shown in FIG. 2, the peripheral region 4 outside the display region 3 on the first insulating substrate 1 has an input / output terminal for inputting power and signals from the outside to a plurality of gate lines and source lines. 5 is formed.

図1において、外部からの電源、信号は、制御基板11からフレキシブル基板(Flexible Printed Circuit:FPC)8を介してドライバーLSI6に送られる。図3に示すように、ドライバーLSI6と入出力端子5との接続は、ドライバーLSI6に形成されたAuなどのバンプ7(以下、Auバンプと称する)を第1の絶縁性基板1にACF9を用いて直接実装することで行われる。   In FIG. 1, a power supply and a signal from the outside are sent from a control board 11 to a driver LSI 6 via a flexible printed circuit (FPC) 8. As shown in FIG. 3, the driver LSI 6 and the input / output terminal 5 are connected by using bumps 7 such as Au (hereinafter referred to as Au bumps) formed on the driver LSI 6 and ACF 9 on the first insulating substrate 1. It is done by implementing directly.

ACF9はエポキシなどの絶縁性樹脂中にNi/Auめっきで覆われたプラスチック粒子や、Ni粒子などの導電粒子10が分散されており、この導電粒子10がAuバンプ7と入出力端子5との間で捕捉されることによりドライバーLSI6と入出力端子5との導通がなされる。   In the ACF 9, plastic particles covered with Ni / Au plating or conductive particles 10 such as Ni particles are dispersed in an insulating resin such as epoxy, and the conductive particles 10 are connected to the Au bumps 7 and the input / output terminals 5. The driver LSI 6 and the input / output terminal 5 are brought into conduction by being captured between them.

図2および図3に示すように、周辺領域4のドライバーLSI配置領域6aにおいて、複数のAuバンプ7を取り囲むように、膜部材により膜壁部15を形成する。なお、膜壁部15を形成しない領域であって、膜壁部15の内部を凹部15aとする。膜壁部15はドライバーLSI配置領域6aと同じサイズ、もしくはドライバーLSI配置領域6aよりも内側において、複数のAuバンプ7を取り囲むように形成する。また、隣接するAuバンプ7間には膜壁部15を形成させない。なお、凹部15aには、複数のAuバンプ7と接続する複数の入出力端子5が設けられており、この入出力端子上にITO16を形成してAuバンプ7との接続部5aとする。凹部15aおよびドライバーLSI配置領域6aより、若干外側にはみ出すようにACF9を貼り付け、入出力端子5の接続部5aとAuバンプ7とを第1の絶縁性基板1上に直接接続させている。   As shown in FIGS. 2 and 3, a film wall portion 15 is formed by a film member so as to surround a plurality of Au bumps 7 in the driver LSI arrangement area 6 a in the peripheral area 4. In addition, it is an area | region which does not form the film wall part 15, Comprising: Let the inside of the film wall part 15 be the recessed part 15a. The film wall 15 is formed so as to surround the plurality of Au bumps 7 at the same size as the driver LSI placement area 6a or inside the driver LSI placement area 6a. Further, the film wall portion 15 is not formed between the adjacent Au bumps 7. A plurality of input / output terminals 5 connected to the plurality of Au bumps 7 are provided in the recess 15a, and ITO 16 is formed on the input / output terminals to form a connection portion 5a with the Au bump 7. The ACF 9 is pasted so as to protrude slightly outward from the recess 15a and the driver LSI placement region 6a, and the connection portion 5a of the input / output terminal 5 and the Au bump 7 are directly connected to the first insulating substrate 1.

次に、本発明の表示装置20の第1の絶縁性基板1上に膜壁部15と凹部15aを形成する製造方法について、図4を参照して詳細に説明を行う。図4(a)〜(e)は本発明にかかわる第1の絶縁性基板1に入出力端子5を備える表示装置の周辺領域および表示領域の製造工程について説明するための断面図である。   Next, a manufacturing method for forming the film wall 15 and the recess 15a on the first insulating substrate 1 of the display device 20 of the present invention will be described in detail with reference to FIG. 4A to 4E are cross-sectional views for explaining a peripheral region of a display device including the input / output terminal 5 on the first insulating substrate 1 according to the present invention and a manufacturing process of the display region.

図4(a)において、ガラスなどの第1の絶縁性基板1上にスパッタリング、写真製版などを用いて、周辺領域にゲート線側の全ての入出力端子5、および表示領域にゲート電極(ゲート線)21を2000〜3000Åの厚さで形成する。配線材料としては、アルミニウム、アルミニウム合金、クロム、モリブデン、チタン等が用いられる。   In FIG. 4A, sputtering, photoengraving or the like is used on the first insulating substrate 1 such as glass, all the input / output terminals 5 on the gate line side in the peripheral region, and the gate electrode (gate) in the display region. Line) 21 is formed with a thickness of 2000 to 3000 mm. As the wiring material, aluminum, aluminum alloy, chromium, molybdenum, titanium, or the like is used.

次に図4(b)において、プラズマCVD法を用い、SiN等を用いて全面にゲート絶縁膜12を形成する。   Next, in FIG. 4B, the gate insulating film 12 is formed on the entire surface using SiN or the like by plasma CVD.

次に図4(c)において、表示領域の各画素を駆動するためのスイッチング素子としてゲート電極21、ゲート絶縁膜12上にa−Siからなるチャネル層22、コンタクト層23、ソース電極24、ドレイン電極25をプラズマCVD法、写真製版法により形成する。次にSiN等を用いて、表示領域、周辺領域ともにパッシベーション膜13を形成する。このパッシベーション膜13はソース電極24から延在し、ソース線側の周辺領域の入出力端子(図示せず)において、ソース線材料の表面が露出し配線間で腐食が発生することを防止する。   Next, in FIG. 4C, a gate electrode 21 as a switching element for driving each pixel in the display region, a channel layer 22 made of a-Si on the gate insulating film 12, a contact layer 23, a source electrode 24, a drain The electrode 25 is formed by plasma CVD or photolithography. Next, a passivation film 13 is formed in both the display region and the peripheral region using SiN or the like. The passivation film 13 extends from the source electrode 24 and prevents the surface of the source line material from being exposed and corroding between the wirings at input / output terminals (not shown) in the peripheral region on the source line side.

次に図4(d)に示すように、全面にアクリル樹脂等で構成される有機膜14を形成する。   Next, as shown in FIG. 4D, an organic film 14 made of an acrylic resin or the like is formed on the entire surface.

次に図4(e)に示すように、表示領域の絶縁膜12、パッシベーション膜13および有機膜14をドライエッチングで除去する。   Next, as shown in FIG. 4E, the insulating film 12, the passivation film 13, and the organic film 14 in the display region are removed by dry etching.

また、同時に周辺領域のドライバーLSI配置領域6aにおいて、絶縁膜12、パッシベーション膜13および有機膜14で形成した膜を複数のAuバンプ7を取り囲むようにドライエッチングで除去して、膜壁部15および膜壁部15を形成しない凹部15aを形成する。また、前述した通り、膜壁部15はドライバーLSI配置領域6aと同じサイズ、もしくはドライバーLSI配置領域6aよりも内側において、複数のAuバンプ7を取り囲むように形成し、隣接するAuバンプ7間には膜壁部15を形成させない。Auバンプ7間に膜壁部15を形成させないことで、Auバンプ7と入出力端子5をACF9によって接続させる際に、気泡が残存することを防止することができる。   At the same time, in the driver LSI arrangement region 6a in the peripheral region, the film formed of the insulating film 12, the passivation film 13, and the organic film 14 is removed by dry etching so as to surround the plurality of Au bumps 7, and the film wall 15 and A recess 15a that does not form the film wall 15 is formed. Further, as described above, the film wall portion 15 is formed so as to surround the plurality of Au bumps 7 within the same size as the driver LSI arrangement region 6 a or inside the driver LSI arrangement region 6 a, and between the adjacent Au bumps 7. Does not form the membrane wall 15. By not forming the film wall portion 15 between the Au bumps 7, it is possible to prevent bubbles from remaining when the Au bumps 7 and the input / output terminals 5 are connected by the ACF 9.

最後に、入出力端子5上のAuバンプ7との接続部5aおよび表示領域に0.1μmの厚さのITO16をスパッタリングで成膜する。   Finally, an ITO 16 having a thickness of 0.1 μm is formed by sputtering on the connection portion 5a with the Au bump 7 on the input / output terminal 5 and the display area.

さらに、ドライバーLSI6を第1の絶縁性基板1の周辺領域4に接続する方法について説明を行う。   Further, a method for connecting the driver LSI 6 to the peripheral region 4 of the first insulating substrate 1 will be described.

図2および図3に示すように、まず、第1の絶縁性基板1上の周辺領域に形成した入出力端子5の接続部5aおよび凹部15aの内部を完全に覆い、ドライバーLSI配置領域6aより若干はみ出すようにACF9を貼付する。   As shown in FIGS. 2 and 3, first, the inside of the connection portion 5a and the recess portion 15a of the input / output terminal 5 formed in the peripheral region on the first insulating substrate 1 is completely covered, and from the driver LSI arrangement region 6a. ACF9 is applied so that it protrudes slightly.

次にドライバーLSI6のAuバンプ7と入出力端子5の接続部5aとを精度良く配置させた後、加熱加圧ツールを用いて熱圧着し、ACF9を硬化させることで接続させる。このときの圧着条件は、例えば、ACF9の到達温度170〜200℃、時間5〜10秒、圧力30〜100MPaとする。   Next, after arranging the Au bump 7 of the driver LSI 6 and the connection portion 5a of the input / output terminal 5 with high accuracy, the ACF 9 is cured by thermocompression bonding using a heating / pressurizing tool and then connected. The pressure bonding conditions at this time are, for example, an ultimate temperature of ACF9 of 170 to 200 ° C., a time of 5 to 10 seconds, and a pressure of 30 to 100 MPa.

この条件で熱圧着すると、ドライバーLSI6のAuバンプ7と入出力端子5間に存在する導電粒子10は扁平してAuバンプ7と入出力端子5の方向(上下方向)のみ導通を有する。また、凹部15a上には各々の捕捉された導電粒子10の周囲に絶縁性のエポキシ樹脂が存在するために絶縁が保たれる。   When thermocompression bonding is performed under these conditions, the conductive particles 10 existing between the Au bump 7 and the input / output terminal 5 of the driver LSI 6 are flattened and conductive only in the direction (vertical direction) between the Au bump 7 and the input / output terminal 5. Further, since the insulating epoxy resin is present around each captured conductive particle 10 on the recess 15a, insulation is maintained.

なお、図3に示すように、膜壁部15の高さhは、Auバンプ7よりも低くなるように形成する。膜壁部15の高さhを1.5μm以上とすることで、ドライバーLSI配置領域6aに形成した膜壁部15と、凹部15aとの段差が十分となりACF9が膜壁部15の最上部15bに乗り上げて凹部15aの外部へ流れ出る速度および量を減少させることができる。本発明においては、例えば、ゲート絶縁膜12、パッシベーション膜13を計0.6〜0.8μm、さらに有機膜14を1.0μm以上、好ましくは2〜3μm以上で形成する。   As shown in FIG. 3, the height h of the film wall portion 15 is formed to be lower than the Au bump 7. By setting the height h of the film wall portion 15 to 1.5 μm or more, the step between the film wall portion 15 formed in the driver LSI placement region 6a and the recess 15a becomes sufficient, and the ACF 9 becomes the uppermost portion 15b of the film wall portion 15. It is possible to reduce the speed and amount of running out to the outside of the recess 15a. In the present invention, for example, the gate insulating film 12 and the passivation film 13 are formed in a total thickness of 0.6 to 0.8 μm, and the organic film 14 is formed in a thickness of 1.0 μm or more, preferably 2 to 3 μm.

以上説明したとおり、本発明による表示装置20は、ドライバーLSI配置領域6aに膜壁部15を形成したので、膜壁部15と凹部15aとの段差により、ACF9が膜壁部15の最上部15bに乗り上げて凹部15aの外部へ流れ出る量が減少するとともに、ACF9が流れ出る速度(流速)が落ちるため、ドライバーLSI6の圧着時にACF9中に存在する導電粒子10が凹部15aの内部から流れ出る量が減少する。よって、凹部15aの内部にACF9中の導電粒子10を残留させることができる。すなわち、Auバンプ7と入出力端子5間を導通させるための導電粒子10が凹部15a内に十分に確保されることにより、Auバンプ7と入出力端子5間の導通不良が発生することが防止できるため、線欠陥などの表示不良が防止できる。   As described above, in the display device 20 according to the present invention, since the film wall portion 15 is formed in the driver LSI arrangement region 6a, the ACF 9 is formed on the uppermost portion 15b of the film wall portion 15 by the step between the film wall portion 15 and the concave portion 15a. The amount of flowing out to the outside of the recess 15a decreases and the speed (flow velocity) at which the ACF 9 flows out decreases, so that the amount of the conductive particles 10 existing in the ACF 9 flowing out of the inside of the recess 15a when the driver LSI 6 is pressed is reduced. . Therefore, the conductive particles 10 in the ACF 9 can remain inside the recess 15a. That is, when the conductive particles 10 for conducting between the Au bump 7 and the input / output terminal 5 are sufficiently secured in the recess 15a, the occurrence of poor conduction between the Au bump 7 and the input / output terminal 5 is prevented. Therefore, display defects such as line defects can be prevented.

なお、従来であれば、ドライバーLSI6を接続させた後に、ACF9が移動して入出力端子5が露出してしまい、入出力端子5が腐食して不良を起こすという不具合が生じていたが、本発明の表示装置20のように膜壁部15を形成することで、ドライバーLSI6接続後のACF9の移動を防止することができる。   Conventionally, after the driver LSI 6 is connected, the ACF 9 moves and the input / output terminal 5 is exposed, and the input / output terminal 5 is corroded to cause a defect. By forming the film wall portion 15 as in the display device 20 of the invention, it is possible to prevent the ACF 9 from moving after the driver LSI 6 is connected.

また、図3に示すように、膜壁部15は対向するAuバンプ7の側部との距離Lを近づけるように形成させることで、Auバンプ7と膜壁部15間から流れ出るACF9の量が減少するため、凹部15aの内部から外部へ流れ出ようとする導電粒子10の量をさらに減少させることができる。なお、距離Lは近づけるように形成するが、0.1μm以上とすることで、実装時の組み立て性を低下させることなく、凹部15aの内部から外部へ流れ出ようとする導電粒子10の量をさらに減少させることができる。   Further, as shown in FIG. 3, the film wall portion 15 is formed so as to have a distance L from the side portion of the opposing Au bump 7 so that the amount of ACF 9 flowing out between the Au bump 7 and the film wall portion 15 can be reduced. Therefore, the amount of the conductive particles 10 that are about to flow from the inside of the recess 15a to the outside can be further reduced. Although the distance L is formed so as to be close to 0.1 μm or more, the amount of the conductive particles 10 that flow out from the inside of the recess 15a is further reduced without deteriorating the assembling property at the time of mounting. Can be reduced.

膜壁部15は絶縁膜12、パッシベーション膜13および有機膜14で形成させたが、膜壁部15と凹部15aによって段差を形成させる構成であればよく、有機膜14の代わりにオーバーコート膜などで形成することによっても、同様な効果を奏する。また、膜壁部15は、単層の膜部材で構成することもできる。例えば、表示領域に形成する有機膜14と同工程で、周辺領域に有機膜14単層の膜壁部15を形成することもできる。   The film wall portion 15 is formed of the insulating film 12, the passivation film 13, and the organic film 14. However, the film wall portion 15 may have a configuration in which a step is formed by the film wall portion 15 and the concave portion 15a. The same effect can be obtained by forming the film. Moreover, the membrane wall part 15 can also be comprised with a single layer film | membrane member. For example, the single-layer film wall 15 of the organic film 14 can be formed in the peripheral region in the same process as the organic film 14 formed in the display region.

また、膜壁部15は、表示領域に膜部材である絶縁膜12、パッシベーション膜13および有機膜14を形成する工程と同工程で形成することで、膜壁部15の形成工程を簡略化させたが、膜壁部15を形成する工程は、別の工程で形成させることもできる。   Further, the film wall 15 is formed in the same process as the process of forming the insulating film 12, the passivation film 13, and the organic film 14 that are film members in the display region, thereby simplifying the process of forming the film wall 15. However, the step of forming the film wall portion 15 can be formed in a separate step.

また、本発明においては、膜壁部15を複数のドライバーLSIの配置領域6aにAuバンプ7を取り囲むために、略矩形状で形成させたが、凹部15aに貼付したACF9が膜壁部15の最上部15bに乗り上げて凹部15aの外部へ流れ出る量が減少するとともに、ACF9が流れ出る速度(流速)が落ちる形状であれば特に制限されることはない。   In the present invention, the film wall portion 15 is formed in a substantially rectangular shape so as to surround the Au bumps 7 in the plurality of driver LSI arrangement regions 6a. However, the ACF 9 attached to the recess 15a is formed on the film wall portion 15. There is no particular limitation as long as it has a shape that rides on the uppermost portion 15b and flows out of the recess 15a and the speed (flow velocity) at which the ACF 9 flows out decreases.

図5は本発明による表示装置の変形例を示す主要部拡大図である。図5において、ドライバーLSI6の短辺6b側にAuバンプ7を形成しない場合、短辺6b側の一部に膜壁部15を設けず、開口部を有する凹部15cを形成させる。この凹部15cを設けることで、ドライバーLSI6配置領域6aに貼付されたACF9が、短辺6b側に設けた開口部からドライバーLSI配置領域6aの外部へ流れ出るようにする。これにより、長辺6c側の膜壁部15の最上部から外部へ流れ出るACF9の総量が少なくなり、Auバンプ7と入出力端子5間を導通させるための導電粒子10が、入出力端子5の接続部5a上に十分に確保されることにより、Auバンプ7と入出力端子5間の導通不良が発生することが防止できるため、線欠陥などの表示不良が防止できる。なお、開口部は短辺6b側の一部に設ける構造としたが、短辺6b側の全部に開口部を設ける構造であってもよい。   FIG. 5 is an enlarged view of a main part showing a modification of the display device according to the present invention. In FIG. 5, when the Au bump 7 is not formed on the short side 6b side of the driver LSI 6, the film wall portion 15 is not provided on a part of the short side 6b side, and the concave portion 15c having an opening is formed. By providing the recess 15c, the ACF 9 affixed to the driver LSI 6 arrangement area 6a flows out of the driver LSI arrangement area 6a from the opening provided on the short side 6b side. Thereby, the total amount of ACF 9 flowing out from the uppermost part of the film wall 15 on the long side 6 c side is reduced, and the conductive particles 10 for conducting the Au bump 7 and the input / output terminal 5 are connected to the input / output terminal 5. By ensuring sufficiently on the connection part 5a, it is possible to prevent a poor conduction between the Au bump 7 and the input / output terminal 5, and thus a display defect such as a line defect can be prevented. In addition, although it was set as the structure which provides an opening part in the part by the side of the short side 6b, the structure which provides an opening part in the whole of the short side 6b side may be sufficient.

本実施の形態では、ゲート線から延在する入出力端子5について、説明してきたが、ソース線側の入出力端子についても同様に膜壁部および凹部を形成することで、上記と同様の効果を奏することができる。   In the present embodiment, the input / output terminal 5 extending from the gate line has been described. However, the same effect as described above can be obtained by forming the film wall portion and the concave portion in the input / output terminal on the source line side as well. Can be played.

本発明に係る表示装置の概略構成を示す正面図である。It is a front view which shows schematic structure of the display apparatus which concerns on this invention. 図1の表示装置の周辺領域における主要部拡大図である。It is a principal part enlarged view in the peripheral region of the display apparatus of FIG. 図2のA−A方向における断面図である。It is sectional drawing in the AA direction of FIG. 本発明の表示装置の各製造工程を示す断面図である。It is sectional drawing which shows each manufacturing process of the display apparatus of this invention. 本発明の変形例における主要部拡大図である。It is a principal part enlarged view in the modification of this invention.

1 第1の絶縁性基板、2 第2の絶縁性基板、 3 表示領域、 4 周辺領域、
5 入出力端子、 6 ドライバーLSI、 7Auバンプ、 9 ACF、
10 導電粒子、 12 絶縁膜、 13 パッシベーション膜、 14 有機膜、15 膜壁部、 15a 凹部、 6a ドライバーLSIの配置領域、20 表示装置。
1 first insulating substrate, 2 second insulating substrate, 3 display area, 4 peripheral area,
5 I / O terminals, 6 Driver LSI, 7 Au bump, 9 ACF,
DESCRIPTION OF SYMBOLS 10 Conductive particle, 12 Insulating film, 13 Passivation film | membrane, 14 Organic film | membrane, 15 Film | membrane wall part, 15a Recessed part, 6a Driver LSI arrangement | positioning area | region, 20 Display apparatus.

Claims (7)

絶縁性基板上の表示領域に形成された複数の画素から延在され、周辺領域に形成される複数の入出力端子と、
前記入出力端子に外部からの信号を入力し、前記画素を駆動させるための複数のバンプを有するドライバーLSIと、
前記周辺領域のドライバーLSI配置領域において、前記複数のバンプを取り囲むように膜壁部が設けられ、
前記複数のバンプは、前記膜壁部の内側に貼付された異方性導電膜によって、前記複数の入出力端子と接続されることを特徴とする表示装置。
A plurality of input / output terminals extending from a plurality of pixels formed in a display region on the insulating substrate and formed in a peripheral region;
A driver LSI having a plurality of bumps for inputting an external signal to the input / output terminal and driving the pixel;
In the peripheral area of the driver LSI, a film wall is provided so as to surround the plurality of bumps.
The display device, wherein the plurality of bumps are connected to the plurality of input / output terminals by an anisotropic conductive film affixed to the inside of the film wall portion.
前記膜壁部は、前記ドライバーLSI配置領域よりも内側において、前記複数のバンプを取り囲むように設けられることを特徴とする請求項1記載の表示装置。 The display device according to claim 1, wherein the film wall portion is provided inside the driver LSI arrangement region so as to surround the plurality of bumps. 前記膜壁部は、前記表示領域の画素上に膜部材を形成する工程と同工程で形成されることを特徴とする請求項1または2に記載の表示装置。 3. The display device according to claim 1, wherein the film wall portion is formed in the same step as a step of forming a film member on a pixel in the display region. 前記膜壁部は、少なくとも有機膜を含むことを特徴とする請求項1乃至3のいずれかに記載の表示装置。 The display device according to claim 1, wherein the film wall portion includes at least an organic film. 前記膜壁部は、絶縁膜、パッシベーション膜をさらに含むことを特徴とする請求項4記載の表示装置。 The display device according to claim 4, wherein the film wall portion further includes an insulating film and a passivation film. 絶縁性基板上の表示領域に形成された複数の画素から延在され、周辺領域に形成される複数の入出力端子と、
前記入出力端子に外部からの信号を入力し、前記画素を駆動させるための複数のバンプを有するドライバーLSIとを備えた表示装置の製造方法において、
前記絶縁性基板の周辺領域に前記入出力端子を形成する工程と、
前記絶縁性基板の表示領域に絶縁膜を形成し、前記画素を駆動するためのスイッチング素子形成後に、パッシベーション膜と、有機膜とを順次積層するとともに周辺領域に少なくとも有機膜を積層する工程と、
前記周辺領域のドライバーLSI配置領域において、積層した前記有機膜を前記複数のバンプを取り囲むように、エッチングによって除去して膜壁部を形成する工程と、
前記複数のバンプを前記膜壁部の内側に貼付された異方性導電膜によって、前記複数の入出力端子と接続させる工程、とを含むことを特徴とする表示装置の製造方法。
A plurality of input / output terminals extending from a plurality of pixels formed in a display region on the insulating substrate and formed in a peripheral region;
In a method for manufacturing a display device including a driver LSI having a plurality of bumps for inputting an external signal to the input / output terminal and driving the pixel,
Forming the input / output terminals in a peripheral region of the insulating substrate;
Forming an insulating film in the display region of the insulating substrate, forming a switching element for driving the pixel, sequentially laminating a passivation film and an organic film, and laminating at least an organic film in a peripheral region;
Forming a film wall portion by removing the stacked organic film by etching so as to surround the plurality of bumps in the driver LSI arrangement region in the peripheral region; and
And a step of connecting the plurality of bumps to the plurality of input / output terminals by an anisotropic conductive film affixed to the inside of the film wall.
前記表示領域に絶縁膜、パッシベーション膜を形成する工程とともに前記周辺領域に前記絶縁膜およびパッシベーション膜を積層する工程をさらに含み、周辺領域のドライバーLSI配置領域において、前記複数のバンプを取り囲むように、絶縁膜、パッシベーション膜および有機膜をエッチングによって除去して前記膜壁部を形成することを特徴とする請求項6記載の表示装置の製造方法。
In addition to forming an insulating film and a passivation film in the display region, the method further includes a step of laminating the insulating film and the passivation film in the peripheral region, and surrounding the plurality of bumps in the driver LSI arrangement region in the peripheral region. 7. The method of manufacturing a display device according to claim 6, wherein the film wall is formed by removing an insulating film, a passivation film, and an organic film by etching.
JP2006229555A 2006-08-25 2006-08-25 Display device, and manufacturing method therefor Pending JP2008053547A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108476591A (en) * 2015-06-16 2018-08-31 迪睿合株式会社 Connector, the manufacturing method of connector, detection method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108476591A (en) * 2015-06-16 2018-08-31 迪睿合株式会社 Connector, the manufacturing method of connector, detection method
CN108476591B (en) * 2015-06-16 2021-01-01 迪睿合株式会社 Connected body, method for producing connected body, and method for detecting connected body

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