JP2011229361A - Phase detection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a phase of an input signal with high accuracy without being affected by an unbalanced component and a harmonic component.SOLUTION: The phase detection device 10 includes: a fundamental wave orthogonal component calculating part 10 A including a three-phase/two-phase converting part 11 for converting three-phase voltage signals v, v, vinto voltage signals vα, vβ that are orthogonal to each other, a complex coefficient filter 12 for eliminating an unbalanced component and a harmonic component included in an input signal and a normalizing part 13 for normalizing the output thereof; and a phase calculating part 10B for using a voltage signal (sin(θ), cos(θ))(θ is a phase of the input signal) outputted from the fundamental wave orthogonal component calculating part 10 A to calculate a phase θ'. The complex coefficient filter 12 is configured by a complex coefficient bandpass filter that allows only a fundamental wave to pass through, and the unbalanced component and the harmonic component are prevented from being inputted to the phase calculating part 10B by filtering voltage signals vα, vβ outputted from the three-phase/two-phase converting part 11 as a complex input of vα+jvβ.

Description

  The present invention relates to a phase detector that detects the phase of a three-phase voltage signal of a power system.

One of the three-phase voltages of the power system is v = A _m · sin (ω · t) = A _m · sin (θ) (A _m : amplitude, θ: phase, ω: angular frequency, t: reference time Elapsed time), and when the three-phase voltage v is expressed by a vector symbol method, the voltage vector V is expressed by V = A _m · exp (j · θ) = A _m · exp (j · ω · t) . As shown in FIG. 23, this voltage vector V indicates a rotation vector that rotates counterclockwise at an angular frequency ω with the reference time as the direction of the real axis R, and the voltage vector V is projected onto the imaginary axis J at time t. The value is an instantaneous value of the three-phase voltage v. In the following description, in principle, a symbol indicating a voltage vector is expressed in capital letters, and a symbol indicating an instantaneous value of a three-phase voltage is expressed in small letters.

Conventionally, a PLL (Phase Locked Loop) method is known as a method for detecting the phase of a three-phase voltage signal of a power system. In the PLL method, when a voltage vector V ′ having a phase θ ′ calculated by a PLL circuit is A _m · exp (j · θ ′) = A _m · exp (j · ω ′ · t), a predetermined sampling period is set. To calculate the phase difference Δθ between the voltage vector V ′ and the voltage vector V of the power system, change the phase θ ′ of the voltage vector V ′ based on the phase difference Δθ, and change the voltage vector V ′ to the voltage vector V In this method, the phase θ ′ is controlled so as to coincide with.

Non-Patent Document 1 shows a configuration diagram of a phase detection apparatus using the multiplication type PLL method shown in FIG. The multiplying PLL method is based on the trigonometric formula.
sin (Δθ) = sin (θ−θ ′) = sin (θ) · cos (θ ′) − cos (θ) · sin (θ ′) (1)
If | Δθ | [rad] is very small, sin (Δθ) ≈Δθ. Therefore, the phase difference Δθ for changing the angular frequency ω ′ of the voltage vector V ′ is calculated by the above equation (1). This is a method of calculating by processing.

In the phase detection device 100 shown in FIG. 24, the three-phase voltage signals v _u , v _v , and v _w of the power system are _expressed as v _u = A _m · sin (θ), v _v = A _m · sin (θ−2π / 3), v _w = A _m · sin (θ−4π / 3), voltage signals vα = Aα · sin (θ) and vβ = −Aβ · cos (θ ), And the normalization unit 102 normalizes the amplitudes of the voltage signals vα and vβ to “1” to calculate the values of sin (θ) and −cos (θ) in the above equation (1). . The PLL processing unit 103 calculates the phase difference Δθ by performing the arithmetic processing of the above equation (1), and changes the phase θ ′ output from the PLL processing unit 103 based on the calculated value.

The phase detector 100 calculates the phase difference Δθ each time detection values (instantaneous values detected at a predetermined sampling period) of the three-phase voltage signals v _u , v _v , v _w of the power system are input, The phase θ ′ is changed based on the phase difference Δθ, and the loop processing for feeding back the phase θ ′ to the calculation processing of sin (θ−θ ′) is repeated, and the phase θ ′ output from the PLL processing unit 103 is changed. An operation for converging to a value at which the phase difference Δθ becomes zero, that is, the phase θ of the three-phase voltage signal of the actual power system is performed.

  A cosine value calculation unit 103a and a sine value calculation unit 103b are provided in the feedback path of the phase θ ′ of the PLL processing unit 103, and cos (θ ′) in the above equation (1) is calculated by the cosine value calculation unit 103a. The sine value calculation unit 103b calculates sin (θ ′) in the above equation (1). The operation value of the cosine value operation unit 103a is multiplied by sin (θ) from the normalization unit 102 by the multiplier 103c, and the operation value of the sine value operation unit 103b is −cos (θ from the normalization unit 102 by the multiplier 103d. ) And the two multiplied values are added by the adder 103e.

  Therefore, in the phase detection device 100, the three-phase to two-phase conversion unit 101 to the adder 103e of the PLL processing unit 103 constitute the arithmetic unit of the above equation (1), and the subsequent stage from the adder 103e has a phase difference Δθ. Based on this, a phase θ ′ calculated by the PLL processing unit 103 is changed, and a calculation unit is configured to converge the phase θ ′ of the voltage vector V ′ to the phase θ of the voltage vector V of the power system.

The phase detection apparatus 100 using the multiplying PLL method shown in FIG. 24 causes an abnormal voltage shortage or voltage imbalance when a ground accident occurs or a phase is lost at the closest end, and PLL processing occurs. Similarly, the voltage signals v _u , v _v , and v _w that are input to the unit 103 also become abnormal voltages, so that the calculation accuracy of the phase difference Δθ decreases, and the phase θ ′ is converged to the phase θ of the power system accordingly. There is a problem that the speed also decreases.

  Therefore, Non-Patent Document 1 and Patent Document 1 focus on the fact that the three-phase voltage signal of each phase is dominated by the positive phase even when the three-phase voltage signal becomes unbalanced due to an accident in the power system. 25, a PLL method has been proposed in which the phase θ ′ output from the PLL processing unit 103 ′ follows the phase of the positive phase of the three-phase voltage signal.

  The phase detection device 100 ′ shown in FIG. 25 is different from the phase detection device 100 shown in FIG. 24 in that the three-phase / two-phase conversion unit 101 is changed to the symmetric coordinate conversion unit 104 and the cosine value calculation unit 103a is changed to sin (θ ′ + 2π / The sine value calculation unit 103a ′ for calculating the sine value of 3) is changed.

In the symmetric coordinate conversion unit 104, the U-phase, V-phase, and W-phase voltage signals v _u , v _v , and v _w are converted into voltage signals v _up , v _vp , and v _wp for the positive phase of each phase by the following arithmetic expression. The normalization unit 102 normalizes the voltage signals v _up , v _vp , v _{wp for} the positive phase of each phase, respectively, and normalizes the voltage signals v _up ′ = sin (θ), v _vp ′ = sin (θ−2π / 3), v _wp ′ = sin (θ−4π / 3) is calculated.

When obtaining a phase difference Δθ = (θ−θ ′) using two sin (θ), sin (θ + ψ) and phase θ ′ having different phases,
sin (θ) · sin (θ '+ ψ) = sin (θ) · {sin (θ') · cos (ψ) + cos (θ ') · sin (ψ)}
sin (θ ′) · sin (θ + ψ) = sin (θ ′) · {sin (θ) · cos (ψ) + cos (θ) · sin (ψ)}
From the trigonometric formula of
sin (θ) ・ sin (θ '+ ψ) −sin (θ ′) ・ sin (θ + ψ)
= Sin (ψ) · {sin (θ) · cos (θ ′) − cos (θ) · sin (θ ′)}
= Sin (ψ) · sin (θ−θ ′) (2)
Is established, and sin (θ−θ ′) can be obtained from equation (2).

In the phase detection apparatus 100 ′ shown in FIG. 25, ψ = −4π / 3, and the voltage signal v _up ′ = sin (θ), v _wp ′ = sin (θ−4π) from the normalization unit 102 to the PLL processing unit 103 ′. / 3) is input, and sin (θ′−4π / 3) = sin (θ ′ + 2π / 3) in equation (2) is calculated by the sine value calculation unit 103a ′. Then, sin (θ) · sin (θ ′ + 2π / 3) is calculated by the multiplier 103c, and sin (θ-4π / 3) · sin (θ ′) = sin (θ + 2π / 3) · sin (θ ′) is calculated, and both calculated values are added by the adder 103e, and sin (−4π / 3) · sin (θ−θ ′) = {√ (3) / 2} · sin (θ−θ ') Is calculated.

If | θ−θ ′ | = | Δθ | [rad] is very small, {√ (3) / 2} · sin (θ−θ ′) ≈0.866 × Δθ. Information (0.866 × Δθ) of the phase difference Δθ is output. Therefore, to generate the adder control value based on the calculation result of the adder 103e is in a subsequent 103e [Delta] [omega (corresponding to a differential value of [Delta] [theta]), the angular frequency by adding a predetermined reference value omega ₀ to the control value [Delta] [omega A corresponding value ω ′ is generated, and an integration process is performed on the angular frequency ω ′ to calculate the phase θ ′.

  As shown in the vector diagram of FIG. 23, when the voltage vector V of the power system advances by Δθ with respect to the voltage vector V ′ generated by the PLL processing unit 103 ′, the adder 103e has a subsequent stage of the adder 103e. The angular frequency ω ′ is increased by Δω based on the calculated value, and the rotational speed ω ′ of the voltage vector V ′ generated by the PLL processing unit 103 ′ is set higher than the rotational speed ω of the voltage vector V of the power system. A PLL operation is performed to match the vector V ′ with the voltage vector V. When the voltage vector V ′ matches the voltage vector V, the PLL processing unit 103 ′ operates so as to maintain the state, and the phase θ that is the same as the voltage vector V of the power system is output from the phase detection device 100 ′. Will be.

JP 2000-116148 A

"PLL and frequency detection method to cope with abnormal voltage in case of power system failure" Denki Theory B, Vol. 118, No. 9, 1998

According to Non-Patent Document 1, the phase detection apparatus 100 ′ shown in FIG. 25 performs symmetric coordinate conversion on the detected values of the three-phase voltage signals v _u , v _v , and v _w of the power system. Since the voltage signals v _up , v _vp , and v _wp for the positive phase of the phase are calculated, unbalanced components and third, fifth, and seventh harmonic components are removed, and the PLL processing unit 103 ′ Although the adverse effect of these components can be eliminated by the above arithmetic processing, there is a feature that eleventh-order and thirteenth-order harmonic components cannot be removed.

Therefore, the conventional phase detection apparatus using the multiplying PLL method cannot completely eliminate unbalanced components and harmonic components that adversely affect the PLL processing, and there is room for improvement in terms of accuracy. . Further, in the phase detection apparatus 100 ′ shown in FIG. 25, the symmetric coordinate conversion processing is performed on the three-phase voltage signals v _u , v _v , and v _w , so at least the voltage signals v _u , v _v , and v of each phase Symmetric coordinate transformation processing is required for data corresponding to a quarter period of _w (about 4 milliseconds when the frequency is 60 Hz), which is also disadvantageous in terms of processing speed of phase detection.

  The present invention has been conceived under the circumstances described above, and removes an unbalanced component, a harmonic component, and a noise component by providing a filter circuit using a complex coefficient filter before the PLL processing unit. An object of the present invention is to provide a phase detection device capable of detecting a phase with high accuracy and high speed without being affected by these effects.

  According to the first aspect of the present invention, there is provided a phase generation unit that generates a phase, and a phase generated by the phase generation unit and a phase of the input AC signal each time an AC signal is input at a predetermined sampling period. If the phase difference is not zero, the phase generated by the phase generation means is changed based on the phase difference in a direction in which the phase difference decreases, and if the phase difference is zero In the phase detection apparatus including a phase synchronization unit having a phase control unit that performs control to hold the phase generated by the phase generation unit, an unbalanced component included in the AC signal is provided in a stage preceding the phase synchronization unit. Filter means comprising a complex coefficient filter for removing harmonic components is provided.

  According to a preferred embodiment, the complex coefficient filter is a bandpass filter that uses the fundamental wave as a center frequency of a passband, or a notch filter that blocks the unbalanced component and a harmonic component of a predetermined order, or the bandpass filter. And a multi-stage filter in which the notch filter is combined (claims 2 to 4).

  According to another preferred embodiment, the AC signal is a detection signal obtained by detecting a single-phase AC voltage flowing through a power system. Further, the AC signal is a detection signal obtained by detecting a three-phase AC voltage flowing through the power system, and converts the three-phase detection signal into two signals orthogonal to each other before the filter means. It is preferable to further comprise three-phase to two-phase conversion means for inputting the signal to the filter means as the signal of the real part of the complex signal and the other signal as the signal of the imaginary part of the complex signal.

  According to another preferred embodiment, the filter means outputs a sine value and a cosine value of a phase of a fundamental wave component included in the AC signal, and the phase control means calculates the phase difference. In order to do so, first sine value calculation means for calculating the sine value of the phase generated by the phase generation means, cosine value calculation means for calculating the cosine value of the phase generated by the phase generation means, Using the sine value and cosine value input from the filter means, the sine value calculated by the first sine value calculation means, and the cosine value calculated by the cosine value calculation means, a predetermined trigonometric function is obtained. And second sine value calculating means for calculating a sine value of the phase difference expressed by a multiplication formula.

In the phase detection device according to claim 7, the multiplication function of the trigonometric function is:
sin (θ) ・ cos (θ ') − cos (θ) ・ sin (θ ′) = sin (θ−θ ′)
Where θ is the phase of the fundamental component included in the AC signal
θ ′: phase generated by the phase generation means
sin (θ): Sine value input from the filter means
cos (θ): cosine value input from the filter means −sin (θ ′): sine value calculated by the first sine value calculation means
cos (θ ′): a cosine value calculated by the cosine value calculating means (claim 8).

  According to another preferred embodiment, the filter means outputs a sine value of the phase of the fundamental wave component included in the AC signal, and the phase control means calculates the phase difference. A sine value calculating means for calculating a sine value of the phase generated by the phase generating means; a first zero cross detecting means for detecting a timing at which a sine value input from the filter means crosses a zero level; and the sine A second zero cross detecting means for detecting a timing at which the sine value calculated by the value calculating means crosses a zero level; a detection timing of the first zero cross detecting means; and a detection timing of the second zero cross detecting means. And a phase difference calculating means for calculating the phase difference based on the time difference measured by the time measuring means.

  According to the present invention, when an unbalanced component or a harmonic component is included in an alternating current signal input at a predetermined sampling period, these components are removed by the complex coefficient filter. Only the fundamental wave of the AC signal is input. Accordingly, the phase synchronization means can accurately and quickly match the phase generated by the phase generation means with the phase of the fundamental wave of the input AC signal by the PLL processing by the phase control means.

When the phase detection device according to the present invention is applied to, for example, a device that detects the phase of a voltage signal of a power system having a system frequency f _s (for example, 60 Hz), In addition to the fundamental wave having the frequency f _s , an unbalanced component (a frequency component of −f _s ) and a harmonic component (mainly harmonic components of −5 × f _s , + 7 × f _s , and −11 × f _s ) are included. For example, an unbalanced component and a harmonic component are removed by a band-pass type complex coefficient filter (Band Pass Filter) having a system frequency f _s as a center frequency, and the phase synchronization means has the same phase as the fundamental wave. Only a phase signal and a quadrature signal whose phase is different from that of the fundamental wave by π / 2 are input. For example, if the fundamental wave component is cos (θ) (θ is the phase of the fundamental wave), the phase synchronization means has an instantaneous value of the in-phase signal represented by cos (θ) and the quadrature signal represented by sin (θ). Is entered.

In the phase synchronization means, the sine value represented by −sin (θ ′) and the cosine value represented by cos (θ ′) with respect to the phase θ ′ generated by the phase generation means at the previous signal input by the phase control means. For example, sin (θ) · cos (θ ′) using these calculated values and the sine value represented by sin (θ) and the cosine value represented by cos (θ) output from the filter means. ) −cos (θ) · sin (θ ′) = sin (θ−θ ′) is performed. If | Δθ | = | θ−θ ′ | is small, since sin (θ−θ ′) ≈θ−θ ′ = Δθ, the phase control means passes the phase difference Δθ of the multiplication result through the loop filter. A control value Δω (corresponding to an angular frequency) is obtained, and after the control value Δω is added to the reference value ω ₀ , an integration process is performed to update the phase θ ′. With this update process, if Δθ ≠ 0, the phase θ ′ is updated so that Δθ decreases, and when Δθ = 0, the phase θ ′ is held.

Therefore, even if an unbalanced component or a harmonic component is included in the voltage signal of the power system in addition to the fundamental wave having the system frequency f _s , these components do not affect the PLL calculation processing of the phase synchronization means. The phase θ of the voltage signal of the power system can be calculated quickly and accurately.

It is a figure which shows the basic composition of the grid connection inverter to which the phase detection apparatus which concerns on this invention is applied. It is a figure for demonstrating the voltage vector output from a grid connection inverter. It is a figure which shows an example of the block configuration of the phase detection apparatus which concerns on this invention. It is a block diagram which shows the arithmetic circuit of a three-phase two-phase conversion part. It is a figure which shows the frequency characteristic of the complex coefficient filter part using a complex coefficient band pass filter. It is a figure which shows the symmetrical three-phase voltage vector which has a positive frequency, and the symmetrical voltage vector which has a negative frequency. It is a block diagram which shows the arithmetic processing of the complex coefficient filter part using a complex coefficient band pass filter. It is a figure which shows the circuit structure which performs the complex arithmetic process of the complex coefficient filter part using a complex coefficient band pass filter. It is a figure which shows the circuit structure which performs the calculation process of a phase difference calculating part. It is a figure which shows the circuit structure of another phase difference calculating part. It is a wave form diagram for demonstrating the calculation process of the phase difference in the phase difference calculating part shown in FIG. The phase detection response characteristic of the phase detection device (the phase output from the phase detection device is the phase difference calculation unit that calculates the phase difference using a multiplication function of a trigonometric function). It is a figure which shows the result of having simulated the fluctuation state of the frequency of the voltage vector which has. It is the figure which expanded the fluctuation state of the frequency of the voltage vector which has the phase output from the phase detection apparatus 0.3 second after the simulation start of the simulation result shown in FIG. It is a figure which shows the frequency characteristic of the complex coefficient filter part using a complex coefficient notch filter. It is a block diagram which shows the arithmetic processing of the complex coefficient filter part using a complex coefficient notch filter. It is a figure which shows the circuit structure which performs the complex arithmetic process of the complex coefficient filter part using a complex coefficient notch filter. It is a figure which shows the multistage structure of the complex coefficient notch filter provided in a complex coefficient filter part. Phase detection response characteristics of the phase detection device (having the phase output from the phase detection device), wherein the complex coefficient filter unit is a complex coefficient notch filter, and the phase difference calculation unit is a method of calculating the phase difference by a multiplication function of a trigonometric function. It is a figure which shows the result of having simulated the fluctuation state of the frequency of a voltage vector. It is the figure which expanded the fluctuation state of the frequency of the voltage vector which has the phase output from the phase detection apparatus 0.3 second after the simulation start of the simulation result shown in FIG. Phase detection response characteristics of the phase detection device in which the complex coefficient filter unit is a complex coefficient notch filter and the phase difference calculation unit directly counts the phase difference (the frequency of the voltage vector having the phase output from the phase detection device) It is a figure which shows the result of having simulated the fluctuation state). It is the figure which expanded the fluctuation state of the frequency of the voltage vector which has the phase output from the phase detection apparatus in 4.9 second after the simulation start of the simulation result shown in FIG. It is a figure which shows the block configuration of the phase detection apparatus applied to a single phase grid connection inverter. It is a vector diagram for demonstrating the principle of the phase detection by PLL method. It is a block diagram of the phase detection apparatus using the conventional multiplication type PLL method. It is a block diagram of the other phase detection apparatus using the conventional multiplication type PLL method.

Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings, taking as an example the case where the phase detection device according to the present invention is applied to a grid-connected inverter. In the following description, for convenience of explanation, the fundamental components of the three-phase voltage signals v _u , v _v , and v _w of the power system are represented by v _u = A _m · cos (θ) (A _m : amplitude, θ: (Phase of system voltage), v _v = A _m · cos (θ−2π / 3), and v _w = A _m · cos (θ−4π / 3).

  First, the grid interconnection inverter will be described with reference to FIG. FIG. 1 is a diagram showing a basic configuration of a grid-connected inverter to which a phase detection device according to the present invention is applied.

  A grid-connected inverter 1 shown in FIG. 1 is a three-phase grid-connected inverter that converts DC power into AC power and supplies it to a commercial power system.

  The grid interconnection inverter 1 includes a DC power source 2 that outputs DC power, an inverter circuit 3 that converts DC power output from the DC power source 2 into AC power, and on / off of switching elements TR1 to TR6 in the inverter circuit 3 An inverter control unit 4 that controls the operation, a filter circuit 5 that removes switching noise included in the AC voltage output from the inverter circuit 3, and a power system 9 that matches the level of the AC voltage output from the filter circuit 5 with the system voltage. A voltage detector 8 for detecting the voltage of the power system 9 and a current detector 7 for detecting the output current output from the transformer 6 to the power system 9.

  The DC power source 2 includes a solar cell 211 that converts solar energy into electric energy. In addition, you may be comprised with other DC power supplies, such as a fuel cell. The inverter circuit 3 is configured by a known voltage control type inverter circuit in which six switching elements TR1 to TR6 are bridge-connected. As the switching element, for example, a semiconductor switching element such as a bipolar transistor, a field effect transistor, a thyristor, or an IGBT (Insulated Gate Bipolar Transistor) is used. FIG. 1 shows an example using a transistor. Feedback transistors D1 to D6 are connected in parallel to the transistors TR1 to TR6.

  The six transistors TR <b> 1 to TR <b> 6 are each controlled to be turned on / off by a PWM signal output from the inverter control unit 4. From the inverter control unit 4, two PWM signals Spwm, / Spwm whose levels are opposite to each other are taken as one set, and three sets of PWM signals (Spwmi, / Spwmi having the same period and different on periods (pulse widths) are used. ) (I indicates the number of the set, i = 1, 2, 3). The first set of PWM signals (Spwm1, / Spwm1) is input to the bases of the transistors TR1 and TR2, and the second set of PWM signals (Spwm2, / Spwm2) is input to the bases of the transistors TR3 and TR4. The third set of PWM signals (Spwm3, / Spwm3) is input to the bases of the transistors TR5 and TR6. The transistors TR1 to TR6 are turned on (conductive state) when the PWM signals Spwmi and / Spwmi are at a high level, and are turned off (off state) when the PWM signals Spwmi and / Spwmi are at a low level.

  The inverter control unit 4 is constituted by a microcomputer, and the microcomputer executes predetermined arithmetic processing according to a preset program, whereby three sets of PWM signals (Spwmi, / Spwmi) (i = 1, 2, 3). ) Is generated. Note that the inverter control unit 4 can be realized by an FPGA (Field Programmable Gate Array).

The filter circuit 5 is equivalently a low-pass filter having a circuit configuration in which inductors L _F are connected in series to the three output lines of the inverter circuit 3 and capacitors C _F are connected in parallel between the three output lines. . From a connection point a~c inverter circuit 3 voltage signal of the three-phase waveform level changes stepwise _{v a ', v b',} v c ' is output. The voltage signals v _a ′, v _b ′, and v _c ′ include switching noise of the transistors TR1 to TR6 due to the PWM signals Spwmi and / Spwmi. By passing through the filter circuit 5, the switching noise is removed, and the sine Voltage signals v _a , v _b , and v _c having _a wavy waveform are output. The three-phase voltage signals (phase voltage signals) v _a , v _b and v _c output from the filter circuit 5 are adjusted to the same level as the system voltage by the transformer 6 and output to the power system 9. Is done.

Inverter control unit 4 is, for example, when the system interconnection inverter 1 of the voltage signal v _a to output the U-phase of the power system 9, as shown in FIG. 2, the same voltage and the voltage vector of the U-phase of the power system 9 Control is performed to generate _a voltage vector V _a by combining the vector V _ar and the voltage vector V _aL .

Voltage vector V _aL, when a current flows I _aL from system interconnection inverter 1 to the power system 9 (when powering), occurs in the load L _a between the system interconnection inverter 1 and the power system 9 This is a voltage vector corresponding to the voltage drop. While the load L _a strictly includes a resistor-because its value is smaller than the reactance, ignoring the resistance component in FIG. 2 describes a load L _a as an inductance circuit. The voltage vector V _ar is a voltage vector for connecting the grid interconnection inverter 1 to the power grid 9. Since the load L _a is the inductance, the voltage vector V _aL phase to operation of the power factor of 1, and advanced by approximately [pi / 2 with respect to the voltage vector V _ar.

The inverter control unit 4 controls the currents I _aL , I _bL , and I _cL supplied to the power system 9 by the maximum power point tracking control, whereby each of the U, V, and W of the power system 9 is controlled from the grid-connected inverter 1. The voltage signals v _a , v _b and v _c (voltage signals corresponding to the voltage vector V _aL ) output to the phases are controlled. The inverter control unit 4 monitors the maximum power point of the solar cell 211 based on the output voltage V _dc of the solar cell 211 input from the voltage detector 212, and also includes a current detector provided in the output line of the transformer 6. The output currents I _aL , I _bL , I _cL of U, V, W input from 7 are monitored, and the output currents I _aL , I _bL , I _{cL of} each phase follow the maximum power point by the current minor loop. Control is performed so that the target value set by the control is obtained.

The inverter control unit 4 also supplies voltage signals v _u , v _v , and v _{w for} the U, V, and W phases of the power system 9 that are input from the voltage detector 8 that is provided between the output lines of the transformer 6. calculating the amplitude a _m and the phase of the fundamental wave component of the voltage signal of the power system 9 theta (corresponding to the amplitude and phase of the voltage vector V _ar) used. In order to calculate this phase θ, the inverter control unit 4 is provided with a phase detection device 10 (see FIG. 3) according to the present invention. Since the phase detection device 10 calculates the phase θ by digital arithmetic processing as will be described later, the inverter control unit 4 is installed as a phase calculation program to be executed by the microcomputer.

The inverter control unit 4 calculates the amplitude A _L of the voltage vector V _aL based on the control value of the current I _aL calculated in the current minor loop, and the amplitude A _L and the amplitude of the fundamental component of the voltage signal of the power system 9. calculating a target value of the voltage signal v _a U-phase to be outputted from the system interconnection inverter 1 by using the a _m and the phase theta. Further, the inverter control unit 4 calculates target values of the V-phase and W-phase voltage signals v _b and v _c by the same method.

Then, the inverter control unit 4, the PWM signal Spwm1 based on the voltage signal v _a, generates / Spwm1, generates a PWM signal Spwm2, / Spwm2 based on the voltage signal v _b, based on the voltage signal v _c PWM Signals Spwm3 and / Spwm3 are generated.

  Next, a phase detection device provided in the inverter control unit 4 will be described. FIG. 3 is a diagram showing a block configuration of the phase detection apparatus according to the present invention.

The phase detection device 10 shown in FIG. 3 removes unbalanced components and harmonic components contained in the signals detected from the three-phase voltage signals (phase voltage signals) v _u , v _v , and v _w of the power system 9, A fundamental wave quadrature component calculation unit 10A that calculates a fundamental wave component (sine wave signal) of a normalized voltage signal and a signal (cosine wave signal) that is orthogonal to the fundamental wave component, and a fundamental wave quadrature component calculation unit 10A that are output. PLL processing for outputting the phase (θ) of the voltage signal of the power system 9 by PLL calculation processing using the sine wave signal (instantaneous value) and cosine wave signal (instantaneous value) and the phase output from the phase detector 10 Part 10B.

The fundamental wave quadrature component calculation unit 10A has two phases (α that are orthogonal to each other) of the three-phase voltage signals v _u , v _v , v _w (instantaneous values input at a predetermined sampling period) input from the voltage detector 8. Phase / β-phase) voltage signals vα, vβ, and three-phase / two-phase converter 11, and unbalanced components included in voltage signals vα, vβ output from the three-phase / two-phase converter 11 and a predetermined order. A complex coefficient filter unit 12 using a complex coefficient filter that removes the higher harmonic components, and a normalization unit 13 that normalizes the voltage signals v _r and v _j output from the complex coefficient filter unit 12. The normalization unit 13 can be omitted by adjusting the gain of the complex coefficient filter unit 12.

The three-phase / two-phase converter 11 performs the operations of the following equations (3) and (4) on the three-phase voltage signals v _u , v _v , v _w inputted from the voltage detector 8. Conversion into orthogonal voltage signals vα and vβ.

  FIG. 4 is a block diagram showing an arithmetic circuit of the three-phase / two-phase converter 11. As shown in the figure, the three-phase to two-phase conversion unit 11 includes five multipliers 11a to 11e and two adders 11f and 11g. The multipliers 11a, 11b, and 11d are calculators that calculate each term of the equation (3), and the multipliers 11c and 11e are calculators that respectively calculate each term of the equation (4). The adder 11f is an arithmetic unit that adds the terms of the equation (3), and the adder 11g is an arithmetic unit that adds the terms of the equation (4).

The three-phase voltage signals v _u , v _v , v _w detected by the voltage detector 8 are generally non-balanced components and odd-order components such as third, fifth, seventh, and eleventh in addition to the fundamental component. It is an unbalanced three-phase signal including harmonic components (see frequency components in FIG. 5). Therefore, the three-phase / two-phase converter 11 outputs a voltage signal obtained by three-phase / two-phase conversion for these components.

The fundamental wave components v _su , v _sv , v _sw of the voltage signals v _u , v _v , v _w are
v _su = A _sm · cos (ω _s · t)
v _sv = A _sm · cos (ω _s · t−2π / 3)
v _sw = A _sm · cos (ω _s · t−4π / 3)
Where A _{sm is} the amplitude of the fundamental wave component, ω _{s is} the angular frequency of the system voltage, and ω _s = 2π · f _s
Then, the voltage vectors V _su , V _{sv, and} V _sw of the fundamental wave component are expressed as V _s = A _sm · exp (j · ω _s · t), a = exp (j · 2π / 3),
V _su = V _s …………………… (3A)
V _sv = exp (-j ・ 2π / 3) ・ V _s
= A ^-1 · V ₊ = a ² · V _s (3B)
V _sw = exp (-j ・ 4π / 3) ・ V _s
= A ^-2 · V = a · V _s (3C)
It is represented by

Also, the unbalanced components v _su ', v _sv ', v _sw 'are
v _su '= A _sm ' ・ cos (ω _s・ t)
v _sv '= A _sm ' · cos (ω _s · t−4π / 3)
v _sw '= A _sm ' ・ cos (ω _s・ t−2π / 3)
Where A _sm ': amplitude of unbalanced component,
The unbalanced component voltage vectors V _su ′, V _sv ′, and V _sw ′ are expressed as V _s ′ = A _sm ′ · exp (j · ω _s · t),
V _su '= V _s ' (4A)
V _sv '= exp (-j ・ 4π / 3) ・ V _s '
= A ^-2 · V _s '= a · V _s ' (4B)
V _sw '= exp (-j ・ 2π / 3) ・ V _s '
= A ^-1 · V _s '= a ² · V _s ' (4C)
It is represented by

As shown in FIG. _6A , the voltage vectors V _su , V _sv , and V _sw of the fundamental wave components are counterclockwise when the voltage vectors V _su , V _sv , and V _sw of the U, V, and W phases are ( These are vectors that are arranged evenly in the order of U, W, and V in the counterclockwise direction and rotate counterclockwise at the angular frequency ω _s = θ / t. On the other hand, since the phase difference between the V phase and the W phase with respect to the U phase is opposite to the phase difference between the V phase and the W phase with respect to the U phase of the fundamental wave component, the phase order of the unbalanced component is fundamental. It is reversed with respect to the phase order of the wave components. Therefore, the voltage vectors V _su ′, V _sv ′, and V _sw ′ of the unbalanced component are obtained as shown in FIG. 6B by using the voltage vectors V _su ′, V _sv ′, V _sw ′ is evenly arranged in the clockwise order in the phase order of U, W, and V, and is a vector that rotates counterclockwise at the angular frequency ω _s = θ / t.

となる。 Substituting the voltage vectors V _su , V _sv , and V _sw of the fundamental wave components expressed by the equations (3A) to (3C) into the equations (3) and (4), the voltage vectors V _s α and V _s β are ,

It becomes.

Since the two-phase voltage signals v _s α and v _s β of the fundamental wave component are given as projection values on the real axis of the voltage vectors V _s α and V _s β, they are output from the three-phase / two-phase converter 11. The two-phase voltage signals v _s α and v _s β of the fundamental wave component
v _s α = √ (3/2) · A _sm · cos (ω _s · t) (7)
v _s β = √ (3/2) · A _sm · sin (ω _s · t) (8)
It becomes.

Similarly, when the equations (4A) to (4C) are substituted into the equations (5) and (6), the voltage vectors V _s α ′ and V _s β ′ are expressed as V _s α ′ = √ (3/2) Since V _s ′, V _s β ′ = j · √ (3/2) · V _s ′, the phase voltage signal v _s α ′, which is an unbalanced component output from the three-phase / two-phase converter 11, v _s β ′ is
v _s α ′ = √ (3/2) · A _sm '· cos (ω _s · t) (9)
v _s β ′ = − √ (3/2) · A _sm ′ · sin (ω _s · t) (10)
It becomes. Also, since cos (ω _s · t) = cos (−ω _s · t) and sin (ω _s · t) = − sin (−ω _s · t), these are expressed by Equation (9) and (10) When assigned to an expression,
v _s α ′ = √ (3/2) · A _sm '· cos (−ω _s · t) (9 ′)
v _s β ′ = √ (3/2) · A _sm '· sin (−ω _s · t) (10 ′)
It becomes.

Comparing the equations (9 ′) and (10 ′) with the equations (7) and (8), the angular frequency of the fundamental component is “ω _s ”, whereas the angular frequency of the unbalanced component is “ −ω _s ”is different. That is, _{assuming that} the frequencies of the two-phase voltage signals v _s α and v _s β of the fundamental wave component output from the three-phase / two-phase converter 11 are “positive frequencies”, the two-phase voltage signal v _{s of the} unbalanced component. It can be said that α ′ and v _s β ′ are output from the three-phase / two-phase converter 11 at a “negative frequency”.

5, displays a fundamental component in the position of the frequency "f _s" of the positive frequency domain, the frequency "-f _s negative frequency domain unbalanced component frequencies of the unbalanced components as" -f _s """ Indicates the relationship of the above frequencies. FIG. 5 shows only the fifth, seventh, and eleventh harmonic components that affect frequency detection. This is because the harmonic component of an integer multiple of 3 does not appear in the line voltage, and even the phase voltage is removed by the Δ-connected transformer, and the odd-order harmonic component larger than the 11th order has a low level and can be ignored. .

The reason why the unbalanced component has a negative frequency is that the phase order of the unbalanced component is reversed with respect to the phase order of the fundamental wave component, and therefore the frequency f _s of the fundamental wave component is multiplied by n (n: 2 or more). The same applies to the nth-order harmonic component, and when the phase order of the nth-order harmonic component is the same as the fundamental wave component, the frequency f _ns (subscript n is the order) is a positive frequency, When the phase order of the n-th harmonic component is opposite to the fundamental component, the frequency f _ns is a negative frequency.

For the fifth, seventh, and eleventh harmonic components, the voltage vector of each phase of U, V, and W is expressed as V _nu , V _nv , V _nw (the subscript n is the order), and the voltage vector V _n Is V _n = A _nm · exp (j · n · ω _s · t) (A _nm : amplitude of the nth-order harmonic component),
V _nu = V _n
V _nv = V _n · exp (-j · 2nπ / 3)
V _nw = V _n · exp (-j · 4nπ / 3)
However, n = 5, 7, 11
It is represented by exp (−j · 2nπ / 3) = {exp (−j · 2π / 3)} ⁿ = a ²ⁿ , exp (−j · 4nπ / 3) = {exp (−j · 4π / 3)} ⁿ = a ^{Since n} , the voltage vectors V _nu , V _nv , V _nw are
V _nu = V _n
V _nv = a ²ⁿ・ V _n
V _nw = a ⁿ・ V _n
It is expressed as

The fifth harmonic component of the voltage vector V _5u, V _5v, V _5w and 11th harmonic components of the voltage vector V _11u, V _11v, V _11w is
(V _5u , V _5v , V _5w ) = (V ₅ , a ¹⁰ · V ₅ , a ⁵ · V ₅ )
_{= (V 5, a · V} 5, a 2 · V 5)
_{(V 11u, V 11v, V} 11w) = (V 11, a 22 · V 11, a 11 · V 11)
_{= (V 11, a · V} 11, a 2 · V 11)
Thus, since the phase order of U, V, and W is opposite to the fundamental component, the frequencies of the fifth harmonic component and the eleventh harmonic component are negative frequencies.

On the other hand, the seventh harmonic component of the voltage vector V _7u, V _7v, V _7w is
_{(V 7u, V 7v, V} 7w) = (V 7, a 14 · V 7, a 7 · V 7)
^{_{= (V 7, a 2 ·}} V 7, a · V 7)
Thus, the phase order of U, V, and W is in phase with the fundamental component, so the frequency of the seventh harmonic component is a positive frequency.

Therefore, in FIG. 5, the fifth harmonic component and the eleventh harmonic component are displayed at the positions of the frequencies “−5f _s ” and “−11 f _s ” in the negative frequency region, respectively, and the seventh harmonic component is positive. Is displayed at the position of the frequency “7f _s ” in the frequency region.

In addition, the voltage signal (v ₅ α, v ₅ β) obtained by converting the fifth harmonic component into three-phase two-phase conversion is the voltage signal (v _s α ′, v _s β ′) obtained by converting the unbalanced component into three-phase two-phase conversion. The voltage signal (v ₁₁ α, v ₁₁ β) obtained by three-phase to two-phase conversion of the 11th harmonic component is the frequency of the voltage signal (v _s α ′, v _s β ′). The voltage signal (v ₇ α, v ₇ β) obtained by three-phase two-phase conversion of the _seventh harmonic component is a voltage signal (v _s α, v obtained by three-phase two-phase conversion of the fundamental wave component. _Since the frequency of _s β) is 7 times,
v ₅ α = √ (3/2) · A _5m · cos (−5ω _s · t) (11)
v ₅ β = √ (3/2) · A _5m · sin (−5ω _s · t) (12)
v ₇ α = √ (3/2) · A _7m · cos (7ω _s · t) (13)
v ₇ β = √ (3/2) · A _7m · sin (7ω _s · t) (14)
v ₁₁ α = √ (3/2) · A _11m · cos (−11ω _s · t) (15)
v ₁₁ β = √ (3/2) · A _11m · sin (−11ω _s · t) (16)
It is represented by

Therefore, from the three-phase / two-phase conversion unit 11 to the complex coefficient filter unit 12, the fundamental wave component, the unbalanced component, and the fifth, seventh, and eleventh harmonics expressed by the equations (7) to (16). Two-phase voltage signals (v _s α, v _s β), (v _s α ′, v _s β ′), (v _n α, v _n β) (n = 5, 7, 11) Voltage signals (vα, vβ) are output.

The complex coefficient filter unit 12 includes a complex coefficient bandpass filter (BPF) including a first-order IIR filter whose transfer function H (z) expressed by z-transform expression is expressed by the following equation (17). In the equation (17), f _d [Hz] in the complex coefficient a ₁ is a normalized frequency obtained by normalizing the center frequency f ₀ of the pass band by the sampling rate, and Ω _d [rad / s] is a normalized angular frequency. . For example, if the center frequency f ₀ is set to the system frequency f _s and the sampling frequency is “f _sr ”, f _d is f _s / f _sr , and Ω _d is 2π · f _d = 2π · (f _s / f _sr ). The normalized angular frequency Ω _d is −π <Ω _d <π. R is a parameter (0 <r <1) that determines the bandwidth of the passband.

FIG. 7 is a block diagram showing a processing circuit for performing the arithmetic processing of the equation (17). As shown in the figure, the complex coefficient filter unit 12 is configured by a circuit that multiplies the output of the feedback circuit by a numerator coefficient b _0, with the denominator calculation process of equation (17) being configured by a feedback circuit.

In the block diagram shown in FIG. 7, u [k] (k: index number representing discrete time) is input data, x [k] is state data of the complex coefficient filter unit 12, and y [k] is the complex coefficient filter unit 12. Output data. Between input data u [k], state data x [k] and output data y [k]
x [k] = r · exp (j · Ω _d ) · x [k−1] + u [k] (18)
y [k] = (1-r) .x [k] (19)
Is established.

Since the complex coefficient filter unit 12 is configured by a complex coefficient filter, the state data x [k] regardless of whether the input data u [k] is complex data or real data (data in which the imaginary part of the complex data is “0”). ] And output data y [k] are complex signal data. Accordingly, the input data u [k], state data x [k] and the output data y [k], respectively _{u [k] = u r [} k] + ju j [k], x [k] = x r [k] + J · x _j [k], y [k] = y _r [k] + j · y _j [k], the complex coefficient a ₁ is expressed as a ₁ = r · exp (j · Ω _d ) = r · cos (Ω _d ) + J · {r · sin (Ω _d )} is substituted into the equations (18) and (19), and divided into the relational expressions of the real part and the imaginary part.
_{x r [k] = r ·} cos (Ω d) · x r [k-1] -r · sin (Ω d) · x j [k-1] + u r [k] ... (20)
_{x j [k] = r ·} cos (Ω d) · x j [k-1] + r · sin (Ω d) · x r [k-1] + u j [k] ... (21)
y _r [k] = (1−r) · x _r [k] (22)
y _j [k] = (1−r) · x _j [k] (23)
It becomes.

When the bandpass filter is configured by a real coefficient second-order IIR filter, the transfer function H (z) (z = exp (j · ω) of the second-order IIR-filter is
H (z) = (1-r ² +2 (r-1) · r · cos (Ω _d ) · z ^-1 ) / (1-2r · cos (Ω _d ) · z ^-1 + r ² · z ^-2 )
It is represented by When the amplitude characteristic M (ω) of the transfer function H (z) is obtained, a pole appears at ω satisfying (1-2r · cos (Ω _d ± ω) + r ² ) = 0, and the second-order IIR filter It has the characteristic of passing the pole frequency. If r≈1, then cos (Ω _d ± ω) ≈1, the normalized frequency f _d that passes through the second-order IIR filter is f _d = ± Ω _d / 2π, and the normalized angular frequency Ω _d is the fundamental wave component The real coefficient second-order IIR filter set at an angular frequency of 1 also passes an unbalanced component.

When the amplitude characteristic M (ω) of the transfer function H (z) shown in the equation (17) is obtained for a real coefficient second-order IIR filter, M (ω) = (1−r) / √ {1-2r · cos (Ω _d −ω) + r ² }, and the pole appears only in ω that satisfies (1-2r · cos (Ω _d −ω) + r ² ) = 0, and therefore the normalized angular frequency Ω _d is the angle of the fundamental component. In the first-order IIR filter having a complex coefficient set to the frequency, only the fundamental wave component is allowed to pass, and the unbalanced component and the harmonic component are not allowed to pass. Accordingly, since the complex coefficient filter unit 12 has the frequency characteristics shown in FIG. 5, the complex coefficient filter unit 12 includes the voltage signals vα and vβ by setting the center frequency f ₀ to the system frequency f _s. The unbalanced component and the harmonic component (the components shown in the equations (9) to (16)) can be suitably removed.

FIG. 8 is a diagram showing a circuit configuration for performing complex operation processing of the complex coefficient filter unit 12 based on the equations (20) to (23). In the figure, coefficient a _r and coefficient a _j are the real part and imaginary part of complex coefficient a ₁ = r · e ^j Ω ^d , respectively, and a _r = r · cos (Ω _d ), a _j = r · sin (Ω _d ).

As shown in the figure, the complex coefficient filter unit 12 includes six multipliers 12a to 12f, two adders 12g and 12h, and two delay circuits 12i and 12j. The delay circuit 12i is a circuit that generates a real part x _r [k-1] of state data, and the delay circuit 12j is a circuit that generates an imaginary part x _j [k-1] of state data. The multipliers 12a and 12b are arithmetic units for calculating the first term and the second term (including a negative sign) of the equation (20), respectively, and the adder 12g is the first term and the second term of the equation (20). And an arithmetic unit for adding the third term. Therefore, the real part x _r [k] of the state data indicated by the equation (20) is output from the adder 12g.

On the other hand, the multipliers 12d and 12c are arithmetic units for calculating the first term and the second term of the equation (21), respectively, and the adder 12h is the first term, the second term, and the third term of the equation (21). An arithmetic unit to add. Therefore, the imaginary part x _j [k] of the state data indicated by the equation (21) is output from the adder 12h. The multipliers 12e and 12f are arithmetic units for calculating the expressions (22) and (23), respectively.

In the present embodiment, a three-phase to two-phase converter 11 is provided to convert the three-phase voltage signals v _u , v _v , and v _w into voltage signals vα and vβ that are orthogonal to each other. , The real part and the imaginary part of the complex data u _r + ju _j can be respectively corresponded, so that the sampling data of the voltage signal vα is input to the adder 12g as the real part u _r [k] of the input data, and the voltage signal vβ Are input to the adder 12h as the imaginary part u _j [k] of the input data.

Every time sampling data of the voltage signal vα is input to the complex coefficient filter unit 12, the arithmetic processing of the expressions (20) and (22) is repeated in the delay circuit 12i, the multipliers 12a, 12b, and 12e and the adder 12g. As a result, the multiplier 12e outputs only the output data y _r [k] of the three-phase to two-phase conversion signal v _s α of the fundamental wave component expressed by the equation (7). Further, every time sampling data of the voltage signal vβ is input to the complex coefficient filter unit 12, the delay circuit 12j, the multipliers 12c, 12d, 12f, and the adder 12h perform the arithmetic processing of the expressions (21) and (23). As a result, output data y _j [k] of only the three-phase two-phase conversion signal v _s β of the fundamental wave component shown by the equation (8) is output from the multiplier 12f.

In FIG. 3, in order to distinguish the voltage signal output from the first complex coefficient filter unit 12 by the output data y _r [k], y _j [k] from the input voltage signals vα, vβ, “v _r ”and“ v _j ”.

The voltage signals v _r and v _j output from the complex coefficient filter unit 12 and expressed by the equations (7) and (8) are based on the rotation axis of the U-phase voltage vector V _u of the power system 9 as the real axis R. The phase angle ψ of the U-phase voltage signal v _u is set to “0”, but when the phase of the U-phase voltage signal v _u of the power system 9 is shifted and the phase angle ψ ≠ 0, The voltage signals v _r and v _j output from the complex coefficient filter unit 12 are v _r = A _sm · cos (ω _s · t + ψ) and v _j = A _sm · sin (ω _s · t + ψ).

The normalizing unit 13 performs arithmetic processing for normalizing the levels of the voltage signals v _r and v _j output from the complex coefficient filter unit 12 to “1”. The voltage signals v _r and v _j output from the complex coefficient filter unit 12 are a sine wave signal and a cosine wave signal having the same amplitude, and the amplitude is obtained by calculating √ (v _r ² + v _j ² ). In the normalization unit 13, y _r [k] / √ (y _r [k] ² + y _j [k] ² ) and y _j [k] are output data y _r [k] and y _j [k], respectively. Normalization processing of the voltage signals v _r and v _j is performed by performing calculation processing of / √ (y _r [k] ² + y _j [k] ² ). Therefore, the normalization unit 13 outputs signal data represented by v _r ′ = cos (θ) and v _j ′ = sin (θ) (θ = ω · t).

The PLL processing unit 10B includes the normalized voltage signals v _r and v _j output from the fundamental wave quadrature component calculation unit 10A and the phase θ ′ (hereinafter referred to as “output phase θ ′” output from the PLL processing unit 10B. Is used to calculate the phase difference Δθ (= θ−θ ′) between the phase θ of the voltage signals v _r and v _j (hereinafter referred to as “input phase θ”) and the output phase θ ′. The calculation unit 14 includes a phase update unit 15 that updates the output phase θ ′ based on the phase difference Δθ.

The phase difference calculation unit 14 performs a calculation represented by a multiplication function of a trigonometric function of sin (θ) · cos (θ ′) − cos (θ) · sin (θ ′). As shown in FIG. 9, the phase difference calculation unit 14 includes a sine value calculator 14 a that calculates a sine value −sin (θ ′) for the output phase θ ′, and a cosine value cos (θ) for the output phase θ ′. '), A cosine value calculator 14b, a sine value -sin (θ'), and a normalized voltage signal v _r (cosine value cos (θ)) output from the fundamental wave orthogonal component calculation unit 10A. A multiplier 14c for multiplying, a multiplier 14d for multiplying the cosine value cos (θ ′) and the normalized voltage signal v _j (sine value sin (θ)) output from the fundamental wave orthogonal component calculation unit 10A, The adder 14e adds the multiplication result of the multiplier 14c and the multiplication result of the multiplier 14d.

より、ｖ_q＝−cos(θ)・sin(θ’)＋sin(θ)・cos(θ’)＝sin(θ−θ’)であるから、位相差演算部１４における演算処理は、基本波直交成分算出部１０Ａから出力される正規化された互いに直交する相電圧信号ｖ_r，ｖ_jに対してｄｑ変換処理を行い、ｑ軸上の電圧信号ｖ_qを算出する処理と言うこともできる。 If sin (θ) · cos (θ ′) − cos (θ) · sin (θ ′) = sin (θ−θ ′) and | θ−θ ′ | = | Δθ | Since −θ ′) ≈Δθ, the phase difference calculation unit 14 substantially calculates the phase difference Δθ. Note that performs dq conversion processing on voltage signals orthogonal to each other are normalized v _r, v _j, when calculating the voltage signal v _q on the voltage signal v _d and q axis on the d-axis, the dq conversion Processing is

Thus, since v _q = −cos (θ) · sin (θ ′) + sin (θ) · cos (θ ′) = sin (θ−θ ′), the calculation processing in the phase difference calculation unit 14 is performed by the fundamental wave. It can also be said to be a process of calculating a voltage signal v _q on the q axis by performing dq conversion processing on the normalized phase voltage signals v _r and v _j output from the orthogonal component calculation unit 10A. .

The phase update unit 15 passes the phase difference Δθ output from the phase difference calculation unit 14 through the loop filter 15a, and then adds the output (a differential value of the phase difference Δθ corresponding to the angular frequency Δω) to the output by the adder 15b. A predetermined reference value ω ₀ (in this embodiment, the angular frequency ω _s = 2πf _s of the system frequency f _s ) is added, and the added value ω ′ = ω ₀ + Δω is integrated by the integrator 15c to obtain the phase. θ ′ is calculated.

For example, if the phase θ = 2πf _s · t of the power system 9 is stable, the output phase θ ′ output from the phase update unit 15 converges to the input phase θ and is output from the phase difference calculation unit 14. Since the phase difference Δθ is “0”, the output phase θ ′ output from the phase update unit 15 is held at θ ′ = θ = 2πf _s · t. In this state, if the phase θ of the electric power system 9 increases momentarily by ψ, the phase difference calculation unit 14 outputs the phase difference Δθ of (θ + ψ) −θ ′ = ψ, so that the phase update unit 15 'Increases by Δω based on the phase difference Δθ, the rotation speed of the voltage vector V ′ (see voltage vector V ′ shown in FIG. 23) in the phase update unit 15 increases, and the voltage vector V (see FIG. 23) of the power system 9 increases. It changes so as to follow the fluctuation of the phase θ of the voltage vector V shown in FIG. Therefore, the phase difference Δθ is reduced by repeating the update process of the output phase θ ′ in the PLL processing unit 103, and when Δθ = 0, that is, when the output phase θ ′ becomes θ ′ = θ = 2πf _s · t + ψ. The output phase θ ′ output from the phase update unit 15 is held at that value.

FIG. 10 is a block diagram showing a phase difference calculation unit 14 ′ of another method for obtaining the phase difference Δθ. FIG. 9 shows a method for calculating the sine value sin (Δθ) of the phase difference Δθ by using a multiplication function of a trigonometric function. However, the method shown in FIG. 10 uses the output phase θ ′ as shown in FIG. A sine wave signal sin (θ ′) is generated, and the phase difference between the sine wave signal sin (θ ′) and the normalized voltage signal v _j ′ = sin (θ) output from the fundamental wave orthogonal component calculation unit 10A In this method, Δθ is directly counted. Specifically, the timing t1 at which the voltage signal v _j ′ = sin (θ) crosses the zero level from the negative side to the positive side is detected, and the sine wave signal sin (θ ′) is zero from the negative side to the positive side. This is a method of detecting a timing t1 ′ at which the level is crossed, obtaining a time ΔT between t1 and t1 ′, and obtaining a phase difference Δθ from the time ΔT. If the period of sin (θ) is T, ΔT / T = Δθ / 2π, and therefore the phase difference Δθ can be obtained by calculating Δθ = 2π · ΔT / T.

  The phase difference calculation unit 14 ′ illustrated in FIG. 10 includes a comparator 14f that compares the level of the normalized voltage signal sin (θ) output from the fundamental wave quadrature component calculation unit 10A with a zero level, and a comparator 14f. A first zero cross detector 14g that detects the timing at which the level of the voltage signal sin (θ) crosses the zero level using the output signal, and a sine that calculates a sine value sin (θ ′) with respect to the output phase θ ′. The value calculator 14h, the comparator 14i that compares the level of the sine value sin (θ ′) output from the sine value calculator 14h with the zero level, and the sine value sin (θ ′) using the output signal of the comparator 14i ) Of the second zero cross detector 14j for detecting the timing at which the level of zero) crosses the zero level, a clock generator 14k for generating a clock CLK higher in frequency than the frequency of the voltage signal sin (θ), and a first zero cross detector. 14g and second A counter 141 that counts the number of pulses of the clock CLK using the detection signal output from the zero-cross detector 14j, and a phase difference calculator 14m that calculates the phase difference Δθ from the count number N counted by the counter 14l. Yes.

For example, the comparators 14f and 14i output a low level when the levels of the voltage signals sin (θ) and sin (θ ′) are lower than the zero level, and output a high level when the level is equal to or higher than the zero level. Therefore, as shown in FIG. 11, from the comparator 14f, the level of the voltage signal sin (θ) becomes high level at a timing t1 when the level crosses from the negative level to the positive level, and at timing t2 when the level crosses from the positive level to the negative level. The zero cross detection signal S _z1 that becomes low level is output, and the comparator 14i becomes high level at the timing t1 ′ when the level of the voltage signal sin (θ ′) crosses from negative level to positive level, and from positive level to negative level. The zero-cross detection signal S _{z2 that} goes to the low level at the timing t2 ′ that crosses the signal is output.

When the sine wave signal sin (θ ′) is delayed from the voltage signal v _j ′ = sin (θ) output from the fundamental wave quadrature component calculation unit 10A, the counter 14l detects the zero cross as shown in FIG. The count value is reset to zero by the rising signal of the signal S _z1 and the counting of the clock CLK pulse is started, and the counting of the clock CLK pulse is stopped by the rising signal of the zero cross detection signal S _z2 and the count number N is changed. It outputs to the phase difference calculator 14m. On the other hand, when the sine wave signal sin (θ ′) is ahead of the voltage signal v _j ′ = sin (θ), the count value is reset to zero by the rising signal of the zero cross detection signal S _z2 and the pulse of the clock CLK is Counting is started, the pulse count of the clock CLK is stopped by the rising signal of the zero cross detection signal _Sz1 , and the count number N is output to the phase difference calculator 14m. That is, the counter 14l calculates the count number N indicating the period of | t1-t1 ′ |.

The phase difference calculator 14m multiplies the count number N and the coefficient K = 2π / N _T (N _T : the pulse count number of the clock CLK in the period T) to calculate the phase difference Δθ. When the period of the clock CLK is τ, the period T = N _T · τ and ΔT = N · τ. Since Δθ = 2π · ΔT / T as described above, Δθ = 2π · N · τ / N _T · τ = 2π · (N / N _T ).

  FIG. 12 shows the phase detection apparatus 10 (complex coefficient filter unit 12 is a complex coefficient bandpass filter, and the phase difference calculation unit 14 calculates a phase difference using a trigonometric multiplication equation sin (θ−θ ′). This is a result of simulating the response characteristic of the frequency f ′ of the voltage vector V ′ having the output phase θ ′ output from the system). FIG. 13 is an enlarged view of the fluctuation state of the frequency f ′ of the voltage vector V ′ 0.3 seconds after the start of the simulation. Note that the phase difference calculation unit 14 of the phase detection device 10 has the configuration shown in FIG. 12 and 13, the vertical axis represents the frequency f ′ = ω ′ / (2π) [Hz] of the voltage vector V ′.

FIG. 12 shows that the simulation is started in a state where the phase θ (frequency f = system frequency f _s = 60 Hz, phase angle ψ = 0) of the voltage signal of the power system is stable, and the power is 0.2 seconds after the simulation starts. The response characteristic of the phase detector 10 when the phase θ of the system 9 is instantaneously advanced by 90 degrees (when θ = 2πf _s · t + π / 2) is shown. The content condition of the unbalanced component included in the detection voltage signals v _u , v _v , v _w of the voltage detector 8 is 5%, and the content condition of the fifth, seventh and eleventh harmonic components is 5% respectively. Yes. The center frequency f _{0 of the} passband of the complex coefficient filter unit 12 is set to the system frequency f _s = 60 Hz.

As shown in FIG. 12, when the phase θ of the power system is instantaneously changed from “2πf _s · t” to “2πf _s · t + π / 2” 0.2 seconds after the simulation starts, the phase detection device 10 Since the phase difference Δθ output from the phase difference calculator 14 suddenly changes from “0” to “π / 2”, the output phase θ ′ is increased based on the sudden change of the phase difference Δθ. At the time of sudden phase change (time 0.2 seconds), since the phase difference Δθ is large, the phase detection device 10 causes the frequency f ′ of the voltage vector V ′ in the PLL processing unit 103 to rapidly increase so that the voltage vector V ′ is The PLL operation is performed so as to match the voltage vector V of the power system 9, but thereafter, the increased frequency f ′ is decreased and the PLL operation is performed so that the voltage vector V ′ matches the voltage vector V of the power system 9.

The frequency f ′ of the voltage vector V ′ in the PLL processing unit 103 changes in a pulse shape with a peak at about 75 Hz between the time of sudden phase change (time 0.2 seconds) and the elapse of 0.05 seconds. , Showing the situation. Further, when 0.1 second has elapsed (time 0.3 seconds) from the time of sudden phase change (time 0.2 seconds), as shown in FIG. 13, the PLL operation in the phase detection device 10 is performed at the frequency f ′. Since the ripple is about ± 0.012 Hz (the fluctuation range is about 0.04% with respect to the system frequency f _s = 60 Hz), the output phase θ ′ of the phase detector 10 is at the time of sudden phase change (time 0.2 seconds). It can be said that the phase θ after the change of the electric power system is settled within 0.1 seconds from 1 sec.

  From the simulation results of FIGS. 12 and 13, according to the phase detection device 10 according to the present invention, even when the phase θ of the power system 9 fluctuates sharply, the power system 9 sufficiently follows the fluctuation and has high response accuracy. This produces an effect of detecting the phase θ.

In the above embodiment, the complex coefficient filter unit 12 is configured by a bandpass filter. However, if an unbalanced component and a harmonic component to be suppressed are known, a complex coefficient notch filter (BEF) for suppressing those components is used. It may be configured. For example, suppression want frequency unbalanced component (-f _s) and fifth, seventh, eleventh order harmonic component _{(-5f s, + 7f s,} -11f s) For, z transform representation for each their frequency It is preferable to provide a notch filter having a frequency characteristic shown in FIG. 14 by providing a complex coefficient notch filter whose transfer function H (z) is expressed by the following equation (24) and connecting them in multiple stages.

Note that Ω _d is Ω _d = 2π · (f / f _sr ), and when set to f = −f _s , a complex coefficient notch filter for the unbalanced component (−f _s ) is obtained. When f = −5f _s , f = + 7 f _s , and f = −11 f _s are set, a complex coefficient notch filter is obtained for the fifth, seventh, and eleventh harmonic components, respectively. Accordingly, as shown in FIG. _{17, -f s, -5f s,} + 7f s, by cascading complex coefficient notch filter 121, 122, 123, and 124 to prevent the frequency of -11F _s, 14 A notch filter having frequency characteristics is configured.

The block diagram of the processing circuit that performs the arithmetic processing of the above equation (24) has the configuration shown in FIG. 15, and the circuit that performs the complex arithmetic processing of the complex coefficient filter unit 12 using the complex coefficient notch filter (BEF) The configuration is as shown in FIG. FIG. 15 is obtained by adding a circuit that subtracts output data y [k] from input data u [k] and outputs the subtraction value as deviation output data e [k] to the block diagram shown in FIG. It is. 16 adds an adder 12k after the real part multiplier 12e to the block diagram shown in FIG. 8, and the adder 12k outputs the output data from the real part u _r [k] of the input data. The real part y _r [k] of y [k] is subtracted to output the real part _er [k] of the deviation output data, and an adder 12l is added after the multiplier 12f of the imaginary part. 12l subtracts the imaginary part y _j [k] of the output data y [k] from the imaginary part u _j [k] of the input data to output the imaginary part e _j [k] of the deviation output data. is there.

  The circuit shown in FIG. 16 differs from the circuit shown in FIG. 8 only in the addition of the subtraction process in the adders 12k and 12l described above. Is omitted.

  FIG. 18 illustrates a phase in which the complex coefficient filter unit is a complex coefficient notch filter having the frequency characteristics shown in FIG. 14, and the phase difference calculation unit is a method of calculating a phase difference using a trigonometric multiplication equation sin (θ−θ ′). It is the result of simulating the response characteristic of the phase detection of the detection apparatus 10 (the fluctuation state of the frequency of the voltage vector V ′ having the phase θ ′ output from the phase detection apparatus). FIG. 19 is an enlarged view of the fluctuation state of the frequency f ′ of the voltage vector V ′ output from the phase detection device 10 0.3 seconds after the simulation is started. The simulation conditions and the graph display mode are the same as those in FIGS.

  When the complex coefficient notch filter is used, as shown in FIG. 18, the frequency f ′ of the voltage vector V ′ in the PLL processing unit 103 rapidly increases immediately after the sudden phase change (time 0.2 seconds), and approximately 110 Hz. After changing to a peak in the form of a pulse, the output phase θ ′ of the phase detection device 10 is set to the phase θ after the change of the power system after about 0.02 seconds have elapsed from the time of sudden phase change (time 0.22 seconds). I was able to confirm. Further, as shown in FIG. 19, it was also confirmed that the ripple of the frequency f ′ after the lapse of 0.1 seconds (time 0.3 seconds) from the sudden phase change was almost zero. Therefore, it was confirmed that when the complex coefficient notch filter is used, both the response speed and the detection accuracy are higher than those when the complex coefficient band pass filter is used.

  In FIG. 20, the complex coefficient filter unit is a complex coefficient notch pass filter, and the phase difference calculation unit directly counts the phase difference Δθ between sin (θ) and sin (θ ′) (the phase difference calculation unit 14 shown in FIG. 10). This is a result of simulating the phase detection response characteristic of the phase detection device 10 (using “)” (the fluctuation state of the frequency of the voltage vector V ′ having the phase θ ′ output from the phase detection device). FIG. 21 is an enlarged view of the fluctuation state of the frequency f ′ of the voltage vector V ′ output from the phase detection device 10 4.9 seconds after the start of the simulation. The simulation conditions and the graph display mode are the same as those in FIGS.

  When the phase difference calculation unit 14 ′ shown in FIG. 10 is used, as shown in FIG. 20, the frequency f ′ of the voltage vector V ′ in the PLL processing unit 103 is immediately after the sudden phase change (time 0.2 seconds). The frequency rises to about 60.48 Hz, but then gradually decreases, and after about 2.8 seconds have elapsed since the sudden phase change (time 3.0 seconds), the output phase θ ′ of the phase detector 10 has changed after the power system has changed. Set to the phase θ. Further, as shown in FIG. 21, the ripple of the frequency f ′ becomes almost zero after 4.7 seconds have elapsed from the time of sudden phase change (time 4.9 seconds).

  When the phase difference calculation unit 14 ′ shown in FIG. 10 is used, it takes more time for the output phase θ ′ to settle from the sudden phase change to the phase θ after the change than when the phase difference calculation unit 14 shown in FIG. 9 is used. This is considered to be because the phase difference Δθ is calculated by comparing the instantaneous value of sin (θ) with the instantaneous value of sin (θ ′). The decrease in rapid response due to the use of the phase difference calculator 14 'can be improved by adjusting the value of the loop filter. Moreover, the ripple at the time of settling is almost zero is considered to be due to the use of a complex coefficient notch filter.

  As described above, when the phase detection device 10 according to the present embodiment is used, an unbalanced component and a harmonic component of a predetermined order are removed using a complex coefficient filter in the previous stage of the PLL processing unit 10B that detects the phase using the PLL method. Therefore, phase detection that is not affected by unbalanced components and harmonic components can be performed at high speed. Further, if a complex coefficient bandpass filter that removes noise mixed in by the voltage detector 8 or the like is combined, noise that adversely affects phase detection other than unbalanced components and harmonic components can also be removed. There is no need to newly provide a filter for this purpose. Further, since a complex coefficient bandpass filter or a complex coefficient notch filter is used, there is an advantage that no phase difference occurs between the input and output of the complex coefficient filter unit 12.

  Note that a complex coefficient bandpass filter or a complex coefficient notch filter may be used as the filter of the complex coefficient filter unit 12, but it is preferable to use a complex coefficient notch filter rather than a complex coefficient bandpass filter. Detection characteristics can be obtained. In addition, when a complex coefficient notch filter and a complex coefficient bandpass filter are combined, a synergistic effect of the characteristics of both can be expected, and a faster and more accurate phase detection characteristic can be obtained.

  As is well known, if the complex coefficient notch filter and the complex coefficient band pass filter have a multi-stage configuration, a steep filter characteristic can be obtained, and unbalanced and harmonic component removal characteristics and responsiveness can be easily obtained. Therefore, when mounting, a multi-stage configuration with an appropriate number of stages is preferable. For example, when the power system 9 that connects the grid-connected inverter 1 is a system that includes many second-order harmonic components, a complex coefficient notch filter that removes second-order harmonics and a complex coefficient bandpass filter can be combined. If the system does not contain much unbalanced components and harmonic components, a filter configuration with a fast response speed may be used.

In the above embodiment, the three-phase grid-connected inverter 1 has been described. However, the phase detection device according to the present invention can also be applied to a single-phase grid-connected inverter. FIG. 22 is a block diagram of a phase detection device 10 ′ applied to a single-phase grid-connected inverter, but the three-phase / two-phase conversion unit 11 is not provided for the phase detection device 10 of FIG. Only the point is different. In the case of a single phase, since there is only one voltage signal v, the sampling data of the voltage signal v is input to the complex coefficient filter unit 12 as the real part u _r [k] of the input data, and the imaginary part u of the input data “0” is input to _j [k]. 3, the three-phase / two-phase converter 11 is removed, and the sampling data of the voltage signal v of any one of U, V, and W is used as the real part u _r [k of the input data. ] May be input to the complex coefficient filter unit 12 and “0” may be input to the imaginary part u _j [k] of the input data.

In the complex coefficient filter unit 12 using a complex coefficient filter, even when a single-phase voltage signal is input, voltage signals v _r and v _j (sine wave and cosine wave signals) that are orthogonal to each other as in the three-phase case. Therefore, the complex coefficient filter unit 12, the normalization unit 13, and the PLL processing unit 10B can be realized with the same configuration as the three-phase phase detection device 10 shown in FIG. In addition, in the case of a single phase, it is generally difficult to take measures against unbalanced components, but by applying the present invention, unbalanced components and harmonic components can be easily removed even in the case of a single phase. There is an advantage that measures can be taken effectively.

  Therefore, the present invention can be widely applied to various system-connected inverter phase detectors with a simple configuration.

DESCRIPTION OF SYMBOLS 1 System interconnection inverter 2 DC power supply 3 Inverter circuit 4 Inverter control part 5 Filter circuit 6 Transformer 7 Current detector 8 Voltage detector 9 Electric power system 10, 10 'Phase detection apparatus 10A Fundamental wave orthogonal component calculation part 10B PLL processing part (Phase synchronization means)
11 Three-phase / two-phase converter (three-phase two-phase converter)
12, 12 'complex coefficient filter unit (complex coefficient filter means)
121, 122, 123, 124 Complex coefficient notch filter 13 Normalization unit 14 Phase difference calculation unit (element of phase control means)
14a Sine value calculator (first sine value calculator)
14b Cosine value calculator (cosine value calculation means)
14c, 14d Multiplier (element of second sine value calculation means)
14e Adder (element of second sine value calculation means)
14f Comparator (element of first zero cross detection means)
14g Zero cross detector (element of first zero cross detection means)
14h Sine value calculator (Sine value calculator)
14i comparator (element of second zero cross detection means)
14j Zero cross detector (element of second zero cross detection means)
14k clock generator (element of time measuring means)
14 l counter (element of time measuring means)
14m phase difference calculator (phase difference calculator)
15 Phase update unit 15a Loop filter (element of phase control means)
15b Adder (element of phase generation means)
15c integrator (element of phase generation means)

Claims (9)

Each time an AC signal is input at a predetermined sampling period, a phase difference between the phase generated by the phase generator and the phase of the input AC signal is calculated. If the phase difference is not zero, the phase generated by the phase generation unit is changed based on the phase difference in a direction in which the phase difference decreases, and if the phase difference is zero, the phase generated by the phase generation unit In the phase detection device comprising the phase synchronization means having the phase control means for performing control to hold
A phase detection apparatus comprising filter means comprising a complex coefficient filter for removing unbalanced components and harmonic components contained in the AC signal, in front of the phase synchronization means.   The phase detection device according to claim 1, wherein the complex coefficient filter is a bandpass filter having the fundamental wave as a center frequency of a pass band.   The phase detection apparatus according to claim 1, wherein the complex coefficient filter is a notch filter that blocks the unbalanced component and a harmonic component of a predetermined order.   2. The multi-stage filter according to claim 1, wherein the complex coefficient filter is a multi-stage filter that combines a band-pass filter having the fundamental wave as a center frequency of a pass band, and a notch filter that blocks the unbalanced component and a harmonic component of a predetermined order. The phase detector as described.   The phase detection device according to any one of claims 1 to 4, wherein the AC signal is a detection signal obtained by detecting a single-phase AC voltage flowing through a power system. The AC signal is a detection signal that detects a three-phase AC voltage flowing through the power system,
Before the filter means, the three-phase detection signal is converted into two signals orthogonal to each other, one signal is a signal of the real part of the complex signal, and the other signal is a signal of the imaginary part of the complex signal. The phase detection apparatus according to claim 1, further comprising a three-phase to two-phase conversion unit that inputs to the filter unit. The filter means outputs a sine value and a cosine value of the phase of the fundamental wave included in the AC signal,
The phase control means calculates the phase difference,
First sine value calculating means for calculating a sine value of the phase generated by the phase generating means;
Cosine value calculating means for calculating the cosine value of the phase generated by the phase generating means;
Using the sine value and cosine value input from the filter means, the sine value calculated by the first sine value calculation means, and the cosine value calculated by the cosine value calculation means, a predetermined trigonometric function Second sine value calculating means for calculating the sine value of the phase difference represented by the multiplication formula:
The phase detection device according to claim 1, comprising: The multiplication function of the trigonometric function is
sin (θ) ・ cos (θ ') − cos (θ) ・ sin (θ ′) = sin (θ−θ ′)
Where θ is the phase of the fundamental wave included in the AC signal
θ ′: phase generated by the phase generation means
sin (θ): Sine value input from the filter means
cos (θ): cosine value input from the filter means −sin (θ ′): sine value calculated by the first sine value calculation means
cos (θ '): The phase detector according to claim 7, which is a cosine value calculated by the cosine value calculating means. The filter means outputs a sine value of a phase of a fundamental wave included in the AC signal;
The phase control means calculates the phase difference,
Sine value calculating means for calculating the sine value of the phase generated by the phase generating means;
First zero cross detection means for detecting timing at which a sine value input from the filter means crosses a zero level;
Second zero cross detecting means for detecting timing at which the sine value calculated by the sine value calculating means crosses the zero level;
Timing means for measuring a time difference between the detection timing of the first zero-cross detection means and the detection timing of the second zero-cross detection means;
A phase difference calculating means for calculating the phase difference based on the deviation time measured by the time measuring means;
The phase detection device according to claim 1, comprising:

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