WO2018122391A1 - Precise real-time advanced grid monitoring - Google Patents

Abstract

A hardware-synchronised integrator for grid monitoring that eliminates the offset in the determination of the grid frequency. The equation for the integrator is: y(n) = y(n-1) plus a term in Ts, the sampling time. The hardware synchronisation involves the use of T _s-act rather than an estimate T_s. An inverter is described which includes the hardware-synchronised.

Description

Precise real-time advanced grid monitoring

The present invention relates to grid converters, inverters, integrators, and grid detectors and methods of operating the same.

Background Power electronic (PE) converters are being connected to the low- voltage grid (LV grid) and are being used to interface distributed generation (DG), like solar and small-scale wind power units. They can allow connection of a battery or charging of a plug-in electric vehicle (PEV). These converters have in common that they convert the grid's AC voltage to DC for the consumer or vice versa. More applications exist for these AC-DC converters on the LV grid, like controlling motors (e.g. compressors and heat pumps) and generators (e.g. small wind turbines and micro water turbines) as well as future applications, as DC microgrids, will have an AC-DC converter as a component.

These AC-DC converters need to adhere to the grid code in the respective country where they are installed. Their topology is composed of a number of half bridges (two switches in series), which together can form a full bridge (two half bridges in parallel, i.e. a single phase converter as in Figure 1). Three half bridges are required for a three phase converter without neutral connection (i.e. one half bridge per phase, as in Figure 2). Adding a fourth half bridge is required for an active neutral connection (as in Figure 3). Furthermore, each half bridge, except the one for the neutral connection, uses an LCL- filter. Hence, Figure 1 shows one LCL filter (two inductors and one capacitor), while Figure 2 and Figure 3 show three LCL filters. This topology is the most common for low voltage converters.

Two distinctive ways of providing measurement data for a converter are known:

1) An integrated measurement system, that is capable of running on the control unit of the converter

2) An external measurement system that is physically an additional component with its own processor and a communication bus towards the control unit running the control scheme.

The first method is common for small-scale (residential) converters. There is only one control unit, running all the required algorithms. This is the cheapest and simplest solution as the required hardware is limited. The second method is common for large-scale (utility) converters. Multiple control units are connected together and the computational burden is distributed. This increases the cost of the system as more hardware is required. Furthermore, when purchasing an external measurement device, also the knowledge over the software is distributed.

Voltage and frequency control are a crucial element of the grid. Frequency stability can be inherently implemented where the inertia of the rotating synchronous generators allowed for a very fast frequency response. Furthermore, Frequency Containment Reserve (FCR), automated Frequency Restoration Reserve (FRR) and manual FRR control have been proposed in three different time frames, to allow for an accurate control of the frequency using conventional generating plants. A similar behaviour can be implemented in DG converters. If the control is fast enough, it could act on the frequency deviation via primary control (/). If it is faster and more accurate, it could implement a similar response to inertia (df /dt).

As converters have a direct influence on the local grid' s voltage, reactive power support by converters has been proposed for Electric Vehicle Supply Equipment (EVSE) and DG. Reactive power support can be implemented as droop control for residential grids, but until now, reactive power droop control was only implemented in the context of microgrids. Voltage control can also be expanded with droop control for active power. Active and reactive power droop control can increase the grid-support capabilities of a battery system, in some cases even replacing the battery with the converter.

Fast faults on the grid should be cleared by the appropriate protection devices. During the fault however, there is an impact on e.g. the grid voltage. This means that even if they are cleared in the ms-timeframe, the converter will still see this happening. Hence, the converter should be able to ride through the fault. Fault ride-through (FRT) is an important feature for any converter, as it vastly increases reliability. The converter can stay connected during single or two-phase faults or brief three-phase faults.

A converter can respond to an imbalanced grid in many different ways. It can inject balanced currents, it can inject balanced powers (active or reactive) or it can inject only the positive sequence, with injection of currents being independent of imbalance. A converter could also actively compensate imbalance, which can e.g. decrease grid losses. Also different imbalance compensation techniques are available, although some are dependent on the available hardware (i.e. a neutral connection or not). The connection to the neutral is required to be able to compensate not only the negative sequence, but also the zero sequence.

The control system can also participate in limiting other disturbances, like harmonics. In this case, the measurement system should provide information about those harmonics, e.g. at the relevant frequencies.

Earlier three-phase inverters are equipped with a three-phase Synchronous Reference Frame Phase-Locked Loop (SRF-PLL) to determine the frequency, phase-angle and amplitude of the grid voltage. However, this traditional SRF-PLL has disadvantages:

• Frequency fluctuations caused by sudden changes in the grid-load (large load starting up or load-shedding) or production (Intermittent behaviour of renewable energy sources or generation loss of large power plant).

• Voltage imbalance in the grid caused by unequal load and generation currents in the grid (e.g. single phase PV plants in distribution grid)

• Presence of harmonic distortion in the voltage and currents.

• Voltage sags and swells.

In the presence of these disturbances, the SRF-PLL will not be able to correctly determine the grid frequency, and hence the phase-angle will be badly determined, resulting in poor synchronization with the grid and consequently low power quality of the injected currents.

In order to address the disadvantages of the traditional SRF-PLL, the problem has been decoupled in two separate reference frames. The first reference frame focuses on the positive voltage sequence, the second reference frame focuses on the negative sequence. This method is called the Decoupled Double Synchronous Reference Frame Phase-Locked Loop (DDSRF- PLL).

Decoupling terms have to be added to both frames to get rid of the 100 Hz oscillation present on both signals due to the rotating of both 50 Hz vectors (positive and negative sequence) in opposite directions. In order to determine the decoupling voltages, the output-signals of the decoupling modules are filtered with a 100 Hz Low-Pass Filter. This is very close to the 50 Hz signal that it is desired to detect and to apply on the inverter to synchronize with the grid. The consequence is that obtained positive and negative sequence values are considerable delayed compared to the actual signal which deteriorates its ability to synchronize with the grid and makes the system slow to respond to high frequency events. This delay and filtering is also detrimental to its ability to detect harmonics in the grid voltage and to counter inject current harmonics.

The DDSRF-PLL also assumes that the phase-angle of the negative sequence is the opposite of the positive sequence and does not contain a phase shift compared to the positive sequence. This lack of information requires an extra calculation to determine the actual phase shift of the negative sequence when the inverter needs to inject negative sequence currents.

The Enhanced Synchronous Reference Frame Phase Locked Loop (ESRF-PLL or EPLL) is also based on the Clark and Park transformation to convert a sinusoidal three-phase voltage to a positive and negative sequence d-q voltage (Vd₊/V_q+ & VdW_q-). Each phase is equipped with a frequency adaptive band-pass filters (FABPF) and a PLL which reconstructs the fundamental component of the input signal in real time by estimating its amplitude, phase and frequency through the steepest descent algorithm.

The outputs of the EPLL are two signals per phase which represent the fundamental component of the input signal and its quadrature. For a three-phase EPPL this leads to 6 signals. These 6 signals are the input of a Positive Negative Sequence Converter (PNSC) which determines the positive and negative sequence components. As the positive sequence is already filtered, harmonics and other disturbances are no longer present in the positive sequence signal. This allows a fourth EPLL to lock on the phase-angle of the positive sequence voltage, such that the Park transformation can be used to determine the d/q components of the positive and negative sequence. The drawback of this structure is that the phase-angle is used as a feedback signal to determine the quadrature components at the output of the band-pass filter. A sudden change in the phase- angle causes a distortion on these quadrature signals which affects the PLL itself and the estimated values of the grid frequency and the positive/negative sequence. A next step was the use of Second-Order Generalized Integrators (SOGIs) in grid detectors. These SOGIs are bandpass filters based on the concept of the generalized integrator which adapt to the estimated frequency to retrieve the fundamental component of the input signal. By adding a feedback loop that determines the error between fundamental component and the actual signal, the SOGI can be extended to a Quadrature Signal Generator SOGI (SOGI-QSG) which produces both the fundamental and the quadrature of the fundamental of the input signal. The outputs of the Clark Transformation (Vo/Vp) act as the inputs of two separate SOGTQSGs. Hence the fundamental signal of Vo/Vp and their quadrature signals are extracted. This allows the determination of the positive and negative sequence of Vo/V using a Positive Negative Sequence Converter (PNSC), based, for example on the instantaneous symmetrical components (ISC) method. Next, these 4 signals (V_a+/V ₊ & V_aWp-) are converted using the Park Transformation to obtain (Vd₊/V_q+ & VdW_q-). As the SOGI is a high- quality band-pass filter, very little noise and harmonics are present on the calculated positive and negative sequence. The positive sequence signal is the input of a single SRF-PLL which determines the frequency and phase-angle and is used for the Park Transformation to obtain Vd₊/Vq₊. Due to the high quality filtering of the SOGI and the fact that the PNSC delivers a balanced voltage (V⁺) signal to the SRF-PLL, the retrieved frequency and phase-angle is much more accurate and stable than in the conventional three-phase SRF-PLL case. As this scheme uses two SOGI-filters and a single PLL, this scheme is referred to as the Dual SOGI PLL or DSOGI-PLL.

Advanced as it may be, the DSOGI-PLL does not solve the inherit drawback of the PLL; When the PLL is submitted to a sudden change in the phase-angle, the estimated frequency will deviate strongly from the actual frequency and consequently the retrieved fundamental signal and its quadrature experience a significant error. In order to cope with this inherit drawback, the phase-locked loop has been replaced by a frequency-locked loop (FLL) as the frequency is much more stable and does not suffer from sudden phase-angle changes. The FLL does not require a Park transformation to lock on the phase of Vq. The FLL uses the quadrature of the fundamental signal and the error between the actual and fundamental signal as inputs. The product of the latter is processed by an integrator to determine the estimated grid frequency, which is used by the SOGIs to obtain a frequency adaptive band-pass filter. The Dual SOGI delivers Va/Υβ and their quadrature signals, such that the Positive Negative Sequence Converter (PNSC) can extract the positive and negative sequence signals.

Summarising: conventional algorithms are limited to positive and negative sequence components. For frequency droop control, the measurement system should thus be able to provide a very fast and reliable frequency measurement. For voltage droop control, the measurement system should thus be able to provide a fast and reliable voltage amplitude or rms-value measurement. Furthermore, during imbalanced situations, the positive sequence voltage is the most relevant one. For current redistribution, the measurement system should thus be able to provide a positive, negative and zero sequence decomposition of the grid, either for the currents that need to be compensated or for the voltages, of which the currents can be derived. For FRT, the measurement system should thus be able to provide a reliable voltage measurement that responds fast enough to transients in order to know that a fault is happening. Furthermore, this will enable the controller to decide on the appropriate action.

Summary of the invention

Embodiments of the present invention provide methods and apparatus:

a. Generating a reference for the positive, negative and zero-sequence components of either the voltage or current.

b. Using single-phase systems in a three-phase system

c. Using a method (using a SOGI), which is usually only used in the context of phase synchronization, in a system that calculates all of the required parameters for a converter and thus fully describes the state of the grid.

d. Using of the same building blocks for voltage and the current determinations.

In one aspect the present invention provides a hardware- synchronised integrator that eliminates the offset in the determination of the grid frequency for grid monitoring. Positive, negative and zero-sequence components of either the voltage or current are determined. For example, several grid parameters can be determined such as at least one, any or all of grid frequency, grid voltage, e.g. per phase and decomposition into positive-, negative- and zero- sequence components, inverter current, per phase and decomposition into positive-, negative - and zero-sequence components. The equation for the integrator is : y(n) = y(n-l) plus a term in T_s, the sampling time. The hardware synchronisation involves the use of T_s__act rather than an estimate T_s and y(n) is the nth output of the integrator.

A discrete-time integrator for use in grid monitoring, the discrete-time integrator operating with a sampling time, the discrete-time integrator comprising: a signal generator with a first output of a first signal having a resonant frequency, a first input for a second signal having the resonant frequency and a second input for an error signal in the resonant frequency, means for perturbing the first output dependent upon the error signal, wherein the signal generator has an inverter with a digital processing engine operating with a cycle time, the sampling time of the integrator being a multiple of the cycle time of the processing engine. Positive, negative and zero-sequence components of either the voltage or current are determined.

Advantages of embodiments of the present invention can be robustness, speed and accuracy of grid detection using current and voltage measurements that are inherently available in grid- connected inverters. Embodiments of the present invention can provide the advantage of methods and devices for determination of several grid parameters such as at least one, any or all of grid frequency, grid voltage, e.g. per phase and decomposition into positive-, negative- and zero-sequence components, inverter current, per phase and decomposition into positive-, negative- and zero-sequence components.

An aspect of embodiments of the present invention is an implementation of a method of grid detection and a grid detector based on a Synchronized Discrete Integrator (SOGI) using real or hardware determined sampling timings, which can be implemented per phase at the fundamental and required harmonic frequencies. The integrator can be used in an inverter or inversion process and can convert the inverter into a PMU (Phasor Measurement Unit) which is able to track the grid state. It also allows the inverter or inversion process to provide grid services which require less expensive external measurements.

An inverter or inversion process according to embodiments of the present invention can provide at least one, any or all of local voltage services, system services such as frequency droop and inertia emulation as well as distribution grid services such as current redistribution between phases. A grid detector or grid detection process according to embodiments of the present invention can be both suited for conventional inverters or inversion processes using 3 half -bridges as well as inverters or inversion processes using a neutral point connection, e.g. inverters or inversion processes using 4 half-bridges.

A grid detector or grid detection process according to embodiments of the present invention can be used with single-phase or multiple phase inverters or inversion processes and can also benefit as embodiments of the present invention can be implemented per phase and for a number of phases.

A grid detector or grid detection process according to embodiments of the present invention can be used for inverters or inversion processes which inject or consume a controlled amount of current in the three- phases and/or the neutral current. A grid detector or grid detection process according to embodiments of the present invention can be used to decompose measured phase voltages and currents into positive-, negative- and zero-sequence components. A grid detector or grid detection process according to embodiments of the present invention can be used to decompose measured phase voltages and currents in a vector format which provides information on the actual (grid) voltages and (inverter) currents. This can avoid providing information in a two-phase reference frame which is not directly related to the actual voltage and current. A grid detector or grid detection process according to embodiments of the present invention can allow control of the positive, negative and zero sequence components of the voltage and current. This can provide an improvement over control of only the positive and negative sequence components. The vector format can provide the advantage of decoupling the time and magnitude components of the signal, allowing for different types of control. A grid detector or grid detection process according to embodiments of the present invention can be used with three-phase inverters with neutral connection which satisfies the need to control the current in the neutral connection. A grid detector or grid detection process according to embodiments of the present invention can also be used in conventional three-phase inverters, e.g. to actively control the common mode voltage.

Embodiments of the present invention provide a SOGI to calculate frequency and voltage. Embodiments of the present invention do not need a low pass filter after the voltage and current measurement, to generate a useful output. To calculate the powers P and Q from the outputs of embodiments of the present invention one needs U times I, and no filtering is required.

The inventors have found from measurements that using the sampling frequency T_s is significantly less good than using the actual sampling frequency T_{s act} as is done in embodiments of the present invention. If a sampling frequency is set of 40kHz for example, that does not mean that the actual sampling time is exactly l/40kHz. It might be, e.g. 40.001 kHz and such a difference is big enough to generate a significant difference and, hence, to provide embodiments of the present invention with significant advantages.

In another aspect of the present invention, a method for use in an inverter for grid monitoring and having a discrete-time integrator is provided, the discrete-time integrator operating with a sampling time, the method comprising hardware- synchronizing the integrator implemented on a processing engine; synchronizing to an actual sampling frequency of the inverter, wherein the hardware timing period of the processing engine is used in implementing the discrete integrator.

The grid detector can detect and allow control of positive, negative and zero sequence currents or voltages.

An output of the discrete-time integrator is preferably given by an equation: y(n) = y(n-l) plus a function of T_s__act wherein T_s__act is a sampling time being a multiple of the hardware timing period of the processing engine and y(n) is the nth output of the integrator.

The method is preferably implemented per phase at a fundamental and harmonic frequencies.

A feedback signal of the fundamental signal is preferably provided at the output of a discrete SOGI.

Pulse width modulation of the inverter is preferably applied based on a carrier signal having a carrier period which is a multiple of the hardware timing period.

In the method the discrete-time integrator can be a second or third order discrete integrator. A retrieved fundamental frequency can be used in a frequency locked loop.

The method can be operated so that an error in a calculated grid frequency is less than 50 mHz.

The method can include determining at least one, any or all of grid frequency, grid voltage, grid frequency or grid voltage per phase, decomposition into positive-, negative- and zero- sequence components, inverter current per phase and decomposition into positive-, negative - and zero-sequence components.

The method can include providing at least one, any or all of local voltage services, frequency droop and inertia emulation and current redistribution between phases. The method can include decomposing measured phase voltages and currents into a vector format which provides information on grid voltages and inverter currents.

In another aspect of the present invention, a computer program product is provided which when executed on a processing engine preforms any of the method steps described below. A non-transitory signal storage medium can be provided storing the computer program product. Any of the embodiments of the present invention can be implemented by a digital device with processing capability including one or more microprocessors, processors, microcontrollers, or central processing units (CPU) and/or a Graphics Processing Units (GPU) adapted to carry out the respective functions programmed with software, i.e. one or more computer programs. The software can be compiled to run on any of the microprocessors, processors, microcontrollers, or central processing units (CPU) and/or a Graphics Processing Units (GPU). Suitable signal storage media include magnetic tapes or such as hard disks, solid state memories such as flash memories or drives, optical disks such as CD)Oms or DVD-ROMS, or any other storage devices.

Brief description of the drawings Figure 1: Prior art single phase converter.

Figure 2: Prior art three phase converter (without neutral connection). Figure 3: Prior art three phase converter (with active neutral connection). Figure 4: Implementation of the discretized SOGI according to embodiments of the present invention.

Figure 5: discrete 3rd order integrator for use in the SOGI according to embodiments of the present invention. Figure 6: Hardware Synchronized Discrete SOGI-QSG according to embodiments of the present invention.

Figure 7: Multiple SOGIs for harmonic detection and rejection according to embodiments of the present invention.

Figure 8: the discretized frequency locked loop according to embodiments of the present invention.

Figure 9: gain normalization according to embodiments of the present invention.

Figure 10: Theta calculation according to embodiments of the present invention.

Figure 11: a single phase MHSDiSOGI-FLL with vector outputs according to embodiments of the present invention. Figure 12: Lyon transformation according to embodiments of the present invention.

Figure 13: Determining the actual three-phase frequency according to embodiments of the present invention.

Figure 14: Triple Frequency Locked Loop with Lyon Transformation according to embodiments of the present invention. Figure 15: Summarized operation of the TF3LT according to embodiments of the present invention.

Figure 16: Control scheme of an advanced converter according to embodiments of the present invention.

Figure 17: Current decomposition according to embodiments of the present invention. gure 18 which shows the five pages of Table I.

Definitions

DDSRF-PLL Double Decoupled SRF-PLL

DG Distributed Generation

DSOGI Dual SOGI

DiSOGI Discrete SOGI

EPLL Enhanced (SRF-)PLL

EVSE Electric Vehicle Supply Equipment

FLL Frequency Locked Loop

FPGA Field Programmable Gate Array

FRT Fault Ride Through

HSDiSOGI-QSG Hardware Synchronized DiSOGI-QSG which is an

embodiment of the present invention

LV Low Voltage

MHSDiSGOI Multiple HSDiSOGI

MHSDiSOGI-QSG Multiple Hardware Synchronized DiSOGI-QSG which is an embodiment of the present invention

MSOGI Multiple SOGI

PE Power Electronic(s)

PEV Plug-In Electric Vehicle

PLL Phase Locked Loop

PMU Phasor Measurement Unit

PNSC Positive Negative Sequence Convertor

PV Photovoltaic

PWM Pulse Width Modulation

QSG Quadrature Signal Generator

SNR Signal to Noise Ratio

SOGI Second Order Generalized Integrator

SRF-PLL Synchronous Reference Frame PLL TF3LT Triple Frequency Locked Loop with Lyon

Transformation which is an embodiment of the present invention

THD Total Harmonic Distortion

Reference support, each of which is incorporated by reference in its entirety

[1] P. Rodriguez, A. Luna, R. S. Munoz-Aguilar, I. Etxeberria-Otadui, R. Teodorescu, and F. Blaabjerg, "A Stationary Reference Frame Grid Synchronization System for Three-Phase Grid-Connected Power Converters Under Adverse Grid Conditions," IEEE Trans. Power Electron., vol. 27, no. 1, pp. 99-112, Jan. 2012.

[2] P. Rodriguez, A. Luna, M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, "Advanced grid synchronization system for power converters under unbalanced and distorted operating conditions," in IECON 2006 - 32nd Annual Conference on IEEE Industrial ElectronicsECON 2006-32nd 2006, no. 2, pp. 5173-5178. [3] Y. Park, S.-K. Sul, W. Kim, and H.-Y. Lee, "Phase Locked Loop Based on an Observer for Grid Synchronization," 2013 Twenty- Eighth Annu. IEEE Appl. Power Electron. Conf. Expo., vol. PP, no. 99, pp. 308-315, Mar. 2013.

[4] W.-L. Chen, B.-S. Lin, and M.-J. Wang, "Dynamic symmetrical components analysis and compensation for unbalanced distribution systems," in 2015 9th International Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia), 2015, pp. 2221-2226.

[5] F. J. Rodriguez, E. Bueno, M. Aredes, L. G. B. Rolim, F. A. S. Neves, and M. C. Cavalcanti, "Discrete-time implementation of second order generalized integrators for grid converters," Proc. - 34th Annu. Conf. IEEE Ind. Electron. Soc. IECON 2008, no. 1, pp. 176- 181, 2008. [6] G. Kampitsis, A. P. Tsoumanis, S. N. Manias, and S. Papathanassiou, "Experimental Investigation of the DSOGI PLL Response to Grid Disturbances for PV System Applications," in Ninth Japanese-Mediterranean Workshop on Applied Electromagnetic Engineering for Magnetic, Super-conducting, Multifunctional and Nanomaterials, JAPMED'9, 2015, no. July, pp. 2-4. [7] M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, "A New Single-Phase PLL Structure Based on Second Order Generalized Integrator," in 37th IEEE Power Electronics Specialists Conference, 2006, pp. 1-6.

[8] P. Rodriguez, A. Luna, I. Candela, R. Mujal, R. Teodorescu, F. Blaabjerg, P. Rodriguez, A. Luna, I. Candela, R. Mujal, R. Teodorescu, and F. Blaabjerg, "Multiresonant frequency- locked loop for grid synchronization of power converters under distorted grid conditions," IEEE Trans. Ind. Electron., vol. 58, no. 1, pp. 127-138, Jan. 2011.

[9] P. Rodriguez, A. Luna, I. Candela, R. Teodorescu, F. Blaabjerg, and J. I. Candela, "Grid synchronization of power converters using multiple second order generalized integrators," in IECON 2008 - Annual Conference on IEEE Industrial Electronics, 2008, pp. 755-760.

Description of the illustrative embodiments

PE converters are a common cause for problems in the LV grid, for example for PEV charging, the amount of power of a single device already has an impact on the respective grid, e.g. local deviation from the voltage setpoint, causing voltage stability problems. DG like PV could influence the energy imbalance could, potentially, causing grid collapse if the quantity of small units causes global frequency deviations, reduced inertia and rapid disconnections.

Local interphase imbalances can be a consequence of the construction of the grid. The typical European residential LV grid has three phases at 400V line-to-line and a neutral (230V phase voltage). Most loads are single -phase, automatically leading to imbalance, as these can only be balanced out by other loads. DG can make this problem worse, as currents can flow from the customer to the grid, instead of the other way around. So while consumption and generation can be balanced from a system perspective, they can be locally imbalanced, e.g. a PV installation producing power on phase 1 and an equal but opposite consumption on another phase. This is a cause for neutral-point- shifting and imbalanced grids. PE converters according to embodiments of the present invention can make use of a behaviour of the converter that is fully programmable. Three aspects influence behaviour towards the grid, for example: • A fast and reliable control scheme to determine and execute the PE converter set- points

• Embodiments of the present invention can provide a quick and accurate measurement system to determine what the situation in the grid is and to be able to supply the control scheme with the required data.

• A suitable control unit (hardware), that is capable of running the above software

Embodiments of the present invention focus on the second and third points: the measurement system and its implementation. An advantage of embodiments of the present invention can be to supply the control scheme with all the data it requires, the data being free of disturbances (i.e. has been filtered) and arrives with little to no delay. In the case of embodiments of the present invention, a measurement system and a measurement method can be implemented as software and thus can run on a control unit, together with the control scheme.

Measuring the state of the grid needs to happen quickly, with a small error tolerance and should be able to filter out any unwanted disturbances. Commonly, these disturbances are:

• Measurement noise

• Harmonics (disturbance for all, except for determining the harmonics)

• Phase shifts (disturbance for the frequency, measurable for the other components)

• Amplitude changes (disturbance for the frequency, measurable for the other components)

• Any combination of the above

Signals that are useful to be measured are:

• The frequency (for the frequency droop control)

• The amplitude of the positive sequence voltage (for the voltage droop control)

• The positive-, negative- and zero-sequence of the grid voltage or grid current (for current redistribution)

• A representation of the grid voltage (for the FRT)

• The harmonic contents of the grid voltage (for the harmonic compensation) The disturbances above are also true for the current. Hence the current should be able to be determined in a similar manner.

Furthermore, any control system will require some sort of current controller to inject the current, determined in previous steps. This current controller might need the positive-, negative- and zero-sequence components of the grid voltage in phasor representation as a feed-forward term and will need the positive-, negative- and zero-sequence representation in phasor representation of the injected current as feedback terms.

One of the main problems with known grid detectors is the low accuracy of the frequency detection. If the frequency detection is performed at the switching frequency of the inverter, than the error on the frequency estimation will be several tens of mHz using the current state- of-the-art grid detection algorithms. This accuracy of the frequency estimation is far below the level required to allow these inverters to participate in frequency related grid services if, for example, the dead-band of the frequency reserves is 10 mHz and the standard frequency range is 50 mHz. In utility scale installations, i.e. PV inverters or battery inverters, a separate frequency measurement module can be foreseen which measures the grid frequency and communicates this value to the controller of the inverter. Based on the received frequency information, the inverter controller can adjust the power output to the required response, which can be related to frequency containment and frequency restoration reserves. In residential installations the required grid frequency accuracy is currently tens of mHz as the different frequency bands in which the inverters need to operate are several hundreds of mHz wide. For example, PV inverters need to operate continuously between 49 and 50.2 Hz, while the power needs to decrease at 40% Pinit (initial power or starting power) per Hz between 50.2 and 51.5 Hz. Thus, for a 4 kW inverter operating at full power at an instance of a frequency disturbance, an error in the estimated grid frequency of 50 mHz will only result in an error of the output power of 80 W or 2% of the nominal power. Hence, the effect of the low frequency accuracy of these residential inverters is limited due to the wide frequency bands in which they operate. However, this lack of accuracy limits the grid services the current inverters can offer without an expensive external grid frequency measurement device, as grid services such as the frequency containment reserve and automated frequency restoration reserve require an accuracy of the grid frequency estimation below 10 mHz.

Embodiments of the present invention are able to estimate the grid frequency with an accuracy of approximately 5 mHz which is updated at the switching frequency of the inverter.

This allows the inverters to participate in the frequency reserve grid services without expensive external measurements. Moreover, the combination of high accuracy grid frequency detection and the speed at which the frequency is tracked, allows the implementation of inertia emulation by the inverter. This allows the inverter to react on frequency deviations (df/dt) and increases the grid stability by emulating the inertia of rotating machines.

A grid detector or a grid detection process according to embodiments of the present invention can be used with three-phase inverters with 3 half -bridges and does not require use of a two- phase bandpass filter such an inverter or inversion process according to embodiments of the present invention can control more than the (differential) positive and negative voltage. Control schemes according to embodiments of the present invention can detect and control the zero sequence current. Software of these inverters according to embodiments of the present invention are designed to inject or absorb an imbalanced three-phase current. As the goal is to detect and inject imbalanced currents, a grid detection process or a grid detector according to embodiments of the present invention is not only able to detect positive and negative sequence voltages and currents, but is also capable to detect the phase-angle and amplitude of the zero sequence current. Whereas grid detection algorithms only intended for the positive and negative sequence and thus requiring only two independent reference frames, almost exclusively use the Clark transformation to convert from a three-phase a,b,c-frame to a two-phase α,β-frame, embodiments of the present invention are not so limited. Embodiments of the present invention provide information that can be directly related to actual voltages and currents, and hence do not require a transition to positive and negative sequence α,β-components, which do not contain any direct information on the grid state do not require a second step to obtain the actual grid state.

As grid detection processes and grid detectors according to embodiments of the present invention do not experience loss of redundancy by using a two-phase reference frame, information on imbalanced harmonic currents in the individual phases is not lost and embodiments of the present invention do not need to use the Clark transformation nor are they based on the assumption that the sum of the currents is zero.

Embodiments of the present invention provide a discrete integrator and discrete integration method to construct a Discrete SOGI (DiSOGI) which is extended with a feedback signal of the fundamental signal, which is present at the output of the DiSOGI, to obtain a DiSOGI- QSG. Grid detectors and a grid detection method according to embodiments of the present invention make use of a value of the inverter period that is the actual sampling period T_s-_act of the inverter, measured in the number of hardware determined timings such as clock cycles of a processor such as an FPGA used in the implementation of embodiments of the present invention.

A conventional grid detector used in an inverter with a rated switching frequency f_s__r and a rated period of T_s__r will use the rated period T_s__r in the discrete integrator. However, this value is not exact as the inverter period is in reality a multiple of hardware determined timings such as clock cycles of a processor such as an FPGA, e.g. the FPGA-period. Therefore, in embodiments of the present invention, the rated inverter frequency is adjusted until the inverter period is an integer multiple of the hardware determined timings such as clock cycles of a processor such as FPGA -periods. The inventors have found from measurements that using the sampling frequency T_s is significantly less good than using the actual sampling frequency T_{s act} as is done in embodiments of the present invention. If a sampling frequency is set of 40kHz for example, that does not mean that the actual sampling time is exactly l/40kHz. It might be, e.g. 40.001 kHz and such a difference is big enough to generate a significant difference and hence to provide embodiments of the present invention with significant advantages. Embodiments of the present invention take into account that the PWM of the inverter is based on a carrier signal. This carrier signal usually is a symmetrical sawtooth signal. Hence, the number of FPGA -periods per carrier-period needs to be a multiple of 4. The combination of both requirements results in inverter period which is preferably an integer multiple of 4 times the hardware determined timing such as clock cycle of a processor such as an FPGA period. For example, for an inverter with a rated frequency of 16 kHz and a processor clock cycle frequency such as an FPGA period frequency of 62.5 MHz, this results in a inverter/carrier- period of 3096 times the 16 ns period or 62.464 and an actual inverter frequency of 16009 Hz.

Hence, the embodiments of the present invention synchronize the actual switching frequency of the inverter with the hardware sampling period of the processor used in implementing the discrete integrator of the DiSOGTQSG, which is therefore called a Hardware Synchronized Discrete SOGI-QSG or HSDiSOGI-QSG.

This HSDiSOGI-QSG according to embodiments of the present invention can be implemented with different discrete integrators, e.g. trapezoidal, first, second order or third order discrete integrator. In the present invention a third order integrator is preferred as this has been shown to perform the best. When the inverter is switched at the calculated frequency and the discrete integer uses the exact hardware determined inverter period, the measurement error in the calculated grid frequency is reduced from some 50 mHz to 5 mHz.

This HSDiSOGI-QSG can be repeated (1+n) times for the fundamental frequency and n harmonics in a structure similar to the conventional Multiple-SOGI (MSOGI), resulting in the creation of a MHSDiSOGI-QSG which is an embodiment of the present invention. The retrieved fundamental frequency signals are used in a Frequency-Locked Loop (FLL) to obtain the fundamental grid frequency rapidly and accurately and to determine the amplitude and phase-angle of the fundamental voltage and current vector. Moreover, this MHSDiSOGI- QSG structure can be implemented for each phase, so that the amplitude and phase-angle of the fundamental voltage and current vector per phase are determined separately. The benefit of this structure is that the grid information is now available as 3 independent vectors. The decomposition in a vector format provides information on the actual (grid) voltages and (inverter) currents, not using a two-phase reference frame which is not directly related to the actual voltage and current. Firstly, this provides fast and accurate information on the actual amplitude and phase-angle of the fundamental frequency and harmonics per phase. Secondly, this allows to control both the positive, negative and zero sequence components of the voltage and current, thus not being limited to control of only the positive and negative sequence components.

As far as the measurements of voltages and currents are concerned, embodiments of the present invention allow at least one, any or all of:

• Determination of the positive/negative/zero sequence of the actual voltage and current e.g. in a single step using, for example, the Lyon Transformation including determination of the zero sequence voltage and current. Known grid detectors require an extra step as the output of their positive/negative sequence converter is V_a+/V β+ & Va-/V β-, which is of no direct use. Embodiments of the present invention do not require an additional conversion to the a,b,c reference frame.

• The obtained information can be directly used for current control and grid services and some information is redundantly available:

o The frequency can be obtained separately per phase, and this allows to increase the accuracy in normal operation and allows easy detection of single- and two- phase grid faults during disturbances, resulting in very robust frequency detection and droop control.

o The positive sequence fundamental voltage is directly available for usage in the voltage droop control even in the presence of large voltage imbalances. Other grid detectors will suffer from a less accurate positive sequence fundamental voltage determination as they are unable to entirely remove the influence of the zero- sequence component.

o Harmonics are detected per phase, hence the harmonic compensation is able to compensate imbalanced current harmonics. Other grid detectors are unable to detect this.

o The setpoints for the current redistribution per phase are readily obtained as the negative and zero sequence components are directly available for control.

• The zero sequence voltage is filtered out of the positive and negative sequence voltage and current, while other grid detectors are unable to completely remove the influence of the zero sequence form the positive and negative sequence as they are restricted by a two-phase reference frame. • The combination of the high speed of the measurements and their accuracy allows to determine the derivate of the frequency at a much higher bandwidth, and this allows an inverter according to embodiments of the present invention to provide actual inertia emulation without expensive external measurements. The decomposition is preferably in vector format of the phase voltages/currents and sequence voltages/currents implemented per phase. Hence, this can be used in single -phase inverters, three-phase inverters, three-phase + N inverters and other multiple -phase inverters.

The availability of all relevant data (Amplitude and phase-angle of the positive/negative/zero sequence voltage and current at the fundamental frequency and its harmonics, triple redundant frequency, current imbalance) effectively turns the inverter in a PMU (phasor measurement unit). The parallel implementation per phase and harmonic allows simultaneous detection of all grid parameters without increasing the delay, thus resulting in a very fast PMU.

While other grid detectors are built to detect and allow control of positive and negative sequence voltages and currents, the present invention additionally allows to detect and control zero sequence currents. This is feature is both based on properties of the HSDiSOGI-QSG according to embodiments of the present invention as well as the decomposition per phase in a vector format and single-step transition to the positive, negative and zero sequence. As other grid detectors are based on a two-phase reference frame, some of the information is irrevocably lost, while embodiments of the present invention preserve more information. As three MHSDiSOGTQSG according to embodiments of the present invention can be combined to calculate the positive, negative and zero sequence components, this combination is designated "Triple Frequency Locked Loop with Lyon Transformation" or "TF3LT" which is also an embodiment of the present invention.

In embodiments of the present invention, the control of the zero sequence current is straightforward as the zero sequence voltage is available for the feed-forward part of the current control and the zero- sequence currents can be further controlled by a zero sequence current feedback-controller using the measured zero sequence current. Due to the implementation of the MHSDiSOGI-QSG according to embodiments of the present invention, it is possible to separately control: • The zero sequence component at the fundamental frequency which is used for the current distribution between the phases.

• The zero sequence component of the third harmonic and its multiples which can be actively controlled within the bandwidth of its current controller and filter. This allows active control of the common mode voltages in a 3ph+N inverter and reduces voltage stress on the components of the inverter.

• The zero sequence components of the other harmonics which can be actively controlled if a these harmonics are imbalanced.

The control of the positive, negative and zero sequence can be useful for both conventional three-phase and three-phase + N inverters as well as other single -phase and multiple -phase inverters.

SOGI a) Operation

A basic component of a method or system according to embodiments of the present invention is a Discretized Second Order Generalized Integrator (SOGI), as depicted in Figure 4. It is in essence an oscillator at a tunable resonant frequency. The resonant frequency ω' is perturbed by error signal e. This generates an in-phase output v' and quadrature output qv' (90° phase shift of v'). The oscillator requires an integrator - (implemented as component (1) in the next section). This yields following transfer functions: v' (JO'S qv' ω'²

e s² + ω'² e s² + ω'²

An implementation is presented in Figure 4 and can be implemented by programming a digital processor such as a microprocessor, ASIC, FPGAor similar. The software can be embodied in a computer program product adapted to carry out the relevant functions, when the software is loaded onto respective device or devices, and executed on one or more processing engines such as the microprocessor, ASIC, FPGA etc. b) Reference to literature A SOGI has been used for three-phase power converters in e.g. as disclosed in references [1] to [4]. However, these known integrators are implemented in the continuous time domain (1/s), which makes it impossible to be used on a microprocessor. Embodiments of the present invention discretize the integrator. 3rd order discrete integrator a) Operation i

The integrator - for the SOGI needs to track a time-dependent signal (which will later be used to determine time itself, i.e. the frequency). Embodiments of the present invention perform this integration to a high level of accuracy. Furthermore, as later both the in-phase (i ) and quadrature output (qv') will be used, it is also advantageous if the phase shift of the integrator is as close to 90° as possible and independent of the frequency. Such deviations would also become more and more important for higher frequencies that need to be detected (i.e. harmonics). For these reasons a 3^rd order integrator is implemented as an example of an embodiment of the present invention. The 3^rd order integrator uses three delay blocks: 1/z - see Figure 5. Embodiments of the present invention are not limited thereto and any other integration method would also work. The input in is thus integrated as: out = in t - 1) + (23m(t - 1) - 16m(t - 2) + 5in t - 3)) where (t— i) is a delay over i samples. Thus an output y(n) = y(n-l) plus a function of Ts-act wherein T_s__act is a sampling time being a multiple of the hardware timing period of the processing engine, and y(n) is the nth output of the integrator.

Additionally, as the outputs are used to determine a time signal (the frequency), a new parameter is introduced: the actual hardware determined sample time T_s__act. A possible implementation is illustrated in Figure 5

The discrete 3 order integrator can also include an anti- wind-up component— ^ , which limits the signals to realistic values and aids the disturbance rejection. The anti-wind-up operates by limiting the absolute value of the feedback signal i.e.: in if \in\ < in max anti-wind-up { sign(jri)^■ in max if I in I > in, max

Where in_anti__wind__up is the limited value, in is the input of the anti-wind-up, sign() is the operator which determines the sign of in and in_max is the limit of the anti- wind-up.

The actual value of this maximum depends on the application. For example it can be used to track the grid. For tracking a grid voltage, assuming a line-to-line voltage of 400V, a peak value of 400V · 2 = S66V can be expected. As the integrator includes a gain control of 1/12, a value of 566V/12=47V would be normal. A value 50% larger would be abnormal, so the anti- wind-up value in_max would be set to 47V* 1.5 = 71V. b) Reference to literature

The 3^rd order integrator is implemented in a similar way as in [5]. The decision to use a 3^rd order integrator in the SOGI over others is based on a comparison between discretized integrators. Such a comparison can be based on:

• The computational effort

• The steady-state offset in tracking the fundamental frequency and its harmonics

• Disturbance rejection of a DC offset

• Disturbance rejection of harmonics

• Disturbance rejection of noise

The use of the actual hardware determined sample time T_s__act is important and its use cannot be derived from literature. Furthermore, whereas it is not essential to the described discretizing the integrator, it is however important to use T_s__act.

Determining T_s__act

Discrete integrators according to embodiments of the present invention use the hardware determined sample time T_s__act and not an estimated sample time T_s. With integrators according to embodiments of the present invention for control systems, an error on the sample time is avoided and the fundamental frequency can be determined more accurately. Ts-act i^s the ti^me over which the input is actually delayed as determined by the hardware used. It is important that this actual sample time is as correct as possible, as any errors here translate directly in to the frequency and one of the main contributions of this is invention is the very accurate tracking of the frequency. The present invention can be easily adapted for errors: by modifying T_s__act.

In order to determine T_s__act for an application it is necessary to understand the measurement system that is used to gather a measurement point i.e. a sample gather at sampling periods. While a typical sampling device would just send the sample, it is now also important to determine for which time this sample was measured. The latter time is T_s__act. According to embodiments of the present invention an application sends samples on which there is also information about the actual time over which that sample was gathered.

For example: a measurement system can be implemented using a processor such as an FPGA. Assume an FPGA with a clock frequency of 65 Mhz. For each time step of the FPGA (i.e. 16ns (l/65MHz) +- the deviation of the clock) it will measure a value. The control system runs at another frequency (e.g. 16 kHz) and thus one measured sample is required every 62.5μ8 (1/16 kHz). The FPGA than averages all its measurements during this 62.5μ8 sample. This would require 3906.25 samples (62^s/16ns). Depending on the algorithm used, the 0.25 samples cannot be included. Furthermore, requesting a sample time of 62.5μ8 might not result in an exact sample time of 62.5μ8 (e.g. for symmetrical reasons, it could require an even number of FPGA-samples in one control sample). These deviations can and should be included according to embodiments of the present invention in T_s__act . Consider this example, including also the symmetry requirement. Setting a sampling time of 62.5μ8 on a 65 Mhz FPGA would thus result in 3906.25 samples. If the FPGA decides to implement this using 3908 FPGA-samples (closest achievable result which also includes the 0.25 samples), this introduces an error of 2 FPGA-samples. If the user uses T_s (i.e. 62.5μ8) instead of T_s__act (i.e. 3908 · 16ns = 62.528μ5), this results in an offset error of

62.528μ5

—— · 50Hz - 50Hz = 22.4mHz

62.5 μ5

This error is large, given the accuracy obtainable according to embodiments of the present invention. At higher frequencies (e.g. harmonics), the error becomes even bigger. HSDi SOGI-QSG a) Operation

Using the SOGI (component (2) from Figure 4 and implementing it in a feedback loop, as presented in Figure 6, creates an adaptive band pass filter which generates a filtered signal v' from an input v as well as a quadrature component qv' . The frequency of this band pass filter is the resonant frequency of the SOGI, i.e. the detected frequency ω'. The SOGI is used in a feedback loop to act on an error signal e which is amplified by the gain k to achieve the other input for the SOGI: e. The error signal is the difference between the filtered and tracked signal v' and the input signal v, i.e.: e = v— v'→ e = ke = k( — v')

Such that v' ko)'s qv' ko)'²

— = & -— =

v s² + k >'s + v s² + k >'s +

1

Using the proposed discretization for the integrator - (component (1) from Figure 5) then yields a hardware synchronized discrete SOGI: HSDi SOGI. b) Reference to literature

This was proposed in a.o. [1], [2], but without discretization using the actual sample time

T s-act-

M HSDi SOGI-QSG a) Operation Using the HSDi SOGI (component (3) from Figure 6) at multiple frequencies, yields a harmonic filtering system according to embodiments of the present invention that also generates the separate harmonic signals. This is shown in Figure 7, detecting e.g. the 3^rd, 5^th and 1^th harmonic as examples. The harmonics (especially the low ones) form a disturbance for the band pass HSDi SOGI- QSG filter. However, when these harmonics are specifically detected with their own band pass filter, tuned at their own frequency, these can be subtracted from the signal that is used to track the fundamental component. This yields a significantly better result for tracking the fundamental components as well as its frequency according to embodiments of the present invention. Secondly, the harmonics are now also quantified (even a filtered version) and can thus be easily used in a harmonic compensator according to embodiments of the present invention.

It should be clear from Figure 7 that the M HSDiSOGI can be extended to include as many disturbing frequencies as desirable. This can be achieved by adding more HSDiSOGIs at more frequencies and as visualized in Figure 7 by the implementation of the 1^th multiple. b) Reference to literature

This system was proposed in [8] [9], but the frequency locked loop in [8] [9] is not included in the loop. Furthermore, the system developed according to embodiments of the present invention is a discrete time system, while that from [8] [9] is still continuous and thus not directly applicable to digital controllers. For higher frequencies, such as harmonics, the impact of using T_s__act instead of T_s becomes even more important. Furthermore, [8] [9] use the MSOGI in the alfa-beta transformed system, which yields less usable results.

Frequency Locked Loop a) Operation

The frequency of the signal that needs to be tracked can be calculated from the information of the HSDiSOGTQSG. This is called a Frequency Locked Loop (FLL). The operation is further improved by using a gain normalizer (see later). The normalized gain G is delayed by one sample (1/z) to avoid algebraic loops. It is multiplied by an error signal e and the quadrature filtered signal qv^ multiplied by -1. This signal is boosted by gain k₂ and then integrated to eliminate the steady-state offset. Therefore, this integrated offset is added to the nominal frequency ω_η to boost start-up behavior. This I-controller determines the locked frequency ω'. A possible implementation is shown in Figure 8 according to an embodiment of the present invention. 1

ω ' = - {-e - qv - G t - 1)^■ k₂ ) + ω ',n

Again, the integrator has been discretized, although this time the precision of the discretized integrator is not that important as any I-controller can filter out a steady- state offset. Also an anti-wind-up is again integrated in the FLL. The settings for the anti-windup also form bounds for which frequencies can be tracked, thus its settings are important. The operation is identical as explained above, but the limits are the maximal expected frequency offset. b) Reference to literature

This is based on the Frequency Locked Loop (FLL) presented in [2] . Although the discretization is not handled as such in [2] . Gain Normalization and Amplitude Calculation a) Operation

The gain normalization ensures the tuning of the FLL is correct, independent of the frequency and amplitude of the signals used. The filtered input signal and its quadrature component qv are squared and added together to calculate their amplitude \v'\ :

Dividing \v'\ by Λ/2 would yield the rms-value of the signal.

The normalized gain is dependent on the inverse of this amplitude. Hence, to avoid any numerical errors, a dead band is added to avoid division by zero. It operates as: sign(in) if \in\ < in mm

^deadband in if \in\ > in max Where in_deadband is the limited value, in is the input of the deadband, sign() is the operator which determines the sign of in and in_min is the limit of the deadband, e.g. 0.001 . The detected frequency ω' is then divided by \ v'\ (corrected with the deadband) and multiplied by a gain k to determine the normalized gain G for the FLL:

A possible implementation is shown in Figure 9. b) Reference to literature

The system presented in Figure 9 is based on [1].

However, [1] fails to mention that the amplitude of the detected signal is a direct outcome of the calculation. This is however a very important outcome as it is a very useful parameter which determines also the reconfiguration of the other components. Calculation of the phase angle

The system according to an embodiment of the present invention from Figure 10 enables the calculation of the phase angle of the signal im (which is e.g. the phase voltage/current) and its quadrature component 1112. This is achieved by using the four quadrant arctangent atanl and adding ^ (depending on the convention used). A complete single phase controller

Combining (4) from Figure 7, (5) from Figure 8, (6) from Figure 9, and (7) from Figure 10 yields the single phase controller according to an embodiment of the present invention in Figure 11. This controller is able to accurately track an AC signal {im), determine its (filtered) frequency {outi), its (filtered) amplitude {out 3) and its (filtered) phase angle {outi). Furthermore it also captures the harmonic content (out*) of selected frequencies.

Lyon transformation

According to embodiments of the present invention a phasor representation as a complex number can be calculated for the three phases by multiplying the amplitude 1111,3,5 with the phase angle i ^fi times j to the exponential power exp. The Lyon transformation Ttyon can then be applied see M. H. J. Bollen, IEEE Power Engineering Society., IEEE Power Electronics Society., and IEEE Industry Applications Society., Understanding power quality problems : voltage sags and interruptions. 2000:

with a = e^~J : a 120° phase shift see Figure 12. This yields the complex representation of the positive, negative and zero sequence. Taking then the absolute value and the angle of each complex number in polar coordinates yields the amplitudes out 1,3,5 and phase angles out2,4,6 of these sequences. Hence at the output stage, of Figure 12 the amplitude and phase angles of the voltage have been without locking on these parameters but using the much more stable frequency of the present invention. The vector-representation (amplitude and phase angle) is used in the Lyon transformation to directly determine the positive, negative and zero sequence of the signals (voltage and current). Hence the zero sequence is calculated directly and separately.

Calculating the three-phase frequency Three separate frequencies are determined for the three phase grid (1111,2,3) - see Figure 14. Theoretically they should be exactly the same at every moment. However, they are not the same during transients and under perturbations. According to embodiments of the present invention the redundancy can be used to calculate a more robust frequency (e.g. the average) or to determine the frequency based on fewer signals during a fault and thereby omitting the influence of a fault (out) see Figure 13. According to embodiments of the present invention the three frequencies themselves even be used to detect whether a fault is present.

The complete three phase algorithm: TF3LT

According to an embodiment of the present invention, three single phase controllers (8) from Figure 11 can now be combined to track a three-phase grid in Figure 14, using im in2 and «j.

Using the , β system requires only two SOGI-QSGs instead of three here. However, using the a, β system has some distinct disadvantages and is mainly used because this enables the use of the Positive/Negative-sequence calculation (PNSC) block, which only requires 90° phase shifted signals and not 120° shifted signals for a normal Lyon/Fortescue transformation. Moreover, the influence of the zero sequence on the positive and negative sequence is still present in the other grid detectors, while the TF3LT according to embodiments of the present invention produces a positive and negative sequence without this interference.

Using three single phase systems as inputs to (10) from Figure 13 yields three independently determined frequencies which can be used in a redundant way, using (10) to determine the actual frequency - see Figure 14.

Using the vector representation of the three independent phases (using the phase angle and amplitude) as input to the Lyon/Fortescue transformation (9) from Figure 12 yields the vector representation of the positive, negative and zero sequence 0M3, as well as the phase angles of these sequences (outi). This can be easily reformed to the ac signals as well.

Combining all the harmonic outputs, yields the harmonic content of the tracked grid (0M4). The harmonics can even be imbalanced and thus different per phase. Combining the filtered vector representation of the fundamental single phases yields the complete filtered vector representation of the three phase grid at the fundamental frequency (outs).

Figure 15 shows more concisely how the TF3LT according to embodiments of the present invention operates and what the flow of information is. As embodiments of the present invention have a separate grid detection per phase, they have redundant information on some grid parameters, such as the grid frequency. The grid frequency is a global parameter which is the same in all three phases. As redundant information is available on this global parameter, a further increase in the accuracy of the grid frequency detection is obtained e.g.by taking the average of the three detected frequencies. Also, in case of faults in one or two phases, the actual grid frequency can still be obtained by ignoring unrealistic values detected in the faulty phases.

Information availability

The TF3LT according to embodiments of the present invention presented in Figure 14 fields all the available information that is required for an inverter or converter with enhanced grid- supporting features such as imbalance compensation, voltage droop control, frequency droop control, harmonic compensation etc. Figure 16 visualizes such a system where it is made clear which signals are required for which component. How and for what the signals are then used is summarized in Table I (end of figures shown as Fig. 18).

Current detection

The TF3LT according to embodiments of the present invention presented in Figure 15 uses the three single -phase voltages to determine all the information. The same components can also be used to determine information from the current. Figure 17 shows the principle: one HSDi SOGI (3) now receives the calculated frequency (in₂) and the current it needs to determine (ini). The outputs are again an in-phase and quadrature signal, which can again be used for the theta calculation (7) and the amplitude calculation (6). The part from (6) which adapted the gain of the FLL is no longer required, as the frequency was already determined based on the voltage. It is again possible to combine the current decomposition three times, for the phase currents, and link them to the Lyon transformation (9). This yields the positive-, negative- and zero- sequence decomposition of a three-phase current. This system is represented in Figure 16 by '3xSOGI-QSG + Lyon'.

Results/Comparative data Results

In order to demonstrate that the present invention works, measurement results were compared to a calibrated Fluke 434 Power Quality Analyzer Fluke, ("Fluke 434/435 Three Phase Power Quality Analyzer," Users manual.. Available:

assets.fluke.com/manuals/434_435_umeng0300.pdf), which was set-up to measure according to the EN50160 standard. The voltage and frequency were measured from a grid connection. For the current measurement an RLC load was connected: R+C on phase 1, L on phase 2 and 2R on phase 3. The load angle was calculated as the difference between the angle of the respective phase current and the angle of the voltage on phase 1. Results are presented in Table II, Table III and Table IV. Table II: Comparison of the frequency measurement

Table III: Comparison of voltage measurements

TF3LT Fluke 434

Comparative data The TF3LT according to embodiments of the present invention was compared with some known devices:

• A regular three-phase synchronous reference frame phase locked loop (SRF-PLL) • A double decoupled synchronous reference frame PLL (DDSRF PLL) and

• A double second order generalized integrator frequency locked loop (DOSGI FLL)

The SRF-PLL was modelled according to S. Golestan, M. Monfared, and F. D. Freijedo, "Design-oriented study of advanced synchronous reference frame phase-locked loops," IEEE Trans. Power Electron., vol. 28, no. 2, pp. 765-778, 2013, the DDSRF-PLL according to P. Rodriguez, J. Pou, J. Bergas, J. I. Candela, R. P. Burgos, and D. Boroyevich, "Decoupled Double Synchronous Reference Frame PLL for Power Converters Control," IEEE Trans. Power Electron., vol. 22, no. 2, pp. 584-592, May 2007,

and the DSOGI FLL according to P. Rodriguez, A. Luna, M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, "Advanced grid synchronization system for power converters under imbalanced and distorted operating conditions," in IECON 2006 - 32nd Annual Conference on IEEE Industrial ElectronicsECON 2006-32nd 2006, no. 2, pp. 5173-5178 using the gain normalization from . Rodriguez, A. Luna, I. Candela, R. Mujal, R. Teodorescu, F. Blaabjerg, P. Rodriguez, A. Luna, I. Candela, R. Mujal, R. Teodorescu, and F. Blaabjerg, "Multiresonant frequency-locked loop for grid synchronization of power converters under distorted grid conditions," IEEE Trans. Ind. Electron., vol. 58, no. 1, pp. 127-138, Jan. 2011.

In order to compare them, the methods from literature had to be discretized. All integrators in the methods were discretized using a backwards Euler scheme, as suggested in F. J. Rodriguez, E. Bueno, M. Aredes, L. G. B. Rolim, F. A. S. Neves, and M. C. Cavalcanti, "Discrete-time implementation of second order generalized integrators for grid converters," Proc. - 34th Annu. Conf. IEEE Ind. Electron. Soc. IECON 2008, no. 1, pp. 176-181, 2008.for the DSOGI (as this is the most prone to errors in the discretization).

As the TF3LT according to embodiments of the present invention provides much more useful outputs than its competitors, not all could be compared. However, following output could be compared:

• Detected frequency

• Detected (positive sequence) phase angle of the system

o The SRF-PLL doesn't provide the positive sequence phase angle, it provides one phase angle for the system • Detected voltage (in the abc-frame; output not present for the SRF-PLL)

• Detected positive sequence voltage (in the abc-frame; output not present for the SRF- PLL)

• Detected negative-sequence voltage (in the abc-frame; output not present for the SRF- PLL)

The influence of following disturbances are compared:

• A frequency jump

• A phase angle jump

• An amplitude jump

• Harmonics

• Noise

Furthermore, an error of 0.06% on the sample time (T_s) was introduced, to resemble more a realistic system (such an error can be observed in real systems). For a system running at 16.000 Hz this would resemble an error of 39ns on T_s.

Method

The results are compared based on the deviation from the desirable value, so for each output, perfect tracking would result in 0. The time-scale in each figure is 100ms (5 periods of a 50Hz wave). Each column represents one algorithm, as mentioned at the top of each figure. Each row presents a calculated output, as mentioned at the left of each figure.

The first row displays the detected frequency deviation from 50Hz (in Hz). The second row displays the deviation from the detected phase angle (in degrees), for the positive sequence when available. The third row displays the deviation from the three detected phase voltages (in per unit). The fourth row displays the deviation from the three detected positive sequence voltages (in per unit). The fifth row displays the deviation from the three detected negative sequence voltages (in per unit).

The PI controllers used in the methods were tuned in such a way that they have almost exactly the same response to a frequency jump (i.e. the same settling time). This was done to achieve results that are fair to compare. Furthermore, that response was chosen to enhance the ease of comparison and visualization. It therefore not necessarily resembles the way one would tune the PI controllers for the use in a real-time control algorithm.

Frequency jump

At t=0s, the frequency drops by 500 mHz from 50.5Hz to 50Hz. The results are thus a step response to a frequency change. Because the results of the algorithms are very dependent on the tuning, this was also used as a reference: the settling time of the four algorithms was tuned to be as close to each other as possible for this step response on the frequency. The results presented here are therefore not necessarily realistic and could be significantly different in a real-world scenario, but they are suited to be compared to each other in a fair way. These tests have shown that:

The SRF-PLL suffers from oscillations and a small offset on the frequency as well as the phase (30mHz and 0.29° offset, 63mHz and 0.04° peak-to-peak (pp) oscillations) The DDSRF PLL suffers from a small offset on the frequency (31.6mHz) but tracks the phase without error, as well as the other parameters

The DSOGI FLL suffers from oscillations on the voltages (5 to 1.5%) and an offset on the frequency and phase (26mHz and -0.28°)

The TF3LT tracks all parameters perfectly with similar transients as the others.

Amplitude jump At t=0s, the amplitude changes from a balanced scenario to 125% in phase 1, 100% in phase 2 and 30% in phase 3.

These tests have shown that:

• The SRF-PLL cannot track the frequency under imbalance, the frequency and phase angle measurement suffer from huge oscillations (33.7Hz and 19.3° pp).

· The DDSRF PLL suffers from a small offset on the frequency (31.6 mHz).

Furthermore, in tracking the grid voltage, an oscillation equal to the zero sequence can still be observed. Also the transient response on tracking the frequency is remarkably bad (7.4Hz peak).

• The DSOGI FLL suffers from oscillations on the voltages (5 to 1.5%) and an offset on the frequency and phase (26 mHz and -0.28°). Furthermore, in tracking the grid voltage, an oscillation equal to the zero sequence can still be observed. Phase angle jump

At t=0s, the phase angles change from a balanced scenario to a 20° deviation in phase 1, a - 10° deviation in phase 2 and a 30° deviation in phase 3.

These tests have shown that:

• The SRF-PLL cannot track the frequency under imbalance, the frequency and phase angle measurement suffer from huge oscillations (25.7Hz and 15° pp).

• The DDSRF PLL suffers from a small offset on the frequency (31.6 mHz).

Furthermore, in tracking the grid voltage, an oscillation equal to the zero sequence can still be observed. Also the transient response on tracking the frequency is remarkably bad (9.7Hz peak).

• The DSOGI FLL suffers from oscillations on the voltages (5 to 1.5%) and an offset on the frequency and phase (26 mHz and -0.28°). Furthermore, in tracking the grid voltage, an oscillation equal to the zero sequence can still be observed.

• The TF3LT tracks all parameters perfectly with similar transients as the others.

Noise

At t=0s, 10% random white Gaussian noise is added to the three phase voltages (different per phase). The results therefore also include a Signal to Noise Ratio (SNR) to determine the impact of the noise on the measured signal (higher is better). The SNR was calculated as:

SNR = 20 log₁₀ rms(s) — 20 log₁₀ rms (As)

With s the signal, As the deviation from the signal (as plotted) and rms the rms value over the respective time interval (0.1s). The SNR is displayed in dB in the plot.

It is noted that for the negative sequence detection, the SNR is not relevant as there is no signal.

These tests have shown that:

• The SRF-PLL has a low SNR value for the frequency and has deviations up to ±5Hz.

• The DDSRF PLL has a low SNR value for the frequency and has deviations up to ±2Hz.

• The DSOGI FLL suffers from an offset on the frequency and phase (26 mHz and - 0.28°) and has a better frequency detection then the SRF-PLL and DDSRF PLL.

• The TF3LT has an equal or better SNR for all parameters and also the absolute deviations are better or similar than the others.

Harmonics

At t=0s, following harmonics are added: -22.5% 5^th harmonic, -9.58% 7^th harmonic, 6.1% 11^th harmonic, 4.06% 13^th harmonic, -2.26% 17^th harmonic, -1.77% 19^th harmonic, 1.12% 21th harmonic and 0.86% 25^th harmonic. This yields a total harmonic distortion (THD) of 22.3%.

These tests have shown that:

• The SRF-PLL suffers from huge oscillations on the frequency and phase angle (35Hz and 7° pp).

• The DDSRF PLL suffers from huge oscillations on the frequency (16Hz pp) and oscillations on the others as well (3° pp on the phase angle, 20% pp on the grid voltage, 14.5% pp on the positive sequence and 8.4% pp on the negative sequence).

• The DSOGI FLL suffers from oscillations on all components (0.53Hz pp on the frequency, 4.2° pp on the phase angle,17% pp on the grid voltage, 10% pp on the positive sequence and 8% pp on the negative sequence).

• The TF3LT suffers from minor oscillations, using only a filter for the 5^th and 7^th harmonic (0.047Hz pp on the frequency, 0.34° pp on the phase angle, 1% pp on the grid voltage, 0.6% pp on the positive sequence and 0.52% pp on the negative sequence).

Grid measurement An experiment was also conducted for a real grid measurement. These tests have shown that:

• The SRF-PLL suffers from oscillations of about 2Hz pp under the current tuning.

Thus, it would either require a less responsive tuning or a low-pass filter to enable useful results.

· The DDSRF PLL suffers from oscillations of about 0.4Hz pp under the current tuning and quite probably still the same offset as before. Furthermore, the detected negative sequence voltage is too noisy to establish control. Thus, it would either require a less responsive tuning or a low-pass filter to enable useful results.

• The DSOGI FLL suffers from smaller oscillations (10 mHz pp for the high frequency oscillations) and quite probably still the same offset as before. The tracking of the negative sequence is better than the DDSRF but still not quite sinusoidal and hence too noisy to use. Thus, it would fare well with a less responsive tuning.

• The TF3LT according to embodiments of the present invention tracks all parameters with a much better accuracy. It is clearly a much better filtered version of the other measurements. Also, the presumed offset is not seen. The negative sequence voltage is tracked in such a way that it provides useful results for compensation.

Implementation

The grid detection algorithm according to embodiments of the present invention has been implemented on a 3ph+N inverter, including

• A functional and realistic measurement system comparable to the measurement systems used in e.g. PV inverters. No expensive current or voltage measurements are used which would be unavailable on commercial implementations of the inverter.

• The hardware of a commercially available KEB inverter, hence the hardware is entirely in line with what one would expect in an actual implementation.

• The control is implemented on a dual core 2.26 GHz PC with 4 GB of RAM. This is due to the implementation of the control on a rapid prototyping platform and is not related to the present invention. The present invention can be implemented on much smaller and microprocessor or other type of CPU such as an FPGA.

This inverter- system is tested on the grid of an office building with realistic grid voltages and harmonics and is able to inject current into this grid.

Embodiments of the present invention can be implemented in any kind of inverter control scheme useful for a wide range of grid-connected loads/generators, especially to perform grid- supporting actions, such as in:

• Wind turbines and PV-modules

• Heat pumps

• Chargers for electric vehicles

• Active Front End inverters of large industrial applications or of transport

infrastructure

Embodiments of the present invention allow monitoring the grid state and control of inverters which are able to reduce current imbalance in the consumer's grid. This reduces grid losses and can increase the effectively available power as the grid current is more balanced across the phases. It allows an increased voltage protection at the local level to mitigate damage caused by overvoltages.

Aggregators using Demand Side Management of inverter controlled loads and sources can use embodiments of the present invention to give the aggregator a better view on the grid state in the different locations as the grid state can prevent the loads and sources from delivering the services required by the aggregator. Hence the aggregator benefits from accurate knowledge on the grid state as this helps him to estimate the available services.

A Distribution System Operator can use embodiments of the present invention: a) The imbalance reducing currents of the inverter are beneficial for the current balance in the grid.

b) Inverters are able to inject and absorb balanced currents even in presence of imbalanced voltages, thus preventing escalation of the imbalance situation.

c) The possibility to implement an active harmonic filter decreases the harmonic content of the currents. This causes the grid losses due to the skin effect in the cables and iron losses (eddy currents and hysteresis losses at higher frequencies) in the transformer to decrease. The grid losses of the DSO thus decrease. d) Embodiments of the present invention allows the implementation of accurate and fast voltage and frequency services which allow the DSO and TSO to maintain grid stability.

Any of the embodiments of the present invention can be implemented by a digital device with processing capability including one or more microprocessors, processors, microcontrollers, or central processing units (CPU) and/or a Graphics Processing Units (GPU) adapted to carry out the respective functions programmed with software, i.e. one or more computer programs. The software can be compiled to run on any of the microprocessors, processors, microcontrollers, or central processing units (CPU) and/or a Graphics Processing Units (GPU).

Software can be embodied in a computer program product adapted to carry out any of the method described above in an inverter for grid monitoring and having a discrete-time integrator, the discrete-time integrator operating with a sampling time. The discrete-time integrator can be a second or third order discrete integrator.

Software can be embodied in a computer program product adapted to carry out any the relevant functions, when the software is loaded onto respective device or devices, and executed on one or more processing engines such as the microprocessor, ASIC, FPGA, etc. these functions being at least any of the following: hardware-synchronizing the integrator implemented on a processing engine; and/or synchronizing to an actual sampling frequency of the inverter, and/or using the hardware timing period of the processing engine in implementing the discrete integrator, the grid detector detecting and allowing to control positive and negative zero sequence currents.

Software can be embodied in a computer program product adapted to carry out any the relevant functions, when the software is loaded onto respective device or devices, and executed on one or more processing engines such as the microprocessor, ASIC, FPGA, etc. These functions being at least any of the following: an output of the discrete-time integrator is given by an equation: y(n) = y(n-l) plus a function of T_s__act wherein T_s__act is a sampling time being a multiple of the hardware timing period of the processing engine and y(n) is the nth output of the integrator.

Software can be embodied in a computer program product adapted to carry out any the relevant functions, when the software is loaded onto respective device or devices, and executed on one or more processing engines such as the microprocessor, ASIC, FPGA, etc. these functions being at least any of the following:

Implementing the method per phase at a fundamental and harmonic frequencies, and/or providing a feedback signal of the fundamental signal at the output of a discrete SOGI.

Software can be embodied in a computer program product adapted to carry out any the relevant functions, when the software is loaded onto respective device or devices, and executed on one or more processing engines such as the microprocessor, ASIC, FPGA, etc. these functions being at least any of the following: pulse width modulation of the inverter based on a carrier signal having a carrier period which is a multiple of the hardware timing period.

Software can be embodied in a computer program product adapted to carry out any the relevant functions, when the software is loaded onto respective device or devices, and executed on one or more processing engines such as the microprocessor, ASIC, FPGA, etc. these functions being at least any of the following: using a retrieved fundamental frequency in a frequency locked loop.

Software can be embodied in a computer program product adapted to carry out any the relevant functions, when the software is loaded onto respective device or devices, and executed on one or more processing engines such as the microprocessor, ASIC, FPGA, etc. these functions being at least any of the following: determining at least one, any or all of grid frequency, grid voltage, grid frequency or grid voltage per phase, decomposition into positive-, negative- and zero-sequence components, inverter current per phase and decomposition into positive-, negative- and zero-sequence components.

Software can be embodied in a computer program product adapted to carry out any the relevant functions, when the software is loaded onto respective device or devices, and executed on one or more processing engines such as the microprocessor, ASIC, FPGA, etc. these functions being at least any of the following: providing at least one, any or all of local voltage services, frequency droop and inertia emulation and current redistribution between phases. Software can be embodied in a computer program product adapted to carry out any the relevant functions, when the software is loaded onto respective device or devices, and executed on one or more processing engines such as the microprocessor, ASIC, FPGA, etc. these functions being at least any of the following: decomposing measured phase voltages and currents into a vector format which provides information on grid voltages and inverter currents.

Claims

Claims

1. A grid detector for use in an inverter for grid monitoring, comprising a discrete-time integrator, the discrete-time integrator operating with a sampling time, the discrete-time integrator being a hardware-synchronized integrator implemented on a processing engine configured to synchronize to an actual sampling frequency to be applied to the inverter, wherein the hardware timing period of the processing engine is used in implementing the discrete integrator.

2. The grid detector according to claim 1 being adapted to detect and to allow control of positive, negative and zero sequence currents or voltages.

3. A grid detector according to claim 1 or 2, wherein an output of the discrete-time integrator is given by an equation: y(n) = y(n-l) plus a function of T_s__act wherein T_s__act is the sampling time being a multiple of the hardware timing period of the processing engine, and y(n) is the nth output of the integrator.

4. A grid detector according to any of the previous claims, implemented per phase at a fundamental and harmonic frequencies.

5. A grid detector according to any of the previous claims, the discrete-time integrator being a discrete SOGI having a feedback signal of the fundamental signal present at the output of the discrete SOGI.

6. A grid detector according to any of the previous claims, wherein pulse width modulation of the inverter is based on a carrier signal having a carrier period which is a multiple of the hardware timing period.

7. A grid detector according to any of the previous claims, wherein the discrete -time integrator is a second or third order discrete integrator.

8. A grid detector according to any of the previous claims, wherein a retrieved fundamental frequency is used in a frequency locked loop.

9. A grid detector according to any of the previous claims, wherein an error in a calculated grid frequency is less than 50 mHz.

10. An inverter including the grid detector of any of the claims 1 to 9.

11. The inverter according to claim 10, configured to determine at least one, any or all of grid frequency, grid voltage, grid frequency or grid voltage per phase, decomposition into positive-, negative- and zero-sequence components, inverter current per phase and decomposition into positive-, negative- and zero-sequence components.

12. The inverter according to claim 10 or 11, configured to provide at least one, any or all of local voltage services, frequency droop and inertia emulation and current redistribution between phases.

13. The inverter according to any of the claims 10 to 12, further comprising 3 half- or 4 half- bridges.

14. The inverter according to any of the claims 10 to 13, configured to decompose measured phase voltages and currents into a vector format which provides information on grid voltages and inverter currents.

15. The inverter according to any of the claims 10 to 14, configured to control positive, negative and zero sequence components of voltage and current.

16. The inverter according to any of the claims 10 to 15, being a phasor measurement unit.

17. A method for use in an inverter for grid monitoring and having a discrete-time integrator, the discrete-time integrator operating with a sampling time, the method comprising hardware-synchronizing the integrator implemented on a processing engine; synchronizing to an actual sampling frequency of the inverter, wherein the hardware timing period of the processing engine is used in implementing the discrete integrator.

18. The method according to claim 17 the grid detector detecting and allowing to control positive, negative and zero sequence currents or voltages.

19. The method according to claim 17 or 18, wherein an output of the discrete-time integrator is given by an equation: y(n) = y(n-l) plus a function of T_s__act wherein T_s__act is the sampling time being a multiple of the hardware timing period of the processing engine, and y(n) is the nth output of the integrator.

20. The method according to any of the claims 17 to 19, implemented per phase at a fundamental and harmonic frequencies.

21. The method according to any of the claims 17 to 20, providing a feedback signal of the fundamental signal at the output of a discrete SOGI.

22. The method according to any of the claims 17 to 21, comprising pulse width modulation of the inverter based on a carrier signal having a carrier period which is a multiple of the hardware timing period.

23. The method according to any of the claim 17 to 22, wherein the discrete-time integrator is a second or third order discrete integrator.

24. The method according to any of the claims 17 to 23, wherein a retrieved fundamental frequency is used in a frequency locked loop.

25. The method according to any of the claims 17 to 24, wherein an error in a calculated grid frequency is less than 50 mHz.

26. The method according to any of the claims 17 to 25, further comprising determining at least one, any or all of grid frequency, grid voltage, grid frequency or grid voltage per phase, decomposition into positive-, negative- and zero-sequence components, inverter current per phase and decomposition into positive-, negative- and zero-sequence components.

27. The method according to claim 26, further comprising providing at least one, any or all of local voltage services, frequency droop and inertia emulation and current redistribution between phases.

28. The method according to claim 26 or 27, further comprising decomposing measured phase voltages and currents into a vector format which provides information on grid voltages and inverter currents.

29. A computer program product which when executed on a processing engine preforms any of the method steps of the method of any of the claims 17 to 28.

30. A non-transitory signal storage medium storing the computer program product of claim 29.

31. A discrete-time integrator comprising:

a signal generator with a first output of a first signal having a resonant frequency, a first input for a second signal having the resonant frequency and a second input for an error signal in the resonant frequency, means for perturbing the first output dependent upon the error signal, wherein the signal generator has an inverter implemented on a digital processing engine operating with a cycle time, the sampling time of the integrator being a multiple of the actual cycle time of the processing engine wherein positive, negative and zero-sequence components of either the voltage or current are determined.