JP2011229247A - Dc/dc voltage converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DC/DC voltage converter which is made compact and light in weight while achieving efficiency improvement and an increase in output power capacity in comparison with the conventional DC/DC voltage converter, and secures the endurance reliability required in the device by preventing the occurrence of audible noise.SOLUTION: The DC/DC voltage converter includes: a conversion main circuit 2 provided with field effect transistors FET1 to FET4 made of a wide bandgap semiconductor material, an inductor L, an energy transition capacitor C0, and smoothing capacitors C1, C2, such that a pair of FETs of each set with FET1 and FET4 as a set, and FET2 and FET3 as a set has a complementary relation, making on and off opposite; and a control unit 3 for performing on/off control of FET1 to FET4 with a switching frequency that is equal to or greater than the upper limit of an audible frequency.

Description

  The present invention relates to a DC / DC voltage conversion device that converts a DC voltage into a DC voltage that is stepped up or stepped down.

Conventionally, by using the switch-on and switch-off operations of series-connected semiconductor switch elements, the operation of accumulating energy in the inductor, discharging and charging the energy transfer capacitor, and discharging is combined to produce a voltage from DC to DC. An apparatus that performs conversion is used (Patent Document 1, Non-Patent Document 1).
This is a semiconductor switch element and a power device in which a rectifier element is connected in anti-parallel to this, and at the same time, only half of the power devices are turned on (switch-on for semiconductor switch element, forward bias for rectifier element). Thus, the withstand voltage of each power device can be set low. For this reason, the handling voltage of the DC / DC voltage converter can be set to a high voltage while suppressing an increase in conduction loss of each power device due to the high withstand voltage.

Here, a DC / DC voltage converter for converting a voltage after rectifying a commercial AC power supply (AC100V, AC200V), or a DC / DC having an output power capacity of about 4 kW or more for converting a voltage in a range of about 100V to 1000V. In the voltage conversion device, an IGBT (Insulated Gate Bipolar Transistor) made of Si (silicon) as a power device is mainly used as a power device, and Si is also used as a rectifier in the same manner. A PIN diode is used.
Such a DC / DC voltage conversion apparatus may be configured in combination with an inverter that converts direct current into alternating current. For example, an electric drive system for a hybrid vehicle or an electric vehicle shown in FIG. 29, shown in FIG. Examples include a power conversion system for photovoltaic power generation and a power conversion system such as an air conditioner.

  The electric drive system of FIG. 29 includes a battery 41 such as a nickel metal hydride battery, a lithium ion battery, or a fuel cell at primary terminals P1, N1 of the DC / DC voltage converter 1, and an inverter 51a at secondary terminals P2, N2. 51b is connected. Further, a rotating machine 52a is connected to the inverter 51a, and a rotating machine 52b is connected to the inverter 51b. The DC / DC voltage conversion apparatus 1 converts the voltage of the battery 41 on the primary side into a DC / DC voltage and supplies it to the inverters 51a and 51b on the secondary side. The inverter 51a exchanges AC power with the rotating machine 52a, and the inverter 51b exchanges AC power with the rotating machine 52b.

The solar power generation power conversion system in FIG. 30 has a solar cell 42 connected to the primary terminals P1, N1 of the DC / DC voltage converter 1 and an inverter 51c connected to the secondary terminals P2, N2. The inverter 51c is connected to the commercial AC power supply 7 through the filter 6, and the DC / DC voltage converter 1 converts the generated voltage of the primary solar cell 42 into a DC / DC voltage to convert it to a secondary inverter 51c. To supply. The inverter 51c converts the DC voltage into a predetermined commercial AC voltage amplitude and frequency, and supplies it to the commercial power system.
The DC / DC voltage converter used in these systems has a power supply state (for example, a light irradiation amount of a solar battery of a solar power generation system) and a load state (for example, a rotational speed of a motor of an electric drive system of a hybrid vehicle). ), The ratio of the voltage to be converted is adjusted, and the output voltage is controlled.

JP-A-62-53171

Mitsubishi Electric Technical Report Vol. 61 1987 No. 2

However, in the conventional DC / DC voltage converter described above, if a high output power capacity is to be obtained, there is a problem that the apparatus becomes large and heavy due to the occurrence loss of each element and the cooling means thereof.
First, the generated losses of the semiconductor switch element and the rectifying element, which are power devices, have the following components, respectively.
In the semiconductor switch element, a conduction loss and a switching loss due to an ON resistance at the time of current conduction when the switch is on are generated. Switching loss is the voltage and conduction current across the semiconductor switch element during transitional rise and fall when switching from switch-off to switch-on (turn-on) and switching from switch-on to switch-off (turn-off). Is the time integral of the product of

Further, the rectifier element has a conduction loss due to an ON resistance during forward conduction and a reverse recovery loss during reverse recovery. The reverse recovery loss is the time integration of the product of the voltage across the rectifier element and the reverse recovery current in transitional rising and falling changes in the reverse recovery operation.
As described above, the switching loss of the semiconductor switching element and the reverse recovery loss of the rectifying element are generated at the timing of switching, and are proportional to the switching frequency. The increase in the switching frequency leads to the increase in the loss of the power device and the cooling means. Increase in size.
If the switching frequency is constant, the switching speed can be reduced to reduce the switching loss. However, this increases the rate of change of the current conducted to the power device. A large surge voltage is generated by the inductance component Ls parasitic to the conductor, and there is a concern that a high voltage is applied to the power device and the capacitor, resulting in damage.

Second, the fact that the heat sink and inductor using metal materials occupy most of the volume and weight of the entire DC / DC voltage converter is also a factor in increasing the weight.
If the DC / DC voltage converter attempts to obtain a high output power capacity, the cooling heat sink is enlarged in order to mitigate the rise in the semiconductor junction temperature of the power device as the power device loss increases. There is a need.
In addition, as the output power capacity increases, the conduction current of the inductor also increases.On the other hand, the core of the inductor does not saturate even at a large current, and the core is increased to increase the cross-sectional area of the magnetic path in order to obtain a desired inductance value. In order to increase the size and suppress the increase in heat generation of the inductor winding, it is necessary to increase the cross-sectional area of the winding and reduce the resistance of the winding.
Since these cooling heat sinks and inductors use a large amount of metal material, they have a relatively high specific gravity compared to the resin material and have a great influence on the weight.

Thirdly, the conventional DC / DC voltage converter has an audible audible noise.
As described above, since the main loss of the power device increases in proportion to the switching frequency, the switching frequency cannot be set too high. For this reason, an awkward noise was generated due to an alternating current component (ripple component) of the current flowing through the capacitor and the inductor. Since the generation of audible noise impairs the merchantability of DC / DC voltage converters, it is necessary to take measures such as attaching a vibration absorbing member to suppress noise propagation to the outside and adopting a core material with low magnetostriction for the inductor. was there. This further causes a side effect of increasing the cost and weight of the DC / DC voltage converter.

  The present invention has been made in order to solve the above-described conventional problems at the same time. While achieving improved efficiency and increased output power capacity as compared with the conventional DC / DC voltage converter, An object of the present invention is to provide a DC / DC voltage conversion device that is reduced in size and weight, prevents the generation of audible noise, and ensures the durability and reliability required for the device.

A DC / DC voltage conversion apparatus according to the present invention includes a conversion main circuit and a control unit, and performs DC voltage conversion between a primary side voltage and a secondary side voltage higher than the primary side voltage. A DC voltage converter,
The conversion main circuit is connected between a primary-side positive-side terminal and a negative-side terminal, and is connected between a primary-side smoothing capacitor that smooths the primary-side voltage, and a secondary-side positive-side terminal and a negative-side terminal. The secondary side smoothing capacitor for smoothing the secondary side voltage, the energy transfer capacitor and inductor for storing and releasing energy, and the semiconductor unit capable of on / off switching operation and reverse conduction operation are provided with 2n (n Is an integer greater than or equal to 2) and is connected in series to each other and includes a power module formed by connecting between a positive side terminal and a negative side terminal on the secondary side,
The control unit divides 2n semiconductor units into two pairs of n pairs, and has a complementary relationship in which the on / off of the pair of semiconductor units constituting each pair is opposite to each other, and the inductor Control so that the AC component of the current flowing through the n unit is n times the switching frequency for on / off control of the semiconductor unit, and the frequency exceeds the upper limit of the audible frequency,
The energy transfer capacitor is connected between a terminal closest to the secondary positive electrode terminal and a terminal closest to the secondary negative electrode terminal in each pair of semiconductor units,
The inductor is a pair of semiconductor units that are directly connected to each other, and is connected between the connection point and the positive terminal on the primary side.

As described above, in the DC / DC voltage converter according to the present invention, in particular, the control unit divides n semiconductor units into two pairs of n, and a pair of semiconductors constituting each pair. The unit is controlled so that the ON / OFF of the unit is opposite to each other, and the AC component of the current flowing through the inductor is higher than the upper limit of the audible frequency by n times the switching frequency for ON / OFF control of the semiconductor unit. To do.
Therefore, as the frequency of the current flowing through the inductor increases, the AC component (ripple component) can be reduced or the required inductance can be reduced. In any case, the inductor loss is reduced and the size is reduced. As a result, the cooling heat sink can be reduced in size.
Furthermore, since the frequency of the current flowing through the inductor is more than twice the switching frequency and more than the upper limit of the audible frequency, the frequency of the noise generated by the inductor is reduced to the audible frequency without substantially increasing the switching loss of the semiconductor unit. It is possible to prevent the generation of audible noise above the upper limit.

1 is an overall configuration diagram of a system of a DC / DC voltage converter according to the present invention. It is explanatory drawing which shows the flow of the electric power of the DC / DC voltage converter by this invention. It is a figure which shows the connection structure of the conversion main circuit of Embodiment 1 by this invention. It is a wave form diagram explaining the operation | movement at the time of pressure | voltage rise (on duty less than 50%) of Embodiment 1 by this invention. It is a wave form diagram explaining the operation | movement at the time of pressure | voltage rise (on-duty 50% or more) of Embodiment 1 by this invention. It is a wave form diagram explaining the operation | movement at the time of pressure | voltage fall (less than 50% of on-duty) of Embodiment 1 by this invention. It is a wave form diagram explaining the operation | movement at the time of pressure | voltage fall (ON duty 50% or more) of Embodiment 1 by this invention. It is a figure which shows the frequency characteristic of the impedance of the capacitor of Embodiment 1 by this invention. It is a block diagram which shows the structure of the control unit and conversion main circuit of Embodiment 1 by this invention. It is a characteristic view which shows the relationship between on-duty and DC / DC voltage conversion ratio by this invention. It is a figure which shows the connection structure different from FIG. 3 of the conversion main circuit of Embodiment 1 by this invention. It is an external view of the DC / DC voltage converter of Embodiment 2 by this invention. It is explanatory drawing which shows typically the cooling path | route of the DC / DC voltage converter of Embodiment 2 by this invention. It is a figure which shows the connection structure of the conversion main circuit which has the parasitic inductance component of Embodiment 2 by this invention. It is a block diagram which shows the structure of the control unit and conversion main circuit of Embodiment 3 by this invention. It is a block diagram which shows the detailed structure of the gate drive circuit of Embodiment 3 by this invention. It is a figure explaining the selection method of the switch-off circuit of Embodiment 3 by this invention. It is a wave form diagram explaining the turn-off operation | movement of the field effect transistor of Embodiment 3 by this invention. It is a figure which shows the connection structure of the conversion main circuit of Embodiment 4 by this invention. It is a block diagram which shows the structure of the control unit of Embodiment 4 by this invention. It is explanatory drawing which shows the relationship between the switching frequency of Embodiment 4 by this invention, and the emitted-heat amount of an inductor, a capacitor, and a power semiconductor unit. It is a block diagram which shows the detailed structure of the frequency regulator of Embodiment 4 by this invention. It is a flowchart explaining the process of the selection process means of Embodiment 4 by this invention. It is a figure which shows the connection structure of the conversion main circuit of Embodiment 5 by this invention. It is a wave form diagram explaining the operation | movement at the time of pressure | voltage rise (less than on-duty 100/3%) of Embodiment 5 by this invention. It is a wave form diagram explaining the operation | movement at the time of the pressure | voltage rise (on-duty 100/3% or more and less than 100x (2/3)%) of Embodiment 5 by this invention. It is a wave form diagram explaining the operation | movement at the time of pressure | voltage rise (on-duty 100x (2/3)% or more) of Embodiment 5 by this invention. It is a figure which shows the further modification of the connection structure of the conversion main circuit by this invention. It is a block diagram of the electric drive system for motor vehicles using a DC / DC voltage converter. It is a block diagram of the power conversion system for solar power generation using a DC / DC voltage converter.

Embodiment 1 FIG.
Hereinafter, the DC / DC voltage converter according to Embodiment 1 of the present invention will be described with reference to FIGS.
FIG. 1 is a block diagram showing the overall configuration of the system according to the present embodiment. The DC / DC voltage conversion apparatus 1 includes a conversion main circuit 2 and a control unit 3. The DC / DC voltage converter 1 includes a positive side terminal P1 and a negative side terminal N1 on the primary side of the conversion main circuit 2 as connection terminals of the power path, and a positive side terminal P2 and a negative side terminal N2 on the secondary side. .
FIG. 2 schematically illustrates voltage conversion and power flow between the primary side and the secondary side of the DC / DC voltage conversion apparatus 1 according to this embodiment. A DC power supply 4 is connected to terminals P1 and N1 on the primary side of the DC / DC voltage converter 1, and an electric device 5 is connected to terminals P2 and N2 on the secondary side.
In FIG. 2, the DC power supply 4 is assumed to be a combination of a secondary battery such as a lithium ion battery, a nickel metal hydride battery, or a lead battery, as well as a power source such as a solar battery or a fuel cell combined with an electric double layer capacitor or a secondary battery. Is done. The electrical device 5 is a device that includes an electrical load and is combined with a power generation device or a power storage device.

The DC / DC voltage conversion apparatus 1 performs voltage conversion on the primary side terminal voltage V1 and the secondary side terminal voltage V2 under the relationship of V1 ≦ V2, and exchanges power with each other. Here, as shown in FIG. 2A, when the DC power supply 4 is in a discharging operation and the electric device 5 is in a power consuming operation, the DC / DC voltage converting apparatus 1 applies a voltage in the direction from the primary side to the secondary side. Boost the power and send power. In addition, as shown in FIG. 2B, when the DC power supply 4 is in a charging operation and the electric device 5 is in a power supply operation, the DC / DC voltage conversion device 1 applies a voltage from the secondary side to the primary side. Step down the power to feed in.
At this time, the voltage conversion is performed by controlling on / off of a semiconductor switch element in a power semiconductor unit (described later) provided in the conversion main circuit 2 in accordance with the gate drive signal 8 output from the control unit 3.

Here, the operation content of the DC / DC voltage converter 1 will be described with reference to FIGS. 3 to 11. FIG. 3 is a diagram showing circuit wiring of the conversion main circuit 2, in which four power semiconductor units are connected in series to supply boosted power from the primary side to the secondary side, and from the secondary side to the primary side. Supply voltage to step-down.
The conversion main circuit 2 includes a primary-side smoothing capacitor C1 that smoothes the primary-side terminal voltage V1, a secondary-side smoothing capacitor C2 that smoothes the secondary-side terminal voltage V2, and an inductor L that stores and discharges energy. And an energy transfer capacitor C0 and four power semiconductor units.

  In the example of FIG. 3, the first to fourth power semiconductor units employ field effect transistors FET4, FET3, FET2, and FET1 each including a parasitic diode. Note that these field effect transistors are formed of a wide band gap semiconductor whose band gap is larger than that of silicon. This will be described in detail later.

Next, details of the connection of the conversion main circuit 2 will be described.
Both terminals of the smoothing capacitor C1 are connected to a primary side positive terminal P1 and a negative side terminal N1 on the primary side of the conversion main circuit 2, and the negative side terminal N1 is also a secondary side negative side terminal N2 of the conversion main circuit 2 On connection, it is grounded as Vcom. The positive terminal P1 is connected to one terminal of the smoothing capacitor C1 and one terminal of the inductor L, and the other terminal of the smoothing capacitor C1 is connected to the negative terminal N1.
Further, both terminals of the smoothing capacitor C2 are connected to the positive side terminal P2 and the negative side terminal N2 on the secondary side of the conversion main circuit 2.

The drain terminal of the FET 4 is connected to the positive terminal P2 on the secondary side of the conversion main circuit 2, the source terminal is connected to the drain terminal of the FET 3, the source terminal of the FET 3 is connected to the drain terminal of the FET 2, and the source terminal of the FET 2 is connected to the drain terminal of the FET 1. , FET1 has a source terminal connected to a secondary negative terminal N2, respectively.
The energy transfer capacitor C0 has one terminal connected to the connection point between the FET 4 and the FET 3, and the other terminal connected to the connection point between the FET 2 and the FET 1.

  In this example, as mentioned in the explanation of the operation at the later stage, FET1 and FET4 and FET2 and FET3 are each a pair, and the pair of FETs forming each pair is on / off controlled so as to have a so-called complementary relationship. The Therefore, the energy transfer capacitor C0 is a terminal closest to the drain terminal of the FET 3 which is the terminal closest to the secondary positive terminal P2 and the secondary negative terminal N2 in the pair of FET2 and FET3. It can be said that it is connected between the source terminal of FET2.

  As shown in FIG. 3, the inductor L has one terminal connected to the primary positive terminal P1 on the primary side of the conversion main circuit 2, and the other terminal directly connected to each other, which is the pair of FETs described above. It is connected to the connection point between FET3 and FET2.

  From the control unit 3 not shown in FIG. 3, signals for controlling on / off of the field effect transistor as the gate drive signal 8 correspond to FET4, FET3, FET2, and FET1, respectively, Gate4, Gate3, Gate2, and Gate1. A signal is connected from the FET 4 to the gate electrode of the FET 1 as a signal. The FET 4 performs a switching operation according to a voltage change of the Gate 4 signal, the FET 3 of the Gate 3 signal, the FET 2 of the Gate 2 signal, and the FET 1 of the Gate 1 signal.

Next, the operation of the conversion main circuit 2 will be described.
As described above, the DC / DC voltage conversion apparatus 1 performs voltage conversion so as to step up the voltage from the primary side to the secondary side or step down the voltage from the secondary side to the primary side. The step-up operation and the step-down operation are controlled by adjusting the timing of the on / off operation of the field effect transistor using Gate 4, Gate 3, Gate 2, and Gate 1 which are gate drive signals 8.
The voltage conversion control by the gate drive signal 8 will be described separately for the step-up operation and the step-down operation.

During boost operation:
1) On duty less than 50%:
However, the on-duty is the value for the Gate1 signal and the Gate2 signal, and the Gate3 signal and the Gate4 signal are complementary to the Gate1 signal and the Gate2 signal, respectively. , Gate2 signal on-duty).

FIG. 4 shows a waveform when the on-duty of the gate drive signal is less than 50% during the boosting operation. 4A shows the gate drive signal, FIG. 4B shows the inductor current IL, and FIG. 4C shows the switching mode and its switching timing.
The inductor current IL has a positive polarity in which the inductor L flows in the direction from the connection terminal on the positive terminal P1 side to the connection terminal on the FET3 side.
In FIG. 4A, FET1 is turned on when the Gate1 signal is high, and FET2 is turned on when the Gate2 signal is high, and a current flows from the drain to the source.

The FET3 is turned on when the Gate3 signal is high, and the FET4 is turned on when the Gate4 signal is high. However, during the step-up operation, current flows from the source to the drain instead of the parasitic diode inherent in the FET3 and FET4.
As a result, there is an advantage that the voltage drop in the part is small, the loss generated is reduced correspondingly, and the efficiency is improved. This advantage is an effect obtained when the field effect transistor FET is employed in the power semiconductor unit in the control system according to the present invention.

Here, the Gate1 signal and the Gate4 signal are complementary signals whose logics of high and low are opposite to each other. When the Gate1 signal is high, the Gate4 signal is low, and when the Gate1 signal is low, the Gate4 signal is high. However, when switching between high and low logic, a blocking time (dead time) is provided so that both are not turned on at the same time due to a response delay of the switching operation of the field effect transistor.
Similarly, the Gate2 signal and the Gate3 signal are complementary signals in which high and low logics are opposite to each other, and the Gate1 signal and the Gate2 signal have a phase difference of 180 degrees. That is, the gate drive signal 8 has two pairs of signals as complementary signals, and the phase difference between them is equal.

  At this time, the high and low logic combinations of the gate drive signals from Gate 1 to Gate 4 are classified into three switching modes B, C, and D, and are switched in the order of B → D → C → D → B.

In switching mode B, FET1 and FET3 are on, FET2 and FET4 are off,
The current flows in the path of the positive terminal P1, the inductor L, the FET 3, the energy transfer capacitor C0, the FET 1, and the negative terminal N1, and the energy is stored in the inductor L and the energy transfer capacitor C0. The electric device 5 is applied with the voltage across the smoothing capacitor C2 stored in the operation described later, and is supplied with energy from the smoothing capacitor C2.
Since FET1 and FET3 are turned on and current is conducted, the potential of the FET1 side connection terminal of the energy transfer capacitor C0 is approximately Vcom = 0, and the potential of the FET3 side connection terminal is approximately VL. Therefore, the voltage VL at the connection terminal on the FET3 side of the inductor L = the voltage Vc0 across the energy transfer capacitor C0.

In switching mode D, FET3 and FET4 are on, FET1 and FET2 are off,
A current flows through the path of the positive terminal P1, the inductor L, the FET 3, the FET 4, the positive terminal P2, the electrical device 5, and the negative terminal N2, and the energy accumulated in the inductor L is released.
In addition, since the voltage VL is approximately V2 when current flows between the FET3 and the FET4, the difference between the voltage of the FET3 side connection terminal of the inductor L and the voltage of the positive side terminal P1 side connection terminal is (V1−V2). It becomes negative, and the inductor current IL decreases toward IL <0.

In switching mode C, FET2 and FET4 are on, FET1 and FET3 are off,
The current flows through the path of the positive terminal P1, the inductor L, the FET 2, the energy transfer capacitor C0, the FET 4, the positive terminal P2, the electrical device 5, and the negative terminal N2, and the energy is stored in the inductor L. Released from the transfer capacitor C0. At the same time, a current also flows through the smoothing capacitor C2 to store energy.
Since FET2 and FET4 are turned on and current is conducted, the potential of the FET2 side connection terminal of the energy transfer capacitor C0 is about VL, and the potential of the FET4 side connection terminal is about V2. Therefore, the voltage VL = V2−Vc0 at the FET3 side connection terminal of the inductor L.

  Here, since the on-duty of the Gate1 signal and the Gate2 signal is equal, the voltages VL in the switching modes B and C are equal in terms of time average and Vc0 = (V2−Vc0). Therefore, the voltage Vc0 across the energy transfer capacitor C0 is V2 / 2, which is ½ times the secondary terminal voltage V2.

To summarize the above, the voltage VL at the FET3 side connection terminal of the inductor L is:
In switching mode B, VL = Vc0 = V2 / 2,
In switching mode C, VL = (V2−Vc0) = V2 / 2,
In switching mode D, VL = V2
It becomes.
Accordingly, the potential difference between both ends of the inductor L, the switch-on time ton and the switch-off time toff of the FET1 and FET2 are expressed by the following relationship.

Switching mode B, C: L · ILrpl = ton · (V1−V2 / 2) ··· (1a) Switching mode D: L · ILrpl = −toff · (V1−V2) ·· (1b) where L is The inductance of the inductor L, ILrpl, indicates the amplitude of the ripple current component (alternating current component) flowing through the inductor L.

  Since the left sides of Formula (1a) and Formula (1b) are equal, the following relationship is established.

  ton · (V1−V2 / 2) = toff · (V2−V1) (2)

  The above formula (2) can be summarized with respect to the primary terminal voltage V1 and the secondary terminal voltage V2 as follows.

(V2 / V1) = (ton + toff) / (ton + toff-ton + ton / 2) = 1 / (1-ton / T) (3)
However, ton + toff = T / 2

In the above equation (3), the period T indicates a period in which the switching mode B → D → C → D → B is switched in order and makes a round. Within the period T, the ton period is twice and the toff period is It is included twice. Ton + toff is T / 2.
Further, V2 / V1 on the left side of the expression (3) is a ratio between the primary side voltage V1 and the secondary side voltage V2 of the DC / DC voltage converter 1, and is a DC / DC voltage conversion ratio.
In the operation in which the on-duty of the gate drive signal shown in FIG. 4 is less than 50%, ton / T <0.5, and when applied to the equation (3), the DC / DC voltage conversion ratio is less than 2. . Therefore, V2 <(V1 × 2).

  From these, in the switching modes B and C, the voltage VL = V2 / 2 <V1 of the FET3 side connection terminal of the inductor L, and the voltage of the connection terminal of the inductor L on the positive side terminal P1 side is V1. Therefore, the potential difference between both ends of the inductor L becomes positive with respect to VL, and the inductor current IL increases in the positive direction.

As described above, in switching mode B → D → C → D → B,
In the switching modes B and C, the inductor current IL changes from the state of IL ≧ 0 further in the positive direction,
In the switching mode D, the inductor current IL changes toward the state of IL <0.
From this, increase and decrease of the inductor current IL are repeated twice in the T / 2 period over the switching period T of the field effect transistor. That is, an alternating current having a frequency twice that of the switching frequency of the field effect transistor is conducted to the inductor L.

2) When the on-duty is 50% or more:
Next, a case where the on-duty of the gate drive signal is 50% or more during the boosting operation will be described. FIG. 5 shows operation waveforms at that time. (A) is a gate drive signal, (b) is an inductor current IL, and (c) is a switching mode and its switching timing.
5A, as in FIG. 4A, FET1 is turned on when the Gate1 signal is high, and FET2 is turned on when the Gate2 signal is high, and a current flows from the drain toward the source.
The FET3 is turned on when the Gate3 signal is high, and the FET4 is turned on when the Gate4 signal is high. However, during the step-up operation, current flows from the source to the drain instead of the parasitic diode inherent in the FET3 and FET4.

  The Gate1 signal and the Gate4 signal, and the Gate2 signal and the Gate3 signal are complementary signals, respectively, and when the logic is switched between high and low, a blocking time (dead) is set so that both are not turned on simultaneously due to a response delay of the switching operation of the field effect transistor. Time). The phase difference between the Gate1 signal and the Gate2 signal is 180 degrees.

  At this time, the high and low logic combinations of the gate drive signals from Gate 1 to Gate 4 are classified into three types of switching modes A, B, and C, and are switched in the order of A → B → A → C → A.

First, in switching mode A, FET1 and FET2 are on, FET3 and FET4 are off,
The current flows through the path of the positive terminal P1, the inductor L, the FET 2, the FET 1, and the negative terminal N1, and energy is stored in the inductor L.
The voltage VL is such that a current flows between FET1 and FET2 and approximately Vcom = 0. Therefore, the difference between the voltage VL at the FET2 side connection terminal of the inductor L and the voltage at the positive terminal P1 side is (V1). −0) becomes positive, and the inductor current IL increases in the positive direction.

In switching mode B, FET1 and FET3 are on, FET2 and FET4 are off,
The current flows through the path of the positive terminal P1, the inductor L, the FET 3, the energy transfer capacitor C0, the FET 1, and the negative terminal N1, and the energy is discharged from the inductor L and stored in the energy transfer capacitor C0. The electric device 5 is applied with the voltage across the smoothing capacitor C2 stored in the operation described later, and is supplied with energy from the smoothing capacitor C2.
Since FET1 and FET3 are turned on and current is conducted, the potential of the FET1 side connection terminal of the energy transfer capacitor C0 is approximately Vcom = 0, and the potential of the FET3 side connection terminal is approximately VL.
Therefore, the voltage VL at the FET3 side connection terminal of the inductor L becomes Vc0.

In switching mode C, FET2 and FET4 are on, FET1 and FET3 are off, and the current is positive terminal P1 → inductor L → FET2 → capacitor C0 for energy transfer → FET4 → positive terminal P2 → electric equipment 5 → negative electrode. The energy flows through the path of the side terminal N2, and energy is discharged from the inductor L and the energy transfer capacitor C0.
Since FET2 and FET4 are turned on and current is conducted, the potential of the FET2 side connection terminal of the energy transfer capacitor C0 is approximately VL, and the potential of the FET4 side connection terminal is approximately V2.
Therefore, the voltage VL = V2−Vc0 of the connection terminal of the inductor L on the FET3 side.

  Similarly to the above-described operation with an on-duty of less than 50%, since the on-duty of the Gate1 signal and the Gate2 signal is equal, the voltages VL in the switching modes B and C are equal in terms of time average Vc0 = (V2−Vc0) It becomes the relationship. Therefore, the voltage Vc0 across the energy transfer capacitor C0 is V2 / 2, which is ½ times the secondary terminal voltage V2.

To summarize the above, the voltage VL at the FET3 side connection terminal of the inductor L is:
In switching mode A, VL = 0,
In switching mode B, VL = Vc0 = V2 / 2,
In switching mode C, VL = (V2−Vc0) = V2 / 2
It becomes.
Accordingly, the potential difference between both ends of the inductor L, the switch-on time ton and the switch-off time toff of the FET1 and FET2 are expressed by the following relationship.

Switching mode A: L.ILrpl = (ton-toff) /2.V1 .. (4a)
Switching modes B and C: L · ILrpl = −toff · (V1−V2 / 2)
.. (4b)

  Since the left sides of the equations (4a) and (4b) are equal, the following relationship is established.

  (Ton-toff) /2.V1=-toff. (V1-V2 / 2) (5)

  The above equation (5) can be summarized with respect to the primary terminal voltage V1 and the secondary terminal voltage V2 as follows.

(V2 / V1) = (ton + toff) / toff = 1 / (1-ton / T)
(6)
However, ton + toff = T

In the above equation (6), the period T indicates a period in which the switching mode A → B → A → C → A is switched in order, and the ton period is once in the period T, and the toff period. Is included once. Ton + toff = T.
Equation (6) is equivalent to Equation (3), that is, whether the on-duty is less than 50% or more than 50%, DC / DC continuously according to the change in on-duty. The voltage conversion ratio is adjusted.
In the operation in which the on-duty of the gate drive signal shown in FIG. 5 is 50% or more, ton / T ≧ 0.5, and when applied to Equation (6), the DC / DC voltage conversion ratio is 2 or more. Become. Therefore, V2 ≧ (V1 × 2).

  From these, in the switching modes B and C, the voltage VL = V2 / 2 ≧ V1 of the FET3 side connection terminal of the inductor L, and the voltage of the positive terminal P1 side connection terminal of the inductor L is V1. Therefore, the potential difference between both ends of the inductor L with respect to VL becomes negative, and the inductor current IL decreases in the negative direction.

As described above, in the switching mode A → B → A → C → A,
In switching mode A, the inductor current IL changes so as to further increase in the positive direction from the state of IL ≧ 0,
In the switching modes B and C, the inductor current IL changes toward the state of IL <0.
From this, increase and decrease of the inductor current IL are repeated twice in the T / 2 period over the switching period T of the field effect transistor. That is, even when the on-duty of the gate drive signal is 50% or more, an alternating current having a frequency twice that of the switching frequency of the field effect transistor is conducted to the inductor L.

Next, the step-down operation will be described.
During step-down operation:
1) On duty less than 50%:
In the step-down operation, as shown in FIG. 2 (b), the electric power generated by the electric device 5 connected to the secondary side of the DC / DC converter 1 is DC / DC from V2 to V1 in the relationship of voltage V1 ≦ voltage V2. The voltage is converted and recovered by the DC power supply 4.
FIG. 6 illustrates a waveform in which the on-duty of the gate drive signal is less than 50% during the step-down operation. 6A shows the gate drive signal, FIG. 6B shows the inductor current IL, and FIG. 6C shows the switching mode and the switching timing thereof.

6A, when the Gate3 signal is high, the FET3 is turned on, and when the Gate4 signal is high, the FET4 is turned on, and a current flows from the drain toward the source. The FET1 is turned on when the Gate1 signal is high, and the FET2 is turned on when the Gate2 signal is high. However, during the step-down operation, a current flows from the source to the drain instead of the parasitic diode inherent in the FET1 and FET2.
The gate drive signal of FIG. 6A, the switching mode of FIG. 6C, and the switching timing thereof are shown in FIGS. 4A and 4C when the on-duty of the gate drive signal is less than 50% during the boost operation. Same as c).
That is, the gate drive signal has the same waveform during the step-down operation and the step-up operation, and the combination of high and low logic of the gate drive signals from Gate 1 to Gate 4 is in the order of switching mode B → D → C → D → B. Switch.

In switching mode D, FET3 and FET4 are on, FET1 and FET2 are off,
The current flows through the path of the positive terminal P 2 → FET 4 → FET 3 → inductor L → positive terminal P 1 → DC power supply 4 → negative terminal N 1, and energy is stored in the inductor L. From the direction of current conduction, the polarity of the inductor current IL is negative.
In addition, since FET3 and FET4 are turned on and current is conducted, the voltage VL is approximately V2.
Therefore, the difference between the voltage at the connection terminal on the FET3 side of the inductor L and the voltage at the connection terminal on the positive terminal P1 side becomes negative at (V1−V2), and the inductor current IL decreases from the state of IL <0 in the negative direction. To increase.

In switching mode B, FET1 and FET3 are on, FET2 and FET4 are off,
A current flows in the path of energy transfer capacitor C0 → FET3 → inductor L → positive electrode side terminal P1 → DC power supply 4 → negative electrode side terminal N1 → FET1, and energy is discharged from the inductor L and the energy transfer capacitor C0. Further, the power generation voltage V2 of the electric device 5 is applied to the smoothing capacitor C2, and energy is supplied to the smoothing capacitor C2.
Since FET1 and FET3 are turned on and current is conducted, the potential of the FET1 side connection terminal of the energy transfer capacitor C0 is approximately Vcom = 0, and the potential of the FET3 side connection terminal is approximately VL.
Therefore, the voltage VL at the FET3 side connection terminal of the inductor L becomes Vc0.

In switching mode C, FET2 and FET4 are on, FET1 and FET3 are off,
Current flows in the path of positive terminal P2 → FET4 → energy transfer capacitor C0 → FET2 → inductor L → positive terminal P1 → DC power supply 4 → negative terminal N1 and energy is discharged from the inductor L for energy transfer. Stored in capacitor C0.
Since FET2 and FET4 are turned on and current is conducted, the potential of the FET2 side connection terminal of the energy transfer capacitor C0 is approximately VL, and the potential of the FET4 side connection terminal is approximately V2.
Therefore, the voltage VL = V2−Vc0 of the connection terminal of the inductor L on the FET3 side.

Here, since the on-duty of the Gate3 signal and the Gate4 signal is equal, the voltages VL in the switching modes B and C are equal in terms of time average, and the relationship is Vc0 = (V2-Vc0).
Therefore, the voltage Vc0 across the energy transfer capacitor C0 becomes V2 / 2, which is ½ times the secondary terminal voltage V2, as in the boost operation.

To summarize the above, the voltage VL at the FET3 side connection terminal of the inductor L is:
In switching mode B, VL = Vc0 = V2 / 2,
In switching mode C, VL = (V2−Vc0) = V2 / 2,
In switching mode D, VL = V2
It becomes.
Accordingly, the potential difference between both ends of the inductor L and the switch-on time ton and the switch-off time toff of the FET1 and FET2 are expressed by equations (1a) and ( Same as 1b).
For this reason, the relationship of Formula (2) and Formula (3) is similarly established.
That is, the voltage conversion ratio (V2 / V1) of the DC / DC voltage conversion apparatus 1 is expressed by Expression (3).

  In the operation in which the on-duty of the gate drive signal in FIG. 6 is less than 50%, ton / T <0.5, and the DC / DC voltage conversion ratio is less than 2 when applied to Equation (4). Therefore, V2 <(V1 × 2). That is, the primary side terminal voltage V1 is stepped down to a voltage that is higher than ½ times the secondary side terminal voltage V2 and lower than 1 time.

  From these, in the switching modes B and C, the voltage VL = V2 / 2 <V1 of the FET3 side connection terminal of the inductor L, and the voltage of the connection terminal of the inductor L on the positive side terminal P1 side is V1. Therefore, the potential difference between both ends of the inductor L becomes positive with respect to VL, and the inductor current IL decreases in the positive direction. That is, IL changes from the state where the inductor current IL <0 during the step-down operation toward the state where IL ≧ 0.

As described above, when switching mode B → D → C → D → B,
In switching modes B and C, the inductor current IL changes toward a state where IL ≧ 0,
In the switching mode D, the inductor current IL changes so as to further increase in the negative direction from the state of IL <0.
From this, increase and decrease of the inductor current IL are repeated twice in the T / 2 period over the switching period T of the field effect transistor. That is, as in the step-up operation, an alternating current having a frequency twice that of the switching frequency of the field effect transistor is conducted to the inductor L.

2) When the on-duty is 50% or more:
Next, a case where the on-duty of the gate drive signal is 50% or more during the step-down operation will be described. FIG. 7 shows operation waveforms at that time, where (a) is a gate drive signal, (b) is an inductor current IL, and (c) is a switching mode and its switching timing.
In FIG. 7A, the FET 3 is turned on when the Gate 3 signal is high, and the FET 4 is turned on when the Gate 4 signal is high, and a current flows from the drain to the source.
The FET1 is turned on when the Gate1 signal is high, and the FET2 is turned on when the Gate2 signal is high. However, during the step-down operation, a current flows from the source to the drain instead of the parasitic diode inherent in the FET1 and FET2.

The gate drive signal shown in FIG. 7A, the switching mode shown in FIG. 7C, and the switching timing thereof are shown in FIGS. ).
That is, the gate drive signal has the same waveform during the step-down operation and the step-up operation, and the combination of high and low logic of the gate drive signals from Gate 1 to Gate 4 is in the order of switching modes A → B → A → C → A. Switch.

First, in switching mode C, FET2 and FET4 are on, FET1 and FET3 are off,
The current flows through the path of the positive terminal P2, the FET 4, the energy transfer capacitor C0, the FET 2, the inductor L, the DC power supply 4, and the negative terminal N1, and the energy is stored in the inductor L and the energy transfer capacitor C0.
Since FET2 and FET4 are turned on and current is conducted, the potential of the FET2 side connection terminal of the energy transfer capacitor C0 is approximately VL, and the potential of the FET4 side connection terminal is approximately V2.
Therefore, the voltage VL = V2−Vc0 of the connection terminal of the inductor L on the FET3 side.

In switching mode B, FET1 and FET3 are on, FET2 and FET4 are off,
A current flows in the path of energy transfer capacitor C0 → FET3 → inductor L → positive electrode side terminal P1 → DC power supply 4 → negative electrode side terminal N1 → FET1 and energy is stored in the inductor L and discharged from the energy transfer capacitor C0. The
Since FET1 and FET3 are turned on and current is conducted, the potential of the FET1 side connection terminal of the energy transfer capacitor C0 is approximately Vcom = 0, and the potential of the FET3 side connection terminal is approximately VL.
Therefore, the voltage VL at the FET3 side connection terminal of the inductor L becomes Vc0.

In switching mode A, FET1 and FET2 are on, FET3 and FET4 are off,
The current flows in the path of inductor L → positive terminal P1 → DC power supply 4 → negative terminal N1 → FET 1 → FET 2, and energy is released from inductor L.
The voltage VL is such that a current is conducted between FET1 and FET2, and Vcom = 0, so that the difference between the voltage VL at the FET2 side connection terminal of the inductor L and the voltage at the positive terminal P1 side connection terminal is V1. The inductor current IL changes from the state of IL <0 toward the positive direction.

Similarly to the above-described operation in which the on-duty is less than 50%, since the on-duty of the Gate3 signal and the Gate4 signal is equal, the voltages VL in the switching modes B and C are equal in time average, and Vc0 = (V2−Vc0). ).
Therefore, as in the step-up operation, the voltage Vc0 across the energy transfer capacitor C0 is V2 / 2, which is ½ times the secondary terminal voltage V2.

To summarize the above, the voltage VL at the FET3 side connection terminal of the inductor L is:
In switching mode A, VL = Vcom = 0,
In switching mode B, VL = Vc0 = V2 / 2,
In switching mode C, VL = (V2−Vc0) = V2 / 2
It becomes.
Accordingly, the relationship between the potential difference between both ends of the inductor L and the switch-on time ton and the switch-off time toff of the FET1 and FET2 is an expression (4a) showing the relationship when the on-duty of the gate drive signal during the boosting operation is 50% or more. , (4b). For this reason, the relationship of Formula (5) and Formula (6) is formed similarly.
That is, the voltage conversion ratio (V2 / V1) of the DC / DC voltage conversion apparatus 1 is expressed by Expression (6).

  In the operation in which the on-duty of the gate drive signal in FIG. 7 is 50% or more, ton / T ≧ 0.5, and when applied to Expression (6), the DC / DC voltage conversion ratio is 2 or more. Therefore, V2 ≧ (V1 × 2). That is, the primary side terminal voltage V1 is stepped down to a voltage lower than ½ times the secondary side terminal voltage V2.

  From these, in the switching modes B and C, the voltage VL = V2 / 2 ≧ V1 of the FET3 side connection terminal of the inductor L, and the voltage of the positive terminal P1 side connection terminal of the inductor L is V1. Therefore, the potential difference between both ends of the inductor L with respect to VL becomes negative, and the inductor current IL increases in the negative direction. That is, the voltage changes from the state where the inductor current IL <0 during the step-down operation further increases in the negative direction.

As described above, when switching mode A → B → A → C → A,
In switching mode A, the inductor current IL changes toward a state where IL ≧ 0,
In the switching modes B and C, the inductor current IL changes so as to increase further in the negative direction from the state of IL <0.
From this, increase and decrease of the inductor current IL are repeated twice in the T / 2 period over the switching period T of the field effect transistor. That is, even when the on-duty of the gate drive signal is 50% or more, an alternating current having a frequency twice that of the switching frequency of the field effect transistor is conducted to the inductor L.

As described above, the AC current of twice the frequency is conducted to the inductor L with respect to the switching frequency of the field effect transistor in both cases of step-up and step-down.
And the field effect transistor of the DC / DC voltage converter 1 of this invention operate | moves with the switching frequency of 20 kHz or more which is the upper limit of an audible frequency.

  By the way, in the conventional DC / DC voltage converter, since the IGBT and PIN diode which used Si for the power semiconductor unit are used, there exists a restriction | limiting that the upper limit of practical semiconductor junction temperature becomes about 175 degreeC. If this upper limit temperature is exceeded, the power semiconductor unit made of Si will be damaged due to changes in physical properties such as increased leakage current. Therefore, the output power capacity of the DC / DC voltage converter must be set so as to be within the upper limit of 175 ° C. even if the semiconductor junction temperature of the power semiconductor unit rises. Here, the semiconductor junction temperature of the power semiconductor unit is in accordance with the balance between the heat generation characteristics due to the generated loss of the power semiconductor unit and the heat dissipation characteristics determined by the cooling structure for cooling the power semiconductor unit and the temperature of the refrigerant.

On the other hand, since FET1, FET2, FET3, and FET4 in the DC / DC voltage converter of the present invention use field effect transistors made of a semiconductor material having a wide bandgap that is larger than that of Si, DC The output power capacity that can be handled by the DC / DC voltage converter 1 is much larger than that based on the prior art, and the power density is improved.
This is because the upper limit of the semiconductor junction temperature of the wide band gap material is raised above the upper limit of the semiconductor junction temperature of the Si material. The reason for this will be described.

  Si often used as a semiconductor material in the prior art has a band gap value of 1.12 eV. On the other hand, typical materials generally referred to as wide band gaps include silicon carbide 4H—SiC (band gap: 3.25 eV), gallium nitride GaN (band gap: 3.39 eV), diamond (band Gap: 5.47 eV).

  When comparing the Si material and the wide band gap material, the larger the band gap (the wider) the band structure representing the state of electrons in the crystal, the more the electrons transition from the valence band to the conduction band. Energy is required, but in the case of a wide band gap, electrons cannot jump to the conduction band unless they are excited by giving more thermal energy than Si. Considering that this property is applied to the leakage current of the PN junction of the power device, when the power semiconductor unit is turned off, the semiconductor material of the wide band gap is more than the temperature at which the leakage current starts flowing in the Si material. It is equivalent to the leakage current finally starting to flow at high temperatures. In other words, the power semiconductor unit of the wide band gap material has a higher upper limit of the semiconductor junction temperature that normally operates as a semiconductor than the power semiconductor unit of the Si material. For example, if the band gap value is 2.0 eV or more, the band gap value is about 80% or more larger than the Si band gap value 1.12 eV, so that the difference in the upper limit of the semiconductor junction temperature appears significantly. .

When the handling power of the DC / DC voltage converter is increased, the loss generated in the power semiconductor unit increases and the semiconductor junction temperature rises. By using a power semiconductor unit made of a material having a band gap value of 2.0 eV or more, The deterioration of characteristics is suppressed to a small extent, and the heat resistance performance is improved.
Therefore, the DC / DC voltage conversion apparatus 1 of the present invention can be operated until the semiconductor junction is further heated as compared with the case where a power semiconductor unit made of a conventional Si material is used. Capacity increases and power density improves.

  On the other hand, the cooling performance required by the cooling heat sink can be lowered by utilizing the fact that the upper limit of the semiconductor junction temperature is increased. If the cooling performance is lowered, the cooling heat sink is also reduced in size, so that a small and lightweight DC / DC voltage converter can be realized even with a high output capacity.

  Further, in order to switch the field effect transistor, which is a semiconductor switching element, at an audible frequency upper limit of 20 kHz or more, an alternating current having a frequency of 40 kHz or more is conducted to the inductor L, and the volume and weight of the inductor L are further increased than the conventional one. Can be reduced. Hereinafter, this point will be described.

  As described above for the operation of the conversion main circuit 2, the ripple current component of the inductor L is generated by periodically switching the polarity of the potential difference between the terminals of the winding of the inductor L, and the polarity of the potential difference between the terminals. Is linked to the switching operation of the semiconductor switch element. That is, the polarity of the potential difference between the terminals of the winding is switched in a shorter cycle as the semiconductor switch element is switched at a higher frequency. This is because the increase / decrease → increase → decrease of the ripple current component of the inductor L is repeated in a short time, so that the increase amount and decrease amount of the inductor current IL in this repetition decrease. The amplitude of the ripple current component is reduced.

For this reason, the alternating current conducted to the inductor L is reduced, and the total amount of current in which the direct current and the alternating current are superimposed is also reduced.
Therefore, since the amplitude of the ripple current component changes depending on the inductance value of the inductor L, instead of reducing the amplitude of the alternating current as it is, the inductance value is lowered to reduce the cross-sectional area of the magnetic path of the inductor, and the inductor L Can be made smaller and lighter than before.
At this time, if the amplitude of the ripple current component is ILrpl, the inductance value is Lc, the potential difference between terminals of the inductor winding is ΔV, and the switching period of the semiconductor switch element is T, the period of the ripple current component is T / 2. Expressed in relationship.

  Lc · ILrpl = ΔV · (T / 4) (7)

Now, when the switching frequency of the semiconductor switch element is 5 kHz (T = 200 μs), the ripple current component frequency of the inductor L is 10 kHz, the terminal-to-terminal potential difference ΔV = 350 V, and the inductance value Lc = 350 μH, the ripple is obtained from the equation (7). The current component amplitude ILrpl = 50A.
Here, when the switching frequency is increased to 20 kHz (T = 50 μs), which is the upper limit of the audible frequency, when the ripple current component frequency of the inductor L is 40 kHz and the potential difference between terminals ΔV = 350 V, Lc · ILrpl = 4375 from Equation (7). × 10 ^ -6.

If the inductance value Lc = 350 μH is maintained, ILrpl = 12.5 A, which is 25% lower than the above-mentioned 50 A. However, if ILrpl = 50 A is maintained, L = 87.5 μH and the inductance value Lc is Reduce to 25%.
Reducing the inductance value Lc leads to lowering the number of turns of the inductor winding and the effective cross-sectional area of the inductor core, and the volume of the winding part and the core part is reduced, that is, the volume of the inductor L is reduced.

  Copper is mainly used for the winding of the inductor, and an electromagnetic steel plate or soft magnetic material mainly composed of iron, ferrite, or an alloy of iron, aluminum, or nickel is used for the core. The specific gravity of these metals is 8.95 g / cc for copper and 7.87 g / cc for iron, which is several times higher than the specific gravity of the resin. Among the constituent materials, the DC / DC voltage converter 1 of the present invention that makes the inductor L, which is a metal-based structure, small and light, can be realized with excellent light weight even with high output capacity.

By the way, the DC / DC voltage converter 1 of the present invention is required to handle a voltage in the range of about 100 V to 1000 V, switch at an audio frequency upper limit of 20 kHz or more, and have a high output power capacity, a small size, and a light weight. The
However, the DC / DC voltage converter of the prior art uses a semiconductor switch element made of Si material, and it is extremely difficult to perform a switching operation at an audio frequency upper limit of 20 kHz or more.
Even if the semiconductor switch element is made of a Si material, if it is a field effect transistor, it is a unipolar device and has a short operation reaction time, and switching operation at a frequency higher than the upper limit of the audible frequency becomes possible. . However, only a semiconductor switch element with a withstand voltage of about 100 V or less has been put into practical use in order to meet the high output power capacity required for a DC / DC converter and to have a low loss. Therefore, the FET made of Si cannot be used for the application of the DC / DC voltage converter 1 of the present invention.

  In addition, when an IGBT is used as a semiconductor switch element made of Si as in the prior art, it is suitable as an element withstand voltage for handling a voltage range of 100 V to 1000 V, but a switching operation at a frequency higher than the upper limit of the audible frequency. Could not be used. In an IGBT having an element withstand voltage that matches the above voltage range, the drift layer in the device structure becomes thick in order to obtain the withstand voltage. Since the IGBT is a bipolar device, it takes time to eliminate minority carriers in the thick drift layer during the turn-off operation, and has a disadvantage that the operation reaction time is long. Due to the length of this operation reaction time, it is difficult to apply to a switching operation at a high frequency higher than the upper limit of the audible frequency.

On the other hand, the DC / DC voltage converter 1 of the present invention uses a field effect transistor or a rectifier diode using a semiconductor material having a wide band gap of, for example, 2.0 eV or more as the power semiconductor unit. It can handle voltages in the range of about 100 V to 1000 V, and can perform switching operation at 20 kHz or more of the upper limit of the audible frequency, and can be realized in a small size and light weight with a high output power capacity.
This is based on the characteristics that a wide band gap semiconductor has a higher breakdown field strength and a higher saturation drift velocity than a semiconductor made of Si.
In a semiconductor made of Si, the dielectric breakdown strength is 0.3 MV / cm and the saturation drift velocity is 1 × 10 7 cm / s, whereas in a wide band gap semiconductor, the dielectric breakdown strength is 4H-SiC. Is 3 MV / cm, GaN is 3 MV / cm, diamond is 2 MV / cm, saturation drift velocity is 4 × 10 ^ 7 cm / s for 4H-SiC, 2.4 × 10 ^ 7 cm / s for GaN, and diamond is 2.5 × 10 ^ 7 cm / s.

  The higher the dielectric breakdown strength, the thinner the layer applied to the drift region in the structure of the power semiconductor unit when obtaining the withstand voltage required for the power semiconductor unit. In addition, since the saturation drift speed is high, electrons can move quickly in the drift region. That is, as a feature of the wide band gap semiconductor, it is possible to perform a switching operation at a high frequency higher than the upper limit of the audible frequency because the electrons move quickly through the thin drift layer and the operation reaction time is short.

  Further, the DC / DC voltage converter 1 of the present invention switches the semiconductor switch element at a frequency higher than the upper limit of the audible frequency, and the frequency of the ripple current component of the inductor L becomes twice the switching frequency. Further, it is possible to eliminate the generation of annoying audible noise, which is remarkable with the inductor L, the energy transfer capacitor C0, and the smoothing capacitors C1 and C2. Therefore, conventionally, there is no need to take measures to bring about adverse effects such as increasing the cost, increasing the volume, and increasing the weight, such as attaching a vibration absorbing member for suppressing noise propagation to the outside or adopting a low magnetostrictive core material for the inductor. May be.

In addition, since the DC / DC voltage converter 1 of the present invention switches the semiconductor switch element at a frequency higher than that of the conventional one, the capacitance required for the energy transfer capacitor C0 and the smoothing capacitors C1 and C2 is increased. In addition, it is possible to reduce the loss generated and to make the device compact and lightweight.
This will be described with reference to FIG. FIG. 8 is a diagram showing the impedance characteristics of a capacitor with the horizontal axis representing the logarithmic value of the frequency and the vertical axis representing the logarithmic value of the impedance.

  In the figure, the alternate long and short dash line indicates the characteristics of the capacitance Ca, and the solid line indicates the characteristics of the capacitance Cb. The capacitance relationship is Cb <Ca, and Ca has a larger capacitance. The impedance decreases as the frequency increases from a low frequency range. This is because the capacitance component of the capacitor element is a main component that determines the impedance in a low frequency range. As the frequency increases, the impedance becomes a minimum value at a certain frequency, and when the frequency further increases beyond the frequency that becomes the minimum value, the slope is inverted and the impedance increases. This is because at a high frequency, the inductive component of the lead portion that becomes the current path of the capacitor element becomes the main component that determines the impedance.

Here, in the low frequency range where the capacitance component of the capacitor element is the main component of the impedance, the capacitance Cb having a smaller capacitance has a larger impedance than the capacitance Ca. On the other hand, in a high frequency range where the inductive component is the main component of impedance, the capacitance Ca having a larger capacitance has a larger impedance than the capacitance Cb.
Now, let the impedance be ZaΩ when the semiconductor switch element is switched at 10 kHz in the conventional DC / DC voltage converter and the frequency of the alternating current flowing in the capacitor is the same frequency. In the DC / DC voltage converter according to the present invention, if switching is performed within the range up to the frequency where the impedance characteristic of the capacitor becomes a minimum value and the upper limit of the audible frequency is 20 kHz, the impedance is higher than in the case of switching at 10 kHz as usual. To reduce.

Therefore, even if the capacitance is reduced from Ca to Cb, if Cb is selected so that the impedance Zb at 20 kHz satisfies Zb <Za, the capacitor can be reduced in size and weight by reducing the capacitance. Impedance can be reduced at the same time.
Further, since the impedance is reduced from Za to Zb, the loss that occurs when an alternating current flows through the capacitor is reduced, which is preferable because the temperature rise due to heat generation of the capacitor is mitigated. The temperature rise due to heat generation promotes the deterioration of the resin material used for the capacitor, and thus becomes a factor for shortening the durability of the DC / DC voltage converter using the capacitor. The DC / DC voltage converter according to the present invention can achieve the effect of facilitating the reduction in size and weight of the capacitor and the securing of durability reliability.

Next, the operation of the control unit 3 will be described with reference to FIG. FIG. 9 is a block diagram illustrating the configuration of the control unit 3 and the conversion main circuit 2.
The control unit 3 internally inputs the primary side terminal voltage V1, the secondary side terminal voltage V2, the inductor current IL, and the DC / DC voltage conversion ratio instruction from an external device (not shown) from the conversion main circuit 2. The control calculation is performed in this manner, and a gate drive signal 8 for controlling the switching operation of the FET 4, FET 3, FET 2, and FET 1 in the conversion main circuit 2 is output.

  The primary side terminal voltage V 1, secondary side terminal voltage V 2, inductor current IL, and DC / DC voltage conversion ratio instruction that are input to the control unit 3 are input to the conversion control unit 10. The conversion control unit 10 calculates the voltage conversion ratio of the conversion main circuit 2 that is actually operating from the ratio of the secondary terminal voltage V2 and the primary terminal voltage V1, and converts the DC / DC voltage from an external device. A negative feedback control calculation using a known proportional integration (PI) calculation or the like is performed in comparison with the ratio instruction to calculate a target amount Lduty of the on-duty of FET1 and FET2. Lduty is a range in which the lower limit of the duty is 0% and the upper limit is 100%. For example, Lduty = 0.0 when 0% and Lduty = 1.0 when 100%. To express.

The inductor current IL is used as an input amount for a negative feedback control calculation performed by matching the inductor current target amount IL_ref and the inductor current IL as a control calculation loop included in the negative feedback control calculation loop having the voltage conversion ratio. It is done.
By applying the negative feedback minor control calculation of the inductor current, the control band of the negative feedback control system of the DC / DC voltage conversion ratio on the outer periphery can be set to a high frequency, and a wide band gap semiconductor is applied to the semiconductor switch element. Combined with switching at a higher frequency than before, the follow-up response of the conversion ratio control to the DC / DC voltage conversion ratio instruction is improved.

  Next, Lduty is input to the gate PWM generator 11. The gate PWM generator 11 performs pulse width modulation (PWM) corresponding to the value of Lduty, and FIG. 4 (a), FIG. 5 (a), FIG. 6 (a), FIG. 7 (a). The rectangular gate PWM signals Gpwm1, Gpwm2, Gpwm3, and Gpwm4 that are the original signals of the gate drive signal 8 (Gate1, Gate2, Gate3, and Gate4) shown in FIG. This is generated, for example, by using a triangular wave comparison method to compare the magnitude of a triangular wave having a frequency of 1.0 and an amplitude of 1.0 with a switching frequency of the semiconductor switch element.

  The gate PWM signals Gpwm1, Gpwm2, Gpwm3, and Gpwm4 are input to the gate drive circuit 12. The gate drive circuit 12 outputs a gate drive signal 8 for turning on / off the semiconductor switch element according to the logic of the gate PWM signal. Since the gate drive circuit 12 needs to transfer the gate PWM signal to and from the gate PWM generation unit 11, the gate drive circuit 12 receives the signal after being insulated. This is because the source potentials of FET4, FET3, FET2, and FET1 have individual values, and in order to switch on / off of FET4, FET3, FET2, and FET1, the gate potential is set based on the source potential of each field effect transistor. This is because the gate PWM generator 11 generates and outputs a gate PWM signal at the same reference potential.

In addition, as described above, the gate drive circuit 12 includes the gate drive circuit (1) 121, the gate drive circuit (2) 122, and the gate drive circuit (3) so that each field effect transistor having an individual source potential is operated. 123 and the gate drive circuit (4) 124.
Each gate drive circuit is signal-connected to the source potential of the corresponding field effect transistor, and switching between switching on and switching off by switching the voltage of the gate driving signal 8 between the power supply voltage VD and the source potential. Control. Since the power supply voltage VD needs to be individually supplied according to each field effect transistor, four mutually isolated power supply voltages VD1, VD2, VD3, and VD4 are generated by the gate power supply circuit 13, and each of the gate drive circuits (1) 121, a gate drive circuit (2) 122, a gate drive circuit (3) 123, and a gate drive circuit (4) 124.

  The gate drive circuit (1) 121 outputs a Gate1 signal to output FET1, the gate drive circuit (2) 122 outputs a Gate2 signal to output FET2, and the gate drive circuit (3) 123 outputs a Gate3 signal to drive FET3 to gate drive. The circuit (4) 124 outputs a Gate4 signal and performs switching operation of each FET4.

The relationship between the on-duty of the FET1 and FET2 and the DC / DC voltage conversion ratio has the characteristics shown in FIG. 10 according to the equations (3) and (6). As described above, the DC / DC voltage conversion apparatus 1 performs an operation in the control unit 3 so as to follow a DC / DC voltage conversion ratio instruction from an external device (not shown), and in a steady state, on the characteristic line in FIG. A gate drive signal 8 with an on-duty corresponding to the instructed DC / DC voltage conversion ratio is output to control switch-on and switch-off of the semiconductor switch element in the conversion main circuit 2.
When the on-duty is 0%, the primary terminal voltage V1 and the secondary terminal voltage V2 of the DC / DC voltage converter 1 are equal. As the on-duty increases, the voltage conversion ratio V2 / V1 increases. In the step-up operation, power is sent in the range from the primary side to the secondary side in the step-up ratio V2 / V1 being 1.0 or more, and in the step-down operation, the step-down ratio V1 / V2 is moved from the secondary side to the primary side. Sends power in the range of 1.0 or less.

As described above, according to the first embodiment, a DC / DC voltage converter using a field effect transistor made of a semiconductor material having a wide band gap larger than that of Si as a power semiconductor unit. Therefore, the switching operation at an audio frequency upper limit of 20 kHz or more is possible, and the upper limit of the semiconductor junction temperature of the power semiconductor unit is significantly increased as compared with the conventional Si material.
Further, by adopting the conversion main circuit configuration of the present invention, the ripple current component frequency of the inductor L can be doubled the switching frequency of the semiconductor switch element.
Therefore, even if the output power capacity of the DC / DC voltage converter is increased and the loss generated in the power semiconductor unit is increased, the heat-resistant temperature of the power semiconductor unit is increased. The balanced relationship of is not inconsistent. On the other hand, by reducing the cooling performance required for the cooling heat sink, the cooling heat sink can be made smaller and lighter. Along with the downsizing of the device, the transportation and the packaging during transportation become simple.

Furthermore, since the frequency of the ripple current component of the inductor L is increased, the inductance of the inductor L can be lowered, and the volume and weight of the inductor are significantly reduced compared to those based on the prior art.
Therefore, it is possible to realize a small and lightweight DC / DC voltage conversion device while expanding the output power capacity that can be handled and improving the power density.
In particular, the generation of annoying audible noise, which is remarkable with the inductor L, the energy transfer capacitor C0, and the smoothing capacitors C1 and C2, can be solved.

  Within the scope of the present invention, the power semiconductor unit of the conversion main circuit 2 is replaced with a field effect transistor made of a wide band gap semiconductor material as shown in FIG. An IGBT having characteristics adjusted so that it can operate and a rectifying element made of a wide band gap semiconductor material connected in reverse parallel to the IGBT may be applied. In FIG. 11, the semiconductor switch elements are IGBT1, IGBT2, IGBT3, and IGBT4. The rectifying elements made of the wide band gap material are Di1, Di2, Di3, and Di4. IGBT1 and Di1, IGBT2 and Di2, IGBT3 and Di3, and IGBT4 and Di4 are connected in antiparallel to form a power semiconductor unit capable of conducting current bidirectionally.

With this configuration, the semiconductor junction temperature of the IGBT, which is a semiconductor switching element, must be kept below the upper limit of 175 ° C. However, since a wide band gap semiconductor material is applied as the rectifying element, the reverse recovery time is Short reverse recovery current can be achieved.
Therefore, even if an IGBT made of Si material is used, the switching response speed of the IGBT can be increased and the switching loss can be reduced. Therefore, there is a margin in the temperature rise of the IGBT, and the DC / DC voltage converter can be handled. The output power capacity is increased and the power density is improved.

  In the above description, the switching frequency of the power semiconductor unit is set to the upper limit of the audible frequency, but the condition that the frequency of the AC component flowing through the inductor that is twice the switching frequency is higher than the upper limit of the audible frequency is satisfied. In particular, since the noise generated by the inductor, whose noise is a problem, is equal to or higher than the upper limit of the audible frequency, generation of harsh audible noise can be prevented in the same manner as described above.

Embodiment 2. FIG.
Hereinafter, a DC / DC voltage conversion apparatus according to Embodiment 2 of the present invention will be described with reference to FIGS.
FIG. 12 is an external view of the DC / DC voltage converter 1 according to this embodiment. (A) is a perspective view, (b) is the side view seen from the arrow Ds direction on the perspective view. In FIG. 12A, the cooling heat sink 15 absorbs heat from a structure that abuts on the upper and lower surfaces having a large area as a cooling surface, and dissipates heat to the refrigerant circulating inside. The pipes 16 a and 16 b are refrigerant inlets and outlets into the cooling heat sink 15.
An inductor L and a capacitor C are placed on the upper surface of the cooling heat sink 15. In the capacitor C, smoothing capacitors C1 and C2 of the conversion main circuit 2 and an energy transfer capacitor C0 are integrally stored.

  The inductor L and the capacitor C generate heat internally when a current flows, but are radiated through a cooling surface that contacts the cooling heat sink 15. On the other hand, a power module 19 having a power semiconductor unit therein is placed on the lower surface of the cooling heat sink 15. Although conduction loss and switching loss occur in the semiconductor switch element in the power semiconductor unit and conduction loss and reverse recovery loss occur in the rectifier element, heat is generated, but heat is radiated through the cooling surface in contact with the cooling heat sink 15.

  Further below the power module 19, the control unit 3 is arranged supported by the holder 18 in the form of an electronic component mounting board. Further, on the side of the cooling heat sink 15 (front side in the figure), a bus bar for electrically connecting the power semiconductor units (FET1 to FET4) constituting the conversion main circuit 2, the capacitors C0, C1, C2, and the inductor L is provided. A built-in wiring component 17 is arranged. The wiring component 17 is also provided with a terminal block for a primary positive terminal P1, a secondary positive terminal P2, and a negative terminal N that combines the primary and secondary sides together. .

  In FIG. 12B, the power module 19 and the control unit 3 are connected by a relay terminal 20 for exchanging signals. As described in the first embodiment, the control unit 3 includes a DC / DC voltage conversion ratio instruction from an external device (not shown), a primary terminal voltage V1, a secondary terminal voltage V2, an inductor from the conversion main circuit 2. The current IL and the source potential of each of the field effect transistors FET1 to FET4 are input. Further, the gate drive signal 8 is output to the conversion main circuit 2. The relay terminal 20 is a path through which these signals are transmitted.

As shown in FIGS. 12A and 12B, the power module 19, the capacitor C, and the inductor L are arranged close to each other with the cooling heat sink 15 interposed therebetween. In this embodiment, the heat generated by the capacitor C and the inductor L is radiated through a cooling path that radiates heat to the refrigerant through the cooling surface of the cooling heat sink 15 that contacts each other. Similarly, the power module 19 is radiated to the refrigerant through the cooling surface of the cooling heat sink 15.
The cooling heat sink 15 also functions as a heat insulating thermal barrier structure that eliminates interference between the heat generated by the capacitor C and the inductor L and the heat generated by the power module 19.

  In this way, when a power semiconductor unit made of a wide band gap material is applied to the semiconductor unit by sandwiching the thermal barrier structure, the semiconductor junction temperature is made to be higher than that of the conventional Si material. However, there is no problem that the temperature of the capacitor C and the inductor L increases due to heat transfer to the capacitor C and the inductor L. This has the advantage that the durability of the capacitor C and the inductor L does not deteriorate.

Various resin materials are used for capacitors and inductors, such as polypropylene (PP), polyethylene terephthalate (PET) for dielectric films of capacitors, epoxy resins for moisture-proof materials, and polyamides for soft magnetic materials as inductor cores. (PA), cast resin for heat transfer insulation, polyurethane resin, silicone resin, and the like.
When the temperature rises in this resin material part, deterioration due to thermal decomposition is promoted, causing a decrease in the capacitance of the capacitor, an increase in leakage current, a decrease in the strength of the inductor core, a decrease in the dielectric strength of the casting material, and the durability. Reliability deteriorates. According to the DC / DC voltage converter of the present invention, this problem can be avoided.

This will be specifically described with reference to FIG. 13 from the relationship between the thermal resistance of the heat dissipation path and the respective temperatures.
FIG. 13 schematically shows the path through which the generated heat is dissipated to the refrigerant in the cooling heat sink 15 and the thermal resistance on the path using the power module 19 and the inductor L as a heating element. (A) shows that the thermal resistance θbk of the portion that bridges between the heat dissipation path of the inductor L and the heat dissipation path of the power module 19 is θbk = 0.3 k / W, and heat is generated between the inductor L and the power module 19. The case where the barrier structure is not sandwiched is shown.
On the other hand, (b) shows the thermal resistance θbk = 10.0 k / W between them, and shows the case where the thermal barrier structure is sandwiched between the inductor L and the power module 19 as in the present invention. Yes.

In the figure, θs1 is the thermal resistance of the cooling heat sink 15 on the heat dissipation path of the power module 19, θs2 is the thermal resistance between the power module 19 and the cooling heat sink 15, and θr1 is the heat dissipation path of the inductor L. The thermal resistance of the cooling heat sink 15, θr 2, is the thermal resistance between the inductor L and the cooling heat sink 15.
Tj is the semiconductor junction temperature of the power semiconductor unit in the power module 19, and Tns is the temperature of the junction with the cooling heat sink 15 on the heat dissipation path of the power module 19. Trc is the temperature of the heat generation part in the inductor L, and Tnr is the temperature of the joint part with the cooling heat sink 15 on the heat dissipation path of the inductor L. Tw is the temperature of the refrigerant.

The power module 19 generates a loss of JEs, and this generates heat as generated heat. A flow JEsa that reaches the refrigerant through the cooling heat sink 15 in the vicinity of the power module 19 at the node Ns in the illustrated thermal resistance network, and a flow JEsb that bypasses the cooling heat sink 15 in the vicinity of the inductor L and reaches the refrigerant.
Similarly, the inductor L causes a loss of JEr, which is generated as heat and generates heat. JEr is a flow JEra that reaches the refrigerant through the cooling heat sink 15 near the inductor L at the node Nr in the illustrated thermal resistance network and a flow JErb that bypasses the cooling heat sink 15 near the power module 19 and reaches the refrigerant. Divided.

13 (a) and 13 (b) have the same thermal resistance values except that the value of θbk is different,
θs1 = 0.1 k / W, θs2 = 0.2 k / W, θr1 = 0.2 k / W, and θr2 = 2.6 k / W.
The generated heat JEs of the power module 19 is 500 W, the generated heat JEr of the inductor L is 40 W, and the refrigerant temperature Tw is 50 ° C.

Specific numerical values for FIG. 13A are as follows. The generated heat JEs of the power module 19 is divided according to the ratio of the thermal resistance of each path to the combined thermal resistance when the cooling heat sink 15 side is viewed from the node Ns. Therefore, the diversion of the cooling path is
JEsa = 500 W × (θbk + θr1) / (θs1 + θbk + θr1) = 500 × (5/6) W,
JEsb = 500W × θs1 / (θs1 + θbk + θr1) = 500 × (1/6) W
Similarly, the generated heat JEr of the inductor L is divided according to the ratio of the thermal resistance of each path to the combined thermal resistance when the cooling heat sink 15 side is viewed from the node Nr. Therefore, the diversion of the cooling path is
JEra = 40W × (θbk + θs1) / (θr1 + θbk + θs1) = 500 × (4/6) W,
JErb = 40W × θr1 / (θr1 + θbk + θs1) = 40 × (2/6) W
It becomes.

The heat passing through θs1 is a combination of JEsa and JErb.
JEsa + JErb = 500 × (5/6) W + 40 × (2/6) W = 430W
It becomes.
The heat passing through θr1 is a combination of JEra and JEsb. From the above, JEsb + JEra = 500 × (1/6) W + 40 × (4/6) W = 110W
It becomes.
Therefore, the temperature of each part is
Tns = θs1 × (JEsa + JErb) + Tw = 0.1 k / W × 430 W + 50 ° C. = 93 ° C.
Tj = θs2 × JEs + Tns = 0.2 k / W × 500 W + 93 ° C. = 193 ° C.
Tnr = θr1 × (JEra + JEsb) + Tw = 0.2 k / W × 110 W + 50 ° C. = 72 ° C.
Trc = θr2 × JEr + Tnr = 2.6 k / W × 40 W + 72 ° C. = 176 ° C.
It becomes.

In FIG. 13B, θbk = 10.0 k / W, so the specific numerical values are as follows.
JEsa = 500 W × (θbk + θr1) / (θs1 + θbk + θr1) = 500 × (10.2 / 10.3) W,
JEsb = 500W × θs1 / (θs1 + θbk + θr1) = 500 × (0.1 / 10.3) W,
JEra = 40W × (θbk + θs1) / (θr1 + θbk + θs1) = 500 × (10.1 / 10.3) W,
JErb = 40W × θr1 / (θr1 + θbk + θs1) = 40 × (0.2 / 10.3) W
It becomes.

The heat passing through θs1 is a combination of JEsa and JErb.
JEsa + JErb = 500 × (10.2 / 10.3) W + 40 × (0.2 / 10.3) W = 495.9W
It becomes.
The heat passing through θr1 is a combination of JEra and JEsb. From the above, JEsb + JEra = 500 × (0.1 / 10.3) W + 40 × (10.1 / 10.3) W = 44.1W
It becomes.

Therefore, the temperature of each part is
Tns = θs1 × (JEsa + JErb) + Tw = 0.1 k / W × 495.92 W + 50 ° C. = 99.6 ° C.
Tj = θs2 × JEs + Tns = 0.2 k / W × 500 W + 99.6 ° C. = 199.6 ° C.
Tnr = θr1 × (JEra + JEsb) + Tw = 0.2 k / W × 44.1 W + 50 ° C. = 58.8 ° C.
Trc = θr2 × JEr + Tnr = 2.6 k / W × 40 W + 58.8 ° C. = 162.8 ° C.
It becomes.

From the above, the semiconductor junction temperature Tj of the power semiconductor unit when the thermal barrier structure is not sandwiched between the inductor L and the power module 19 and θbk = 0.3 k / W is low is 193 ° C., the inductor L In the case where the temperature Trc of the heat generating portion is 176 ° C., and θbk = 10.0 k / W is high while sandwiching the thermal barrier structure, the semiconductor junction temperature Tj of the power semiconductor unit is 199.degree. The temperature Trc of the heat generation part in the inductor L at 6 ° C. is 162.8 ° C.
Therefore, by sandwiching the thermal barrier structure, Tj is increased by 6.6 ° C., and Trc is decreased by 13.2 ° C.
Since the DC / DC voltage conversion apparatus 1 of the present invention uses a power device made of a wide band gap material for a power semiconductor unit, a rise of 6.6 ° C. is relatively permissible at a semiconductor junction temperature level of about 190 ° C. . On the other hand, the temperature of the inductor L using the resin material becomes as low as 13.2 ° C. at the level of about 170 ° C., because the thermal decomposition of the resin material is greatly suppressed by the known Arrhenius chemical reaction law. The durability reliability related to the strength of the core and the dielectric strength of the casting material is greatly improved.

  In other words, even if a power semiconductor unit made of a semiconductor material with a wide band gap is applied and operated until the semiconductor junction temperature becomes higher than that made with a conventional Si material, heat transfer to the capacitor C and the inductor L Therefore, it is not necessary to change the heat resistance. As a result, the effect that the bad influences, such as cost increase and volume increase, do not arise is acquired.

Furthermore, as another advantage, the power module 19 and the energy transfer capacitor C0 stored in the capacitor C are arranged close to each other with the thermal barrier structure interposed therebetween. The wiring distance of the electrical connection conductor (bus bar) can be shortened.
Therefore, the parasitic inductance component Ls present according to the wiring distance is reduced as the bus bar wiring distance is shortened, and the induced voltage Vs (= Ls · dI / dt) generated by the time change of the current I conducted to the bus bar. ) Is also reduced.

Incidentally, the parasitic inductance component Ls exists in the conversion main circuit 2 as shown in FIG. Due to the arrangement of the structure, the parasitic inductance Ls of the bus bar becomes longer between the power module 19 and the energy transfer capacitor C0, the smoothing capacitor C2, and the inductor L, and between the inductor L and the smoothing capacitor C1. It exists as a relatively large value in the part.
The parasitic inductance Ls in the vicinity of the inductor L has little adverse effect because the inductor L is originally a derivative, but has an influence between the power module 19 and the energy transfer capacitor C0 and the smoothing capacitor C2.
The induced voltage Vs is superimposed as a surge voltage component on the electrode of the electrical connection terminal during the switching operation of the semiconductor switch element. If the surge voltage component is large, the withstand voltage of the power semiconductor unit and the energy transfer capacitor is reduced. Overvoltage failure will occur.

Therefore, in the DC / DC voltage conversion apparatus of the second embodiment, the parasitic inductance Ls of the bus bar is reduced, so that the required level of withstand voltage of the power semiconductor unit, the energy transfer capacitor C0, and the smoothing capacitor C2 is lowered. Can do.
By reducing the required level of withstand voltage, the thickness of the drift layer for obtaining the withstand voltage inside the power semiconductor unit can be reduced. If the drift layer is thin, the reaction time of the switching operation of the power semiconductor unit is shortened, making it suitable for high-frequency switching operation, conduction loss due to on-resistance in the drift layer, and semiconductors at turn-on and turn-off The switching loss consisting of the time integration of the product of the voltage across the switch element and the conduction current and the reverse recovery loss consisting of the time integration of the product of the voltage across the rectifier element and the reverse recovery current are reduced.
This, in turn, reduces the heat generated by the power semiconductor unit to improve the efficiency of the DC / DC voltage converter and facilitates further increase of the switching frequency.

  As described above, according to the second embodiment, it is assumed that the power semiconductor unit is operated at a high temperature using a wide band gap semiconductor material by devising the arrangement of the components of the DC / DC voltage converter. However, it is possible to provide a low-loss, high-efficiency DC / DC voltage converter while ensuring durability and reliability and suppressing cost increase.

  In the second embodiment, the power module 19, the inductor L, and the capacitor C are in contact with the cooling surface of the cooling heat sink 15 to form a heat dissipation path, but the power module 19 is within the scope of the present invention. The inductor L and the capacitor C may not be in direct contact with the cooling surface, but may radiate heat through another metal body that is in contact with the cooling surface. That is, even if the metal body is a support structure for fixing the power module 19, the inductor L, and the capacitor C to the cooling heat sink 15 and is a part of the heat dissipation path, As long as the heat dissipation path and the heat dissipation path from the inductor L and capacitor C have no thermal interference, the same effects as those described in this embodiment can be obtained.

  Further, the thermal barrier structure that thermally insulates between the heat dissipation path of the inductor L and the heat dissipation path of the power module 19 may be configured separately from the cooling heat sink. Also in this case, the advantage that the temperature of the heat generating portion in the inductor L described above is effectively reduced can be obtained.

Embodiment 3 FIG.
Hereinafter, a DC / DC voltage converter according to Embodiment 3 of the present invention will be described with reference to FIGS. 15 to 18.
The DC / DC voltage converter of the present embodiment is configured except for the configuration and operation of the gate PWM generator 11 and the gate drive circuit 12 in the control unit 3 and the operation of the field effect transistor in the conversion main circuit 2 when it is turned off. This is the same as in the case of the DC / DC voltage converter of the first embodiment, and hereinafter, the description of the same configuration, operation, and action as in the first embodiment will be omitted as appropriate.

First, a description will be given with reference to FIG. FIG. 15 is a block diagram illustrating the configuration of the control unit 3 and the conversion main circuit 2 according to this embodiment. The control unit 3 internally inputs the primary side terminal voltage V1, the secondary side terminal voltage V2, the inductor current IL, and a DC / DC voltage conversion ratio instruction from an external device (not shown). A control calculation is performed, and a gate drive signal 8 for controlling the switching elements in the conversion main circuit 2 is output. In accordance with the timing and logic gate drive signal 8 shown in the first embodiment, the switching elements in the conversion main circuit 2 are switched on and off to perform desired DC / DC voltage conversion.
The primary terminal voltage V1, the secondary terminal voltage V2, the inductor current IL, and the DC / DC voltage conversion ratio instruction that are input to the control unit 3 are input to the conversion control unit 10, and negative feedback control calculation of the voltage conversion ratio is performed. Then, the target amount Lduty of the on-duty of FET1 and FET2 is output.

Subsequently, the gate PWM generation unit 11a receives Lduty, generates gate PWM signals Gpwm1, Gpwm2, Gpwm3, and Gpwm4 corresponding to the value of Lduty and outputs them to the gate drive circuit 12a.
Further, a switching signal DCsel for selecting either the switch-off circuit (1) or the switch-off circuit (2) of the gate drive circuit 12a is output to the gate drive circuit 12a depending on the magnitude of Lduty.

A detailed configuration of the gate drive circuit 12a is shown in FIG. In FIG. 16, one of four individual drive circuit blocks 121a, 122a, 123a, and 124a constituting the gate drive circuit 12a is shown as a drive circuit block 12xa as a representative. The individual drive circuit blocks 121a, 122a, 123a, and 124a have the same configuration and operation. The drive circuit block 121a corresponds to FET1, 122a corresponds to FET2, 123a corresponds to FET3, and 124a corresponds to FET4.
The drive circuit block 12xa generates and outputs the gate drive signal 8 by operating any one of the switch-on circuit 24, the switch-off circuit (1) 25, and the switch-off circuit (2) 26. The switch-on circuit 24 includes a semiconductor switch 241 such as a small signal field effect transistor and a circuit resistor 242.

  Similarly, the switch-off circuit (1) 25 includes a semiconductor switch 251 and a circuit resistor 252, and the switch-off circuit (2) 26 includes a semiconductor switch 261 and a circuit resistor 262. Here, a relationship of (resistance value of circuit resistor 252) <(resistance value of circuit resistor 262) is given.

When the gate PWM signal Gpwm is input to the gate drive circuit 12a, it is transmitted to the signal buffers 21 and 22 internally. The signal buffer 21 is an amplifier circuit that controls the semiconductor switch 241 to be closed when the logic of the gate PWM signal Gpwm is switch-on logic and open when the logic is switch-off logic.
When Gpwm is switch-on logic, the semiconductor switch 241 is closed, and the voltage of the gate drive signal 8 (Gate) becomes the power supply voltage VD. Therefore, the field effect transistor in the corresponding conversion main circuit 2 is switched on.

The signal buffer 22 is an amplifier circuit that controls the semiconductor switches 251 and 261 so as to be opened when the logic of the gate PWM signal Gpwm is switch-on logic and closed when the logic is switch-off logic.
When Gpwm is switch-off logic, either the semiconductor switch 251 or the semiconductor switch 261 is closed, and the voltage of the gate drive signal 8 (Gate) becomes equal to the source potential. Therefore, the field effect transistor in the corresponding conversion main circuit 2 is switched off.

Here, the circuit switch 23 selects which of the semiconductor switch 251 and the semiconductor switch 261 is closed.
The output of the signal buffer 22 and the switching signal DCsel are input to the circuit switch 23 to select which one of the switch-off circuit (1) 25 and the switch-off circuit (2) 26 is operated, and the switch on the selected side A control signal is transmitted to close the semiconductor switch in the off circuit.

Selection of the switch-off circuit in the circuit switcher 23 is performed in the form shown in FIG.
FIG. 17 is an explanatory diagram schematically showing which of two types of switch-off circuits is selected in accordance with the on-duty. In FIG. 17, switching of the switch-off circuit is performed with hysteresis of an on-duty width ΔD with respect to the on-duty.
That is, when the switch-off circuit (1) 25 is selected and the on-duty is equal to or higher than Da% (second threshold), the switch-off circuit (2) 26 is switched to be selected. Further, when the switch-off circuit (2) 26 is selected and the on-duty is less than (Da−ΔD)% (first) threshold value, the switch-off circuit (1) 25 is switched to be selected.
That is, when the on-duty is high and Da% or more, the switch-off circuit is operated with a high circuit resistance value, and when the on-duty is low and less than (Da−ΔD)%, the switch-off circuit with a low circuit resistance value Operate with.
As described in the first embodiment, if the on-duty is high, the DC / DC voltage conversion ratio is large, and the secondary side voltage V2 of the DC / DC voltage converter is high.

  As will be described later, the circuit switch 23 turns off the semiconductor switch by lowering the gate signal 8 to the semiconductor switch based on the relationship of (resistance value of the circuit resistor 252) <(resistance value of the circuit resistor 262). When the switch-off circuit (1) 25 is selected as the falling steepness when the first setting value is selected as the falling steepness, and the switch-off circuit (2) 26 is selected. Switching to the case where the second set value smaller than the first set value is selected as the falling steepness is performed.

  If operated as described above, when the secondary side voltage of the DC / DC voltage converter 1 is high, the surge voltage generated when the field effect transistor is turned off is reduced. It is possible to prevent the maximum voltage including the surge voltage between the sources (DS) from becoming excessive. This will be described in more detail with reference to FIG.

FIG. 18 shows an operation waveform at the time of turn-off of the field effect transistor, and the horizontal axis represents the passage of time. 18A shows a case where the circuit operates with a switch-off circuit having a low circuit resistance value, and FIG. 18B shows a case where the circuit operates with a switch-off circuit having a high circuit resistance value.
Each symbol in the figure is
Vgs: gate-source (GS) voltage,
Ig: operating current of the gate drive signal 8;
Vds: drain-source (DS) voltage,
Id: current flowing into the drain,
Vth: threshold voltage,
Nfet: the number of series field effect transistors in the conversion main circuit.

The process of the turn-off operation is represented by a change from time ta1 to ta4 in FIG. 18 (a), and a change from time tb1 to tb4 in FIG. 18 (b).
In FIG. 18A, first, the logic of the gate drive signal 8 is switched from switch-on to switch-off at time ta1. Vgs discharges the gate-source capacitance Cgs and reaches Vth at time ta2. Since the voltage Vds starts to increase from time ta2, the voltage across the drain-source capacitance Cds increases and is charged. At the same time, the gate-drain capacitance Cgd is also charged. From the time ta2 to the time ta3, the discharge of Cgs is temporarily stopped, the decrease of the voltage Vgs is stopped and becomes constant at Vth. During this time, the operating current Ig of the gate drive signal 8 increases and becomes Δigp1. At time ta3, the voltage Vds almost increases.

When the charging of Cgd is almost completed at time ta3, the discharging of Cgs resumes and the current Id decreases. At time ta4, Id completely decreases and the turn-off operation is completed.
Here, an induced voltage is generated from the product of the change rate dId / dt of the current Id and the parasitic inductance Ls of the bus bar portion described in the second embodiment, and becomes the surge voltage ΔVsg1. When the transient operation of the turn-off is finished, the voltage converges to Vds = (2 · V2) / Nfet. This is a state in which the portion to which the voltage V2 is applied is handled by half of the Nfet field effect transistors. The half is responsible because it operates as a combination in which the relationship between the switch-on and switch-off of the field effect transistor is complementary.
In a transient state of the turn-off operation, a surge voltage is superimposed on the voltage Vds, and the maximum value reaches Vds_max = (2 · V2) / Nfet + ΔVsg1. If this Vds_max is excessive, there is a greater concern that the withstand voltage of the power device or capacitor will be exceeded and damaged.

On the other hand, FIG. 18B shows a case where the circuit operates with a switch-off circuit having a high circuit resistance value, and therefore, the falling steepness of the gate signal being small and gradual.
In FIG. 18B, the contents of the operation from time tb1, tb2, tb3, tb4 are the same as in FIG. 18A, and time tbx corresponds to time tax. However, due to the difference in circuit resistance value, the operating current Ig of the gate drive signal 8 from time tb2 to time tb3 becomes Δigp2 which is smaller than Δigp1 in FIG. This is because the operating current Ig flows with a circuit resistance value higher than the threshold voltage Vth.

  Therefore, the change rate dId / dt of the current Id when the discharge of Cgs is resumed from the time tb3 to the time tb4 and the current Id decreases is smaller than that of the waveform of FIG. . Accordingly, the surge voltage ΔVsg2 represented by the product of the parasitic inductance Ls of the bus bar portion is lower than ΔVsg1 in FIG. 18A, and the maximum value Vds_max of the voltage Vds in the transient state Vds_max = (2 · V2) / NFET + ΔVsg2 is also lowered.

  From the above, the DC / DC voltage conversion apparatus 1 according to the third embodiment switches the switch-off circuit in the gate drive circuit 12a according to the on-duty so that the secondary voltage V2 is high. The surge voltage superimposed between the drain and source of the field effect transistor is kept low. For this reason, the drain-source voltage becomes excessive and the withstand voltage of the power semiconductor unit or the capacitor is exceeded, so that it can be operated without being damaged.

In the DC / DC voltage converter 1 according to the second embodiment, since the parasitic inductance Ls of the bus bar portion can be reduced, the surge voltage superimposed between the drain and source can be lowered. However, if the switch-off operation speed is increased, the surge voltage increases in a direction that is proportional to the change rate dId / dt of the current Id.
In the third embodiment, when the on-duty is high, the switch-off operation speed is slowed down. Therefore, there is a concern that the secondary side voltage V2 is high and exceeds the withstand voltage of the power semiconductor unit or the capacitor. The switch-off circuit is switched so that the surge voltage is reduced only in the increasing operating range. Therefore, the switch-off operation speed can be increased in the operation range where the secondary terminal voltage V2 is not a high voltage, and there is an advantage that the switching loss is small and the efficiency is high.

Embodiment 4 FIG.
Hereinafter, the DC / DC voltage converter in Embodiment 4 of this invention is demonstrated using FIGS. 19-23.
The DC / DC voltage converter of the present embodiment is configured to adjust the switching frequency of the field effect transistor based on the energy transfer capacitor C0, the inductor L, and the temperature of the field effect transistor that is the power semiconductor unit. Is the same as that of the DC / DC voltage converter of the first embodiment. Hereinafter, the description of the same configuration, operation, and action as in the first embodiment will be omitted as appropriate.

First, FIG. 19 is a diagram showing the configuration of the conversion main circuit 2 according to this embodiment. The FET 1 in the conversion main circuit 2 is provided with a temperature detection diode 271 in the vicinity of the semiconductor chip or on the component surface of the semiconductor chip, and detects the semiconductor chip temperature of the FET 1. Similarly, a temperature detection diode 273 is formed in the vicinity of the semiconductor chip of the FET 3 or on the constituent surface of the semiconductor chip, and detects the semiconductor chip temperature of the FET 3.
An inductor temperature detector 28 and a capacitor temperature detector 29 for detecting respective temperatures are attached to the inductor L and the energy transfer capacitor C0, and each temperature is detected.

  FIG. 20 is a block diagram showing the configuration of the control unit 3 according to this embodiment. The control unit 3 includes an external primary terminal voltage V1, a secondary terminal voltage V2, an inductor current IL, a DC / DC voltage conversion ratio instruction from an external device (not shown), and the conversion main circuit. 2, signals from the temperature detection diodes 271 and 273, the inductor temperature detector 28, and the capacitor temperature detector 29 are input.

Specifically, the signal of the inductor temperature detector 28 is input to the inductor temperature calculation circuit 31 and outputs the inductor temperature TmL. The signal of the capacitor temperature detector 29 is input to the capacitor temperature calculation circuit 32, and the capacitor temperature TmC is output.
The signals of the temperature detection diodes 271 and 273 are input to the semiconductor chip temperature calculation circuit 33, and the semiconductor chip temperature Tmj, which is the higher one of FET1 or FET3, is output.
The temperature detecting diode has a property that the voltage VF between the anode At and the cathode Kt varies depending on the temperature of the PN junction portion under the condition that a predetermined forward bias current is flowing. The semiconductor chip temperature calculation circuit 33 calculates the semiconductor chip temperatures of the FET1 and FET3 using this property.
For convenience, the semiconductor chip temperatures of FET2 and FET4 are not detected. However, this is not necessarily the case, and the semiconductor chip temperatures of all field effect transistors may be detected. Only one semiconductor chip temperature may be detected.

Subsequently, the temperatures TmL, TmC, and Tmj are input to the frequency adjuster 34 that is a switching frequency adjusting unit. The frequency adjuster 34 selects an appropriate value of the switching frequency of the field effect transistors FET1, FET2, FET3, and FET4 based on these input temperatures.
The appropriate value is selected by adjusting the switching frequency to be gradually increased when the temperature of the inductor L or the temperature of the energy transfer capacitor C0 becomes high and approaches the upper limit of the specified operating temperature range.

  This will be described with reference to FIG. FIG. 21A is a schematic diagram for explaining the relationship between the switching frequency fc, the amount of heat generated by the inductor L, and the energy transfer capacitor C0. As shown in FIG. 21A, the heat generation amount increases as the switching frequency fc decreases, and the heat generation amount decreases as the switching frequency fc increases. As described in the first embodiment, this is because the higher the switching frequency, the smaller the amplitude of the alternating current, which is the ripple current component, and the more the loss, that is, the heat generation amount. Similarly, the amount of heat generated by the energy transfer capacitor C0 is reduced because the amplitude of the alternating current is reduced. The reason why the heat generation amount of the inductor L and the energy transfer capacitor C0 decreases at the power root as the switching frequency fc increases is that the heat generation amount mainly depends on the power of the alternating current.

FIG. 21B is a schematic diagram for explaining the relationship between the switching frequency fc and the heat generation amount of the power semiconductor unit. As shown in FIG. 21B, the lower the switching frequency fc, the smaller the heat generation amount, and the higher the switching frequency fc, the larger the heat generation amount. This is because, as the switching frequency is higher, the number of times of switching per predetermined time increases, so that the switching loss that occurs in the semiconductor switch element and the reverse recovery loss that occurs in the rectifier element increase. The field effect transistor is a bidirectional conduction device in which a semiconductor switching element and a rectifying element are integrated.
From the characteristics shown in FIGS. 21A and 21B, the inductor L and the energy transfer capacitor C0 are likely to have a higher temperature as the switching frequency fc is lower, and the semiconductor switch element and the rectifying element are higher as the switching frequency fc is higher. easy.

From this characteristic, the frequency adjuster 34 operates as follows. FIG. 22 is a block diagram showing a detailed configuration of the frequency adjuster 34. In the figure, 341 is a frequency adjustment table L, 342 is a frequency adjustment table C, and 343 is a frequency adjustment table j. Reference numeral 344 denotes selection processing means.
The inductor temperature TmL from the inductor temperature calculation circuit 31 is input to the frequency adjustment table L341, and the switching frequency candidate fcl suitable for TmL is output by referring to the table. In this table, the initial value fc0 is set when the temperature is lower than the threshold value Tl_F in the range of the operating temperature range Tl_min to Tl_max of the inductor L, and is gradually increased until fcl_max is reached corresponding to Tl_max when the temperature is higher than the threshold value Tl_F. Yes. This is intended to gradually increase the switching frequency at high temperatures in accordance with the characteristic that the amount of heat generated by the inductor L decreases when the switching frequency in FIG.
Here, the initial value fc0 is a frequency that is equal to or higher than the upper limit of the audible frequency, and none of the inductor L, the energy transfer capacitor C0, and the power semiconductor unit is at high temperature, and switching is performed when normal operation is performed without fear of overheating. This is the basic frequency setting.

  Similarly, the capacitor temperature TmC from the capacitor temperature calculation circuit 32 is input to the frequency adjustment table C342, and a switching frequency candidate fcc suitable for TmC is output by referring to the table. In this table, the initial value fc0 is set when the temperature is lower than the threshold value Tc_F in the range of the operating temperature range Tc_min to Tc_max of the capacitor C, and gradually increases until fcc_max is reached corresponding to Tc_max when the temperature is higher than the threshold value Tc_F. Yes. Similarly to the case of the inductor L described above, it is desired to gradually increase the switching frequency at a high temperature in accordance with the characteristic that the calorific value of the energy transfer capacitor C0 decreases when the switching frequency is high.

Further, the semiconductor chip temperature Tmj that is the highest detected temperature from the semiconductor chip temperature calculation circuit 33 is input to the frequency adjustment table j343, and a switching frequency candidate fcj suitable for Tmj is output by referring to the table. In this table, the initial value fcj_max is set to be gradually decreased from the operating temperature range Tj_min to Tj_max of the power semiconductor unit when the temperature is lower than the threshold value Tj_F, and gradually increased until fcj_min corresponding to Tj_max when the temperature is higher than the threshold value Tj_F. It is said.
This is because when the switching frequency in FIG. 21B is low, it is desired to gradually decrease the switching frequency at a high temperature in accordance with the characteristic that the amount of heat generated by the power semiconductor unit decreases.

Subsequently, the selection processing means 344 receives the switching frequency candidates fcl, fcc, and fcj, and selects and outputs the switching frequency instruction value fc_ref according to the processing flow shown in FIG.
In the processing flow of FIG. 23, first, in step S101, a larger one of fcl and fcc is set to the switching frequency provisional instruction value fc_tmp. Next, in step S102, the magnitude relationship between the switching frequency provisional instruction value fc_tmp and the switching frequency candidate fcj is compared. If fc_tmp ≦ fcj, the process proceeds to step S104. On the other hand, if fc_tmp> fcj, the process proceeds to step S103. In step S103, fcj is set to the switching frequency provisional instruction value fc_tmp.
Next, in step S104, the provisional instruction value fc_tmp is set to the switching frequency instruction value fc_ref. This fc_ref is output from the selection processing means 344.

  In these operations, the branching in step S102 and the setting of fcj to the switching frequency provisional instruction value fc_tmp in step S103 are performed even when the inductor L or the energy transfer capacitor C0 is at a high temperature and it is desired to gradually increase the switching frequency. If the semiconductor chip temperature of the power semiconductor unit is also high and the switching frequency is to be gradually decreased, the latter is preferentially selected as the switching frequency instruction value.

Next, the switching frequency instruction value fc_ref from the selection processing unit 344 is input to the gate PWM generation unit 11 b as an output of the frequency adjuster 34. Similarly to the gate PWM generation unit 11 of the first embodiment shown in FIG. 9, the gate PWM generation unit 11b performs pulse width modulation corresponding to the value of Lduty, and gate drive signals 8 (Gate1, Gate2, Gate3, Gate4). And generate and output rectangular gate PWM signals Gpwm1, Gpwm2, Gpwm3, and Gpwm4.
At this time, the gate PWM signal is generated by setting the frequency of the carrier wave, that is, the switching frequency to the switching frequency instruction value fc_ref.
Since the configuration and operation of the control unit 3 excluding the contents described above are the same as those of the control unit 3 described in the first embodiment, description thereof will be omitted.

  As described above, according to the DC / DC voltage conversion device 1 of the fourth embodiment, the switching frequency of the power semiconductor unit is adjusted based on the temperature of the energy transfer capacitor, inductor, and power semiconductor unit of the conversion main circuit. To do. For this reason, even if the energy transfer capacitor or inductor is configured using a resin material having relatively low heat resistance compared to the power semiconductor unit, the power semiconductor is The switching frequency is gradually increased within a range where the increase in the temperature of the semiconductor chip of the unit is not a problem, and it is possible to protect the capacitor and the inductor from being damaged due to overheating.

Embodiment 5 FIG.
Hereinafter, a DC / DC voltage conversion apparatus according to Embodiment 5 of the present invention will be described with reference to FIGS.
In this example, the DC / DC voltage converter is different from the one described in the first embodiment, and two sets of two switches in which the switch-on and off states at the same time have a complementary relationship form a pair. Is provided with a conversion main circuit 2 having three sets of power semiconductor units capable of conducting current.
FIG. 24 shows a conversion main circuit 2 having three power semiconductor units. The conversion main circuit 2 in FIG. 24 includes field effect transistors FET1, FET2, FET3, FET4, FET5, FET6, primary side smoothing capacitor C1, secondary side smoothing capacitor C2, and energy transfer capacitors C0a, C0b, which are power semiconductor units. And an inductor L.
All power semiconductor units are connected in series. Here, the voltage at the FET4 side connection terminal of the inductor L is represented as VL.

  The field effect transistor is controlled to be switched on and off in accordance with the gate drive signal 8 from the control unit 3. The control unit 3 is similar to FIG. 9 of the first embodiment, and the on-duty target amount Lduty calculated by the conversion control unit 10 is input to the gate PWM generation unit 11. The gate PWM generator 11 performs pulse width modulation in accordance with the value of Lduty, and gate drive signals 8 (Gate1, Gate2, Gate3, FIG. 27A) shown in FIG. 25 (a), FIG. 26 (a), and FIG. A rectangular gate PWM signal Gpwm1, Gpwm2, Gpwm3, Gpwm4, Gpwm5, Gpwm6, which is an original signal of Gate4, Gate5, and Gate6) is generated and output.

Here, FIG. 25 illustrates a waveform when the on-duty of the gate drive signal is less than 100/3% during the step-up operation. (A) shows the gate drive signal, (b) shows the inductor current IL, and (c) shows the switching mode and its switching timing.
Similarly, FIG. 26 shows that when the on-duty of the gate drive signal is 100/3% or more and less than 100 × (2/3)% during the boost operation, FIG. 27 shows the on-duty of the gate drive signal during the boost operation. Shows a waveform when is 100 × (2/3)% or more. (A) shows the gate drive signal, (b) shows the inductor current IL, and (c) shows the switching mode and its switching timing.
The inductor current IL has a positive polarity in which the inductor L flows from the positive terminal P1 side connection terminal to the FET4 side connection terminal.

The gate PWM signals Gpwm1, Gpwm2, Gpwm3, Gpwm4, Gpwm5, and Gpwm6 are input to the gate drive circuit 12. The gate drive circuit 12 outputs a gate drive signal 8 for turning on and off the semiconductor switch element according to the logic of the gate PWM signal.
Gpwm1 corresponds to FET1, Gpwm2 corresponds to FET2, Gpwm3 corresponds to FET3, Gpwm4 corresponds to FET4, Gpwm5 corresponds to FET5, and Gpwm6 corresponds to FET6, and controls the switching operation of the field effect transistor.

Although not shown, the gate drive circuit 12 includes a gate drive circuit (1) 121, a gate drive circuit (2) 122, a gate drive circuit (3) 123, It is divided into a gate drive circuit (4) 124, a gate drive circuit (5) 125, and a gate drive circuit (6) 126.
The gate power supply circuit 13 generates six mutually isolated power supply voltages VD1, VD2, VD3, VD4, VD5, and VD6 and supplies them to the respective gate drive circuits 121 to 126.

Next, voltage conversion control by the gate drive signal 8 will be described.
During boost operation:
1) On duty less than 100/3%:
First, the case where the on-duty of the gate drive signal is less than 100/3% during the boosting operation will be described. In FIG. 25A, FET1 turns on when the Gate1 signal is high, FET2 turns on when the Gate2 signal is high, and FET3 turns on when the Gate3 signal is high, and a current flows from the drain toward the source. Further, the FET 4 is turned on when the Gate 4 signal is high, the FET 5 is turned on when the Gate 5 signal is high, and the FET 6 is turned on when the Gate 6 signal is high. Instead of the parasitic diode inherent in the FET 6, it flows through the transistor portion.

Here, the Gate 1 signal and the Gate 6 signal, the Gate 2 signal and the Gate 5 signal, and the Gate 3 signal and the Gate 4 signal are complementary signals in which logics of high and low are opposite to each other. As shown in FIG. 25A, the gate drive signal 8 has three pairs of signals as complementary signals, and the phase difference between them is equal.
At this time, the high and low logic combinations of the gate drive signals from Gate 1 to Gate 6 are classified into four types of switching modes E, F, G, and H, and H → E → G → E → F → E → H It switches in order.

In switching mode H, FET3, FET5, FET6 are on, FET1, FET2, FET4 are off,
The current flows through the path of the positive terminal P1, the inductor L, the FET 3, the energy transfer capacitor C0a, the FET 5, the FET 6, the positive terminal P2, the electrical device 5, and the negative terminal N2, and the energy is discharged from the energy transfer capacitor C0a. To do.
Further, since FET3, FET5, and FET6 are on and current is conducted, the potential of the FET3 side connection terminal of the energy transfer capacitor C0a is about VL, and the potential of the FET5 side connection terminal is about V2.
Therefore, the voltage VL at the connection terminal of the inductor L on the FET 4 side is (V2−Vc0a). Here, Vc0a is a voltage across the energy transfer capacitor C0a. The difference between the voltage VL at the FET4 side connection terminal of the inductor L and the voltage at the positive side terminal P1 side connection terminal is (V1−V2 + Vc0a).

In switching mode E, FET4, FET5, FET6 are on, FET1, FET2, FET3 are off,
The current flows through the path of the positive terminal P1, the inductor L, the FET 4, the FET 5, the FET 6, the positive terminal P2, the electrical device 5, and the negative terminal N2, and the energy accumulated in the inductor L is released.
Further, since FET4, FET5, and FET6 are on and current is conducted, the voltage VL is approximately V2. The difference between the voltage VL at the FET4 side connection terminal of the inductor L and the voltage at the connection terminal on the positive side terminal P1 side becomes negative at (V1−V2), and the inductor current IL is in the negative direction when IL ≧ 0. Change towards.

In switching mode F, FET1, FET4, FET5 are on, FET2, FET3, FET6 are off,
The current flows through the path of the positive terminal P1, the inductor L, the FET 4, the FET 5, the energy transfer capacitor C0b, the FET 1, and the negative terminal N1, and the energy is stored in the energy transfer capacitor C0b. A voltage across the smoothing capacitor C2 is applied to the electric device 5, and energy is supplied from the smoothing capacitor C2.
Further, since FET1, FET4, and FET5 are on and current is conducted, the potential of the FET5 side connection terminal of the energy transfer capacitor C0b is about VL, and the potential of the FET1 side connection terminal is about Vcom = 0.
Therefore, the voltage VL of the inductor L on the FET4 side connection terminal is VL = Vc0b. Here, Vc0b is a voltage across the energy transfer capacitor C0b. The difference between the voltage VL at the FET4 side connection terminal of the inductor L and the voltage at the connection terminal on the positive side terminal P1 side is (V1−Vc0b).

In switching mode G, FET2, FET4, FET6 are on, FET1, FET3, FET5 are off,
The current flows through the path of the positive terminal P1, the inductor L, the FET 4, the energy transfer capacitor C0a, the FET 2, the energy transfer capacitor C0b, the FET 6, the positive terminal P2, the electrical device 5, and the negative terminal N2. It is stored in the transfer capacitor C0a and discharged from the energy transfer capacitor C0b.
Since the FET2, FET4, and FET6 are on and the current is conducted, the potential of the FET4 side connection terminal of the energy transfer capacitor C0a is approximately VL, and the potential of the FET2 side connection terminal is the FET2 side of the energy transfer capacitor C0b. It becomes almost equal to the potential of the connection terminal. Further, the potential of the FET6 side connection terminal of the energy transfer capacitor C0b is approximately V2.
Therefore, the voltage VL at the connection terminal of the inductor L on the FET 4 side is (V2−Vc0b + Vc0a). The difference between the voltage VL at the FET4 side connection terminal of the inductor L and the voltage at the connection terminal on the positive side terminal P1 side is (V1− (V2−Vc0b + Vc0a)).

Here, the on-duty of the Gate 1 signal, the Gate 2 signal, and the Gate 3 signal is equal. From this operation, the voltages VL in the switching modes F, G, and H are equal in terms of time average, and Vc0b = (V2−Vc0b + Vc0a) = V2−Vc0a. Therefore, Vc0b = (2/3) · V2, and Vc0a = (1/3) · V2.
From this, the potential difference between both ends of the inductor L, the switch-on time ton and the switch-off time toff of the FET1, FET2, and FET3 are expressed by the following relationship.

Switching modes F, G, H: L · ILrpl = ton · (V1− (2/3) · V2) ·· (8a)
Switching mode E: L.ILrpl = -toff. (V1-V2) .. (8b)

  Since the left sides of Expression (8a) and Expression (8b) are equal, the following relationship is established.

  ton · (V1− (2/3) · V2) = toff · (V2−V1) (9)

The above formula (9) can be summarized with respect to the primary terminal voltage V1 and the secondary terminal voltage V2 as follows.

(V2 / V1) = (ton + toff) / (ton + toff-ton + ton 2/3) = 1 / (1-ton / T) (10)
However, ton + toff = T / 3

In the above equation (10), the period T indicates a period in which the switching mode is switched in the order of H → E → G → E → F → E → H, and the ton period is 3 times in the period T. , Toff period is included three times. Ton + toff is T / 3. The left side (V2 / V1) of Expression (10) is a DC / DC voltage conversion ratio.
In an operation in which the on-duty of the gate drive signal shown in FIG. 25 is less than 100/3%, (ton / T) <(1/3), and when applied to Equation (10), the DC / DC voltage conversion ratio is Less than 3/2. Therefore, V2 <(V1 · 3/2).

  From these, in the switching modes F, G, and H, the voltage VL at the connection terminal on the FET4 side of the inductor L is VL = V2 · (2/3) <V1, and the voltage at the connection terminal on the positive terminal P1 side of the inductor L is V1. It is. Therefore, the potential difference between both ends of the inductor L becomes positive with respect to VL, and the inductor current IL increases in the positive direction. Further, as described above, in the switching mode E, the inductor current IL changes in the negative direction when IL ≧ 0.

As described above, in the switching mode H → E → G → E → F → E → H,
In the switching modes F, G, and H, the inductor current IL changes so as to increase further in the positive direction from the state of IL ≧ 0,
In the switching mode E, the inductor current IL changes toward the state where IL <0.
From this, the increase and decrease of the inductor current IL are repeated three times in the T / 3 period over the switching period T of the field effect transistor.
Accordingly, an alternating current having a frequency three times that of the switching frequency of the field effect transistor is conducted to the inductor L.

2) When the on-duty is 100/3% or more and less than 100 × (2/3)%:
Next, a case where the on-duty of the gate drive signal is 100/3% or more and less than 100 × (2/3)% during the boosting operation will be described.
In FIG. 26A, FET1 is turned on when the Gate1 signal is high, FET2 is turned on when the Gate2 signal is high, and FET3 is turned on when the Gate3 signal is high, and a current flows from the drain toward the source.
Further, the FET 4 is turned on when the Gate 4 signal is high, the FET 5 is turned on when the Gate 5 signal is high, and the FET 6 is turned on when the Gate 6 signal is high. Instead of the parasitic diode inherent in the FET 6, it flows through the transistor portion.

The Gate1 signal and Gate6 signal, the Gate2 signal and Gate5 signal, the Gate3 signal and Gate4 signal are complementary signals whose logics of high and low are opposite to each other, and the gate drive signal 8 has three kinds of signals that form a pair as complementary signals. Thus, the mutual phase differences are equally spaced.
At this time, the high and low logic combinations of the gate drive signals from Gate 1 to Gate 6 are classified into six types of switching modes F, G, H, I, J, and K, and G → J → H → K → F. Switching in order of → I → G.

  The state of each field effect transistor in the switching modes F, G, and H, the current conduction path, and the voltage VL at the FET4 side connection terminal of the inductor L are set such that the on-duty of the gate drive signal during the boosting operation is 100/3%. Since it is the same as the case where it is less than, description is abbreviate | omitted.

In switching mode I, FET1, FET2, FET4 are on, FET3, FET5, FET6 are off,
The current flows through the path of the positive terminal P1, the inductor L, the FET 4, the energy transfer capacitor C0a, the FET 2, the FET 1, and the negative terminal N1, and the energy is stored in the energy transfer capacitor C0a.
The voltage across the smoothing capacitor C2 is applied to the electric device 5, and energy is supplied from the smoothing capacitor C2.
Since FET1, FET2, and FET4 are turned on and current is conducted, the potential of the FET3 side connection terminal of the energy transfer capacitor C0a is approximately Vcom = 0, and the potential of the FET4 side connection terminal is approximately VL. Therefore, the voltage VL at the FET4 side connection terminal of the inductor L is Vc0a. The difference between the voltage VL at the FET4 side connection terminal of the inductor L and the voltage at the connection terminal on the positive side terminal P1 side is (V1−Vc0a).

In switching mode J, FET2, FET3, FET6 are on, FET1, FET4, FET5 are off,
The current flows in the path of the positive terminal P1, the inductor L, the FET 3, the FET 2, the energy transfer capacitor C0b, the FET 6, the positive terminal P2, the electrical device 5, and the negative terminal N2, and energy is transferred from the energy transfer capacitor C0b. Released.
Since FET2, FET3, and FET6 are turned on and the current is conducted, the voltage VL at the FET4 side connection terminal of the inductor L becomes equal to the potential of the low potential side terminal connected to the FET2 of the energy transfer capacitor C0b. Further, the potential of the high potential side terminal connected to the FET 6 of the energy transfer capacitor C0b becomes equal to the voltage V2 of the positive side terminal P2. Therefore, the voltage VL at the FET4 side connection terminal of the inductor L is VL = V2−Vc0b, and the difference between the voltage VL of the inductor L and the voltage at the connection terminal on the positive side terminal P1 side is (V1− (V2−Vc0b)). It is.

In switching mode K, FET1, FET3, FET5 are on, FET2, FET4, FET6 are off,
The current flows in the path of the positive terminal P1, the inductor L, the FET 3, the energy transfer capacitor C0a, the FET 5, the energy transfer capacitor C0b, and the negative terminal N1, and the energy is discharged from the energy transfer capacitor C0a. Stored in capacitor C0b. A voltage across the smoothing capacitor C2 is applied to the electric device 5, and energy is supplied from the smoothing capacitor C2.

Since the FET1, FET3, and FET5 are turned on and current is conducted, the potential of the FET4 side connection terminal of the energy transfer capacitor C0a is equal to the potential of the FET5 side connection terminal of the energy transfer capacitor C0b.
Further, the potential of the FET3 side connection terminal of the energy transfer capacitor C0a is approximately VL. The potential of the FET1 side connection terminal of the energy transfer capacitor C0b is approximately Vcom = 0.
Therefore, the voltage VL of the connection terminal of the inductor L on the FET 4 side is VL = (Vc0b−Vc0a). The difference between the voltage VL of the inductor L and the voltage at the connection terminal on the positive terminal P1 side is (V1- (Vc0b-Vc0a)).

Here, the on-duty of the Gate 1 signal, the Gate 2 signal, and the Gate 3 signal is equal. From this operation, the voltages VL in the switching modes F, G, and H are equal in terms of time average and Vc0b = (V2−Vc0b + Vc0a) = V2−Vc0a.
Further, the voltages VL in the switching modes I, J, and K are equal in terms of time average, and the relationship is Vc0a = (V2−Vc0b) = (Vc0b−Vc0a). Therefore, Vc0b = (2/3) · V2 and Vc0a = (1/3) · V2 as in the case where the on-duty of the gate drive signal is less than 100/3%.
From this, the potential difference between both ends of the inductor L, the switch-on time ton and the switch-off time toff of the FET1, FET2, and FET3 are expressed by the following relationship.

Switching modes F, G, H:
L · ILrpl = (T / 3−ton + T / 3) · (V1− (2/3) · V2) = ((2/3) T−ton) · (V1− (2/3) · V2)・ (11a)
Switching modes I, J, K:
L.ILrpl =-(ton-T / 3). (V1- (1/3) .V2) .. (11b)
However, ton + toff = T

  Since the left sides of Expression (11a) and Expression (11b) are equal, the following relationship is established.

  ((2/3) T-ton) * (V1- (2/3) * V2) =-(ton-T / 3) * (V1- (1/3) * V2) (12)

  The above equation (12) can be summarized with respect to the primary terminal voltage V1 and the secondary terminal voltage V2 as follows.

(V2 / V1) = T / (T-ton) = 1 / (1-ton / T) (13)
However, ton + toff = T

In the above equation (13), the period T indicates a period in which the switching mode G → J → H → K → F → I → G makes a round, and the ton period is once in the period T. , Toff period is included once. Ton + toff is T. The left side (V2 / V1) of Expression (13) is a DC / DC voltage conversion ratio.
In the operation in which the on-duty of the gate drive signal shown in FIG. 26 is 100/3% or more and less than 100 × (2/3)%, (1/3) ≦ (ton / T) <(2/3). When applied to the equation (13), the DC / DC voltage conversion ratio is 3/2 or more and less than 3. Therefore, (V1 · 3/2) ≦ V2 <(3 · V1).

From these, in the switching modes F, G, and H, the voltage VL of the connection terminal on the FET4 side of the inductor L is in the range of V1 to 2 · V1, and the voltage of the connection terminal on the positive terminal P1 side of the inductor L is V1. Therefore, the potential difference between both ends of the inductor L with respect to VL becomes negative, and the inductor current IL changes in the negative direction in a state where IL ≧ 0.
In the switching modes I, J, and K, the voltage VL at the connection terminal on the FET4 side of the inductor L is in the range of V1 / 2 to V1, and the voltage at the connection terminal on the positive terminal P1 side of the inductor L is V1. Therefore, the potential difference between both ends of the inductor L becomes positive with respect to VL, and the inductor current IL increases in the positive direction.

As described above, in the switching mode G → J → H → K → F → I → G,
In the switching modes F, G, and H, the inductor current IL changes from the state of IL ≧ 0 toward the state of IL <0,
In the switching modes I, J, and K, the inductor current IL further changes to increase in the positive direction.
From this, the increase and decrease of the inductor current IL are repeated three times in the T / 3 period over the switching period T of the field effect transistor.
Accordingly, an alternating current having a frequency three times that of the switching frequency of the field effect transistor is conducted to the inductor L.

3) When the on-duty is 100 x (2/3)% or more:
Next, a case where the on-duty of the gate drive signal is 100 × (2/3)% or more during the boosting operation will be described.
In FIG. 27A, FET1 is turned on when the Gate1 signal is high, FET2 is turned on when the Gate2 signal is high, and FET3 is turned on when the Gate3 signal is high, and a current flows from the drain toward the source.
Further, the FET 4 is turned on when the Gate 4 signal is high, the FET 5 is turned on when the Gate 5 signal is high, and the FET 6 is turned on when the Gate 6 signal is high. Instead of the parasitic diode inherent in the FET 6, it flows through the transistor portion.

The Gate1 signal and Gate6 signal, the Gate2 signal and Gate5 signal, the Gate3 signal and Gate4 signal are complementary signals whose logics of high and low are opposite to each other, and the gate drive signal 8 has three types of signals that form a pair as complementary signals. Thus, the mutual phase difference is equally spaced.
At this time, the high and low logic combinations of the gate drive signals from Gate 1 to Gate 6 are classified into four types of switching modes I, J, K, and M. M → K → M → I → M → J → M It switches in order.

  The state of each field effect transistor in switching modes I, J, and K, the current conduction path, and the voltage VL at the FET4 side connection terminal of the inductor L have an on-duty of the gate drive signal of 100/3% during the above boost operation. Since it is the same as the case where it is less than 100x (2/3)% by the above, description is abbreviate | omitted.

In switching mode M, FET1, FET2, FET3 are on, FET4, FET5, FET6 are off,
The current flows in the path of the positive terminal P1, the inductor L, the FET 3, the FET 2, the FET 1, and the negative terminal N1, and energy is stored in the inductor L.
In addition, since FET3, FET2, and FET1 are turned on and the current is conducted, the voltage VL becomes approximately Vcom = 0. Therefore, the voltage VL of the connection terminal on the FET3 side of the inductor L and the connection terminal on the positive terminal P1 side. The difference from the voltage becomes positive at (V1-0), and the inductor current IL further increases in the positive direction.
A voltage across the smoothing capacitor C2 is applied to the electric device 5, and energy is supplied from the smoothing capacitor C2.

Here, the on-duty of the Gate 1 signal, the Gate 2 signal, and the Gate 3 signal is equal. From this operation, the voltages VL in the switching modes I, J, and K are equal in terms of time average, and the relationship is Vc0a = (V2−Vc0b) = (Vc0b−Vc0a).
Therefore, Vc0b = (2/3) · V2, Vc0a = (1/3) · V2 as in the case where the on-duty of the gate drive signal is 100/3% or more and less than 100 × (2/3)%. It becomes.
From this, the potential difference between both ends of the inductor L, the switch-on time ton and the switch-off time toff of the FET1, FET2, and FET3 are expressed by the following relationship.

Switching mode M: L.ILrpl = (T / 3-toff) .V1 .. (14a)
Switching modes I, J, K: L.ILrpl = -toff. (V1- (1/3) .V2) (14b)
However, ton + toff = T

  Since the left sides of Expression (14a) and Expression (14b) are equal, the following relationship is established.

  (T / 3-toff) .V1 = -toff. (V1- (1/3) .V2) .. (15)

  The above formula (15) can be summarized with respect to the primary terminal voltage V1 and the secondary terminal voltage V2 as follows.

(V2 / V1) = T / toff = T / (T-ton) = 1 / (1-ton / T)
(16)
However, ton + toff = T

In the above equation (16), the period T indicates a period in which the switching mode M → K → M → I → M → J → M is switched in order, and the ton period is once in the period T. A toff period is included once. Ton + toff is T. The left side (V2 / V1) of Expression (16) is a DC / DC voltage conversion ratio.
In the operation in which the on-duty of the gate drive signal shown in FIG. 27 is 100 × (2/3)% or more, (2/3) ≦ (ton / T), and when applied to Expression (16), DC / DC The voltage conversion ratio is 3 or more. Therefore, (3 · V1) ≦ V2.

From these, in the switching modes I, J, and K, the voltage VL at the FET4 side connection terminal of the inductor L = (V2 / 3) ≧ V1. The voltage of the positive terminal P1 side connection terminal of the inductor L is V1. Therefore, the potential difference between both ends of the inductor L with respect to VL becomes negative, and the inductor current IL changes in the negative direction in a state where IL ≧ 0.
As described above, in the switching mode M, the inductor current IL further increases in the positive direction.

As described above, in the switching mode M → K → M → I → M → J → M,
In switching modes I, J, and K, the inductor current IL changes from the state of IL ≧ 0 toward the state of IL <0,
In the switching mode M, the inductor current IL further increases in the positive direction from the state where IL ≧ 0.
From this, the increase and decrease of the inductor current IL are repeated three times in the T / 3 period over the switching period T of the field effect transistor.
Accordingly, an alternating current having a frequency three times that of the switching frequency of the field effect transistor is conducted to the inductor L.
In addition, the equations (10), (13), and (16) are equal, that is, the DC / DC voltage is continuously adjusted according to the change of the on-duty regardless of the on-duty. The conversion ratio is adjusted.

Next, the step-down operation will be described.
During step-down operation:
This example also has the symmetry of the operation at the time of step-up and step-down described in the first embodiment. The operation at the time of step-down in the present embodiment is such that the voltage generated by the electrical device 5 connected to the secondary side of the DC / DC voltage converter 1 is changed from V2 to V1 in the relationship of voltage V1 ≦ voltage V2. It converts and collect | recovers with the DC power supply 4. FIG.
The waveform of the gate drive signal 8 is shown in FIG. 25A, FIG. 26A, and FIG. 27A, and is the same as that during the boosting operation. That is,
FIG. 25A shows that when the on-duty of the gate drive signal is less than 100/3%,
FIG. 26A shows that when the on-duty of the gate drive signal is 100/3% or more and less than 100 × (2/3)%,
FIG. 27A shows the waveform of the gate drive signal when the on-duty of the gate drive signal is 100 × (2/3)% or more.

When the Gate 4 signal is high, the FET 4 is turned on, when the Gate 5 signal is high, the FET 5 is turned on, and when the Gate 6 signal is high, the FET 6 is turned on, and a current flows from the drain to the source.
In addition, FET1 is turned on when the Gate1 signal is high, FET2 is turned on when the Gate2 signal is high, and FET3 is turned on when the Gate3 signal is high. Instead of the parasitic diode inherent in the FET 3, it flows through the transistor portion.

The combination of high and low logic of the gate drive signals of Gate1 to Gate6 is that the on-duty of the gate drive signal is 100/3% or more in FIG. 25C when the on-duty of the gate drive signal is less than 100/3%. When the on-duty of the gate drive signal is 100 × (2/3)% or more, it is as shown in FIG. 27C when the gate drive signal on-duty is 100 × (2/3)% or more.
That is, there are eight switching modes: E, F, G, H, I, J, K, and M.

In switching mode E,
The current flows through the path of the positive terminal P 2 → FET 6 → FET 5 → FET 4 → inductor L → positive terminal P 1 → DC power supply 4 → negative terminal N 1, and energy is stored in the inductor L. Further, since FET4, FET5, and FET6 are turned on and current is conducted, the voltage VL is approximately V2. The difference between the voltage VL at the connection terminal on the FET4 side of the inductor L and the voltage at the connection terminal on the positive terminal P1 side becomes negative at (V1-V2), and the inductor current IL further decreases in the state where IL <0. To increase.

In switching mode F,
The current flows in the path of transition capacitor C0b → FET5 → FET4 → inductor L → positive terminal P1 → DC power supply 4 → negative terminal N1 → FET1, and energy is released from the energy transition capacitor C0b.
In addition, since FET1, FET4, and FET5 are turned on to conduct current, the voltage VL = Vc0b.

In switching mode G,
The current flows in the path of positive terminal P2 → FET6 → energy transfer capacitor C0b → FET2 → energy transfer capacitor C0a → FET4 → inductor L → positive electrode terminal P1 → DC power supply 4 → negative electrode terminal N1 and energy is energy. It is stored in the transfer capacitor C0b and discharged from the energy transfer capacitor C0a.
Further, since FET2, FET4, and FET6 are turned on and current is conducted, the voltage VL is approximately (V2−Vc0b + Vc0a).

In switching mode H,
The current flows in the path of the positive terminal P2, the FET 6, the FET 5, the energy transfer capacitor C0a, the FET 3, the inductor L, the positive terminal P1, the DC power supply 4, the negative terminal N1, and the energy is stored in the energy transfer capacitor C0a. It is done.
Further, since FET3, FET5, and FET6 are turned on and current is conducted, the voltage VL is approximately (V2−Vc0a).

In switching mode I,
The current flows in the path of energy transfer capacitor C0a → FET4 → inductor L → positive electrode side terminal P1 → DC power supply 4 → negative electrode side terminal N1 → FET1 → FET2, and energy is released from the energy transfer capacitor C0a.
Further, since FET1, FET2, and FET4 are turned on and current is conducted, the voltage VL is approximately Vc0a.

In switching mode J,
The current flows in the path of the positive side terminal P2, the FET 6, the energy transfer capacitor C0b, the FET 2, the FET 3, the inductor L, the positive side terminal P1, the DC power supply 4, the negative side terminal N1, and the energy is stored in the energy transfer capacitor C0b. It is done.
Further, since FET2, FET3, and FET6 are turned on to conduct current, the voltage VL is approximately (V2−Vc0b).

In switching mode K,
Current flows in the path of energy transfer capacitor C0b → FET5 → energy transfer capacitor C0a → FET3 → inductor L → positive terminal P1 → DC power supply 4 → negative terminal N1 → FET1, and energy flows from energy transfer capacitor C0b. The energy is transferred and stored in the energy transfer capacitor C0a.
Further, since FET1, FET3, and FET5 are turned on and current is conducted, the voltage VL is approximately (Vc0b-Vc0a).

In switching mode M,
The current flows in the path of inductor L → positive terminal P 1 → DC power supply 4 → negative terminal N 1 → FET 1 → FET 2 → FET 3, and energy is released from the inductor L.
Further, since FET1, FET2, and FET3 are turned on and current is conducted, the voltage VL is approximately Vcom = 0.
The difference between the voltage VL at the FET4 side connection terminal of the inductor L and the voltage at the connection terminal on the positive side terminal P1 is positive at (V1-0), and the inductor current IL is directed in the positive direction when IL <0. Change.

Subsequently, each range of the on-duty of the gate drive signal and switching of the corresponding switching mode will be described.
1) On duty less than 100/3%:
When the on-duty of the gate drive signal is less than 100/3%, as shown in FIG. 25 (c), the switching mode is switched in the order of H → E → G → E → F → E → H, and the circuit makes one cycle.
As in the step-up operation, the voltages VL in the switching modes F, G, and H are equal in terms of time average, and the relationship is Vc0b = (V2−Vc0b + Vc0a) = V2−Vc0a. Therefore, Vc0b = (2/3) · V2, and Vc0a = (1/3) · V2.
The potential difference between both ends of the inductor L, the switch-on time ton, the switch-off time toff, the primary terminal voltage V1, and the secondary terminal voltage V2 of the FET1, FET2, and FET3 are expressed by the following equations (8a), (8b), and ( 9) is established.

Therefore, the voltage conversion ratio (V2 / V1) of the DC / DC voltage conversion device 1 is represented by Expression (10).
In an operation in which the on-duty of the gate drive signal is less than 100/3%, ton / T <(1/3), and the DC / DC voltage conversion ratio is less than (3/2) when applied to the equation (10). . Therefore, V2 <(V1 × 3/2). That is, the primary side terminal voltage V1 is stepped down to a voltage higher than (2/3) times the secondary side terminal voltage V2 and lower than 1 time.

From these, in the switching modes F, G, and H, the voltage VL of the FET4 side connection terminal of the inductor L = (2/3) · V2 <V1, and the voltage of the positive terminal P1 side connection terminal of the inductor L is V1. Therefore, the potential difference between both ends of the inductor L becomes positive with respect to VL, and the inductor current IL increases in the positive direction.
In the switching mode E, it increases in the negative direction as described above.
As described above, in the switching mode H → E → G → E → F → E → H,
In the switching modes F, G, and H, the inductor current IL changes from the state of IL <0 toward the state of IL ≧ 0,
In the switching mode E, the inductor current IL increases further in the negative direction from the state of IL <0.
From this, the increase and decrease of the inductor current IL are repeated three times in the T / 3 period over the switching period T of the field effect transistor, and the inductor L has a frequency three times the switching frequency of the field effect transistor. An alternating current will be conducted.

2) When the on-duty is 100/3% or more and less than 100 × (2/3)%:
Next, when the on-duty of the gate drive signal is 100/3% or more and less than 100 × (2/3)%, as shown in FIG. 26C, the switching mode G → J → H → K → It changes in order of F->I-> G, and makes one round with the period T.
As in the step-up operation, the voltages VL in the switching modes F, G, and H are equal in time average, and Vc0b = (2/3) · V2 and Vc0a = (1/3) · V2.
The potential difference between both ends of the inductor L, the switch-on time ton, the switch-off time toff, the primary side connection terminal voltage V1, and the secondary side connection terminal voltage V2 of the FET1, FET2, and FET3 are expressed by the equations (11a), (11b), and The relationship (12) holds.

Therefore, the voltage conversion ratio (V2 / V1) of the DC / DC voltage converter 1 is represented by the equation (13).
In the operation in which the on-duty of the gate drive signal is 100/3% or more and less than 100 × (2/3)%, (1/3) ≦ (ton / T) <(2/3), and the equation (13) ), The DC / DC voltage conversion ratio is 3/2 or more and less than 3. Therefore, (V1 · 3/2) ≦ V2 <(3 · V1). That is, the primary terminal voltage V1 is stepped down to a voltage that is higher than (1/3) times and lower than (2/3) times the secondary side terminal voltage V2.

From these, in the switching modes F, G, and H, the voltage VL at the connection terminal on the FET4 side of the inductor L is in the range from V1 to 2 · V1, and the voltage at the connection terminal on the positive terminal P1 side of the inductor L is V1. . Therefore, the potential difference between both ends of the inductor L with respect to VL becomes negative, and the inductor current IL further increases in the negative direction.
In switching modes I, J, and K, the voltage VL at the FET4 side connection terminal of the inductor L is in the range of (1/2) · V1 to V1, and the voltage at the connection terminal on the positive side terminal P1 side of the inductor L is V1. is there. Therefore, the potential difference between both ends of the inductor L with respect to VL becomes positive, and the inductor current IL changes in the positive direction in a state where IL <0.

As described above, in the switching mode G → J → H → K → F → I → G,
In the switching modes F, G, and H, the inductor current IL increases from the state of IL <0 further in the negative direction,
In the switching modes I, J, and K, the inductor current IL changes from the state of IL <0 toward the state of IL ≧ 0.
From this, the increase and decrease of the inductor current IL are repeated three times in the T / 3 period over the switching period T of the field effect transistor, and the inductor L has a frequency three times the switching frequency of the field effect transistor. An alternating current will be conducted.

3) When the on-duty is 100 x (2/3)% or more:
Further, when the on-duty of the gate drive signal is 100 × (2/3)% or more, as shown in FIG. 27C, the switching modes M → K → M → I → M → J → M It switches and makes one round with the period T.
As in the step-up operation, the voltages VL in the switching modes I, J, and K are equal in time average, and the relationship is Vc0a = (V2−Vc0b) = (Vc0b−Vc0a). Therefore, Vc0b = (2/3) · V2, and Vc0a = (1/3) · V2.
The potential difference between both ends of the inductor L, the switch-on time ton, the switch-off time toff, the primary-side terminal voltage V1, and the secondary-side terminal voltage V2 of the FET1, FET2, and FET3 are expressed by the equations (14a), (14b), and ( The relationship of 15) is established.

Therefore, the voltage conversion ratio (V2 / V1) of the DC / DC voltage converter 1 is represented by the equation (16).
In an operation in which the on-duty of the gate drive signal is 100 × (2/3)% or more, (2/3) ≦ ton / T, and the DC / DC voltage conversion ratio is 3 or more when applied to the equation (16). . Therefore, (3 × V1) ≦ V2. That is, the primary side terminal voltage V1 is stepped down to a voltage lower than (1/3) times the secondary side terminal voltage V2.

From these, in switching modes I, J, and K, the voltage VL at the connection terminal on the FET4 side of the inductor L is V1 ≦ VL, and the voltage at the connection terminal on the positive terminal P1 side of the inductor L is V1. Therefore, the potential difference between both ends of the inductor L with respect to VL becomes negative, and the inductor current IL further increases in the negative direction.
In the switching mode M, as described above, the inductor current IL changes from the state of IL <0 toward the state of IL ≧ 0.

As described above, in the switching mode M → K → M → I → M → J → M,
In switching modes I, J, and K, the inductor current IL further increases in the negative direction,
In the switching mode M, the inductor current IL changes from the state of IL <0 toward the state of IL ≧ 0.
Therefore, the increase and decrease of the inductor current IL is repeated three times in the T / 3 period over the switching period T of the field effect transistor, and the inductor L has a frequency three times the switching frequency of the field effect transistor. AC current will be conducted.

As described above, the DC / DC voltage converter according to the fifth embodiment has a frequency that is three times higher than that of the switching frequency of the field-effect transistor in the inductor L in both cases of step-up and step-down. AC current is conducted.
Accordingly, since the frequency of the ripple current component of the inductor L is further increased as compared with the DC / DC voltage conversion device in the first embodiment, the inductance of the inductor L can be reduced, and the volume and weight of the inductor are reduced. Compared to the conventional technology, it is significantly reduced.

  As described as a modification of the first embodiment, when the frequency of the AC component flowing through the inductor L is set to be equal to or higher than the upper limit of the audible frequency, the switching frequency of the field effect transistor is set to be higher than that in the first embodiment. Since it may be set to a low value, there is an advantage that the switching loss and the like can be reduced as compared with the case of the first embodiment.

In addition, the same effects as those of the first embodiment can be obtained. That is, since the field effect transistor is made of a wide band gap semiconductor material, even if the output power capacity of the DC / DC voltage converter increases and the loss generated in the power semiconductor unit increases, the power semiconductor Since the heat-resistant temperature of the unit is increased, it is possible to realize a small and lightweight DC / DC voltage conversion device while expanding the output power capacity that can be handled and improving the power density.
In addition, it is possible to eliminate the generation of annoying audible noise, which is remarkable with the inductor L, the energy transfer capacitors C0a and C0b, and the smoothing capacitors C1 and C2.

As mentioned above, although the Example regarding this invention was demonstrated by Embodiment 1-Embodiment 5, these are only what illustrated the preferable Example of this invention.
The present invention is not limited to the configuration and operation of these embodiments, and may be implemented by changing other configurations and operations as long as they are within the scope of the present invention.

For example, the configuration of the conversion main circuit 2 described in FIGS. 3, 11, and 24 described in the first and fifth embodiments is an example, and is not necessarily limited thereto. The conversion main circuit of Embodiment 1 can be changed to the form shown in FIG. 28, for example.
However, in the circuit of FIG. 28, FET1 and FET2, and FET3 and FET4 are each set, and the pair of FETs forming each set are complemented and on / off control is performed.
Furthermore, the appearance shown in FIG. 12 is a good example in which the constituent members of the DC / DC voltage converter 1 are arranged, and may take other forms within the scope of the present invention depending on the volume and strength of each constituent member. Is.

1 DC / DC voltage converter, 2 conversion main circuit, 3 control unit, 4 DC power supply,
5 Electrical equipment, 8 Gate drive signal, 11, 11a, 11b Gate PWM generator,
12, 12a Gate drive circuit, 15 cooling heat sink, 19 power module,
23 circuit switcher, 25, 26 switch-off circuit,
271,273 Temperature detection diode, 28 Inductor temperature detector,
29 Capacitor temperature detector, 31 Inductor temperature calculator, 34 Frequency adjuster.

Claims (13)

A DC / DC voltage converter comprising a conversion main circuit and a control unit, and performing DC voltage conversion between a primary voltage and a secondary voltage higher than the primary voltage,
The conversion main circuit includes a primary side smoothing capacitor connected between the primary side positive side terminal and the negative side terminal and smoothing the primary side voltage; the secondary side positive side terminal and the negative side terminal; , A secondary side smoothing capacitor that smoothes the secondary side voltage, an energy transfer capacitor and inductor that stores and discharges energy, and a semiconductor that can perform on / off switching operation and reverse conduction operation 2n (n is an integer of 2 or more) units connected in series, and a power module formed by connecting between the positive side terminal and the negative side terminal on the secondary side,
The control unit divides the 2n semiconductor units into two pairs of n pairs, and has a complementary relationship in which on / off of the pair of semiconductor units constituting each pair is opposite to each other. And, the AC component of the current flowing through the inductor is controlled to be a frequency equal to or higher than the upper limit of the audible frequency at the n times the switching frequency for controlling the on / off of the semiconductor unit,
The energy transfer capacitor is connected between a terminal closest to the secondary positive electrode terminal and a terminal closest to the secondary negative electrode terminal in the pair of semiconductor units of each set,
The inductor is a DC / DC voltage converter that is connected between the connection point of the pair of semiconductor units and directly connected to each other and the positive terminal on the primary side. The power module is composed of four semiconductor units connected in series, first, second, third, and fourth, in order from the one connected to the negative terminal on the secondary side,
The control unit controls the first and fourth semiconductor units, the second and third semiconductor units as the pair, respectively.
The energy transfer capacitor is connected between a connection point of the first and second semiconductor units and a connection point of the third and fourth semiconductor units,
2. The DC / DC voltage converter according to claim 1, wherein the inductor is connected between a connection point of the second and third semiconductor units and the positive terminal on the primary side. The power module is composed of six first, second, third, fourth, fifth, and sixth semiconductor units connected in series in order from the one connected to the negative terminal on the secondary side. Configure
The control unit controls the first and sixth semiconductor units, the second and fifth semiconductor units, and the third and fourth semiconductor units as the pair, respectively.
The energy transfer capacitor includes a first capacitor connected between a connection point of the second and third semiconductor units and a connection point of the fourth and fifth semiconductor units, and the first and second capacitors. And a second capacitor connected between the connection point of the semiconductor unit and the connection point of the fifth and sixth semiconductor units,
2. The DC / DC voltage converter according to claim 1, wherein the inductor is connected between a connection point of the third and fourth semiconductor units and the positive terminal on the primary side. The DC / DC voltage converter according to any one of claims 1 to 3, wherein the semiconductor unit is a field effect transistor. The control unit makes the switching frequency equal to or higher than the upper limit of the audible frequency,
5. The DC / DC voltage converter according to claim 4, wherein the field effect transistor is formed of a wide band gap semiconductor having a band gap larger than that of silicon. The control unit makes the switching frequency equal to or higher than the upper limit of the audible frequency,
4. The semiconductor device according to claim 1, wherein the semiconductor unit includes an IGBT and a rectifier element formed of a wide band gap semiconductor connected in reverse parallel to the IGBT and having a band gap larger than that of silicon. The DC / DC voltage converter according to item. 7. The DC / DC voltage converter according to claim 5, wherein the wide band gap semiconductor is any one of silicon carbide, gallium nitride, and diamond. 8. The DC / DC according to claim 1, wherein the power module and the energy transfer capacitor and / or the inductor are arranged so as to overlap each other with a heat insulating thermal barrier structure interposed therebetween. DC voltage converter. 9. The DC / DC voltage converter according to claim 8, wherein the thermal barrier structure includes a heat sink whose cooling surface is in contact with the power module and the energy transfer capacitor and / or the inductor. The control unit adjusts the falling steepness when the gate signal to the semiconductor unit is lowered and the semiconductor unit is turned off based on an on-duty that is a ratio of an on-time of the semiconductor unit to a switching cycle. 10. The DC / DC voltage converter according to claim 1, further comprising an off signal adjusting unit. The off signal adjusting means includes a predetermined first set value regarding the falling steepness, a second set value smaller than the first set value, a predetermined first threshold value regarding the on-duty, and the first set value. Providing a second threshold greater than the threshold;
When the on-duty is less than the first threshold, the falling steepness is set as the first set value, and when the on-duty is increased to be equal to or higher than the second threshold, the falling steepness is set. Is switched to the second set value, and when the on-duty falls and becomes less than the first threshold value, the falling steepness is switched to the first set value. The DC / DC voltage converter according to claim 10. The control unit is configured to detect a temperature of the energy transfer capacitor, the inductor, and the semiconductor unit, and to set the switching frequency based on the detected temperature of the energy transfer capacitor, the inductor, and the semiconductor unit. 12. The DC / DC voltage converter according to claim 1, further comprising a switching frequency adjusting means for adjusting. The switching frequency adjusting means is configured to increase the switching frequency when the detection temperature of the energy transfer capacitor and the inductor is increased, and to decrease the switching frequency when the detection temperature of the semiconductor unit is increased. 13. The DC / DC voltage converter according to claim 12, wherein the switching frequency is adjusted.

Images