JP2011229129A - Inverter circuit and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverter circuit capable of eliminating variation in output voltage while saving power consumption, and a display device equipped with the inverter circuit.SOLUTION: In the inverter circuit composed of 3Tr2C, transistors Tr1 and Tr3 are provided between the gate of the transistor Tr2 and a low voltage line L1 and between the source of the transistor Tr2 and the low voltage line L1, the transistors Tr1 and Tr3 operating according to a potential difference between the voltages of an input voltage Vin and the low voltage line L1. Capacitive elements C1 and C2 are connected in series to the gate of the transistor Tr2, and connected in parallel to the source of the transistor Tr2.

Description

  The present invention relates to an inverter circuit that can be suitably applied to a display device using, for example, an organic EL (Electro Luminescence) element. Moreover, this invention relates to the display apparatus provided with the said inverter circuit.

  In recent years, in the field of display devices that perform image display, display devices using current-driven optical elements, such as organic EL elements, whose light emission luminance changes according to the value of a flowing current have been developed as light-emitting elements of pixels. Is being promoted. Unlike a liquid crystal element or the like, the organic EL element is a self-luminous element. Therefore, in a display device (organic EL display device) using an organic EL element, a gradation of color can be obtained by controlling a current value flowing through the organic EL element.

  In the organic EL display device, similarly to the liquid crystal display device, there are a simple (passive) matrix method and an active matrix method as its driving method. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display device. For this reason, active matrix systems are currently being actively developed. In this method, a current flowing through a light emitting element arranged for each pixel is controlled by a driving transistor.

  In the drive transistor described above, the threshold voltage Vth and mobility μ may change over time, and the threshold voltage Vth and mobility μ may vary from pixel to pixel due to variations in manufacturing processes. When the threshold voltage Vth and the mobility μ are different for each pixel, the current value flowing through the driving transistor varies from pixel to pixel. Therefore, even if the same voltage is applied to the gate of the driving transistor, the light emission luminance of the organic EL element varies. The uniformity of the screen is lost. In view of this, a display device incorporating a correction function for fluctuations in threshold voltage Vth and mobility μ has been developed (see, for example, Patent Document 1).

  Correction for variations in threshold voltage Vth and mobility μ is performed by a pixel circuit arranged for each pixel. For example, as shown in FIG. 36, the pixel circuit includes a drive transistor Tr100 that controls a current flowing through the organic EL element 111, a write transistor Tr200 that writes the voltage of the signal line DTL into the drive transistor Tr100, and a storage capacitor Cs. The circuit configuration is 2Tr1C. The drive transistor Tr100 and the write transistor Tr200 are formed of, for example, an n-channel MOS thin film transistor (TFT).

  32A to 32E show an example of a voltage waveform applied to the pixel circuit and an example of changes in the gate voltage Vg and the source voltage Vs of the drive transistor Tr100. FIG. 32A shows a state in which the signal voltage Vsig and the offset voltage Vofs are applied to the signal line DTL. FIG. 32B shows a state where a voltage Vdd for turning on the write transistor Tr200 and a voltage Vss for turning off the write transistor Tr200 are applied to the write line WSL. FIG. 32C shows a state where the high voltage VccH and the low voltage VccL are applied to the power supply line PSL. Further, in FIGS. 32D and 32E, the gate voltage Vg and the source voltage Vs of the drive transistor Tr100 change from time to time in response to voltage application to the power supply line PSL, the signal line DTL, and the write line WSL. Is shown.

  32A to 32E, the WS pulse P is applied to the write line WSL twice within 1H, the threshold correction is performed by the first WS pulse P, and the second WS pulse P is applied. It can be seen that mobility correction and signal writing are performed. That is, in FIGS. 32A to 32E, the WS pulse P is used not only for signal writing but also for threshold correction and mobility correction of the drive transistor Tr100.

JP 2008-083272 A

  Incidentally, in an active matrix display device, a horizontal driving circuit (not shown) for driving the signal line DTL and a writing scanning circuit (not shown) for sequentially selecting each pixel 113 are basically shift registers. (Not shown) is provided, and a buffer circuit (not shown) is provided for each stage corresponding to each column or each row of the pixels 113. For example, the buffer circuit in the writing scanning circuit is typically configured by connecting two inverter circuits in series. Here, for example, as shown in FIG. 37, the inverter circuit has a single-channel circuit configuration in which two n-channel MOS transistors Tr11 and Tr12 are connected in series. The inverter circuit 200 illustrated in FIG. 37 is inserted between a low voltage wiring L1 to which a low level voltage is applied and a high voltage wiring L2 to which a high level voltage is applied. The gate of the transistor Tr12 on the high voltage wiring L2 side is connected to the high voltage wiring L2, and the gate of the transistor Tr11 on the low voltage wiring L1 side is connected to the input terminal IN. Further, a connection point C between the transistor Tr11 and the transistor Tr12 is connected to the output terminal OUT.

  In the inverter circuit 200, for example, as shown in FIG. 38, when the voltage of the input terminal IN (input voltage Vin) is Vss, the voltage of the output terminal OUT (output voltage Vout) does not become Vdd, Vdd-Vth. That is, the output voltage Vout includes the threshold voltage Vth of the transistor Tr12, and the output voltage Vout is greatly affected by variations in the threshold voltage Vth of the transistor Tr12.

  Therefore, for example, as shown in the inverter circuit 300 of FIG. 39, the gate and the drain of the transistor Tr12 are electrically separated from each other, and a high voltage wiring to which a voltage Vdd2 (≧ Vdd + Vth) equal to or higher than the drain voltage Vdd is applied. It is conceivable to connect a gate to L3. Further, for example, a bootstrap type circuit configuration as shown in the inverter circuit 400 of FIG. 40 is conceivable. Specifically, the transistor Tr13 is inserted between the gate of the transistor Tr12 and the high voltage wiring L2, the gate of the transistor Tr13 is connected to the high voltage wiring L2, and the gate of the transistor Tr12 and the source of the transistor Tr13 are connected. A circuit configuration in which a capacitive element C10 is inserted between the point D and the connection point C is conceivable.

  However, in any of the circuits of FIGS. 37, 39, and 40, the transistors Tr11 and Tr12 are used until the input voltage Vin is high, that is, until the output voltage Vout is low. A current (through current) flows from the high voltage wiring L2 side toward the low voltage wiring L1 side. As a result, power consumption in the inverter circuit also increases. In the circuits of FIGS. 37, 39, and 40, for example, when the input voltage Vin is Vdd as shown in the portion surrounded by the broken line in FIG. 38B, the output voltage Vout is Vss. In other words, the peak value of the output voltage Vout varies. As a result, there is a problem that threshold correction and mobility correction of the drive transistor Tr100 in the pixel circuit 112 vary for each pixel circuit 112, and variations thereof become luminance variations.

  Note that the above-described problem does not occur only in the scanning circuit of the display device, and may occur in other devices as well.

  The present invention has been made in view of such problems, and an object of the present invention is to provide an inverter circuit capable of suppressing variations in output voltage while suppressing power consumption, and a display device including the inverter circuit. There is.

  A first inverter circuit according to the present invention includes a first transistor, a second transistor, and a third transistor that are of the same channel type, a first capacitor element, a second capacitor element, an input terminal, and an output terminal. is there. Here, the first transistor cuts off the electrical connection between the output terminal and the first voltage line according to the potential difference between the voltage of the input terminal (input voltage) and the voltage of the first voltage line or the corresponding potential difference. It is supposed to be. The second transistor cuts off the electrical connection between the second voltage line and the output terminal according to the potential difference between the gate voltage of the second transistor and the voltage (output voltage) of the output terminal or the corresponding potential difference. It is like that. The third transistor cuts off the electrical connection between the gate of the second transistor and the third voltage line in accordance with the potential difference between the input voltage and the voltage on the third voltage line or the potential difference corresponding thereto. . The first capacitive element and the second capacitive element are inserted in series between the input terminal and the gate of the second transistor, and an electrical connection point between the first capacitive element and the second capacitive element is an output terminal. Is electrically connected.

  A first display device of the present invention includes a display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix. In addition, a drive unit for driving each pixel is provided. The drive unit has a plurality of inverter circuits provided for each scanning line, and each inverter circuit in the drive unit includes the same components as the first inverter circuit.

  In the first inverter circuit and the first display device of the present invention, an ON / OFF operation is performed between the gate of the second transistor and the third voltage line according to the potential difference between the input voltage and the voltage of the third voltage line. A third transistor is provided. Further, a first transistor that is turned on and off according to a potential difference between the input voltage and the voltage of the first voltage line is provided between the source of the second transistor and the first voltage line. Thus, for example, when the gate voltages of the first transistor and the third transistor change from high to low, the on-resistances of the first transistor and the third transistor gradually increase, and the gates of the second transistor and The time required for the source to be charged to the voltage of the first voltage line and the third voltage line becomes longer. Further, for example, when the respective gate voltages of the first transistor and the third transistor change from low to high, the respective on-resistances of the first transistor and the third transistor gradually decrease, and the gate and source of the second transistor Is charged to the voltage of the first voltage line and the third voltage line. In the present invention, the first capacitor element and the second capacitor element are connected in series to the gate of the second transistor, and the first capacitor element and the second capacitor element are connected in parallel to the output terminal. Therefore, the transient is slower at the output terminal than at the gate of the second transistor. As a result, for example, when the gate voltage of each of the first transistor and the third transistor changes from high to low, the gate-source voltage of the second transistor becomes larger than the threshold voltage of the second transistor, and the second transistor Immediately thereafter, the first transistor and the third transistor are turned off. At this time, the output voltage becomes the voltage on the second voltage line side. For example, when the gate voltages of the first transistor and the third transistor change from low to high, the first transistor and the third transistor are turned on, and immediately after that, the second transistor is turned off. At this time, the output voltage becomes the voltage on the first voltage line side.

  A second inverter circuit of the present invention includes a first transistor, a second transistor, and a third transistor that are of the same channel type, a first capacitor element, a second capacitor element, an input terminal, and an output terminal. is there. Here, the gate of the first transistor is electrically connected to the input terminal, the drain or source of the first transistor is electrically connected to the first voltage line, and the first voltage line among the drain and source of the first transistor. The unconnected terminal is electrically connected to the output terminal. The drain or source of the second transistor is electrically connected to the second voltage line, and the terminal not connected to the second voltage line among the drain and source of the second transistor is electrically connected to the output terminal. The gate of the third transistor is electrically connected to the input terminal, the drain or source of the third transistor is electrically connected to the third voltage line, and the drain and source of the third transistor are not connected to the third voltage line. Is electrically connected to the gate of the second transistor. The first capacitive element and the second capacitive element are inserted in series between the input terminal and the gate of the second transistor, and an electrical connection point between the first capacitive element and the second capacitive element is an output terminal. Is electrically connected.

  A second display device of the present invention includes a display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix. In addition, a drive unit for driving each pixel is provided. The drive unit includes a plurality of inverter circuits provided for each scanning line, and each inverter circuit in the drive unit includes the same components as the second inverter circuit.

  In the second inverter circuit and the second display device of the present invention, a third transistor having the gate connected to the input terminal is provided between the gate of the second transistor and the third voltage line. Furthermore, a first transistor having a gate connected to the input terminal is provided between the source of the second transistor and the first voltage line. Thus, for example, when the gate voltages of the first transistor and the third transistor change from high to low, the on-resistances of the first transistor and the third transistor gradually increase, and the gates of the second transistor and The time required for the source to be charged to the voltage of the first voltage line and the third voltage line becomes longer. Further, for example, when the respective gate voltages of the first transistor and the third transistor change from low to high, the respective on-resistances of the first transistor and the third transistor gradually decrease, and the gate and source of the second transistor Is charged to the voltage of the first voltage line and the third voltage line. In the present invention, the first capacitor element and the second capacitor element are connected in series to the gate of the second transistor, and the first capacitor element and the second capacitor element are connected in parallel to the output terminal. Therefore, the transient is slower at the output terminal than at the gate of the second transistor. As a result, for example, when the gate voltage of each of the first transistor and the third transistor changes from high to low, the gate-source voltage of the second transistor becomes larger than the threshold voltage of the second transistor, and the second transistor Immediately thereafter, the first transistor and the third transistor are turned off. At this time, the output voltage becomes the voltage on the second voltage line side. For example, when the gate voltages of the first transistor and the third transistor change from low to high, the first transistor and the third transistor are turned on, and immediately after that, the second transistor is turned off. At this time, the output voltage becomes the voltage on the first voltage line side.

  A third inverter circuit of the present invention includes a first transistor, a second transistor, and a third transistor that are of the same channel type, an input terminal, an output terminal, and a control element. The control element includes a first terminal electrically connected to the input terminal, a second terminal electrically connected to the output terminal, and a third terminal electrically connected to the gate of the second transistor. Have. This control element is designed to make the transient at the second terminal more gradual than the transient at the third terminal when a falling voltage or a rising voltage is input to the first terminal. Here, the first transistor cuts off the electrical connection between the output terminal and the first voltage line according to the potential difference between the voltage of the input terminal (input voltage) and the voltage of the first voltage line or the corresponding potential difference. It is supposed to be. The second transistor cuts off the electrical connection between the second voltage line and the output terminal according to the potential difference between the gate voltage of the second transistor and the voltage (output voltage) of the output terminal or the corresponding potential difference. It is like that. The third transistor cuts off the electrical connection between the gate of the second transistor and the third voltage line in accordance with the potential difference between the input voltage and the voltage on the third voltage line or the potential difference corresponding thereto. .

  A third display device of the present invention includes a display unit including a plurality of scanning lines arranged in a row, a plurality of signal lines arranged in a column, and a plurality of pixels arranged in a matrix. In addition, a drive unit for driving each pixel is provided. The drive unit has a plurality of inverter circuits provided for each scanning line, and each inverter circuit in the drive unit includes the same components as the third inverter circuit.

  In the third inverter circuit and the third display device of the present invention, an ON / OFF operation is performed between the gate of the second transistor and the third voltage line according to the potential difference between the input voltage and the voltage of the third voltage line. A third transistor is provided. Further, a first transistor that is turned on and off according to a potential difference between the input voltage and the voltage of the first voltage line is provided between the source of the second transistor and the first voltage line.

  Thereby, when the first transistor to the third transistor are n-channel type, when the gate voltage of each of the first transistor and the third transistor changes from high to low, each of the first transistor and the third transistor The ON resistance of the transistor gradually increases, and the time required for charging the gate and source of the second transistor to the voltages of the first voltage line and the third voltage line becomes longer. Further, when the gate voltages of the first transistor and the third transistor change from low to high, the on-resistances of the first transistor and the third transistor are gradually reduced, and the gate and source of the second transistor are The time required to charge the voltage of the first voltage line and the third voltage line is shortened. On the other hand, when the first transistor to the third transistor are p-channel type, when the gate voltage of each of the first transistor and the third transistor changes from low to high, each of the first transistor and the third transistor. The on-resistance gradually increases, and the time required for charging the gate and source of the second transistor to the voltages of the first voltage line and the third voltage line becomes longer. Further, when the respective gate voltages of the first transistor and the third transistor change from high to low, the respective on-resistances of the first transistor and the third transistor are gradually reduced, and the gate and source of the second transistor are The time required to charge the voltage of the first voltage line and the third voltage line is shortened.

  In the third inverter circuit and the third display device of the present invention, in the control element, the first terminal is electrically connected to the input terminal, the second terminal is electrically connected to the output terminal, and the third terminal The terminal is electrically connected to the gate of the second transistor, and when the falling voltage or the rising voltage is input to the first terminal, the transient at the second terminal is slower than the transient at the third terminal.

  Thereby, when the first transistor to the third transistor are n-channel type, the gate-source voltage of the second transistor is changed when the gate voltage of each of the first transistor and the third transistor changes from high to low. It becomes larger than the threshold voltage of the second transistor, the second transistor is turned on, and immediately thereafter, the first transistor and the third transistor are turned off. At this time, the output voltage becomes the voltage on the second voltage line side. Further, when the gate voltages of the first transistor and the third transistor change from low to high, the first transistor and the third transistor are turned on, and immediately after that, the second transistor is turned off. At this time, the output voltage becomes the voltage on the first voltage line side. On the other hand, when the first to third transistors are p-channel type, when the gate voltages of the first transistor and the third transistor change from low to high, the voltage between the gate and source of the second transistor is the first. It becomes larger than the threshold voltage of the two transistors, the second transistor is turned on, and immediately thereafter, the first transistor and the third transistor are turned off. At this time, the output voltage becomes the voltage on the second voltage line side. Further, when the gate voltages of the first transistor and the third transistor change from high to low, the first transistor and the third transistor are turned on, and immediately after that, the second transistor is turned off. At this time, the output voltage becomes the voltage on the first voltage line side.

  A fourth inverter circuit according to the present invention includes a first transistor, a second transistor, and a third transistor of the same channel type, an input terminal, an output terminal, and a control element. The control element includes a first terminal electrically connected to the input terminal, a second terminal electrically connected to the output terminal, and a third terminal electrically connected to the gate of the second transistor. Have. This control element is designed to make the transient at the second terminal gentler than the transient at the third terminal when a falling voltage or a rising voltage is input to the first terminal. Here, the gate of the first transistor is electrically connected to the input terminal, the drain or source of the first transistor is electrically connected to the first voltage line, and the first voltage line among the drain and source of the first transistor. The unconnected terminal is electrically connected to the output terminal. The drain or source of the second transistor is electrically connected to the second voltage line, and the terminal not connected to the second voltage line among the drain and source of the second transistor is electrically connected to the output terminal. The gate of the third transistor is electrically connected to the input terminal, the drain or source of the third transistor is electrically connected to the third voltage line, and the drain and source of the third transistor are not connected to the third voltage line. Is electrically connected to the gate of the second transistor.

  A fourth display device of the present invention includes a display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix. In addition, a drive unit for driving each pixel is provided. The drive unit includes a plurality of inverter circuits provided for each scanning line, and each inverter circuit in the drive unit includes the same components as the fourth inverter circuit.

  In the fourth inverter circuit and the fourth display device of the present invention, a third transistor having the gate connected to the input terminal is provided between the gate of the second transistor and the third voltage line. Furthermore, a first transistor having a gate connected to the input terminal is provided between the source of the second transistor and the first voltage line.

  Thereby, when the first transistor to the third transistor are n-channel type, when the gate voltage of each of the first transistor and the third transistor changes from high to low, each of the first transistor and the third transistor The ON resistance of the transistor gradually increases, and the time required for charging the gate and source of the second transistor to the voltages of the first voltage line and the third voltage line becomes longer. Further, when the gate voltages of the first transistor and the third transistor change from low to high, the on-resistances of the first transistor and the third transistor are gradually reduced, and the gate and source of the second transistor are The time required to charge the voltage of the first voltage line and the third voltage line is shortened. On the other hand, when the first transistor to the third transistor are p-channel type, when the gate voltage of each of the first transistor and the third transistor changes from low to high, each of the first transistor and the third transistor. The on-resistance gradually increases, and the time required for charging the gate and source of the second transistor to the voltages of the first voltage line and the third voltage line becomes longer. Further, when the respective gate voltages of the first transistor and the third transistor change from high to low, the respective on-resistances of the first transistor and the third transistor are gradually reduced, and the gate and source of the second transistor are The time required to charge the voltage of the first voltage line and the third voltage line is shortened.

  In the fourth inverter circuit and the fourth display device of the present invention, in the control element, the first terminal is electrically connected to the input terminal, the second terminal is electrically connected to the output terminal, and the third terminal The terminal is electrically connected to the gate of the second transistor, and when the falling voltage is input to the first terminal, the transient at the second terminal is slower than the transient at the third terminal.

  Thereby, when the first transistor to the third transistor are n-channel type, the gate-source voltage of the second transistor is changed when the gate voltage of each of the first transistor and the third transistor changes from high to low. It becomes larger than the threshold voltage of the second transistor, the second transistor is turned on, and immediately thereafter, the first transistor and the third transistor are turned off. At this time, the output voltage becomes the voltage on the second voltage line side. Further, when the gate voltages of the first transistor and the third transistor change from low to high, the first transistor and the third transistor are turned on, and immediately after that, the second transistor is turned off. At this time, the output voltage becomes the voltage on the first voltage line side. On the other hand, when the first to third transistors are p-channel type, when the gate voltages of the first transistor and the third transistor change from low to high, the voltage between the gate and source of the second transistor is the first. It becomes larger than the threshold voltage of the two transistors, the second transistor is turned on, and immediately thereafter, the first transistor and the third transistor are turned off. At this time, the output voltage becomes the voltage on the second voltage line side. Further, when the gate voltages of the first transistor and the third transistor change from high to low, the first transistor and the third transistor are turned on, and immediately after that, the second transistor is turned off. At this time, the output voltage becomes the voltage on the first voltage line side.

  By the way, in the first to fourth inverter circuits and the first to fourth display devices of the present invention, a delay element for inputting a voltage obtained by blunting the waveform of the signal voltage input to the input terminal to the gate of the third transistor. May be further provided. In this case, since a signal delayed from the signal input to the gate of the first transistor is input to the gate of the third transistor, the respective gate voltages of the first transistor and the third transistor are changed from high. The time until the gate-source voltage of the second transistor exceeds the threshold voltage of the second transistor when changing to low or changing from low to high can be shortened.

  The fifth inverter circuit of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor that are of the same channel type. The inverter circuit further includes a first capacitive element and a second capacitive element, and a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first transistor cuts off the electrical connection between the output terminal and the first voltage line according to the potential difference between the voltage of the first input terminal and the voltage of the first voltage line or the corresponding potential difference. Yes. The second transistor cuts off the electrical connection between the second voltage line and the output terminal according to the potential difference between the gate voltage of the second transistor and the voltage at the output terminal or the corresponding potential difference. Yes. The third transistor interrupts the electrical connection between the gate of the fifth transistor and the third voltage line according to the potential difference between the voltage of the second input terminal and the voltage of the third voltage line or the potential difference corresponding thereto. It has become. The fourth transistor electrically connects the first terminal, which is the source or drain of the fifth transistor, and the fourth voltage line according to the potential difference between the voltage of the second input terminal and the voltage of the fourth voltage line or the corresponding potential difference. The connection is to be broken. The first capacitive element and the second capacitive element are inserted in series between the second input terminal and the gate of the fifth transistor. An electrical connection point between the first capacitor element and the second capacitor element is electrically connected to the first terminal. The fifth transistor cuts off the electrical connection between the fifth voltage line and the first terminal according to the voltage between the terminals of the first capacitive element or the voltage corresponding thereto. The sixth transistor interrupts the electrical connection between the gate of the second transistor and the sixth voltage line according to the potential difference between the voltage of the first input terminal and the voltage of the sixth voltage line or the potential difference corresponding thereto. It has become. The seventh transistor cuts off the electrical connection between the first terminal and the gate of the second transistor in accordance with a signal input to the gate of the seventh transistor via the third input terminal. .

  A fifth display device of the present invention includes a display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix. In addition, a drive unit for driving each pixel is provided. The drive unit has a plurality of inverter circuits provided for each scanning line, and each inverter circuit in the drive unit includes the same components as the fifth inverter circuit.

  In the fifth inverter circuit and the fifth display device of the present invention, the voltage difference between the voltage of the second input terminal and the voltage of the third voltage line is between the gate of the fifth transistor and the third voltage line. A third transistor that is turned on and off is provided. In addition, a fourth transistor is provided between the first terminal of the fifth transistor and the fourth voltage line. The fourth transistor is turned on and off according to the potential difference between the voltage of the second input terminal and the voltage of the fourth voltage line. . Accordingly, for example, when the respective gates of the third transistor and the fourth transistor change from high to low, the on-resistances of the third transistor and the fourth transistor gradually increase, and the gate and source of the fifth transistor are increased. Becomes longer to be charged to the voltage of the third voltage line and the fourth voltage line. Further, for example, when the respective gates of the third transistor and the fourth transistor change from low to high, the respective on-resistances of the third transistor and the fourth transistor are gradually reduced, and the gate and source of the fifth transistor are reduced. The time required to charge the voltage of the third voltage line and the fourth voltage line is shortened. In the present invention, the first capacitive element and the second capacitive element connected in series with each other are inserted between the input terminal and the gate of the fifth transistor. Further, the source of the fifth transistor is electrically connected between the first capacitor element and the second capacitor element. Thus, the first capacitor element and the second capacitor element are connected in parallel to the source of the fifth transistor, and the first capacitor element and the second capacitor element are connected in series to the gate of the fifth transistor. The source of the five transistors is slower in transients than the gate of the fifth transistor. As a result, for example, when the gates of the third transistor and the fourth transistor change from high to low, the gate-source voltage of the fifth transistor becomes larger than the threshold voltage of the fifth transistor, and the fifth transistor is turned on. Immediately thereafter, the fourth transistor is turned off. At this time, since the seventh transistor is off, the voltage at the first terminal of the fifth transistor gradually increases. Thereafter, for example, when the voltage at the first terminal of the fifth transistor reaches a predetermined level, the gates of the first transistor and the sixth transistor change from high to low. As a result, the first transistor and the sixth transistor are turned off. Subsequently, for example, the seventh transistor is turned on. As a result, the first terminal of the fifth transistor and the gate of the second transistor are capacitively coupled to each other, so that the gate voltage of the second transistor rises at once, turning on the second transistor and turning off the first transistor. As a result, the output voltage becomes the voltage on the second voltage line side. For example, when the gates of the first transistor, the third transistor, the fourth transistor, and the sixth transistor change from low to high, the first transistor, the third transistor, the fourth transistor, and the sixth transistor are turned on. Immediately thereafter, the second transistor and the fifth transistor are turned off. As a result, the output voltage becomes the voltage on the first voltage line side.

  A sixth inverter circuit of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor that are of the same channel type. The inverter circuit further includes a first capacitive element and a second capacitive element, and a first input terminal, a second input terminal, a third input terminal, and an output terminal. In the first transistor, the gate is electrically connected to the first input terminal, the drain or the source is electrically connected to the first voltage line, and the terminal not connected to the first voltage line among the drain and the source is the output terminal. Is electrically connected. In the second transistor, the gate is connected to the drain or source of the seventh transistor, the drain or source is electrically connected to the second voltage line, and the terminal not connected to the second voltage line among the drain and source is the output terminal. Is electrically connected. In the third transistor, the gate is electrically connected to the second input terminal, the drain or source is electrically connected to the third voltage line, and the terminal not connected to the third voltage line among the drain and source is the fifth. It is electrically connected to the gate of the transistor. In the fourth transistor, the gate is electrically connected to the second input terminal, the drain or source is electrically connected to the fourth voltage line, and the terminal not connected to the fourth voltage line among the drain and source is the fifth. The transistor is electrically connected to a first terminal which is a drain or a source of the transistor. The first capacitive element and the second capacitive element are inserted in series between the second input terminal and the gate of the fifth transistor. An electrical connection point between the first capacitor element and the second capacitor element is electrically connected to the first terminal. In the fifth transistor, the gate is electrically connected to a terminal not connected to the third voltage line among the drain and source of the third transistor, and a terminal different from the first terminal among the drain and source is connected to the fifth voltage line. Electrically connected. In the sixth transistor, the gate is electrically connected to the first input terminal, the drain or source is electrically connected to the sixth voltage line, and the terminal not connected to the sixth voltage line among the drain and source is the second. It is electrically connected to the gate of the transistor. In the seventh transistor, the gate is electrically connected to the third input terminal, the drain or the source is electrically connected to the first terminal, and the terminal not connected to the first terminal of the drain and the source is the second transistor. It is electrically connected to the gate.

  A sixth display device of the present invention includes a display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix. In addition, a drive unit for driving each pixel is provided. The drive unit has a plurality of inverter circuits provided for each scanning line, and each inverter circuit in the drive unit includes the same components as the sixth inverter circuit.

  In the sixth inverter circuit and the sixth display device of the present invention, a third transistor whose gate is connected to the second input terminal is provided between the gate of the fifth transistor and the third voltage line. . Further, a fourth transistor having a gate connected to the second input terminal is provided between the first terminal of the fifth transistor and the fourth voltage line. Accordingly, for example, when the respective gates of the third transistor and the fourth transistor change from high to low, the on-resistances of the third transistor and the fourth transistor gradually increase, and the gate and source of the fifth transistor are increased. Becomes longer to be charged to the voltage of the third voltage line and the fourth voltage line. Further, for example, when the respective gates of the third transistor and the fourth transistor change from low to high, the respective on-resistances of the third transistor and the fourth transistor are gradually reduced, and the gate and source of the fifth transistor are reduced. The time required to charge the voltage of the third voltage line and the fourth voltage line is shortened. In the present invention, the first capacitor element and the second capacitor element are connected in series to the gate of the fifth transistor, and the first capacitor element and the second capacitor element are connected in parallel to the source of the fifth transistor. Therefore, the transient of the source of the fifth transistor is slower than that of the gate of the fifth transistor. As a result, for example, when the gates of the third transistor and the fourth transistor change from high to low, the gate-source voltage of the fifth transistor becomes larger than the threshold voltage of the fifth transistor, and the fifth transistor is turned on. Immediately thereafter, the fourth transistor is turned off. At this time, since the seventh transistor is off, the voltage at the first terminal of the fifth transistor gradually increases. Thereafter, for example, when the voltage at the first terminal of the fifth transistor reaches a predetermined level, the gates of the first transistor and the sixth transistor change from high to low. As a result, the first transistor and the sixth transistor are turned off. Subsequently, for example, the seventh transistor is turned on. As a result, the first terminal of the fifth transistor and the gate of the second transistor are capacitively coupled to each other, so that the gate voltage of the second transistor rises at once, turning on the second transistor and turning off the first transistor. As a result, the output voltage becomes the voltage on the second voltage line side. For example, when the gates of the first transistor, the third transistor, the fourth transistor, and the sixth transistor change from low to high, the first transistor, the third transistor, the fourth transistor, and the sixth transistor are turned on. Immediately thereafter, the second transistor and the fifth transistor are turned off. As a result, the output voltage becomes the voltage on the first voltage line side.

  According to the first to fourth inverter circuits and the first to fourth display devices of the present invention, since the first transistor and the second transistor are hardly turned on at the same time, the first transistor There is almost no current (through current) flowing between the voltage lines via the second transistor. Thereby, power consumption can be suppressed. Further, when the gate voltage of each of the first transistor and the third transistor changes from high to low, the output voltage becomes the voltage on the second voltage line side or the voltage on the first voltage line side, and the first transistor and the third transistor Since the output voltage is set to the voltage opposite to the above when each of the gate voltages changes from low to high, variations in the output voltage can be eliminated. As a result, for example, variations in threshold correction and mobility correction of the drive transistor in the pixel circuit can be reduced for each pixel circuit, and further, luminance variations for each pixel can be reduced.

  Further, in the first to fourth inverter circuits and the first to fourth display devices of the present invention, the voltage obtained by blunting the voltage waveform of the signal voltage input to the input terminal is input to the gate of the third transistor. In this case, when the gate voltage of each of the first transistor and the third transistor changes from high to low, or when the gate voltage changes from low to high, the gate-source voltage of the second transistor becomes the threshold voltage of the second transistor. It is possible to shorten the time until it exceeds. Thereby, the circuit operation can be speeded up.

  According to the fifth and sixth inverter circuits and the fifth and sixth display devices of the present invention, the first transistor and the second transistor are turned on simultaneously, or the fourth transistor and the fifth transistor are turned on simultaneously. The current flowing through the voltage lines (through current) via the first transistor and the second transistor, or the fourth transistor and the fifth transistor is reduced. Almost does not exist. Thereby, power consumption can be suppressed. Also, when the gate voltages of the first transistor, the third transistor, the fourth transistor, and the sixth transistor change from high to low, the output voltage becomes the voltage on the second voltage line side or the voltage on the first voltage line side. Since the output voltage becomes the voltage on the opposite side to the above when the gate voltage of each of the first transistor, the third transistor, the fourth transistor, and the sixth transistor changes from low to high, the output voltage Variations can be eliminated. As a result, for example, variations in threshold correction and mobility correction of the drive transistor in the pixel circuit can be reduced for each pixel circuit, and further, luminance variations for each pixel can be reduced.

  Further, in the fifth and sixth inverter circuits and the fifth and sixth display devices of the present invention, the fifth transistor is used by using a voltage earlier in phase than the voltage input to the gates of the first transistor and the sixth transistor. It is possible to speed up the transient of the gate voltage of the sixth transistor by setting the voltage of the first terminal of the first transistor to a high voltage in advance and increasing the gate voltage of the second transistor at once by capacitive coupling via the seventh transistor. is there. Thereby, the circuit operation can be speeded up.

1 is a circuit diagram illustrating an example of an inverter circuit according to a first embodiment of the present invention. FIG. 2 is a waveform diagram illustrating an example of input / output signal waveforms of the inverter circuit of FIG. 1. FIG. 2 is a waveform diagram illustrating an example of operation of the inverter circuit of FIG. 1. FIG. 2 is a circuit diagram for explaining an example of the operation of the inverter circuit of FIG. 1. FIG. 5 is a circuit diagram for explaining an example of an operation following FIG. 4. FIG. 6 is a circuit diagram for explaining an example of an operation following FIG. 5. FIG. 7 is a circuit diagram for explaining an example of an operation following FIG. 6. FIG. 8 is a circuit diagram for explaining an example of an operation following FIG. 7. It is a circuit diagram showing an example of the inverter circuit which concerns on the 2nd Embodiment of this invention. FIG. 10 is a circuit diagram illustrating a variation of the delay element in FIG. 9. FIG. 10 is a waveform diagram illustrating an example of the operation of the inverter circuit of FIG. 9. FIG. 10 is a waveform diagram illustrating an example of input / output signal waveforms of the delay element in FIG. 9. FIG. 10 is a circuit diagram for explaining an example of the operation of the inverter circuit of FIG. 9. FIG. 10 is a circuit diagram illustrating a modification of the inverter circuit of FIG. 9. FIG. 15 is a waveform diagram illustrating an example of input / output signal waveforms of the inverter circuit of FIG. 14. FIG. 10 is a circuit diagram illustrating another modification of the inverter circuit of FIG. 9. FIG. 15 is a circuit diagram illustrating another modification of the inverter circuit of FIG. 14. It is a circuit diagram showing an example of the inverter circuit which concerns on the 3rd Embodiment of this invention. FIG. 19 is a waveform diagram illustrating an example of the operation of the inverter circuit in FIG. 18. FIG. 19 is a circuit diagram for explaining an example of the operation of the inverter circuit of FIG. 18. FIG. 21 is a circuit diagram for explaining an example of an operation following FIG. 20. FIG. 22 is a circuit diagram for explaining an example of an operation following FIG. 21. FIG. 23 is a circuit diagram for explaining an example of an operation following FIG. 22. FIG. 24 is a circuit diagram for explaining an example of an operation following FIG. 23. FIG. 25 is a circuit diagram for explaining an example of an operation following FIG. 24. FIG. 19 is a circuit diagram illustrating a modification of the inverter circuit of FIG. 18. FIG. 27 is a circuit diagram for explaining an example of the operation of the inverter circuit of FIG. 26. FIG. 28 is a circuit diagram for explaining an example of an operation following FIG. 27. It is a schematic block diagram of the display apparatus which is an example of the application example of the inverter circuit of said each embodiment and those modifications. FIG. 30 is a circuit diagram illustrating an example of a writing line driving circuit and a pixel circuit in FIG. 29. It is a wave form diagram showing an example of a waveform of a synchronizing signal, and an example of a signal waveform outputted to a writing line. FIG. 30 is a waveform diagram illustrating an example of operation of the display device in FIG. 29. FIG. 18 is a circuit diagram illustrating an example of an inverter circuit included in the write line driving circuit of FIG. 17. FIG. 34 is a waveform diagram illustrating an example of input / output signal waveforms of the inverter circuit of FIG. 33. It is a circuit diagram for demonstrating an example of operation | movement of the inverter circuit of FIG. It is a circuit diagram showing an example of the pixel circuit of the conventional display apparatus. It is a circuit diagram showing an example of the conventional inverter circuit. It is a wave form diagram showing an example of the input-output signal waveform of the inverter circuit of FIG. It is a circuit diagram showing the other example of the conventional inverter circuit. It is a circuit diagram showing the other example of the conventional inverter circuit. It is a circuit diagram showing an example of the inverter circuit which concerns on a reference example. FIG. 42 is a waveform diagram illustrating an example of input / output signal waveforms of the inverter circuit of FIG. 41. FIG. 42 is a waveform diagram illustrating an example of the operation of the inverter circuit in FIG. 41. FIG. 42 is a circuit diagram for explaining an example of the operation of the inverter circuit of FIG. 41. FIG. 45 is a circuit diagram for describing an example of an operation following FIG. 44. FIG. 46 is a circuit diagram for explaining an example of an operation following FIG. FIG. 47 is a circuit diagram for explaining an example of an operation following FIG. 46. 48 is a circuit diagram for explaining an example of an operation following FIG. 47. FIG. FIG. 49 is a circuit diagram for describing an example of an operation following FIG. 48. FIG. 42 is a circuit diagram for describing a parasitic capacitance of the inverter circuit of FIG. 41.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the invention will be described in detail with reference to the drawings. The description will be given in the following order.

1. 1st Embodiment (FIGS. 1-8)
2. Second embodiment (FIGS. 9 to 13)
3. Modifications of the above embodiments (FIGS. 14 to 17)
4). 3rd Embodiment (FIGS. 18-25)
5). Modified example of the third embodiment (FIGS. 26 to 28)
6). Application examples (FIGS. 29 to 35)

<1. First Embodiment>
[Constitution]
FIG. 1 shows an example of the overall configuration of the inverter circuit 1 according to the first embodiment of the present invention. 2A and 2B show examples of input / output signal waveforms of the inverter circuit 1 of FIG. The inverter circuit 1 outputs a pulse signal (for example, FIG. 2B) obtained by substantially inverting the signal waveform (for example, FIG. 2A) of the pulse signal input to the input terminal IN from the output terminal OUT. . The inverter circuit 1 is preferably formed on amorphous silicon or an amorphous oxide semiconductor, and includes, for example, three transistors Tr1, Tr2, Tr3 of the same channel type. The inverter circuit 1 includes, in addition to the above three transistors Tr1, Tr2, Tr3, two capacitive elements C1, C2, an input terminal IN and an output terminal OUT, and has a 3Tr2C circuit configuration.

  The transistor Tr1 corresponds to a specific example of the “first transistor” of the present invention, the transistor Tr2 corresponds to a specific example of the “second transistor” of the present invention, and the transistor Tr3 corresponds to the “third transistor” of the present invention. This corresponds to a specific example. The capacitive element C1 corresponds to a specific example of “first capacitive element” of the present invention, and the capacitive element C2 corresponds to a specific example of “second capacitive element” of the present invention.

  The transistors Tr1, Tr2, and Tr3 are, for example, n-channel MOS (Metal Oxide Semiconductor) type thin film transistors (TFTs). For example, the transistor Tr1 has an electrical connection between the output terminal OUT and the low voltage line L1 according to a potential difference (or a potential difference corresponding thereto) between the voltage of the input terminal IN (input voltage Vin) and the voltage of the low voltage line L1. The connection is broken. The gate of the transistor Tr1 is electrically connected to the input terminal IN. The source or drain of the transistor Tr1 is electrically connected to the low voltage line L1, and the terminal not connected to the low voltage line L1 among the source and drain of the transistor Tr1 is electrically connected to the output terminal OUT.

  The transistor Tr2 is electrically connected between the high voltage line L2 and the output terminal OUT in accordance with a potential difference (or potential difference corresponding thereto) between the gate voltage Vg2 of the transistor Tr2 and the voltage (output voltage Vout) of the output terminal OUT. Is supposed to be cut off. The gate of the transistor Tr2 is electrically connected to the source or drain of the transistor Tr3. The source or drain of the transistor Tr2 is electrically connected to the output terminal OUT, and the terminal not connected to the output terminal OUT among the source and drain of the transistor Tr2 is electrically connected to the high voltage line L2.

The transistor Tr3 cuts off the electrical connection between the gate of the transistor Tr2 and the low voltage line L1 in accordance with the potential difference (or potential difference corresponding thereto) between the input voltage Vin and the voltage of the low voltage line L1. Yes. The gate of the transistor Tr3 is electrically connected to the input terminal IN. The source or drain of the transistor Tr3 is electrically connected to the low voltage line L1, and the terminal not connected to the low voltage line L1 among the source and drain of the transistor Tr3 is electrically connected to the gate of the transistor Tr2. . That is, the transistors Tr1 and Tr3 are connected to the same voltage line (low voltage line L1), and the terminals on the low voltage line L1 side of the sources and drains of the transistors Tr ₁ and Tr3 have the same potential. ing.

  The low voltage line L1 corresponds to a specific example of “first voltage line” and “third voltage line” of the present invention, and the high voltage line L2 corresponds to a specific example of “second voltage line” of the present invention. .

  The high voltage line L2 is connected to a power source (not shown) that outputs a higher voltage (constant voltage) than the voltage of the low voltage line L1, and the voltage of the high voltage line L2 is Vdd when the inverter circuit 1 is driven. It has become. The low voltage line L1 is connected to a power source (not shown) that outputs a voltage (constant voltage) lower than the voltage of the high voltage line L2, and the voltage of the low voltage line L1 is a voltage when the inverter circuit 1 is driven. Vss (<Vdd).

The capacitive elements C1 and C2 are inserted in series between the input terminal IN and the gate of the transistor Tr2. An electrical connection point A between the capacitive element C1 and the capacitive element C2 is electrically connected to the output terminal OUT. The capacitive element C1 is inserted on the gate side of the transistor Tr2, and the capacitive element C2 is inserted on the gate side of the transistor Tr1. The capacity of the capacitive element C2 is larger than the capacity of the capacitive element C1. The capacitances of the capacitive elements C1 and C2 preferably satisfy the following formula (1). If the capacitive elements C1 and C2 satisfy Expression (1), as will be described later, when the input voltage Vin falls, the gate-source voltage of the transistor Tr2 can be set to the threshold voltage Vth2 or more, and the output The voltage Vout can change from low to high. Ca is the capacitance of the capacitive element C1, and Cb is the capacitance of the capacitive element C2. In Expression (1), Vdd is the voltage of the high voltage line L2, and Vss is the voltage of the low voltage line L1.
Cb (Vdd−Vss) / (Ca + Cb)> Vth2 (1)

  By the way, the inverter circuit 1 has a control element 10 and a transistor Tr3 inserted between the output stage transistors Tr1 and Tr2 and the input terminal IN in relation to the conventional inverter circuit (inverter circuit 200 of FIG. 37). It corresponds to. Here, for example, as shown in FIG. 1, the control element 10 includes a first terminal P1 electrically connected to the input terminal IN, a second terminal P2 electrically connected to the output terminal OUT, and a transistor. It has a third terminal P3 electrically connected to the gate of Tr2. The control element 10 further includes, for example, capacitive elements C1 and C2, as shown in FIG. For example, when the falling voltage is input to the first terminal P1, the control element 10 makes the transient at the second terminal P2 gentler than the transient at the third terminal P3. Specifically, for example, when the falling voltage is input to the input terminal IN, the control element 10 makes the transient of the source of the transistor Tr2 (terminal on the output terminal OUT side) more gradual than the transient of the gate of the transistor Tr2. It is supposed to be. The operation of the control element 10 will be described together with the following description of the operation of the inverter circuit 1.

[Operation]
Next, an example of the operation of the inverter circuit 1 will be described with reference to FIGS. FIG. 3 is a waveform diagram illustrating an example of the operation of the inverter circuit 1. 4 to 8 are circuit diagrams illustrating an example of a series of operations of the inverter circuit 1.

  First, when the input voltage Vin is high (Vdd), the transistors Tr1 and Tr3 are on, and the gate voltage Vg2 and the source voltage Vs2 of the transistor Tr2 are charged to the voltage (= Vss) of the low voltage line L1. (FIGS. 3 and 4). Therefore, the transistor Tr2 is in an off state (when the gate-source voltage Vgs2 = 0V), and the voltage Vss is output as the output voltage Vout. At this time, the capacitor element C2 is charged with a voltage of Vdd-Vss.

  Next, when the input voltage Vin changes (decreases) from high (Vdd) to low (Vss), the gate voltages Vg1, Vg2 of the transistors Tr1, Tr2 also change (decrease) from Vdd to Vss (FIGS. 3 and 5). ). As a result, the change in the gate voltage of the transistor Tr1 propagates to the source (output terminal OUT) of the transistor Tr2 via the capacitive element C2, and the source voltage Vs2 (output voltage Vout) of the transistor Tr2 changes (decreases) by ΔV1 ′. . Further, the change in the gate voltage of the transistor Tr1 propagates to the gate of the transistor Tr2 via the capacitive elements C1 and C2, and the gate voltage Vg2 of the transistor Tr2 changes (decreases) by ΔV2 ′. However, at this time, the transistors Tr1 and Tr3 are on. Therefore, current flows from the low voltage line L1 toward the source (output terminal OUT) of the transistor Tr2 and the gate of the transistor Tr2, and the current tries to charge them to Vss.

  Here, since the gate voltages of the transistors Tr1 and Tr3 change (decrease) from Vdd to Vss, the on-resistances of the transistors Tr1 and Tr3 gradually increase, and the source (output terminal OUT) and gate of the transistor Tr2 are lowered. The time required to charge the voltage of the voltage line L1 becomes longer.

  Further, comparing the total capacitance visible from the source (output terminal OUT) and the gate of the transistor Tr2, capacitive elements C1 and C2 are connected in parallel to the source (output terminal OUT) of the transistor Tr2, and the capacitive element is connected to the gate of the transistor Tr2. C1 and C2 are connected in series. For this reason, the source (output terminal OUT) of the transistor Tr2 has a slower transient than the gate of the transistor Tr2. As a result, the time required to charge the source (output terminal OUT) of the transistor Tr2 to the voltage of the low voltage line L1 is longer than the time required to charge the gate of the transistor Tr2 to the voltage of the low voltage line L1. Become.

  In addition, when the input voltage Vin is Vss + Vth1 or more and further Vss + Vth3 or more, the transistors Tr1 and Tr3 operate in a linear region. Note that Vth1 is a threshold voltage of the transistor Tr1, and Vth3 is a threshold voltage of the transistor Tr3. On the other hand, when the input voltage Vin is less than Vss + Vth1, and further less than Vss + Vth3, the transistors Tr1 and Tr3 operate in the saturation region. Therefore, a current as shown in FIG. 5 flows through the source (output terminal OUT) and gate of the transistor Tr2, but the transistors Tr1 and Tr3 cannot charge each point to the voltage Vss.

  Finally, when the input voltage Vin changes from Vdd to Vss, the gate-source voltage Vgs2 of the transistor Tr2 becomes ΔV1−ΔV2 (FIGS. 3 and 6). At this time, when the gate-source voltage Vgs2 of the transistor Tr2 becomes larger than the threshold voltage Vth2 of the transistor Tr2, the transistor Tr2 is turned on and current starts to flow from the high voltage line L2.

  When the transistor Tr2 is on, the source voltage Vs2 (output voltage Vout) of the transistor Tr2 is increased by the transistor Tr2 in addition to the transistor Tr1. Further, since the capacitive element C1 is connected between the gate and the source of the transistor Tr2, a bootstrap occurs, and the gate voltage Vg2 of the transistor Tr2 is interlocked with the rise of the source voltage Vs2 (output voltage Vout) of the transistor Tr2. Rise. Thereafter, when the source voltage Vs2 (output voltage Vout) and the gate voltage Vg2 of the transistor Tr2 become Vss−Vth1 or more and further become Vss−Vth3 or more, the transistors Tr1 and Tr3 are turned off, and the source voltage Vs2 of the transistor Tr2 (Output voltage Vout) and gate voltage Vs2 rise only by transistor Tr2.

  After a certain time has elapsed, the source voltage Vs2 (output voltage Vout) of the transistor Tr2 becomes Vdd, and Vdd is output from the output terminal OUT (FIGS. 3 and 7). Then, after a certain time has passed, the input voltage Vin changes (rises) from low (Vss) to high (Vdd) (FIGS. 3 and 8). At this time, when the input voltage Vin is lower than Vss + Vth1 and further lower than Vss + Vth3, the transistors Tr1 and Tr3 are turned off. Therefore, coupling via the capacitive elements C1 and C2 is input to the source (output terminal OUT) and gate of the transistor Tr2, and the source voltage Vs2 (output voltage Vout) and gate voltage Vg2 of the transistor Tr2 rise. Thereafter, when the input voltage Vin becomes Vss + Vth1 or more and further becomes Vss + Vth2 or more, the transistors Tr1 and Tr3 are turned on. Therefore, current flows toward the source (output terminal OUT) and gate of the transistor Tr2, and the current tries to charge them to Vss.

  Here, since the gate voltages of the transistors Tr1 and Tr3 change (rise) from Vss to Vdd, the on-resistances of the transistors Tr1 and Tr3 gradually decrease, and the source (output terminal OUT) and gate of the transistor Tr2 are lowered. The time required to charge the voltage of the voltage line L1 is relatively short. Finally, the source voltage Vs2 (output voltage Vout) and the gate voltage Vg2 of the transistor Tr2 become Vss, and Vss is output from the output terminal (FIGS. 3 and 4).

  As described above, in the inverter circuit 1 according to the present embodiment, the pulse signal (for example, FIG. 2B) obtained by substantially inverting the signal waveform (for example, FIG. 2A) of the pulse signal input to the input terminal IN. ) Is output from the output terminal OUT.

[effect]
Incidentally, for example, the conventional inverter circuit 200 as shown in FIG. 37 has a single-channel circuit configuration in which two n-channel MOS transistors Tr11 and Tr12 are connected in series. In the inverter circuit 200, for example, as shown in FIG. 38, when the input voltage Vin is Vss, the output voltage Vout does not become Vdd but Vdd−Vth. That is, the output voltage Vout includes the threshold voltage Vth of the transistor Tr12, and the output voltage Vout is greatly affected by variations in the threshold voltage Vth of the transistor Tr12.

  Therefore, for example, as shown in the inverter circuit 300 of FIG. 39, the gate and the drain of the transistor Tr12 are electrically separated from each other, and a high voltage to which a voltage Vdd2 (= Vdd + Vth) higher than the drain voltage Vdd is applied. It is conceivable to connect a gate to the wiring L3. Further, for example, a bootstrap type circuit configuration as shown in the inverter circuit 400 of FIG. 40 is conceivable.

  However, in any of the circuits of FIGS. 37, 39, and 40, the transistors Tr11 and Tr12 are used until the input voltage Vin is high, that is, until the output voltage Vout is low. A current (through current) flows from the high voltage wiring L2 side toward the low voltage wiring L1 side. As a result, power consumption in the inverter circuit also increases. In the circuits of FIGS. 37, 39, and 40, for example, when the input voltage Vin is Vdd as shown in the portion surrounded by the broken line in FIG. 38B, the output voltage Vout is Vss. In other words, the peak value of the output voltage Vout varies. Therefore, for example, when these inverter circuits are used in a scanner in an active matrix organic EL display device, threshold correction and mobility correction of the drive transistor in the pixel circuit vary from pixel circuit to pixel circuit. The variation becomes the luminance variation.

  On the other hand, in the inverter circuit 1 of the present embodiment, the input voltage Vin and the low voltage line L1 are connected between the gate of the transistor Tr2 and the low voltage line L1, and between the source of the transistor Tr2 and the low voltage line L1. Transistors Tr1 and Tr3 that are turned on and off according to the potential difference from the voltage are provided. As a result, when the gate voltages of the transistors Tr1 and Tr3 change (decrease) from high (Vdd) to low (Vss), the on-resistances of the transistors Tr1 and Tr3 gradually increase, and the gates of the transistors Tr2 and It takes a long time to charge the source to the voltage of the low voltage line L1. Further, when the gate voltages of the transistors Tr1 and Tr3 change (rise) from low (Vss) to high (Vdd), the on-resistances of the transistors Tr1 and Tr3 gradually decrease, and the gate and source of the transistor Tr2 Takes a short time to be charged to the voltage of the low voltage line L1. In the inverter circuit 1 of the present embodiment, the capacitive elements C1 and C2 are connected in series to the gate of the transistor Tr2, and the capacitive elements C1 and C2 are connected in parallel to the source of the transistor Tr2. As a result, the source of the transistor Tr2 has a slower transient than the gate of the transistor Tr2. As a result, when the gate voltages of the transistors Tr1 and Tr3 change (decrease) from high (Vdd) to low (Vss), the gate-source voltage Vgs2 of the transistor Tr2 becomes larger than the threshold voltage Vth2 of the transistor Tr2. The transistor Tr2 is turned on, and immediately after that, the transistors Tr1 and Tr3 are turned off. That is, when the change in the input voltage Vin is input to the gate and source of the transistor Tr2 via the capacitive elements C1 and C2, the transistor Tr2 is turned on when the gate-source voltage Vgs2 becomes larger than the threshold voltage Vth2 due to the difference in transient. Immediately thereafter, the transistors Tr1 and Tr3 are turned off. At this time, the output voltage Vout becomes a voltage on the high voltage line L2 side. The transistors Tr1 and Tr3 are turned on when the gate voltages of the transistors Tr1 and Tr3 change (rise) from low (Vss) to high (Vdd), and immediately after that, the transistor Tr2 is turned off. At this time, the output voltage Vout becomes a voltage on the low voltage line L1 side.

  As described above, in the inverter circuit 1 of the present embodiment, there is almost no period in which the transistor Tr1 and the transistor Tr2 are simultaneously turned on. Thereby, since there is almost no current (through current) flowing between the high voltage line L2 and the low voltage line L1 via the transistors Tr1 and Tr2, power consumption can be suppressed. Further, when the gate voltages of the transistors Tr1 and Tr3 change (decrease) from high (Vdd) to low (Vss), the output voltage Vout becomes the voltage on the high voltage line L2, and the gates of the transistors Tr1 and Tr3 The output voltage Vout is set to the voltage on the low voltage line L1 side when the voltage changes (rises) from low (Vss) to high (Vdd). As a result, variations in the output voltage Vout can be eliminated. As a result, for example, variations in threshold correction and mobility correction of the drive transistor in the pixel circuit can be reduced for each pixel circuit, and further, luminance variations for each pixel can be reduced.

<2. Second Embodiment>
[Constitution]
FIG. 9 illustrates an example of the overall configuration of the inverter circuit 2 according to the second embodiment of the present invention. As in the inverter circuit 1 of the above-described embodiment, the inverter circuit 2 is a pulse signal (for example, FIG. 2B) obtained by substantially inverting the signal waveform (for example, FIG. 2A) of the pulse signal input to the input terminal IN. ) From the output terminal OUT. The inverter circuit 2 is different from the configuration of the inverter circuit 1 of the above embodiment in that the delay circuit 3 is provided. Therefore, hereinafter, differences from the above embodiment will be mainly described, and description of points in common with the above embodiment will be omitted as appropriate.

  The delay element 3 inputs a voltage obtained by blunting the voltage waveform of the signal voltage input to the input terminal IN to the gate of the transistor Tr3. The delay element 3 is provided between the input terminal IN and the gate of the transistor Tr3. For example, the fall of the voltage waveform is made slower than the fall of the voltage waveform of the signal voltage input to the input terminal OUT. The voltage is input to the gate of the transistor Tr3. It should be noted that the delay element 3 may be configured not only to make the voltage waveform fall, but also to make the rise more gradual than the rise of the voltage waveform of the signal voltage input to the input terminal OUT. However, in that case, the delay element 3 is configured to blunt the voltage waveform of the signal voltage input to the input terminal OUT so that the falling edge becomes more gradual than the rising edge.

  The delay element 3 has, for example, a circuit configuration shown in FIGS. In FIG. 10A, the delay element 3 includes a capacitive element C30. One end of the capacitive element C30 is electrically connected to the gate of the transistor Tr3, and the other end of the capacitive element C30 is electrically connected to the low voltage line L1.

  In FIG. 10B, the delay element 3 includes a transistor Tr31. The transistor Tr31 is a transistor of the same channel type as that of the transistors Tr1, Tr2, and Tr3, and is, for example, an n-channel MOS type TFT. The source or drain of the transistor Tr31 is electrically connected to the gate of the transistor Tr3. Of the source and drain of the transistor Tr31, a terminal not connected to the gate of the transistor Tr3 is electrically connected to the input terminal IN. The gate of the transistor Tr31 is electrically connected to the high voltage line L30. The high voltage line L30 is electrically connected to a power source (not shown) that outputs a pulse signal for turning on and off the transistor Tr31.

  In FIG. 10C, the delay element 3 includes the transistor Tr31 and the transistor Tr32 described above. The transistor Tr32 is a transistor of the same channel type as that of the transistors Tr1, Tr2, Tr3, and is, for example, an n-channel MOS type TFT. The gate and source of the transistor Tr32 are electrically connected to the gate of the transistor Tr3, and the drain of the transistor Tr32 is electrically connected to the input terminal IN.

  In FIG. 10D, the delay element 3 includes the transistor Tr31 described above and the capacitor C30 described above.

[Operation / Effect]
FIG. 11 shows an example of the operation of the inverter circuit 2. FIG. 11 shows a waveform when the delay element 3 having the circuit configuration shown in FIG. 10D is used. The basic operation of the inverter circuit 2 is the same as that shown in FIGS. 3 to 8 are different from each other when the input voltage Vin changes (decreases) from high (Vdd) to low (Vss) and from low (Vss) to high (Vdd). When you are. Vg3 is the gate voltage of the transistor Tr3. Vth3 is a threshold voltage of the transistor Tr3.

  When the input voltage Vin changes (decreases) from high (Vdd) to low (Vss), the gate voltages of the transistors Tr1 and Tr3 change from Vdd to Vss. In the inverter circuit 1 of the first embodiment, this voltage change causes a voltage change ΔV1 to the source of the transistor Tr2 via the capacitive element C2, and further to the gate of the transistor Tr2 via the capacitive elements C1 and C2. A voltage change of ΔV2 was generated. Here, the coupling amount ΔV2 is input to the gate of the transistor Tr2. The gate voltage V of the transistor Tr3 decreases from Vdd to Vss. As a result, the on-resistance of the transistor Tr3 gradually increases. This is because the transient of charging the gate of the transistor Tr2 to Vss is delayed. In other words, the reason why the coupling amount ΔV2 is input to the gate of the transistor Tr2 is that the transistor Tr3 is switched from on to off at the timing when the coupling is input.

  On the other hand, in the present embodiment, a signal voltage obtained by blunting the signal voltage input to the input terminal IN as shown in FIG. 12 by the delay element 3 is input to the gate of the transistor Tr3. As a result, the off-point of transistor Tr3 (the point at which on and off are switched) is delayed as compared with the case where input voltage Vin is directly input to the gate of transistor Tr3. That is, the transistor Tr3 is also turned on at the timing when coupling via the capacitive element C2 is input (FIG. 13). Therefore, the coupling amount (ΔV2) finally input to the gate of the transistor Tr2 can be made smaller than the conventional one (FIG. 11C), and the gate-source voltage Vgs2 of the transistor Tr2 can be made larger. It becomes. As a result, the inverter circuit 2 can be speeded up.

  In the present embodiment, even when the input voltage Vin changes (rises) from low (Vss) to high (Vdd), the signal voltage input to the input terminal IN by the delay element 3 is applied to the gate of the transistor Tr3. As shown in FIG. 12, a signal voltage that has been blunted is input. Therefore, the off-point of the transistor Tr3 is delayed, so that the transistor Tr3 is turned on after the transistor Tr1 is turned on. When the output voltage Vout is in the transition state, a current (through current) from the high voltage line L2 to the low voltage line L1. May flow. However, in actuality, considering the operating point at which the transistor Tr3 is turned on and the waveform of the signal voltage input to the gate of the transistor Tr2, the delay in the signal voltage input to the gate of the transistor Tr3 also results in FIG. As shown in the figure, the time for turning on the transistor Tr3 hardly changes at the rising edge, and on the contrary, the time for turning off the transistor greatly changes at the falling edge. Therefore, the period during which the above-described through current flows is very small, and the power consumption of the inverter circuit 2 is not much different from the power consumption of the inverter circuit 1.

  By the way, in the first embodiment, coupling due to a change in the input voltage Vin is input to the source and gate of the transistor Tr2, and the difference in transient between the source and gate of the transistor Tr2 is used to The gate-source voltage Vgs2 is set to a value equal to or higher than the threshold voltage Vth2 of the transistor Tr2. At this time, the voltage on the high voltage line L2 side is output to the output terminal OUT as the output voltage Vout, but the transient of the output terminal OUT greatly depends on the gate-source voltage Vgs2 of the transistor Tr2. That is, when the gate-source voltage Vgs2 of the transistor Tr2 increases quickly, the output voltage Vout rises quickly, and when the gate-source voltage Vgs2 of the transistor Tr2 increases slowly, the output voltage Vout rises slowly. .

  Therefore, when the speed of the inverter circuit 1 is increased, the gate-source voltage Vgs2 of the transistor Tr2 may be raised quickly. As a method for this, for example, increasing the capacitance of the capacitive element C2 is conceivable. . However, when the capacitance of the capacitive element C2 is increased, the area occupied by the inverter circuit 1 is increased. As a result, for example, in the organic EL display device, when the inverter circuit 1 having a larger capacitance of the capacitive element C2 is used for a scanner or the like, the area occupied by the periphery (frame) in the display panel increases, and the frame becomes narrower. May be disturbed. Further, when the capacitance of the capacitor C2 is increased, a voltage change larger than ΔV1 occurs at the source (output terminal OUT) of the transistor Tr2, and accordingly, a voltage larger than ΔV2 is also applied to the gate of the transistor Tr2. Change occurs. As a result, the gate-source voltage Vgs2 of the transistor Tr2 becomes a value that is not so different from ΔV1−ΔV2 for the capacitance of the capacitive element C2, and the increase in the capacitance of the capacitive element C2 increases the speed of the inverter circuit 1. Does not contribute much to

  On the other hand, in the present embodiment, a signal voltage obtained by blunting the signal voltage input to the input terminal IN as shown in FIG. 12 by the delay element 3 is input to the gate of the transistor Tr2. As a result, the inverter circuit 2 can be speeded up without increasing the capacitance of the capacitive element C2.

<3. Modifications of the above embodiments>
In each of the above embodiments, the transistors Tr1, Tr2, and Tr3 are formed by n-channel MOS type TFTs, but may be formed by, for example, p-channel MOS type TFTs. However, in this case, the positional relationship between the high voltage line L2 and the low voltage line L1 is switched, and further, transients when the transistors Tr1, Tr2, Tr3 change (rise) from low (Vss) to high (Vdd). The response and the transient response when the transistors Tr1, Tr2, and Tr3 change (decrease) from high (Vdd) to low (Vss) are opposite to each other.

  In the second embodiment, the delay element 3 is used to input the signal voltage input to the input terminal IN to the gate of the transistor Tr3, as shown in FIG. However, such a signal may be input to the gate of the transistor Tr3 using another method. For example, as shown in the inverter circuit 4 in FIG. 14, the input terminal IN2 is provided separately from the input terminal IN, the input terminal IN2 and the gate of the transistor Tr3 are electrically connected to each other, and FIG. A signal as shown may be input to the input terminal IN2 from the outside.

  In the second embodiment and its modification, when the input voltage Vin changes (rises) from low (Vss) to high (Vdd), a current (through) from the high voltage line L2 to the low voltage line L1. Current) may flow, but a device for improving the current may be newly added. For example, as shown in FIGS. 16 and 17, a transistor Tr10 may be further provided. The transistor Tr10 is a transistor of the same channel type as that of the transistors Tr1, Tr2, Tr3, and is, for example, an n-channel MOS type TFT.

  The transistor Tr10 is connected in parallel with the transistor Tr3, and the gate of the transistor Tr10 is connected to the input terminal IN. In this case, when the input voltage Vin changes (decreases) from high (Vdd) to low (Vss), the on period of the transistor Tr3 becomes longer, and conversely, the input voltage Vin changes from low (Vss). When shifting (rising) to high (Vdd), the transistor Tr10 can be turned on prior to the transistor Tr3 by the input voltage Vin without delay. As a result, the through current can be reduced.

<4. Third Embodiment>
[Constitution]
FIG. 18 illustrates an example of the overall configuration of the inverter circuit 5 according to the third embodiment of the present invention. FIG. 19 shows an example of input / output signal waveforms of the inverter circuit 5 of FIG. The inverter circuit 5 outputs a pulse signal (for example, FIG. 19D) obtained by substantially inverting the signal waveform (for example, FIG. 19A) of the pulse signal input to the input terminal IN from the output terminal OUT. . The inverter circuit 5 is preferably formed on amorphous silicon or an amorphous oxide semiconductor, and includes, for example, seven transistors Tr1 to Tr7 of the same channel type. The inverter circuit 5 includes two capacitive elements C1 and C2, three input terminals IN1 to IN3, and an output terminal OUT in addition to the seven transistors Tr1 to Tr7, and has a 7Tr2C circuit configuration. ing.

  The transistor Tr1 corresponds to a specific example of the “first transistor” of the present invention, the transistor Tr2 corresponds to a specific example of the “second transistor” of the present invention, and the transistor Tr3 corresponds to the “third transistor” of the present invention. This corresponds to a specific example. The transistor Tr4 corresponds to a specific example of the “fourth transistor” of the present invention, and the transistor Tr5 corresponds to a specific example of the “fifth transistor” of the present invention. The transistor Tr6 corresponds to a specific example of “sixth transistor” of the present invention, and the transistor Tr7 corresponds to a specific example of “seventh transistor” of the present invention. The capacitive element C1 corresponds to a specific example of “first capacitive element” of the present invention, and the capacitive element C2 corresponds to a specific example of “second capacitive element” of the present invention.

  The transistors Tr1 to Tr7 are, for example, n-channel MOS (Metal Oxide Semiconductor) type thin film transistors (TFTs). For example, the transistor Tr1 has an electrical connection between the output terminal OUT and the low voltage line L1 according to a potential difference (or a potential difference corresponding thereto) between the voltage of the input terminal IN1 (input voltage Vin1) and the voltage of the low voltage line L1. The connection is broken. The gate of the transistor Tr1 is electrically connected to the input terminal IN1. The source or drain of the transistor Tr1 is electrically connected to the low voltage line L1, and the terminal not connected to the low voltage line L1 among the source and drain of the transistor Tr1 is electrically connected to the output terminal OUT.

  The transistor Tr2 is electrically connected between the high voltage line L2 and the output terminal OUT in accordance with a potential difference (or potential difference corresponding thereto) between the gate voltage Vg2 of the transistor Tr2 and the voltage (output voltage Vout) of the output terminal OUT. Is supposed to be cut off. The gate of the transistor Tr2 is electrically connected to the source or drain of the transistor Tr6. The source or drain of the transistor Tr2 is electrically connected to the output terminal OUT, and the terminal not connected to the output terminal OUT among the source and drain of the transistor Tr2 is electrically connected to the high voltage line L2.

  The transistor Tr3 electrically connects the gate of the transistor Tr5 and the low voltage line L1 in accordance with the potential difference (or potential difference corresponding thereto) between the voltage of the input terminal IN2 (input voltage Vin2) and the voltage of the low voltage line L1. It is supposed to be relayed. The gate of the transistor Tr3 is electrically connected to the input terminal IN2. The source or drain of the transistor Tr3 is electrically connected to the low voltage line L1, and the terminal not connected to the low voltage line L1 among the source and drain of the transistor Tr3 is electrically connected to the gate of the transistor Tr5. .

  The transistor Tr4 has a potential difference between the source or drain of the transistor Tr5 (hereinafter referred to as “terminal B”) and the low voltage line L1 according to the potential difference (or potential difference corresponding thereto) between the input voltage Vin2 and the voltage of the low voltage line L1. The electrical connection is cut off. The gate of the transistor Tr4 is electrically connected to the input terminal IN2. The source or drain of the transistor Tr4 is electrically connected to the low voltage line L1, and the terminal not connected to the low voltage line L1 among the source and drain of the transistor Tr4 is electrically connected to the terminal B of the transistor Tr5. Yes.

  The transistor Tr5 cuts off the electrical connection between the high voltage line L3 and the terminal B in accordance with the potential difference (or the potential difference corresponding thereto) between the gate voltage Vg5 of the transistor Tr5 and the voltage at the terminal B. Yes. The gate of the transistor Tr5 is electrically connected to a terminal not connected to the low voltage line L1 among the source and drain of the transistor Tr3. The terminal B of the transistor Tr5 is electrically connected to a terminal not connected to the low voltage line L1 among the source and drain of the transistor Tr4, and a terminal different from the terminal B among the source and drain of the transistor Tr5 is a high voltage line. L3 is electrically connected.

  The transistor Tr6 cuts off the electrical connection between the gate of the transistor Tr2 and the low voltage line L1 in accordance with the potential difference (or potential difference corresponding thereto) between the input voltage Vin1 and the voltage of the low voltage line L1. Yes. The gate of the transistor Tr6 is electrically connected to the input terminal IN1. The source or drain of the transistor Tr6 is electrically connected to the low voltage line L1, and the terminal not connected to the low voltage line L1 among the source and drain of the transistor Tr6 is electrically connected to the gate of the transistor Tr2. . That is, the transistors Tr1, Tr3, Tr4, Tr6 are connected to the same voltage line (low voltage line L1). Accordingly, the terminals on the low voltage line L1 side among the sources and drains of the transistors Tr1, Tr3, Tr4, Tr6 have the same potential.

  The transistor Tr7 disconnects the electrical connection between the terminal B of the transistor Tr5 and the gate of the transistor Tr2 in accordance with a voltage (input voltage Vin3) input to the gate of the transistor Tr7 via the input terminal IN3. It has become. The gate of the transistor Tr7 is electrically connected to the input terminal IN3. The source or drain of the transistor Tr7 is electrically connected to the terminal B of the transistor Tr5, and the terminal not connected to the terminal B among the source and drain of the transistor Tr7 is electrically connected to the gate of the transistor Tr2.

  The low voltage line L1 corresponds to a specific example of “first voltage line”, “third voltage line”, “fourth voltage line”, and “sixth voltage line” of the present invention. The high voltage line L2 corresponds to a specific example of the “second voltage line” of the present invention, and the high voltage line L3 corresponds to a specific example of the “fifth voltage line” of the present invention.

  The high voltage lines L2 and L3 are connected to a power supply (not shown) that outputs a higher voltage (constant voltage) than the voltage of the low voltage line L1. The voltage of the high voltage line L2 is Vdd when the inverter circuit 1 is driven, and the voltage of the high voltage line L3 is a voltage Vdd2 higher than Vdd when the inverter circuit 1 is driven. Note that the voltage of the high voltage line L3 is preferably higher than Vdd + Vth2 when the inverter circuit 1 is driven. The low voltage line L1 is connected to a power source (not shown) that outputs a voltage (constant voltage) lower than the voltages of the high voltage lines L2 and L3, and the voltage of the low voltage line L1 is used to drive the inverter circuit 1. Sometimes the voltage Vss (<Vdd).

The capacitive elements C1 and C2 are inserted in series between the input terminal IN2 and the gate of the transistor Tr5. An electrical connection point A between the capacitive element C1 and the capacitive element C2 is electrically connected to a terminal B of the transistor Tr5 (that is, a connection point between the transistor Tr5 and the transistor Tr4). The capacitive element C1 is inserted on the gate side of the transistor Tr5, and the capacitive element C2 is inserted on the gate side of the transistor Tr4. The capacity of the capacitive element C2 is larger than the capacity of the capacitive element C1. The capacitances of the capacitive elements C1 and C2 preferably satisfy the following formula (2). If the capacitive elements C1 and C2 satisfy Expression (2), when the input voltage Vin2 falls, the gate-source voltage of the transistor Tr5 can be set to the threshold voltage Vth5 or more, and the output voltage Vout is low. Can shift to high. In Expression (2), Vdd2 is the voltage of the high voltage line L3, and Vss is the voltage of the low voltage line L1.
Cb (Vdd2-Vss) / (Ca + Cb)> Vth5 (2)

  By the way, the previous stage of the inverter circuit 5 is the one in which the control element 10 and the transistor Tr3 are inserted between the transistors Tr4 and Tr5 and the input terminal IN2 in relation to the conventional inverter circuit (inverter circuit 200 in FIG. 37). Equivalent to. Here, for example, as shown in FIG. 18, the control element 10 includes a first terminal P1 electrically connected to the input terminal IN2, a second terminal P2 electrically connected to the transistor T7, and a transistor Tr5. The third terminal P3 is electrically connected to the gate. The control element 10 further includes, for example, capacitive elements C1 and C2, as shown in FIG. For example, when the falling voltage is input to the first terminal P1, the control element 10 makes the transient at the second terminal P2 gentler than the transient at the third terminal P3. Specifically, for example, when the falling voltage is input to the input terminal IN2, the control element 10 makes the transient of the source of the transistor Tr5 (terminal on the transistor Tr7 side) gentler than the transient of the gate of the transistor Tr5. It is like that. The operation of the control element 10 will be described together with the following description of the operation of the inverter circuit 5.

[Operation]
Next, an example of the operation of the inverter circuit 5 will be described with reference to FIGS. FIG. 19 is a waveform diagram illustrating an example of the operation of the inverter circuit 5. 20 to 28 are circuit diagrams illustrating an example of a series of operations of the inverter circuit 5.

  First, when the input voltages Vin1, Vin2 are high (Vdd), the transistors Tr1, Tr3, Tr4, Tr6 are in an on state, and the gate voltages Vg2, Vg5 and source voltages Vs2, Vs5 of the transistors Tr2, Tr5 are low. It is charged to the voltage of the line L1 (= Vss) (FIGS. 19 and 20). Therefore, the transistors Tr2 and Tr5 are in the off state (when the gate-source voltages Vgs2 and Vgs5 = 0V), and the voltage Vss is output as the output voltage Vout. At this time, the capacitor element C2 is charged with a voltage of Vdd-Vss. Further, since the source voltage Vs5 of the transistor Tr5 and the gate voltage Vg2 of the transistor Tr2 are set to Vss by the transistors Tr4 and Tr6, the potential of each node does not change even when the transistor Tr7 is repeatedly turned on and off.

  Next, when the input voltage Vin1 is high (Vdd) and the transistor Tr7 is off, the input voltage Vin2 changes (decreases) from high (Vdd) to low (Vss) (FIGS. 19 and 21). ). As a result, the change in the gate voltage of the transistors Tr3 and Tr4 propagates to the source (terminal B) of the transistor Tr5 via the capacitive element C2, and the source voltage Vs5 of the transistor Tr5 changes (decreases) by ΔV1 ′. Further, the change in the gate voltage Vg5 of the transistor Tr5 is also propagated to the gate of the transistor Tr5 via the capacitive elements C1 and C2, and the gate voltage Vg5 of the transistor Tr5 changes (decreases) by ΔV2 ′. However, at this time, the transistors Tr3 and Tr4 are on. Therefore, current flows from the low voltage line L1 toward the source (terminal B) of the transistor Tr5 and the gate of the transistor Tr5, and the current tries to charge them to Vss.

  Here, since the gate voltages of the transistors Tr3 and Tr4 change (decrease) from Vdd to Vss, the on-resistances of the transistors Tr3 and Tr4 gradually increase, and the source (terminal B) and gate of the transistor Tr5 become low voltage. The time required to charge the voltage of the line L1 becomes longer.

  Further, comparing the total capacitance seen from the source (terminal B) and the gate of the transistor Tr5, the capacitive elements C1 and C2 are connected in parallel to the source (terminal B) of the transistor Tr5, and the capacitive elements C1 and C2 are connected to the gate of the transistor Tr5. C2 is connected in series. For this reason, the source (terminal B) of the transistor Tr5 has a slower transient than the gate of the transistor Tr5. As a result, the time required to charge the source (terminal B) of the transistor Tr5 to the voltage of the low voltage line L1 is longer than the time required to charge the gate of the transistor Tr5 to the voltage of the low voltage line L1. .

  In addition, when the input voltage Vin2 is Vss + Vth3 or more, and further, Vss + Vth4 or more, the transistors Tr3 and Tr4 operate in a linear region. Vth3 is the threshold voltage of the transistor Tr3, and Vth4 is the threshold voltage of the transistor Tr4. On the other hand, when the input voltage Vin2 is less than Vss + Vth3 and further less than Vss + Vth4, the transistors Tr3 and Tr4 operate in the saturation region. Therefore, a current as shown in FIG. 21 flows through the source (terminal B) and gate of the transistor Tr5, but the transistors Tr3 and Tr4 cannot charge each point to the voltage Vss.

  Finally, when the input voltage Vin2 changes from Vdd to Vss, the gate-source voltage Vgs5 of the transistor Tr5 becomes ΔV1−ΔV2 (FIGS. 19 and 22). At this time, when the gate-source voltage Vgs5 of the transistor Tr5 becomes larger than the threshold voltage Vth5 of the transistor Tr5, the transistor Tr5 is turned on and a current starts to flow from the high voltage line L3.

  When the transistor Tr5 is on, the source voltage Vs5 of the transistor Tr5 is increased by the transistor Tr5 in addition to the transistor Tr4. Further, since the capacitive element C1 is connected between the gate and source of the transistor Tr5, a bootstrap occurs, and the gate voltage Vg5 of the transistor Tr5 also increases in conjunction with the increase of the source voltage Vs5 of the transistor Tr5. After that, when the source voltage Vs5 and the gate voltage Vg5 of the transistor Tr5 become Vss−Vth3 or more and further become Vss−Vth4 or more, the transistors Tr3 and Tr4 are turned off, and the source voltage Vs5 and the gate voltage Vs5 of the transistor Tr5 become It rises only by the transistor Tr5.

  After a certain period of time, the input voltage Vin1 changes (decreases) from high (Vdd) to low (Vss) when the source voltage Vs5 of the transistor Tr5 becomes Vdd2 (FIGS. 19 and 23). At this time, since the transistor Tr7 is off, the gate voltage Vg2 of the transistor Tr2 remains Vss, and the output voltage Vout still remains Vss.

  Next, the transistor Tr7 is turned on (FIG. 24). At this time, since the input voltages Vin1 and Vin2 are both low (Vss) and the transistors Tr1, Tr3, Tr4, and Tr6 are off, the capacitance between the source of the transistor Tr5 (terminal B) and the gate of the transistor Tr2 Bonding occurs. Here, since the capacitive elements C1 and C2 are connected in parallel to the source (terminal B) of the transistor Tr5, the capacitance value is large. On the other hand, only the parasitic capacitance of the transistor is connected to the gate of the transistor Tr2. Therefore, the gate voltage Vg2 of the transistor Tr2 greatly increases from Vss due to capacitive coupling, and the source voltage Vs5 of the transistor Tr5 decreases from Vdd2. As a result, the transistor Tr2 is turned on, the gate-source voltage of the transistor Tr2 increases, and the output voltage Vout changes from Vss to Vdd. Further, while the transistor Tr7 is on, the gate voltage of the transistor Tr2 continues to increase by the transistor Tr5.

  After a certain time has elapsed, the transistor Tr7 is turned off, and the source (terminal B) of the transistor Tr5 and the gate of the transistor Tr2 are electrically disconnected (FIG. 25). As a result, the gate voltage of the transistor Tr2 remains Vx and does not change, but the source voltage of the transistor Tr5 rises and becomes Vdd2 again. Thereafter, when the transistor Tr7 is turned on again, the gate voltage Vg2 of the transistor Tr2 rises due to capacitive coupling. By repeating this for a while, the gate voltage Vg2 of the transistor Tr2 and the source voltage Vs5 of the transistor Tr5 finally become the same voltage (Vdd2).

  Thereafter, the input voltages Vin1 and Vin2 change (rise) from low (Vss) to high (Vdd) (FIG. 19). Then, the transistors Tr1, Tr3, Tr4, Tr6 are turned on, and each node is charged to Vss. Finally, the transistors Tr2 and Tr5 are turned off, and Vss is output as the output voltage Vout.

  As described above, in the inverter circuit 5 of the present embodiment, the pulse signal (for example, FIG. 19D) obtained by substantially inverting the signal waveform (for example, FIG. 19A) of the pulse signal input to the input terminal IN1. ) Is output from the output terminal OUT.

[effect]
In the inverter circuit 5 of the present embodiment, there is almost no period in which the transistors Tr1 and Tr2 are simultaneously turned on and the transistors Tr4 and Tr5 are simultaneously turned on. As a result, almost no current (through current) flows between the high voltage lines L2 and L3 and the low voltage line L1 via the transistors Tr1 and Tr2 and the transistors Tr4 and Tr5, so that power consumption can be suppressed. . Further, when the gate voltages of the transistors Tr1, Tr3, Tr4, and Tr6 change (decrease) from high (Vdd) to low (Vss), the output voltage Vout becomes the voltage on the high voltage line L2, and the transistors Tr1, Tr3 , Tr4, and Tr6, the output voltage Vout is set to the voltage on the low voltage line L1 side when the gate voltage changes (rises) from low (Vss) to high (Vdd). As a result, variations in the output voltage Vout can be eliminated. As a result, for example, variations in threshold correction and mobility correction of the drive transistor in the pixel circuit can be reduced for each pixel circuit, and further, luminance variations for each pixel can be reduced.

  In the inverter circuit 5 according to the present embodiment, the source voltage Vs5 of the transistor Tr5 is set in advance using a voltage (input voltage Vin2) having a phase earlier than the voltage (input voltage Vin1) input to the gates of the transistors Tr1 and Tr6. The transient of the gate voltage Vg2 of the transistor Tr2 is accelerated by setting the gate voltage of the transistor Tr2 at a stretch by capacitive coupling via the transistor Tr7. As a result, the inverter circuit 5 can be speeded up.

  Next, the merit of speeding up the inverter circuit 5 by the above method will be described in comparison with a comparative example.

  FIG. 41 illustrates an example of the overall configuration of the inverter circuit 500 according to the comparative example. FIG. 42 shows an example of input / output voltage waveforms of the inverter circuit 500 of FIG. The inverter circuit 500 outputs, from the output terminal OUT, a pulse signal (for example, FIG. 42B) obtained by substantially inverting the signal waveform (for example, FIG. 42A) of the pulse signal input to the input terminal IN. . The inverter circuit 500 includes five transistors Tr11 to Tr15 having the same channel type, two capacitive elements C11 and C12, an input terminal IN, and an output terminal OUT, and has a 5Tr2C circuit configuration.

  Next, an example of the operation of the inverter circuit 500 will be described with reference to FIGS. FIG. 43 is a waveform diagram illustrating an example of the operation of the inverter circuit 500. 44 to 49 are circuit diagrams illustrating an example of a series of operations of the inverter circuit 500.

  First, when the input voltage Vin is high (Vdd), the transistors Tr11, Tr13, Tr14 are turned on. Then, the gate voltage Vg12 and the source voltage Vs12 of the transistor Tr12 are charged to the voltage (= Vss) of the low voltage line L1, and further, the gate voltage Vg15 and the source voltage Vs15 of the transistor Tr15 are charged to the voltage (= Vss) of the low voltage line L1. (FIGS. 43 and 44). As a result, the transistor Tr12 is turned off, the transistor Tr15 is turned off, and the voltage Vss is output as the output voltage Vout. At this time, the capacitor C12 is charged with a voltage of Vdd-Vss.

  Next, when the input voltage Vin changes (decreases) from high (Vdd) to low (Vss), the gate voltages Vg11, Vg13, Vg14 of the transistors Tr11, Tr13, Tr14 also change (decrease) from Vdd to Vss (FIG. 43, FIG. 45). As a result, the change in the gate voltage Vg11 of the transistor Tr11 propagates to the gate of the transistor Tr12 via the capacitive element C12, and the gate voltage Vg12 of the transistor Tr12 changes (decreases) by ΔV1 ′. Further, the change in the gate voltage Vg11 of the transistor Tr11 is also propagated to the gate of the transistor Tr15 via the capacitive elements C11 and C12, and the gate voltage Vg15 of the transistor Tr15 changes (decreases) by ΔV2 ′. However, at this time, the transistors Tr13 and Tr14 are on. Therefore, current flows from the low voltage line L1 toward the source and gate of the transistor Tr15, and the current tries to charge them to Vss.

  Here, since the gate voltages Vg13 and Vg14 of the transistors Tr13 and Tr14 change (decrease) from Vdd to Vss, the on-resistances of the transistors Tr13 and Tr14 gradually increase, and the source and gate of the transistor Tr15 are connected to the low voltage line. The time required to charge to the voltage of L1 becomes longer.

  Further, comparing the total capacitances visible from the source and gate of the transistor Tr15, the capacitive elements C11 and C12 are connected in parallel to the source of the transistor Tr15, and the capacitive elements C11 and C12 are connected in series to the gate of the transistor Tr15. For this reason, the transient of the source of the transistor Tr15 is slower than that of the gate of the transistor Tr15. As a result, the time required to charge the source of the transistor Tr15 to the voltage of the low voltage line L1 is longer than the time required to charge the gate of the transistor Tr15 to the voltage of the low voltage line L1.

  In addition, when the input voltage Vin is Vss + Vth13 or more, and further, Vss + Vth14 or more, the transistors Tr13 and Tr14 operate in a linear region. Vth13 is the threshold voltage of the transistor Tr13, and Vth14 is the threshold voltage of the transistor Tr14. On the other hand, when the input voltage Vin is less than Vss + Vth13 and further less than Vss + Vth14, the transistors Tr13 and Tr14 operate in the saturation region. Therefore, a current as shown in FIG. 45 flows through the source and gate of the transistor Tr15, but the transistors Tr13 and Tr14 cannot charge each point to the voltage Vss.

  Finally, when the input voltage Vin changes from Vdd to Vss, the gate-source voltage Vgs15 of the transistor Tr15 becomes ΔV1−ΔV2 (FIGS. 43 and 46). At this time, when the gate-source voltage Vgs15 of the transistor Tr15 becomes larger than the threshold voltage Vth15 of the transistor Tr15, the transistor Tr15 is turned on and current starts to flow from the high voltage line L3.

  When the transistor Tr15 is on, the source voltage Vs15 of the transistor Tr15 is increased by the transistor Tr15 in addition to the transistor Tr14. Further, since the capacitive element C1 is connected between the gate and source of the transistor Tr15, a bootstrap occurs, and the gate voltage Vg15 of the transistor Tr15 also rises in conjunction with the rise of the source voltage Vs15 of the transistor Tr15. After that, when the source voltage Vs15 and the gate voltage Vg15 of the transistor Tr15 become Vss−Vth13 or more and further become Vss−Vth14 or more, the transistors Tr13 and Tr14 are turned off, and the source voltage Vs15 and the gate voltage Vg15 of the transistor Tr15 become It rises only by the transistor Tr15.

  When the source voltage Vs15 of the transistor Tr15 (the gate voltage Vg12 of the transistor Tr12) becomes equal to or higher than Vss + Vth12 after a certain time has elapsed, the transistor Tr12 is turned on and current starts to flow from the high voltage line L2 (FIGS. 43 and 47). Vth12 is a threshold voltage of the transistor Tr12. As a result, the voltage Vout of the output terminal OUT gradually increases from Vss. The gate voltage Vg12 of the transistor Tr12 eventually rises to the voltage of the high voltage line L3 due to the current from the transistor Tr15 (FIGS. 43 and 48). Here, since the voltage of the high voltage line L3 is Vdd2 larger than Vdd + Vth12 when the inverter circuit 500 is driven, the transistor Tr12 outputs the voltage Vdd of the high voltage line L2 to the output terminal OUT. As a result, Vdd is output from the output terminal OUT (FIGS. 43 and 48).

  Further, after a predetermined time has elapsed, the input voltage Vin changes (rises) from low (Vss) to high (Vdd) (FIGS. 43 and 49). At this time, when the input voltage Vin is lower than Vss + Vth13 and further lower than Vss + Vth14, the transistors Tr13 and Tr14 are turned off. Therefore, coupling via the capacitive elements C1 and C2 is input to the source and gate of the transistor Tr15, and the source voltage Vs15 and gate voltage Vg15 of the transistor Tr15 rise. Thereafter, when the input voltage Vin becomes Vss + Vth11, Vss + Vth13, and Vss + Vth14 or more, the transistors Tr11, Tr13, Tr14 are turned on. Therefore, current flows toward the source (output terminal OUT) of the transistor Tr12 and the source and gate of the transistor Tr15, and the current tries to charge them to Vss.

  Here, since the gate voltages Vg11, Vg13, Vg14 of the transistors Tr11, Tr13, Tr14 change (rise) from Vdd to Vss, the on-resistances of the transistors Tr11, Tr13, Tr14 gradually decrease, and the transistors Tr12, Tr15 The time required to charge the source and gate of the transistor to the voltage of the low voltage line L1 is relatively shortened. Finally, the source voltage Vs12 of the transistor Tr12, the source voltage Vs15 of the transistor Tr15, and the gate voltage Vg15 become Vss, and Vss is output from the output terminal OUT (FIGS. 43 and 44).

  As described above, in the inverter circuit 500 according to the comparative example, the pulse signal (for example, FIG. 43B) obtained by substantially inverting the signal waveform (for example, FIG. 43A) of the pulse signal input to the input terminal IN. Is output from the output terminal OUT.

  By the way, in the above inverter circuit 500, the coupling amount input to the gate and source of the transistor Tr5 is charged by the voltage input via C12 and C11 and the transistor connected to the gate and source of the transistor Tr15. It is the sum of the voltage. For this reason, when the waveform of the input voltage Vin is input with a dullness, the time for charging each node by the above-described transistor becomes long, so the total coupling amount becomes small. As a result, the increase in the gate voltage Vg12 of the transistor Tr12 becomes moderate, and the output voltage Vout also changes gradually accordingly. That is, the ON time (time when the output voltage Vout is high) is greatly affected by the dullness of the input voltage Vin. Therefore, when the above-described inverter circuit 500 is used in, for example, a drive circuit for the control line (WS line) of the writing transistor of the pixel circuit, the on-time of the transistor Tr11 changes due to the dullness of the input voltage Vin. Therefore, there is a possibility that the signal voltage cannot be normally written to the writing transistor.

  On the other hand, in the inverter circuit 5 of the present embodiment, the transient of the gate voltage of the transistor Tr2 is accelerated by the above-described method. Therefore, the ON time of the output voltage Vout does not change due to the dullness of the input potentials Vin1 and Vin2. For this reason, when the inverter circuit 5 is used as a drive circuit for the control line (WS line) of the writing transistor of the pixel circuit, the on-time of the transistor Tr1 does not change due to the dullness of the input voltages Vin1 and Vin2. A signal voltage can be written to the.

<5. Modification of Third Embodiment>
In the inverter circuit 5 of the above embodiment, for example, as shown in FIG. 26, the capacitive element C3 is provided between the gate of the transistor Tr2 and the source (terminal on the output terminal OUT side) of the transistor Tr2. May be. In this case, the high voltage line L3 connected to the transistor Tr5 can be replaced with the high voltage line L2. That is, by providing the capacitive element C3, the transistors Tr2 and Tr5 can be connected to the same voltage line (high voltage line L2). At this time, terminals on the high voltage line L2 side among the sources and drains of the transistors Tr2 and Tr5 have the same potential.

  Next, the operation of the inverter circuit 5 shown in FIG. 26 will be described. Since the operation of the inverter circuit 5 shown in FIG. 26 is not significantly different from the operation of the inverter circuit 5 shown in FIG. 18, the following description will be made on the parts different from the operation of the inverter circuit 5 shown in FIG.

  When the transistor Tr7 is turned on after the input voltage Vin1 changes from high to low, capacitive coupling occurs between the gate of the transistor Tr2 and the source (terminal B) of the transistor Tr5, and the gate voltage of the transistor Tr2 is Vx. Become. At this time, the gate-source voltage of the transistor Tr2 is held in the capacitor C3. If the value is larger than the threshold voltage Vth2 of the transistor Tr2, a current flows as shown in FIG. 27, and the output voltage Vout increases. Start. As described above, the capacitive element C3 is connected between the gate and the source of the transistor Tr2, and the gate voltage of the transistor Tr2 starts increasing as the output voltage Vout increases. Here, the voltage applied to the gate of the transistor Tr7 in the on state is Vdd. Therefore, when the gate voltage of the transistor Tr2 and the source voltage of the transistor Tr5 become higher than Vdd−Vth7, the transistor Tr7 is automatically turned off, and the gate and source voltages of the transistor Tr2 continue to increase and finally output. Vdd is output as the voltage Vout (FIG. 28).

  In the present modification, Vss is output as the output voltage Vout when Vdd is applied to the input terminal IN1, and Vdd is output as the output voltage Vout when Vss is applied to the input terminal IN1, as in the third embodiment. Is output. Further, the through current flowing from the high voltage line L2 to the low voltage line L1 can be eliminated, and the power consumption of the inverter circuit 5 can be reduced. Further, in this modification, only two types of voltages, Vdd and Vss, need to be input to the inverter circuit 5, so that a power source having a higher voltage than the input voltages Vin1 and Vin2 is not required, and a narrow frame, Yield can be increased.

  In this modification, the source voltage of the transistor Tr5 is set to a high voltage in advance using the input voltage Vin2 having a phase earlier than the input voltage Vin1, and the gate voltage of the transistor Tr2 is increased by capacitive coupling via the transistor Tr7. Thus, the transient of the gate voltage of the transistor Tr2 can be accelerated. As a result, the inverter circuit 5 can be speeded up. Further, since the ON time of the output voltage Vout does not change due to the dullness of the input potentials Vin1 and Vin2, when used in the drive circuit of the control line (WS line) of the writing transistor of the pixel circuit, the dullness of the input voltages Vin1 and Vin2 Since the on-time of the transistor Tr1 does not change, the signal voltage can be normally written to the writing transistor.

<3. Application example>
FIG. 29 illustrates an example of the overall configuration of the display device 100 which is an example of an application example of the inverter circuit 1 according to the embodiment and the modification thereof. The display device 100 includes, for example, a display panel 110 and a drive circuit 120 that drives the display panel 110. The display panel 110 corresponds to a specific example of the “display unit” of the present invention, and the drive circuit 120 corresponds to a specific example of the “drive unit” of the present invention.

(Display panel 110)
The display panel 110 has a display area 110A in which a plurality of display pixels 114 are two-dimensionally arranged, and each display pixel 114 is driven by a drive circuit 120 to display an image on the display area 110A. is there. Each display pixel 114 includes three pixels 113R, 113G, and 113B adjacent to each other. Hereinafter, the pixel 113 is appropriately used as a general term for the pixels 113R, 113G, and 113B.

  The pixel 113R includes an organic EL element 111R and a pixel circuit 112. The pixel 113G includes an organic EL element 111G and a pixel circuit 112. The pixel 113B includes an organic EL element 111B and a pixel circuit 112. The organic EL element 111R is an organic EL element that emits red light, the organic EL element 111G is an organic EL element that emits green light, and the organic EL element 111B is an organic EL element that emits blue light. Hereinafter, the organic EL element 111 is appropriately used as a general term for the organic EL elements 111R, 111G, and 111B.

  FIG. 30 illustrates an example of a circuit configuration in the display region 110A together with an example of a writing line driving circuit 124 described later. In the display area 110 </ b> A, a plurality of pixel circuits 112 are two-dimensionally arranged in pairs with the individual organic EL elements 111. Each pixel circuit 112 includes, for example, a drive transistor Tr100 that controls a current flowing through the organic EL element 111, a write transistor Tr200 that writes the voltage of the signal line DTL to the drive transistor Tr100, and a storage capacitor Cs. 2Tr1C circuit configuration. The drive transistor Tr100 and the write transistor Tr200 are formed of, for example, an n-channel MOS thin film transistor (TFT). The drive transistor Tr100 or the write transistor Tr200 may be, for example, a p-channel MOS type TFT.

  In display area 110A, a plurality of write lines WSL are arranged in rows, and a plurality of signal lines DTL are arranged in columns. The write line WSL corresponds to a specific example of “scan line” of the present invention. In the display area 110A, a plurality of power supply lines PSL (members to which power supply voltage is supplied) are further arranged in rows along the write lines WSL. One pixel 113 is provided near the intersection of each signal line DTL and each write line WSL. Each signal line DTL is connected to an output terminal of a signal line driving circuit 123 described later and one of a drain electrode and a source electrode of the write transistor Tr200. Each write line WSL is connected to an output terminal of a write line drive circuit 124 described later and a gate electrode of the write transistor Tr200. Each power supply line PSL is connected to an output terminal of a power supply line drive circuit 125 described later and one of the drain electrode and the source electrode of the drive transistor Tr100. Of the drain electrode and the source electrode of the write transistor Tr200, the electrode not connected to the signal line DTL is connected to the gate electrode of the drive transistor Tr100 and one end of the storage capacitor Cs. Of the drain electrode and source electrode of the drive transistor Tr100, the electrode not connected to the power supply line PSL and the other end of the storage capacitor Cs are connected to the anode electrode (not shown) of the organic EL element 111. The cathode electrode of the organic EL element 111 is connected to the ground line GND, for example.

(Drive circuit 120)
Next, each circuit in the drive circuit 120 will be described with reference to FIG. 29, FIG. 30, and FIG. FIG. 31 shows an example of the waveform of the synchronization signal and an example of a voltage waveform output from the drive circuit 120 to each write line WSL. The drive circuit 120 includes a timing generation circuit 121, a video signal processing circuit 122, a signal line drive circuit 123, a write line drive circuit 124, and a power supply line drive circuit 125. The drive circuit 120 also includes various power sources (specifically, power sources connected to the low voltage line L1, the high voltage lines L2, L3, L4, and the like) in the above-described embodiment and modifications thereof.

  The timing generation circuit 121 controls the video signal processing circuit 122, the signal line drive circuit 123, the write line drive circuit 124, and the power supply line drive circuit 125 to operate in conjunction with each other. The timing generation circuit 121 outputs a control signal 121A to each circuit described above, for example, in response to (in synchronization with) the synchronization signal 120B input from the outside.

  The video signal processing circuit 122 performs predetermined correction on the video signal 120 </ b> A input from the outside, and outputs the corrected video signal 122 </ b> A to the signal line driving circuit 123. Examples of the predetermined correction include gamma correction and overdrive correction.

  In response to (in synchronization with) the input of the control signal 121A, the signal line driver circuit 123 applies the video signal 122A input from the video signal processing circuit 122 to each signal line DTL and writes it to the pixel 113 to be selected. Is. Note that writing refers to applying a predetermined voltage to the gate of the driving transistor T100.

  The signal line driver circuit 123 includes, for example, a shift register (not shown), and includes a buffer circuit (not shown) for each stage corresponding to each column of the pixels 113. The signal line driving circuit 123 can output, for example, two types of voltages (Vofs, Vsig) to each signal line DTL in response to (in synchronization with) the input of the control signal 121A. Specifically, the signal line driver circuit 123 sequentially applies two types of voltages (Vofs, Vsig) to the pixel 113 selected by the write line driver circuit 124 via the signal line DTL connected to each pixel 113. To supply.

  Here, the offset voltage Vofs has a constant voltage value regardless of the value of the signal voltage Vsig. The signal voltage Vsig is a voltage value corresponding to the video signal 122A. The minimum voltage of the signal voltage Vsig is a voltage value lower than the offset voltage Vofs, and the maximum voltage of the signal voltage Vsig is a voltage value higher than the offset voltage Vofs.

  The write line driving circuit 124 includes, for example, a shift register (not shown), and includes a buffer circuit 2 for each stage corresponding to each row of the pixels 113. The buffer circuit 2 includes a plurality of the inverter circuits 1 described above, and outputs a pulse signal having substantially the same phase as the pulse signal input to the input terminal from the output terminal. The write line driving circuit 124 can output two types of voltages (Vdd, Vss) to each write line WSL in response to (in synchronization with) the input of the control signal 121A. Specifically, the write line drive circuit 124 supplies two types of voltages (Vdd, Vss) to the drive target pixel 113 via the write line WSL connected to each pixel 113, and the write transistor T200. Is to control. For example, as shown in FIG. 31, when the clock ck and the scan pulse sp are input as the control signal 121A, the write line driving circuit 124 has a peak value Vdd for a plurality of write lines WSL. Thus, a voltage Vs (i) including a pulse having a width of 2H (1 ≦ i ≦ N, i and N are positive integers) is sequentially output while shifting the phase of the pulse by 1H.

  Here, the voltage Vdd has a value equal to or higher than the ON voltage of the write transistor T200. The voltage Vdd is, for example, a voltage value output from the write line driving circuit 124 during threshold correction, mobility correction, and light emission operation. The voltage Vss is lower than the on-voltage of the write transistor T200 and lower than the voltage Vdd.

  The power supply line driving circuit 125 includes a shift register (not shown), for example, and includes a buffer circuit (not shown) for each stage corresponding to each row of the pixels 113, for example. The power supply line driving circuit 125 can output two types of voltages (VccH and VccL) in response to (in synchronization with) the input of the control signal 121A. Specifically, the power supply line drive circuit 125 supplies two types of voltages (VccH and VccL) to the drive target pixel 113 via the power supply line PSL connected to each pixel 113, and the organic EL element 111. Light emission and quenching are controlled.

  Here, the voltage VccL is a voltage value lower than a voltage obtained by adding the threshold voltage of the organic EL element 111 and the voltage of the cathode of the organic EL element 111. The voltage VccH is a voltage value equal to or higher than the sum of the threshold voltage of the organic EL element 111 and the cathode voltage of the organic EL element 111.

  Next, an example of the operation (operation from extinction to light emission) of the display device 100 of this application example will be described. In this application example, even if the threshold voltage Vth and mobility μ of the driving transistor Tr100 change with time, the light emission luminance of the organic EL element 111 is kept constant without being affected by the change. A correction operation for variations in threshold voltage Vth and mobility μ is incorporated.

  FIG. 32 shows an example of a voltage waveform applied to the pixel circuit 112 and an example of changes in the gate voltage Vg and the source voltage Vs of the drive transistor Tr100. FIG. 32A shows a state in which the signal voltage Vsig and the offset voltage Vofs are applied to the signal line DTL. FIG. 32B shows a state where a voltage Vdd for turning on the writing transistor Tr200 and a voltage Vss for turning off the writing transistor Tr200 are applied to the writing line WSL. FIG. 32C shows a state where the voltage VccH and the voltage VccL are applied to the power supply line PSL. Further, in FIGS. 32D and 32E, the gate voltage Vg and the source voltage Vs of the drive transistor Tr100 change from time to time in response to voltage application to the power supply line PSL, the signal line DTL, and the write line WSL. Is shown.

(Vth correction preparation period)
First, preparation for Vth correction is performed. Specifically, when the voltage of the write line WSL is Voff and the voltage of the power supply line DSL is VccH (that is, when the organic EL element 111 emits light), the power supply line drive circuit 125. Lowers the voltage of the power supply line DSL from VccH to VccL (T1). Then, the source voltage Vs becomes VccL, and the organic EL element 111 is quenched. Thereafter, when the voltage of the signal line DTL is Vofs, the write line drive circuit 124 increases the voltage of the write line WSL from Vofs to Von, and the gate of the drive transistor Tr100 is set to Vofs.

(First Vth correction period)
Next, Vth is corrected. Specifically, while the write transistor Tr200 is on and the voltage of the signal line DTL is Vofs, the power supply line drive circuit 125 increases the voltage of the power supply line DSL from VccL to VccH (T2). Then, a current flows between the drain and source of the drive transistor Tr100, and the source voltage Vs increases. Thereafter, before the signal line drive circuit 123 switches the voltage of the signal line DTL from Vofs to Vsig, the write line drive circuit 124 lowers the voltage of the write line WSL from Von to Voff (T3). Then, the gate of the drive transistor Tr100 becomes floating, and the correction of Vth is suspended.

(First Vth correction pause period)
During the period when the Vth correction is paused, for example, the voltage of the signal line DTL is sampled in another row (pixel) different from the row (pixel) on which the previous Vth correction has been performed. At this time, since the source voltage Vs is lower than Vofs−Vth in the row (pixel) in which the previous Vth correction has been performed, in the row (pixel) in which the previous Vth correction has been performed even during the Vth correction pause period. A current flows between the drain and source of the drive transistor Tr100, the source voltage Vs rises, and the gate voltage Vg also rises due to coupling via the storage capacitor Cs.

(Second Vth correction period)
Next, Vth correction is performed again. Specifically, when the voltage of the signal line DTL is Vofs and Vth correction is possible, the write line drive circuit 124 increases the voltage of the write line WSL from Vofs to Von, and the drive transistor Tr100. Is set to Vofs (T4). At this time, when the source voltage Vs is lower than Vofs−Vth (when Vth correction is not yet completed), until the drive transistor Tr100 is cut off (until the gate-source voltage Vgs becomes Vth), A current flows between the drain and source of the drive transistor Tr100. Thereafter, before the signal line driver circuit 123 switches the voltage of the signal line DTL from Vofs to Vsig, the write line driver circuit 124 decreases the voltage of the write line WSL from Von to Voff (T5). Then, since the gate of the drive transistor Tr100 is in a floating state, the gate-source voltage Vgs can be kept constant regardless of the magnitude of the voltage of the signal line DTL.

  In the Vth correction period, when the storage capacitor Cs is charged to Vth and the gate-source voltage Vgs becomes Vth, the drive circuit 120 ends the Vth correction. However, if the gate-source voltage Vgs does not reach Vth, the drive circuit 120 repeatedly executes Vth correction and Vth correction pause until the gate-source voltage Vgs reaches Vth.

(Writing / μ correction period)
After the Vth correction pause period ends, writing and μ correction are performed. Specifically, while the voltage of the signal line DTL is Vsig, the write line drive circuit 124 raises the voltage of the write line WSL from Voff to Von (T6), and the gate of the drive transistor Tr100 is connected to the signal line. Connect to DTL. Then, the gate voltage Vg of the drive transistor Tr100 becomes the voltage Vsig of the signal line DTL. At this time, the anode voltage of the organic EL element 111 is still smaller than the threshold voltage Vel of the organic EL element 111 at this stage, and the organic EL element 111 is cut off. Therefore, current flows to the element capacitance (not shown) of the organic EL element 111 and the element capacitance is charged. Therefore, the source voltage Vs rises by ΔVx, and the gate-source voltage Vgs eventually becomes Vsig + Vth−ΔVx. In this way, μ correction is performed simultaneously with writing. Here, since ΔVx increases as the mobility μ of the driving transistor Tr100 increases, the variation in mobility μ for each pixel 113 can be removed by reducing the gate-source voltage Vgs by ΔVx before light emission. it can.

(Light emission period)
Finally, the write line drive circuit 124 lowers the voltage of the write line WSL from Von to Voff (T7). Then, the gate of the drive transistor Tr100 becomes floating, a current flows between the drain and source of the drive transistor Tr100, and the source voltage Vs rises. As a result, a voltage equal to or higher than the threshold voltage Vel is applied to the organic EL element 111, and the organic EL element 111 emits light with a desired luminance.

  In the display device 100, the pixel circuit 112 is controlled to be turned on / off in each pixel 113 as described above, and a driving current is injected into the organic EL element 111 of each pixel 113, whereby holes and electrons are recombined. Light is emitted and the light is extracted outside. As a result, an image is displayed in the display area 110 </ b> A of the display panel 110.

  By the way, in this application example, for example, the buffer circuit 6 in the write line driving circuit 124 includes a plurality of the inverter circuits 1, 2, 4, and 5 described above. Thereby, since there is almost no through current flowing in the buffer circuit 6, the power consumption of the buffer circuit 6 can be suppressed. In addition, since the variation in the output voltage of the buffer circuit 6 is small, variation in the threshold correction and mobility correction of the driving transistor Tr100 in the pixel circuit 112 can be reduced for each pixel circuit 112, and further, for each pixel 113. Variations in luminance can be reduced.

  Further, in this application example, when the inverter circuit 5 is provided for each write line WSL, the write line drive circuit 124 corresponds to, for example, the i-th (i is a positive integer) write line WSL. The input voltage Vin (i) is input to the input terminal IN1 of the inverter circuit 5, and the input of the inverter circuit 5 corresponding to the write line WSL at the ixth stage (x is a positive integer smaller than i). The input voltage Vin (i−x) input to the terminal IN1 is input to the input terminal IN2 of the inverter circuit 5 corresponding to the i-th write line WSL. It may be. For example, x may be 1 as shown in FIGS.

  Next, the basic operation of the inverter circuit 5 shown in FIGS. 33 and 34 will be described. The operation of the inverter circuit 5 shown in FIG. 33 and FIG. 34 is not significantly different from the operation of the inverter circuit 5 shown in FIG. explain.

  In the inverter circuit 5 shown in FIGS. 33 and 34, the timing at which the input voltage Vin (i-1) changes from low to high is earlier than the timing at which the input terminal Vin (i) changes from low to high. This is mainly different from the operation of the inverter circuit 5 shown in FIG. In such a timing, for example, as shown in FIG. 35, the voltage of the source (terminal B) of the transistor Tr5 becomes Vss before the gate voltage of the transistor Tr2. FIG. 35 illustrates a case where the transistor Tr7 is off when the input voltage Vin (i−1) changes from low to high.

  When the transistor Tr7 is turned on when the input voltage Vin (i-1) changes from low to high, when the input voltage Vin (i-1) changes from low to high, the transistor Tr5 The voltage of the source (terminal B) and the gate voltage of the transistor Tr2 are simultaneously Vss. At this time, since the transistor Tr1 is off, Vdd is output to the output voltage Vout.

  The present invention has been described with the embodiment, the modification, and the application example. However, the present invention is not limited to the embodiment and the like, and various modifications can be made.

  For example, in the application example, the inverter circuits 1, 2, 4, and 5 according to the above-described embodiments and modifications thereof are used in the output stage of the write line drive circuit 124. Instead of this output stage, it may be used for the output stage of the power line driver circuit 125, or may be used for the output stage of the power line driver circuit 125 together with the output stage of the write line driver circuit 124. .

  Note that when the inverter circuits 1, 2, 4, and 5 according to the above-described embodiments and modifications thereof are used in the output stage of the power supply line driving circuit 125, for example, the voltage VccL is applied to the low voltage line L1. A power supply (not shown) for output is connected, a power supply (not shown) for outputting the voltage VccH is connected to the high voltage lines L2 and L3, and is higher than the voltage VccH for the high voltage line L4. A power supply (not shown) for outputting a voltage may be connected.

  1, 2, 200, 300, 400, 500 ... inverter circuit, 3 ... delay element, 5 ... buffer circuit, 10 ... control element, 100 ... display device, 110 ... display panel, 110A ... display area, 111, 111R, 111G 111B ... Organic EL element 112 ... Pixel circuit 113, 113R, 113G, 113B ... Pixel, 114 ... Display pixel, 120 ... Drive circuit, 120A, 122A ... Video signal, 120B ... Synchronization signal, 121 ... Timing generation circuit, 121A ... control signal, 122 ... video signal processing circuit, 123 ... signal line drive circuit, 124 ... write line drive circuit, 125 ... power supply line drive circuit, A, C, D ... connection point, B ... terminal, C1, C2 , C3: capacitive element, Cs: holding capacitor, DTL: signal line, GND: ground line, IN, IN2, IN3 ... input terminal, L1: low voltage line L2, L3, L30 ... high voltage line, OUT ... output terminal, P ... WS pulse, P1 ... first terminal, P2 ... second terminal, P3 ... third terminal, PSL ... power supply line, Tr1-Tr7, Tr31, Tr32 ... Transistor, Tr100 ... Drive transistor, Tr200 ... Write transistor, VccH, VccL, Vdd, Vdd2, Vss, [Delta] Vx, [Delta] V1 ', [Delta] V2', [Delta] V1, [Delta] V2 ... Voltage, Vg, Vg1, Vg2, Vg3 ... Gate voltage, Vgs, Vgs1, Vgs2, Vgs3 ... Gate-source voltage, Vin ... Input voltage, Vofs ... Offset voltage, Vout ... Output voltage, Vs, Vs2 ... Source voltage, Vsig ... Signal voltage, Vth, Vth1, Vth2, Vth3, Vel ... Threshold Voltage, WSL ... write line, μ ... mobility.

Claims (21)

A first transistor, a second transistor, and a third transistor of the same channel type,
A first capacitive element and a second capacitive element;
With input and output terminals,
The first transistor disconnects the electrical connection between the output terminal and the first voltage line according to a potential difference between the voltage of the input terminal and the voltage of the first voltage line or a corresponding potential difference. And
The second transistor interrupts the electrical connection between the second voltage line and the output terminal according to a potential difference between the gate voltage of the second transistor and the voltage of the output terminal or a potential difference corresponding thereto. And
The third transistor cuts off the electrical connection between the gate of the second transistor and the third voltage line according to a potential difference between the voltage of the input terminal and the voltage of the third voltage line or a corresponding potential difference. Is supposed to
The first capacitive element and the second capacitive element are inserted in series between the input terminal and the gate of the second transistor,
An inverter circuit in which an electrical connection point between the first capacitive element and the second capacitive element is electrically connected to the output terminal. A first transistor, a second transistor, and a third transistor of the same channel type,
A first capacitive element and a second capacitive element;
With input and output terminals,
The gate of the first transistor is electrically connected to the input terminal, the drain or source of the first transistor is electrically connected to a first voltage line, and the first of the drain and source of the first transistor is the first transistor. A terminal not connected to the voltage line is electrically connected to the output terminal,
The drain or source of the second transistor is electrically connected to a second voltage line, and the terminal not connected to the second voltage line among the drain and source of the second transistor is electrically connected to the output terminal. ,
The gate of the third transistor is electrically connected to the input terminal, the drain or source of the third transistor is electrically connected to a third voltage line, and the third of the drain and source of the third transistor. A terminal not connected to the voltage line is electrically connected to the gate of the second transistor;
The first capacitive element and the second capacitive element are inserted in series between the input terminal and the gate of the second transistor,
An inverter circuit in which an electrical connection point between the first capacitive element and the second capacitive element is electrically connected to the output terminal. The second capacitive element is inserted on the gate side of the first transistor,
The inverter circuit according to claim 1, wherein a capacitance of the second capacitive element is larger than a capacitance of the first capacitive element. The inverter circuit according to claim 3, wherein respective capacities of the first capacitor element and the second capacitor element satisfy the following expression.
Cb (Vdd-Vss) / (Ca + Cb)> Vth2
Ca: capacitance of the first capacitive element Cb: capacitance of the second capacitive element Vdd: voltage of the second voltage line Vss: voltage of the first voltage line Vth2: threshold voltage of the second transistor The inverter circuit according to any one of claims 1 to 4, wherein the first voltage line and the third voltage line are at the same potential. The inverter circuit according to claim 5, wherein the second voltage line is connected to a power source that outputs a voltage higher than voltages of the first voltage line and the third voltage line. 5. The inverter circuit according to claim 1, further comprising a delay element that inputs a voltage obtained by blunting a waveform of the signal voltage input to the input terminal to the gate of the third transistor. A first transistor, a second transistor, and a third transistor of the same channel type,
Input and output terminals;
A first terminal electrically connected to the input terminal; a second terminal electrically connected to the output terminal; and a third terminal electrically connected to a gate of the second transistor, A control element that makes the transient of the second terminal gentler than the transient of the third terminal when a falling voltage or a rising voltage is input to the first terminal;
The first transistor disconnects the electrical connection between the output terminal and the first voltage line according to a potential difference between the voltage of the input terminal and the voltage of the first voltage line or a corresponding potential difference. And
The second transistor interrupts the electrical connection between the second voltage line and the output terminal according to a potential difference between the gate voltage of the second transistor and the voltage of the output terminal or a potential difference corresponding thereto. And
The third transistor cuts off the electrical connection between the gate of the second transistor and the third voltage line according to a potential difference between the voltage of the input terminal and the voltage of the third voltage line or a corresponding potential difference. Inverter circuit that is supposed to be. A first transistor, a second transistor, and a third transistor of the same channel type,
Input and output terminals;
A first terminal electrically connected to the input terminal; a second terminal electrically connected to the output terminal; and a third terminal electrically connected to a gate of the second transistor, A control element that makes the transient of the second terminal gentler than the transient of the third terminal when a falling voltage or a rising voltage is input to the first terminal;
The gate of the first transistor is electrically connected to the input terminal, the drain or source of the first transistor is electrically connected to a first voltage line, and the first of the drain and source of the first transistor is the first transistor. A terminal not connected to the voltage line is electrically connected to the output terminal,
The drain or source of the second transistor is electrically connected to a second voltage line, and the terminal not connected to the second voltage line among the drain and source of the second transistor is electrically connected to the output terminal. ,
The gate of the third transistor is electrically connected to the input terminal, the drain or source of the third transistor is electrically connected to a third voltage line, and the third of the drain and source of the third transistor. A terminal not connected to the voltage line is electrically connected to the gate of the second transistor. A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor of the same channel type;
A first capacitive element and a second capacitive element;
A first input terminal, a second input terminal, a third input terminal and an output terminal;
The first transistor cuts off an electrical connection between the output terminal and the first voltage line according to a potential difference between the voltage of the first input terminal and the voltage of the first voltage line or a corresponding potential difference. And
The second transistor interrupts the electrical connection between the second voltage line and the output terminal according to a potential difference between the gate voltage of the second transistor and the voltage of the output terminal or a potential difference corresponding thereto. And
The third transistor electrically connects the gate of the fifth transistor and the third voltage line according to a potential difference between the voltage of the second input terminal and the voltage of the third voltage line or a corresponding potential difference. It is supposed to be relayed,
The fourth transistor includes a first terminal that is a source or a drain of the fifth transistor according to a potential difference between a voltage of the second input terminal and a voltage of the fourth voltage line or a potential difference corresponding thereto, and the fourth voltage line. It is designed to cut off the electrical connection with
The first capacitive element and the second capacitive element are inserted in series between the second input terminal and the gate of the fifth transistor,
An electrical connection point between the first capacitive element and the second capacitive element is electrically connected to the first terminal;
The fifth transistor is adapted to cut off the electrical connection between the fifth voltage line and the first terminal according to the voltage between the terminals of the first capacitive element or the voltage corresponding thereto.
The sixth transistor electrically connects the gate of the second transistor and the sixth voltage line according to a potential difference between the voltage of the first input terminal and the voltage of the sixth voltage line or a corresponding potential difference. It is supposed to be relayed,
The seventh transistor interrupts the electrical connection between the first terminal and the gate of the second transistor according to a signal input to the gate of the seventh transistor via the third input terminal. Inverter circuit. A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor of the same channel type;
A first capacitive element and a second capacitive element;
A first input terminal, a second input terminal, a third input terminal and an output terminal;
In the first transistor, a gate is electrically connected to the first input terminal, a drain or a source is electrically connected to the first voltage line, and a terminal of the drain and source that is not connected to the first voltage line. Is electrically connected to the output terminal,
In the second transistor, a gate is connected to a drain or a source of the seventh transistor, a drain or a source is electrically connected to a second voltage line, and a terminal of the drain and the source that is not connected to the second voltage line Is electrically connected to the output terminal,
In the third transistor, a gate is electrically connected to the second input terminal, a drain or a source is electrically connected to a third voltage line, and a terminal of the drain and source that is not connected to the third voltage line Is electrically connected to the gate of the fifth transistor,
In the fourth transistor, a gate is electrically connected to the second input terminal, a drain or a source is electrically connected to the fourth voltage line, and a terminal of the drain and source that is not connected to the fourth voltage line Is electrically connected to the first terminal which is the drain or source of the fifth transistor,
The first capacitive element and the second capacitive element are inserted in series between the second input terminal and the gate of the fifth transistor,
An electrical connection point between the first capacitive element and the second capacitive element is electrically connected to the first terminal;
In the fifth transistor, a gate is electrically connected to a terminal not connected to the third voltage line among a drain and a source of the third transistor, and a terminal different from the first terminal among the drain and the source is a first terminal. Electrically connected to 5 voltage lines,
In the sixth transistor, a gate is electrically connected to the first input terminal, a drain or a source is electrically connected to a sixth voltage line, and a terminal of the drain and source that is not connected to the sixth voltage line Is electrically connected to the gate of the second transistor,
In the seventh transistor, a gate is electrically connected to the third input terminal, a drain or a source is electrically connected to the first terminal, and a terminal that is not connected to the first terminal among the drain and the source is An inverter circuit electrically connected to the gate of the second transistor. The second capacitive element is inserted on the gate side of the fifth transistor,
The inverter circuit according to claim 10 or 11, wherein a capacitance of the second capacitive element is larger than a capacitance of the first capacitive element. The inverter circuit according to claim 12, wherein respective capacities of the first capacitor element and the second capacitor element satisfy the following expression.
Cb (Vdd2-Vss) / (Ca + Cb)> Vth5
Ca: capacitance of the first capacitive element Cb: capacitance of the second capacitive element Vdd2: voltage of the fifth voltage line Vss: voltage of the fourth voltage line Vth5: threshold voltage of the fifth transistor The inverter circuit according to any one of claims 10 to 13, wherein the first voltage line, the third voltage line, the fourth voltage line, and the sixth voltage line have the same potential. The second voltage line and the fifth voltage line are connected to a power supply that outputs a voltage higher than the voltages of the first voltage line, the third voltage line, the fourth voltage line, and the sixth voltage line. The inverter circuit according to claim 14. A display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix;
And a driving unit for driving each pixel,
The drive unit includes a plurality of inverter circuits provided for each of the scanning lines,
The inverter circuit is
A first transistor, a second transistor, and a third transistor of the same channel type,
A first capacitive element and a second capacitive element;
An input terminal and an output terminal,
The first transistor disconnects the electrical connection between the output terminal and the first voltage line according to a potential difference between the voltage of the input terminal and the voltage of the first voltage line or a corresponding potential difference. And
The second transistor interrupts the electrical connection between the second voltage line and the output terminal according to a potential difference between the gate voltage of the second transistor and the voltage of the output terminal or a potential difference corresponding thereto. And
The third transistor cuts off the electrical connection between the gate of the second transistor and the third voltage line according to a potential difference between the voltage of the input terminal and the voltage of the third voltage line or a corresponding potential difference. Is supposed to
The first capacitive element and the second capacitive element are inserted in series between the input terminal and the gate of the second transistor,
A display device in which an electrical connection point between the first capacitive element and the second capacitive element is electrically connected to the output terminal. A display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix;
And a driving unit for driving each pixel,
The drive unit includes a plurality of inverter circuits provided for each of the scanning lines,
The inverter circuit is
A first transistor, a second transistor, and a third transistor of the same channel type,
A first capacitive element and a second capacitive element;
An input terminal and an output terminal,
The gate of the first transistor is electrically connected to the input terminal, the drain or source of the first transistor is electrically connected to a first voltage line, and the first of the drain and source of the first transistor is the first transistor. A terminal not connected to the voltage line is electrically connected to the output terminal,
The drain or source of the second transistor is electrically connected to a second voltage line, and the terminal not connected to the second voltage line among the drain and source of the second transistor is electrically connected to the output terminal. ,
The gate of the third transistor is electrically connected to the input terminal, the drain or source of the third transistor is electrically connected to a third voltage line, and the third of the drain and source of the third transistor. A terminal not connected to the voltage line is electrically connected to the gate of the second transistor;
The first capacitive element and the second capacitive element are inserted in series between the input terminal and the gate of the second transistor,
A display device in which an electrical connection point between the first capacitive element and the second capacitive element is electrically connected to the output terminal. A display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix;
And a driving unit for driving each pixel,
The drive unit includes a plurality of inverter circuits provided for each of the scanning lines,
The inverter circuit is
A first transistor, a second transistor, and a third transistor of the same channel type,
Input and output terminals;
A first terminal electrically connected to the input terminal; a second terminal electrically connected to the output terminal; and a third terminal electrically connected to a gate of the second transistor, A control element that makes the transient of the second terminal gentler than the transient of the third terminal when a falling voltage or a rising voltage is input to the one terminal;
The first transistor disconnects the electrical connection between the output terminal and the first voltage line according to a potential difference between the voltage of the input terminal and the voltage of the first voltage line or a corresponding potential difference. And
The second transistor interrupts the electrical connection between the second voltage line and the output terminal according to a potential difference between the gate voltage of the second transistor and the voltage of the output terminal or a potential difference corresponding thereto. And
The third transistor cuts off the electrical connection between the gate of the second transistor and the third voltage line according to a potential difference between the voltage of the input terminal and the voltage of the third voltage line or a corresponding potential difference. Display device that is supposed to be. A display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix;
And a driving unit for driving each pixel,
The drive unit includes a plurality of inverter circuits provided for each of the scanning lines,
The inverter circuit is
A first transistor, a second transistor, and a third transistor of the same channel type,
Input and output terminals;
A first terminal electrically connected to the input terminal; a second terminal electrically connected to the output terminal; and a third terminal electrically connected to a gate of the second transistor, A control element that makes the transient of the second terminal gentler than the transient of the third terminal when a falling voltage or a rising voltage is input to the first terminal;
The gate of the first transistor is electrically connected to the input terminal, the drain or source of the first transistor is electrically connected to a first voltage line, and the first of the drain and source of the first transistor is the first transistor. A terminal not connected to the voltage line is electrically connected to the output terminal,
The drain or source of the second transistor is electrically connected to a second voltage line, and the terminal not connected to the second voltage line among the drain and source of the second transistor is electrically connected to the output terminal. ,
The gate of the third transistor is electrically connected to the input terminal, the drain or source of the third transistor is electrically connected to a third voltage line, and the third of the drain and source of the third transistor. A terminal that is not connected to a voltage line is electrically connected to the gate of the second transistor. A display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix;
And a driving unit for driving each pixel,
The drive unit includes a plurality of inverter circuits provided for each of the scanning lines,
The inverter circuit is
A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor of the same channel type;
A first capacitive element and a second capacitive element;
A first input terminal, a second input terminal, a third input terminal and an output terminal;
The first transistor cuts off an electrical connection between the output terminal and the first voltage line according to a potential difference between the voltage of the first input terminal and the voltage of the first voltage line or a corresponding potential difference. And
The second transistor interrupts the electrical connection between the second voltage line and the output terminal according to a potential difference between the gate voltage of the second transistor and the voltage of the output terminal or a potential difference corresponding thereto. And
The third transistor electrically connects the gate of the fifth transistor and the third voltage line according to a potential difference between the voltage of the second input terminal and the voltage of the third voltage line or a corresponding potential difference. It is supposed to be relayed,
The fourth transistor includes a first terminal that is a source or a drain of the fifth transistor according to a potential difference between a voltage of the second input terminal and a voltage of the fourth voltage line or a potential difference corresponding thereto, and the fourth voltage line. It is designed to cut off the electrical connection with
The first capacitive element and the second capacitive element are inserted in series between the second input terminal and the gate of the fifth transistor,
An electrical connection point between the first capacitive element and the second capacitive element is electrically connected to the first terminal;
The fifth transistor is adapted to cut off the electrical connection between the fifth voltage line and the first terminal according to the voltage between the terminals of the first capacitive element or the voltage corresponding thereto.
The sixth transistor electrically connects the gate of the second transistor and the sixth voltage line according to a potential difference between the voltage of the first input terminal and the voltage of the sixth voltage line or a corresponding potential difference. It is supposed to be relayed,
The seventh transistor interrupts the electrical connection between the first terminal and the gate of the second transistor according to a signal input to the gate of the seventh transistor via the third input terminal. Display device. A display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix;
And a driving unit for driving each pixel,
The drive unit includes a plurality of inverter circuits provided for each of the scanning lines,
The inverter circuit is
A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor of the same channel type;
A first capacitive element and a second capacitive element;
A first input terminal, a second input terminal, a third input terminal and an output terminal;
In the first transistor, a gate is electrically connected to the first input terminal, a drain or a source is electrically connected to the first voltage line, and a terminal of the drain and source that is not connected to the first voltage line. Is electrically connected to the output terminal,
In the second transistor, a gate is connected to a drain or a source of the seventh transistor, a drain or a source is electrically connected to a second voltage line, and a terminal of the drain and the source that is not connected to the second voltage line Is electrically connected to the output terminal,
In the third transistor, a gate is electrically connected to the second input terminal, a drain or a source is electrically connected to a third voltage line, and a terminal of the drain and source that is not connected to the third voltage line Is electrically connected to the gate of the fifth transistor,
In the fourth transistor, a gate is electrically connected to the second input terminal, a drain or a source is electrically connected to the fourth voltage line, and a terminal of the drain and source that is not connected to the fourth voltage line Is electrically connected to the first terminal which is the drain or source of the fifth transistor,
The first capacitive element and the second capacitive element are inserted in series between the second input terminal and the gate of the fifth transistor,
An electrical connection point between the first capacitive element and the second capacitive element is electrically connected to the first terminal;
In the fifth transistor, a gate is electrically connected to a terminal not connected to the third voltage line among a drain and a source of the third transistor, and a terminal different from the first terminal among the drain and the source is a first terminal. Electrically connected to 5 voltage lines,
In the sixth transistor, a gate is electrically connected to the first input terminal, a drain or a source is electrically connected to a sixth voltage line, and a terminal of the drain and source that is not connected to the sixth voltage line Is electrically connected to the gate of the second transistor,
In the seventh transistor, a gate is electrically connected to the third input terminal, a drain or a source is electrically connected to the first terminal, and a terminal that is not connected to the first terminal among the drain and the source is A display device electrically connected to a gate of the second transistor.

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