JP2009169090A - Light-emitting display device and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent picture quality from decreasing owing to potential variation of a precedent stage when an auxiliary capacitor Csub is connected to a power supply scan line DSL(i-1) of the precedent stage. <P>SOLUTION: A pixel circuit 3(i, j) includes a light emitting element (organic light emitting diode OLED: capacitor Coled.) varying in applied voltage value with the potential (Vs) of one electrode (source node NDs), a drive transistor Md having a control node NDC (potential Vg), a sampling transistor Ms, a holding capacitor Cs, and an auxiliary capacitor Csub. A drive circuit is configured to output a low potential Vws_L satisfying Vws_L<Vg-(Vcc_H-Vcc_L)Csub/(Csub+Coled.) in accordance with ranges of Csub, Coled., and Vg, a high potential Vcc_H and a low potential Vcc_L of the power supply scan line, and a potential (Vcc_H, Vcc_L) of the power supply scan line DSL(i-1). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention includes a plurality of pixel circuits and a drive circuit, and video signal lines, power supply scanning lines, and writing scanning lines are wired to the plurality of pixel circuits, and each pixel circuit is applied in accordance with the potential of one electrode. The present invention relates to a self-luminous display device including a light emitting element whose voltage value changes, a driving transistor, a sampling transistor, a holding capacitor, and an auxiliary capacitor, and a driving method thereof. Specifically, the present invention relates to a self-luminous display device in which the auxiliary capacitor is connected between the one electrode in the same pixel circuit as the auxiliary capacitor and a power supply scanning line of another pixel row, and its driving Regarding the method.

In recent years, development of self-luminous display devices using organic EL devices as light-emitting elements has become active. An organic EL device has an organic thin film, and utilizes a phenomenon that emits light when an electric field is applied to the organic thin film.
Since the organic EL device is driven with an applied voltage of 10 [V] or less, the power consumption is low. Since the organic EL device is a self-luminous element that emits light by itself, a display device including the organic EL device does not require an illumination unit and can be easily reduced in weight and thickness. Since the response speed of the organic EL device is as high as several [μs], the display device using the organic EL device does not generate an afterimage when displaying a moving image.

  Among self-luminous display devices that use organic EL devices as self-luminous elements, active matrix display devices in which thin film transistors are integrated and formed as driving elements in each pixel are particularly active.

  An active matrix display device having a self-luminous element, wherein an auxiliary capacitor (additional capacitor) is connected to one electrode (anode electrode) of the self-luminous element on the side into which a drive current corresponding to the data potential flows A display device is known (see, for example, Patent Document 1).

In FIG. 14, an equivalent circuit diagram of the basic configuration of the pixel circuit (FIG. 8 of Patent Document 1) is transcribed with a part of reference numerals changed.
In this example, the light emitting element is an organic light emitting diode OLED. In FIG. 14, the organic light emitting diode OLED is indicated by its equivalent capacitance Coled. In addition, the transistor connected between the supply line of the power supply voltage Vdd and the driving transistor (indicated by reference numeral Tr4) shown in FIG. 8 of Patent Document 1 is not necessary depending on the configuration of the pixel circuit. Omitted.

  Since the potential of the other electrode (cathode) of the organic light emitting diode OLED is fixed at the cathode potential Vcath, the voltage applied to the organic light emitting diode OLED is controlled by the potential (anode potential) Va of the one electrode (anode). A supply line of the power supply voltage Vdd can be connected to the anode of the organic light emitting diode OLED via the drive transistor Md. In the drive transistor Md, the magnitude of the drain current Ids is controlled according to the data potential Vsig input to its gate (control node), and thereby the source potential, that is, the anode potential Va of the organic light emitting diode OLED is determined.

A holding capacitor Cs is connected between the gate and source of the driving transistor Md for the purpose of holding the data potential Vsig. A sampling transistor Ms for sampling the data potential Vsig of the video signal is connected between the gate of the drive transistor Md and the video signal line DTL.
The sampling transistor is controlled according to the potential of a write scanning line (not shown) connected to the gate thereof, and is turned on when the write scanning line is activated, and is a video signal line connected to the drain. Are sampled, and the sampled potential is transmitted to the control node of the driving transistor connected to the source.
Here, the video signal has a waveform in which application of a constant reference potential (hereinafter referred to as a data reference potential Vo) and application of a data pulse DP having an arbitrary potential from the data reference potential Vo are repeated. The potential of the data pulse DP is the data potential Vsig, and the data voltage Vin that determines the display gradation corresponds to the peak value of the data pulse DP obtained by subtracting the data reference potential Vo from the data potential Vsig.
A holding capacitor Cs is connected between the gate and source of the driving transistor Md.

In the pixel circuit having such a configuration, the gate-source voltage Vgs of the driving transistor Md becomes the holding voltage of the holding capacitor Cs as it is. In other words, the holding voltage value of the holding capacitor Cs is determined by the magnitude of the potential “Vsig−Va” applied to the gate of the driving transistor with reference to the source potential of the driving transistor (the anode potential Va of the organic light emitting diode OLED). .
Since the drive transistor Md flows a drain current Ids corresponding to the gate-source voltage Vgs, it is necessary to accurately input and hold the data voltage Vin (the peak value of the data pulse DP) to the holding capacitor Cs.

  For this purpose, prior to the input of the data voltage Vin, the potential (anode potential Va) of the source of the drive transistor Md (one electrode of the light emitting element, anode in this example) is initialized by the data reference potential Vo of the video signal. . The data potential Vsig is input to the control node of the drive transistor Md by sampling the data potential Vsig by the sampling transistor Ms.

When the potential of the control node (gate) of the drive transistor Md rises due to the input of the data potential Vsig, the source potential (anode potential Va) of the drive transistor Md also rises from the data reference potential Vo. In order to hold the data voltage Vin in the holding capacitor Cs at 100 [%], it is necessary to make the fluctuation amount of the source potential (anode potential Va) of the driving transistor Md when the data potential Vsig is input almost zero.
However, the value of the current flowing through the drive transistor Md increases due to the input of the data potential Vsig, and the increase in the current value tends to easily increase the source potential (anode potential Va) of the drive transistor Md.

Therefore, in the pixel circuit described in Patent Document 1, an auxiliary capacitor Csub is connected in parallel with the organic light emitting diode OLED for the purpose of increasing the capacitance value connected to the source of the driving transistor.
The drain current Ids charges the combined capacitance of the capacitance Coled. Of the organic light emitting diode OLED, the auxiliary capacitor Csub, and the parasitic capacitance such as the drive transistor Md. If the drain current Ids is increased by the input of the data potential Vsig, and the auxiliary capacitor Csub is large to some extent at this time, the increased amount of the drain current Ids is consumed to charge the combined capacitance so that the anode potential Va hardly increases. Can be. In this case, the “write gain” defined by the ratio between the voltage actually held in the holding capacitor Cs and the desired data voltage Vin is close to “1”.

Thus, the auxiliary capacitor Csub has an effect of increasing the efficiency of data writing (write gain) when the data voltage Vin is written to the pixel circuit.
JP 2007-102046 A

  When the auxiliary capacitor Csub is connected to a potential line having a large potential difference from the one electrode, the additional capacitance value can be further increased.

  With such an intention, the present inventor does not use the auxiliary capacitor Csub described in the above-mentioned Patent Document 1 as the adjacent other capacitor adjacent to the auxiliary capacitor Csub, instead of the constant potential line (cathode potential Vcath supply line) in the same pixel. A pixel circuit configuration connected to a power supply voltage supply control line (power supply scanning line DSL) of the pixel circuit has been proposed (Japanese Patent Application No. 2006-209327).

However, the power supply scanning line DSL included in another adjacent pixel circuit is controlled from the low potential Vcc_L to the high potential Vcc_H, and at this time, the pixel circuit provided with the auxiliary capacitor Csub connected to the power supply scanning line DSL. There may be a state in which light can be emitted.
In such a case, the potential fluctuation of the power supply scanning line DSL to which the adjacent pixel circuit is connected causes the sampling transistor to be turned off and the drive transistor Md through the auxiliary capacitor Csub and the holding capacitor Cs in the pixel circuit in the light emission enabled state. Lower the gate potential. If the degree of this reduction is large, the sampling transistor Ms that should be turned off in the light emission enabled state is turned on instantaneously, and the potential of the video signal line DTL at that time is sampled for a short time, and the image quality of the display image is remarkably high. descend.

  Even when the sampling transistor Ms is not turned on, the emission luminance level changes when a leak current flows. This change in light emission luminance level is caused by leakage current, so some pixels are not conspicuous, but when leak current occurs particularly during black display, the display becomes whitish, so-called `` black floating '' and the contrast is lowered, resulting in poor image quality. The decline is noticeable.

  According to the present invention, in a self-luminous display device configured to connect an auxiliary capacitor to a power supply scanning line of a pixel circuit in another pixel row, the image quality is prevented from being deteriorated due to a potential change of the power supply scanning line.

A self-luminous display device according to one embodiment (first embodiment) of the present invention includes a pixel array in which a plurality of pixel circuits are arranged in a matrix, and a plurality of pixel circuits in the pixel array connected in a row direction. Each potential of the write scan line and the plurality of power supply scan lines, the plurality of video signal lines connecting the pixel circuits in the pixel array in the column direction, the plurality of write scan lines and the plurality of power supply scan lines And a driving circuit to be controlled.
Each of the plurality of pixel circuits includes a light emitting element whose applied voltage value changes depending on a potential of one electrode, a driving transistor connected between the power supply scanning line and the one electrode, the video signal line, and the driving A sampling transistor connected between the control node of the transistor and controlled according to the potential of the write scan line, a holding capacitor coupled to the control node, the one electrode, and one side in the column direction And an auxiliary capacitor connected between power supply scanning lines of other pixel circuits.
The driving circuit corresponds to a value Csub of the auxiliary capacitor, an equivalent capacitance Coled of the light emitting element, a high potential Vcc_H and a low potential Vcc_L of the power source scanning line, and a potential of the video signal line. Depending on the possible range of the gate potential Vg, the following equation:
Vws_L <Vg− (Vcc_H−Vcc_L) Csub / (Csub + Coled.)
The low potential Vws_L that satisfies the above condition is output to the write scanning line as the lower potential of the binary potential.

  In a self-luminous display device according to another mode (second mode) of the present invention, in the first mode, the drive circuit includes the write scan line corresponding to each of a plurality of pixel rows and the write scan line. A set of power supply scanning lines is sequentially selected in the column direction, and the auxiliary capacitor is connected to a pixel circuit in another pixel row that is selected earlier by the drive circuit than a pixel row to which the pixel circuit having the auxiliary capacitor belongs. Connected to the power supply scanning line.

  In the self-luminous display device according to another mode (third mode) of the present invention, in the first mode, the low potential Vws_L of the writing scanning line is a negative potential having a value satisfying the above formula.

  The self-luminous display device according to another embodiment (fourth embodiment) of the present invention is the data pulse having a data potential in which the potential difference from the data reference potential Vo changes in accordance with the display luminance of the pixel. Is transmitted through the video signal line, and the right side of the equation takes a minimum value when the gate potential Vg is the data reference potential Vo, and the drive circuit is less than the minimum value. The low potential Vws_L is controlled to a low value.

In a driving method of a self-luminous display device according to another embodiment (fifth embodiment) of the present invention, each of a plurality of pixel circuits arranged in a matrix in a pixel array has an applied voltage value depending on the potential of one electrode. A light-emitting element that changes, a driving transistor connected between a power supply scanning line and one electrode of the light-emitting element, a control node of the driving transistor and a video signal line, An auxiliary connected between a sampling transistor controlled in accordance with a potential, a holding capacitor coupled to the control node, the one electrode, and a power supply scanning line of another pixel circuit located on one side in the column direction. A self-luminous display device including a capacitor, wherein the auxiliary capacitor has a value Csub, an equivalent capacitance Coled. Of the light emitting element, a high potential Vcc_H and a low potential Vcc_ of the power source scanning line. , And, depending on the range gate potential Vg can be taken of the driving transistor in response to the potential of the video signal lines, the following formula, namely,
Vws_L <Vg− (Vcc_H−Vcc_L) Csub / (Csub + Coled.)
The sampling transistor is driven by the binary potential of the writing scanning line, which is defined as a lower potential Vws_L that satisfies the above condition.

Here, the operation will be described by taking as an example the case where the power supply scanning line of another pixel circuit changes from the high potential Vcc_H to the power supply potential Vcc_L, for example.
The potential change of the power supply scanning line is represented by (Vcc_H−Vcc_L), and this is input via the auxiliary capacitor to the pixel circuit in which the auxiliary capacitor is provided and in a light emitting state. Since this pixel circuit is in a light emission enabled state, the sampling transistor is turned off and the control node of the driving transistor is in a floating state.
When a potential change (Vcc_H−Vcc_L) is input to one electrode of the light emitting element, this potential change is a potential change proportional to the capacitive coupling ratio g (= Csub / (Csub + Coled.)), That is, (Vcc_H−Vcc_L). It becomes Csub / (Csub + Coled.), And the potential of the control node of the driving transistor is lowered via the holding capacitor. The right side of the above formula shows the bottom value of the potential change that occurs at the control node when the potential drops.

  A write scan line is connected to the control node of the sampling transistor, and the write scan line is controlled by a binary potential having the low potential Vws_L as a lower potential. The sampling transistor is defined to be off by the low potential Vws_L of the writing scan line.

When the transistor is a field effect type, no leakage current is generated if the source potential is the same as the gate potential, but when the source potential is lower than the gate potential, the off-leakage current increases rapidly even if the source potential is not turned on.
Therefore, the above formula defines a condition that the potential of the control node does not become lower than the potential of the control node of the sampling transistor even when the potential of the control node becomes the lowest due to the potential change superimposed on the drive transistor, and this condition is satisfied. If this occurs, the occurrence of on-current and leakage current is prevented.

  According to the present invention, since no current flows through the sampling transistor, the image quality does not deteriorate due to the potential change of the power supply scanning line.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings, using an organic EL display having a 2T · 1C type pixel circuit as a main example.

<Overall configuration>
FIG. 1 shows a main configuration of an organic EL display according to an embodiment of the present invention.
The illustrated organic EL display 1 includes a pixel array 2 in which a plurality of pixel circuits (PXLC) 3 (i, j) are arranged in a matrix, a vertical drive circuit (V scanner) 4 that drives the pixel array 2, and a horizontal And a drive circuit (H selector: HSEL) 5.
A plurality of V scanners 4 are provided depending on the configuration of the pixel circuit 3. Here, the V scanner 4 includes a horizontal pixel line drive circuit (DSCN) 41 and a write signal scanning circuit (WSCN) 42. The V scanner 4 and the H selector 5 are a part of the “drive circuit”. The “drive circuit” includes a circuit for supplying a clock signal to the V scanner 4 and the H selector 5, a control circuit (CPU, etc.), and the like. Also includes a circuit (not shown).

The code “3 (i, j)” of the pixel circuit shown in FIG. 1 indicates that the pixel circuit has an address i (i = 1, 2) in the vertical direction (vertical direction) and an address j ( j = 1,2,3). These addresses i and j take integers of 1 or more with the maximum values being “n” and “m”, respectively. Here, for simplification of the figure, a case where n = 2 and m = 3 is shown.
This address notation is similarly applied to the elements, signals, signal lines, voltages, and the like of the pixel circuit in the following description and drawings.

Pixel circuits 3 (1,1) and 3 (2,1) are connected to the video signal line DTL (1) in the vertical direction. Similarly, the pixel circuits 3 (1,2) and 3 (2,2) are connected to the video signal line DTL (2) in the vertical direction, and the pixel circuits 3 (1,3) and 3 (2,3) are vertical. Direction video signal line DTL (3). The video signal lines DTL (1) to DTL (3) are driven by the H selector 5.
The pixel circuits 3 (1,1), 3 (1,2) and 3 (1,3) in the first row are connected to the write scanning line WSL (1). Similarly, the pixel circuits 3 (2,1), 3 (2,2) and 3 (2,3) in the second row are connected to the write scanning line WSL (2). The write scanning lines WSL (1) and WSL (2) are driven by the horizontal pixel line driving circuit 41.
The pixel circuits 3 (1,1), 3 (1,2) and 3 (1,3) in the first row are connected to the power supply scanning line DSL (1). Similarly, the pixel circuits 3 (2,1), 3 (2,2) and 3 (2,3) in the second row are connected to the power supply scanning line DSL (2). The power supply scanning lines DSL (1) and DSL (2) are driven by the write signal scanning circuit.

Any one of the m video signal lines including the video signal lines DTL (1) to DTL (3) will be represented by the symbol “DTL (j) or DTL”. Similarly, any one of the n write scan lines including the write scan lines WSL (1) and WSL (2) is represented by the reference numeral “WSL (i) or WSL”, and the power scan line DSL (1 ), Any one of the n power supply scanning lines including DSL (2) is represented by a symbol “DSL (i) or DSL”.
For the video signal line DTL (j), line-sequential driving in which video signals are discharged all at once in units of display pixel rows (also referred to as display lines), or video is sequentially applied to video signal lines DTL (j) in the same row. Although there is dot sequential driving in which signals are discharged, any driving method may be used in this embodiment.

<Pixel circuit>
FIG. 2 shows a configuration example of the pixel circuit 3 (i, j).
The pixel circuit 3 (i, j) illustrated is a circuit that controls the organic light emitting diode OLED. In addition to the organic light emitting diode OLED, the pixel circuit includes a drive transistor Md and a sampling transistor Ms made of an NMOS type TFT, and a holding capacitor Cs.

  Although the organic light emitting diode OLED is not particularly shown, for example, in the case of a top emission type, an anode electrode is first formed on a TFT structure formed on a substrate made of transparent glass or the like, and a hole transport layer, A light emitting layer, an electron transport layer, an electron injection layer, and the like are sequentially deposited to form a laminate that forms an organic multilayer film, and a cathode electrode made of a transparent electrode material is formed on the laminate. The anode electrode is connected to the positive power source, and the cathode electrode is connected to the negative power source.

  When a bias voltage for obtaining a predetermined electric field is applied between the anode and cathode electrodes of the organic light emitting diode OLED, the organic multilayer film emits light when the injected electrons and holes recombine in the light emitting layer. The organic light emitting diode OLED can emit light in each color of red (R), green (G), and blue (B) by appropriately selecting the organic material constituting the organic multilayer film. For example, color display is possible by arranging the light emission of R, G, B in the pixels of each row. Alternatively, R, G, and B may be distinguished by the color of the filter using an organic material that emits white light. A four-color configuration in which W (white) is added in addition to R, G, and B may be used.

The drive transistor Md functions as current control means for controlling the amount of current flowing through the organic light emitting diode OLED to define display gradation.
The drain of the driving transistor Md is connected to the power supply scanning line DSL (i) that controls the supply of the power supply voltage VDD, and the source is connected to the anode of the organic light emitting diode OLED. The anode electrode of the organic light emitting diode OLED corresponds to “one electrode”.

  The sampling transistor Ms is connected between the supply line (video signal line DTL (j)) of the data potential Vsig that determines the pixel gradation and the gate (control node NDc) of the drive transistor Md. One of the source and drain of the sampling transistor Ms is connected to the gate (control node NDc) of the drive transistor Md, and the other is connected to the video signal line DTL (j). A data pulse having a data potential Vsig is supplied to the video signal line DTL (j) from the H selector 5 (see FIG. 1) at a predetermined interval. The sampling transistor Ms samples data at a level to be displayed by the pixel circuit at an appropriate timing in a data potential supply period (data pulse duration time). This is to eliminate the influence on the display image in the transition period where the level is unstable at the front or rear of the data pulse having the desired data potential Vsig to be sampled.

  A holding capacitor Cs is connected between the gate (control node) and source (one electrode forming the anode of the organic light emitting diode OLED) of the drive transistor Md. The role of the holding capacitor Cs will be clarified in the operation description described later.

In FIG. 2, the horizontal pixel line drive circuit 41 supplies a power supply drive pulse DS (i) in which the peak value of the high potential Vcc_H with respect to the low potential Vcc_L becomes the power supply voltage VDD to the drain of the drive transistor Md. Power is supplied when correcting Md or when the organic light emitting diode OLED actually emits light.
Further, the write signal scanning circuit 42 supplies a write drive pulse WS (i) having a relatively short duration to the gate of the sampling transistor Ms to perform sampling control.
The power supply control may be configured such that another transistor is inserted between the drain of the drive transistor Md and the supply line of the power supply voltage VDD, and the gate is controlled by the horizontal pixel line drive circuit 41. (Refer to a modification described later).

  In FIG. 2, one electrode (anode) of the organic light emitting diode OLED is supplied with the power supply voltage VDD from the positive power supply via the drive transistor Md. The cathode of the organic light emitting diode OLED is connected to a predetermined voltage line (for example, a negative power supply line) that supplies a cathode potential Vcath.

  Usually, all transistors in the pixel circuit are formed of TFTs. The thin film semiconductor layer in which the TFT channel is formed is made of a semiconductor material such as polycrystalline silicon (polysilicon) or amorphous silicon (amorphous silicon). Polysilicon TFTs can have high mobility, but their characteristic variation is large, so they are not suitable for increasing the screen size of a display device. Therefore, in a display device having a large screen, an amorphous silicon TFT is generally used. However, since it is difficult to form a P-channel TFT in an amorphous silicon TFT, it is desirable that all TFTs be an N-channel type like the pixel circuit 3 (i, j) described above.

Here, the pixel circuit 3 (i, j) described above is an example of a pixel circuit applicable in the present embodiment, that is, a basic configuration example of a two-transistor (2T) / 1-capacitor (1C) type. Therefore, the pixel circuit that can be used in the present embodiment may be a pixel circuit having the pixel circuit 3 (i, j) as a basic configuration and further added with a transistor and a capacitor (refer to a modification described later). In some basic configurations, the holding capacitor Cs is connected between the supply line of the power supply voltage VDD and the gate of the drive transistor Md.
Specifically, some pixel circuits other than the 2T • 1C type that can be employed in the present embodiment will be briefly described in modification examples described later. For example, 4T • 1C type, 4T • 2C type, 5T • 1C type It may be a 3T / 1C type.

In the pixel circuit based on the configuration of FIG. 2, when the organic light emitting diode OLED is reverse-biased at the time of threshold voltage correction or mobility correction, the equivalent capacitance value at the time of reverse biasing of the organic light-emitting diode OLED is maintained, as will be described in detail later. Since it can be made sufficiently larger than the value of the capacitor Cs, the anode of the organic light emitting diode OLED becomes difficult to move in terms of potential, so that the correction accuracy is improved. For this reason, it is desirable to perform correction in a reverse bias state.
The reason why the cathode is connected to a predetermined voltage line without grounding the cathode potential Vcath is to perform reverse bias. In order to reverse bias the organic light emitting diode OLED, for example, the cathode potential Vcath is made smaller than the reference potential (low potential Vcc_L) of the power supply driving pulse DS (i).

  In order to make the anode potential of the organic light emitting diode OLED more difficult to move and fix the potential when writing data, it is preferable to increase the capacitance value seen from the anode of the organic light emitting diode OLED. For this purpose, an auxiliary capacitor is connected to the anode of the organic light emitting diode OLED. Since the operation timing control itself is not changed by the presence or absence of the auxiliary capacitor, the operation (display control) will be described first.

<Display control>
The operation at the time of data writing in the circuit of FIG. 2 will be described together with the threshold voltage and mobility correction operation. A series of these operations is called “display control”.
First, the characteristics of the drive transistor to be corrected and the organic light emitting diode OLED will be described.

A holding capacitor Cs is coupled to the control node NDc of the drive transistor Md shown in FIG. The data potential Vsig, which is the effective potential of the data pulse transmitted through the video signal line DTL (j), is sampled by the sampling transistor Ms, and the potential thus obtained is applied to the control node NDc and held by the holding capacitor Cs. When a predetermined potential is applied to the gate of the drive transistor Md, the drain current Ids is determined according to the gate-source voltage Vgs having a value corresponding to the applied potential.
Here, it is assumed that sampling is performed after the source potential Vs of the drive transistor Md is initialized to the reference potential (data reference potential Vo) of the data pulse. The data potential Vsig after sampling, more precisely, the drain current Ids corresponding to the magnitude of the data voltage Vin defined by the potential difference between the data reference potential Vo and the data potential Vsig flows to the drive transistor Md, which is almost organic. It becomes the drive current Id of the light emitting diode OLED.
Therefore, when the source potential Vs of the driving transistor Md is initialized with the data reference potential Vo, the organic light emitting diode OLED emits light with a luminance corresponding to the data potential Vsig.

FIG. 3 shows a graph of the IV characteristic of the organic light emitting diode OLED and a general formula of the drain current Ids of the drive transistor Md (which is substantially equivalent to the drive current Id of the OLED).
As is well known, the organic light emitting diode OLED changes its IV characteristic as shown in FIG. At this time, in the pixel circuit of FIG. 2, even if the drive transistor Md tries to pass a constant drain current Ids, the applied voltage of the organic light emitting diode OLED increases as can be seen from the graph shown in FIG. Source potential Vs rises. At this time, since the gate of the driving transistor Md is in a floating state, the gate potential rises together with the source potential so that the substantially constant gate-source voltage Vgs is maintained, and the drain current Ids is kept substantially constant. Acts so as not to change the light emission luminance of the organic light emitting diode OLED.

  However, since the threshold voltage Vth and the mobility μ of the driving transistor Md are different for each pixel circuit, the drain current Ids varies according to the equation of FIG. 3, and the data potential Vsig given in the display screen. Even if the two pixels are the same, the light emission luminance differs between the two pixels.

  In the equation of FIG. 3, the symbol “Ids” represents a current flowing between the drain and the source of the drive transistor Md operating in the saturation region. In the drive transistor Md, “Vth” is the threshold voltage, “μ” is the mobility, “W” is the effective channel width (effective gate width), and “L” is the effective channel length (effective gate length). Respectively. “Cox” represents the sum of the unit gate capacitance of the drive transistor Md, that is, the gate oxide film capacitance per unit area, and the fringing capacitance between the source, drain, and gate.

  The pixel circuit having the N-channel type driving transistor Md has an advantage of high driving capability and simplification of the manufacturing process. However, in order to suppress variations in the threshold voltage Vth and the mobility μ, these correction operations can emit light. Must be done prior to bias setting.

Next, the control will be described with reference to FIG. 4. FIG. 4 shows the control before the present invention is applied.
In the following, the period in FIG. 4 is defined and the entire control is described in detail along the time axis in FIG. 4, and then the malfunction in the control in FIG. 4 (occurrence of lateral crosstalk) and the present invention for the control in FIG. Application (features of this embodiment) and effects thereof will be described in this order.

  4A to 4F are timing charts showing waveforms of various signals and voltages in display control. In this display control, data writing is sequentially performed in units of rows. The pixel circuit 3 (1, j) in the first row is a row to be written (display row), and the pixel circuit 3 (2 in the second row). , j) and the pixel circuit 3 (3, j) in the third row are not write targets (non-display rows) at the time of FIG. For the display line, after data is written by the display control shown in FIG. 4 and described below, the display line moves to the second line and the same display control is performed, and the same display control is performed for the third and second lines. One screen is displayed by repeating four lines,... After the display of one screen, display control for displaying other screens is repeated as many times as necessary.

FIG. 4A is a waveform diagram of the video signal Ssig.
FIGS. 4B1 and 4B2 are waveform diagrams of the write drive pulse WS (1) and the power supply drive pulse DS (1) supplied to the first row to be written. Similarly, FIGS. 4C1 and 4C2 are waveform diagrams and diagrams of the write drive pulse WS (2) and the power supply drive pulse DS (2) supplied to the second row to be non-written. 4 (D1) and FIG. 4 (D2) are waveform diagrams of the write drive pulse WS (3) and the power supply drive pulse DS (3) supplied to the third row to be non-written.
FIG. 4E is a waveform diagram of the gate potential (potential of the control node NDc) of the drive transistor Md in the pixel circuit 3 (1, j) in the first row to be written.
FIG. 4F is a waveform diagram of the source potential of the drive transistor Md (the anode potential of the organic light emitting diode OLED) in the pixel circuit 3 (1, j) in the first row to be written.

[Definition of period]
As shown in the lower part of FIG. 4F, FIG. 4 displays a waveform diagram with a span slightly more than four times as long as one horizontal period (1H) of the NTSC video signal standard. Then, in the final one horizontal period (1H), the final third threshold correction (VTC3), the mobility correction, and the actual data writing (W & μ) are continuously executed (this operation). ). The last three horizontal periods ((1H) × 3) prior to the main operation performed in the last one horizontal period (1H) are completely corrected for initialization and for the final threshold correction. Considering the case where there is not, it is expended to perform threshold correction twice in advance to some extent (preliminary operation).
In the display control as shown in FIG. 4, the resolution of the display image is increasing and the drive frequency of the display panel is very high. At present, from the threshold voltage correction to the data writing in one short horizontal period (1H). In view of the shortage of threshold correction time, the threshold correction is performed in several steps. However, for a small to medium-sized display panel or the like whose driving frequency is not so high, if the time of this operation is sufficient for one horizontal period (1H), if there is one horizontal period (1H) for initialization, the preliminary operation is It may be enough. Of course, the preliminary operation may be two horizontal periods (2H), or four horizontal periods (4H) or more.
When this operation is performed for a certain row, the preliminary operation can be executed in parallel for the next row (and the subsequent rows, etc.). Almost no effect. Rather, it is desirable that the preliminary operation is sufficiently performed in order to surely correct the threshold voltage.

The above is the division of the period viewed on a fixed scale of one horizontal period (1H), but it is also possible to functionally grasp the roughly four horizontal periods described in FIG.
Specifically, as described in the upper part of FIG. 4A, the discharge period (D-CHG) in the chronological order after the light emission period (LM0) of the previous screen (one field or one frame), the initial period The “preliminary operation” is executed through the conversion period (INT), the first threshold correction period (VTC1), the first standby period (WAT1), the second threshold correction period (VTC2), and the second standby period (WAT2). Subsequently, after the third threshold value correction (VTC3), the third standby period (WAT3), the writing & mobility correction period (W & μ), the light emission period of the pixel circuit 3 (1, j) in the first row ( The “main operation” is executed by transitioning to LM1).

[Outline of drive pulse]
Further, in FIG. 4, time display is indicated by symbols “T0” to “T21” at appropriate portions of the waveform diagram. Next, an outline of the video signal and the drive pulse will be described with reference to this time display.
In the write drive pulse WS (1) supplied to the first row, as shown in FIG. 4B1, four sampling pulses (SP0 to SP3) which are inactive at the “L” level and active at the “H” level. ) Appear periodically. At this time, the cycle of the four sampling pulses (SP0 to SP3) is constant throughout the preliminary operation (time T0 to time T15) and the main operation (after time T15). However, the write drive pulse WS (1) in this operation has a waveform in which the write pulse (WP) is superimposed after the fourth sampling pulse (SP3).

On the other hand, the video signal Ssig supplied to m (several hundred to several hundreds) video signal lines DTL (j) (see FIGS. 1 and 2) is m video signal lines in line sequential display. DTL (j) is supplied simultaneously. The signal amplitude (Vin) reflecting the data voltage obtained after sampling the video signal Ssig is the data reference potential Vo that repeatedly appears in the first half of one horizontal period (1H) as shown in FIG. This corresponds to the peak value of the video signal pulse (PP) that repeatedly appears in the latter half of one horizontal period (1H) as a reference. Hereinafter, the signal amplitude (Vin) is referred to as a data voltage Vin.
Of the several video signal pulses (PP) shown in FIG. 4A, the video signal pulse important for the first row is the video signal pulse (PPx) in the main operation that overlaps the write pulse (WP) in time. It is. The peak value from the data reference potential Vo of the video signal pulse (PPx) during this operation corresponds to the gradation value to be displayed (written) in FIG. 4, that is, the magnitude of the data voltage Vin. This gradation value (= Vin) may be the same for each pixel in the first row (in the case of monochromatic display), but usually changes according to the gradation value of the display pixel row. FIG. 4 is mainly for explaining the operation of one pixel in the first row, but the control itself is different except that this display gradation value may be different in other pixels in the same row. This is executed in parallel with the pixel drive control shown.

  The power supply driving pulse DS (1) supplied to the drain (see FIG. 2) of the driving transistor Md is the start (time) of the first first threshold correction period (VTC1) from time T0, as shown in FIG. 4 (B2). T6) It is held at the inactive low potential Vcc_L until immediately before, and transitions to the active high potential Vcc_H almost simultaneously with the start of the first threshold correction period (VTC1) (time T6). The holding of the high potential Vcc_H continues until the light emission period (LM1) ends.

The second row (pixel circuit 3 (2, j)) and the third row (pixel circuit 3 (3, j)) are shown in FIGS. 4C1, 4C2, and 4D1, respectively. ) And FIG. 4D2, each pulse is applied with a delay of one horizontal period (1H).
Specifically, in the period of time T5 to T7 in which the second sampling pulse (SP1) corresponding to the first threshold correction period (VTC1) of the first row is applied, the initialization period ( A first sampling pulse (SP0) corresponding to (INT) is applied.
During this pulse application, that is, at time T6, the power supply driving pulse DS (1) in the first row rises to a high level (power supply potential Vcc_H) and becomes active.

Thereafter, in the period of time T10 to T12 in which the third sampling pulse (SP2) corresponding to the second threshold correction period (VTC2) of the first row is applied, in the second row, from the first row to one horizontal period The second sampling pulse (SP1) is applied with a delay of (1H). In the third row, the first sampling pulse (SP0) is delayed by two horizontal periods ((1H) × 2) from the first row. Is applied.
During this pulse application, that is, at time T11, the power supply driving pulse DS (2) in the second row rises to the high potential Vcc_H and becomes active.

Thereafter, in the period of time T15 to T17 in which the fourth sampling pulse (SP3) corresponding to the third threshold correction period (VTC3) of the first row is applied, in the second row, from the first row to one horizontal period The third sampling pulse (SP2) is applied with a delay of (1H), and in the third row, the second sampling pulse (SP1) is delayed by two horizontal periods ((1H) × 2) from the first row. Is applied.
During this pulse application, that is, at time T16, the power supply driving pulse DS (3) in the third row rises to the high potential Vcc_H and becomes active.

When the pulse application timing design is performed as described above, the preliminary operation for several other rows in which the main operation is performed in parallel after one to several horizontal periods is performed in parallel during the period in which the main operation is performed in a certain row. For this reason, when it is limited to this operation, it is executed seamlessly in units of lines. Therefore, no useless period occurs other than the first few horizontal periods.
Since the display screen usually has hundreds to thousands of rows, the time of one to several horizontal periods during one-screen display is so short that it can be ignored. Therefore, even if the threshold voltage correction is divided into several times, there is substantially no time loss.

Next, a change in the potential of the source and gate of the driving transistor Md shown in FIGS. 4E and 4F and the accompanying operation under the above pulse control for each period shown in FIG. 4A. Explained.
Here, the preliminary operation explanatory diagram of the pixel circuit 3 (1, j) in the first row shown in FIGS. 5A to 7B, the time transition graph of the source potential Vs shown in FIG. The operation explanatory diagram of the pixel circuit 3 (1, j) in the first row shown in FIGS. 9A to 9C and FIG.

[Light emission period of previous screen (LM0)]
For the pixel circuit 3 (1, j) in the first row, the light emission period (LM0) for the screen one field or one frame before the time T0 (hereinafter referred to as the previous screen) is shown in FIG. 4B1. Thus, since the write drive pulse WS (1) is at the “L” level, the sampling transistor Ms is turned off. In addition, as shown in FIG. 4B2, the power supply driving pulse DS (1) is in the application state of the high potential Vcc_H.

  At this time, as shown in FIG. 5A, it is assumed that the organic light emitting diode OLED is in a light emitting state in accordance with the data voltage Vin0 input and held in the gate of the driving transistor Md by the data writing operation of the previous screen. . Since the driving transistor Md is set to operate in the saturation region, the driving current Id (= Ids) flowing through the organic light emitting diode OLED is equal to the gate-source voltage Vgs of the driving transistor Md held in the holding capacitor Cs. Accordingly, the value calculated from the above-described equation shown in FIG. 3 is taken.

[Discharge period (D-CHG)]
In FIG. 4, processing related to a new screen display of line sequential scanning is started from time T0.
At time T0, the horizontal pixel line drive circuit 41 (see FIG. 2) switches the power supply drive pulse DS (1) from the high potential Vcc_H to the low potential Vcc_L as shown in FIG. 4 (B2). In the driving transistor Md, since the potential of the node that has been functioning as the drain is suddenly dropped to the low potential Vcc_L and the potential of the source and the drain is reversed, the node that has been the drain until now is used as the source. A discharge operation is performed in which the node that was the source is the drain, and the potential of the drain (however, the source potential Vs remains in the notation in the drawing) is extracted.
Therefore, as shown in FIG. 5B, a drain current Ids in the opposite direction to that of the current flows in the driving transistor Md. A period during which a reverse current flows through the driving transistor Md is referred to as a “discharge period (D-CHG)” in FIGS. 4 and 5B.

When the discharge period (D-CHG) is started, as shown in FIG. 4F, the source potential Vs (the drain potential in actual operation) of the drive transistor Md is suddenly discharged at the time T0, as shown in FIG. The voltage drops to near the low potential Vcc_L.
At this time, when the low potential Vcc_L is smaller than the sum of the light emission threshold voltage Vth_oled. And the cathode potential Vcath of the organic light emitting diode OLED, that is, “Vcc_L <Vth_oled. + Vcath”, the organic light emitting diode OLED is extinguished.
Note that before the end of the discharge period (D-CHG) (time T1), as shown in FIG. 4A, the potential of the video signal Ssig is lowered from the data potential Vsig to the data reference potential Vo. ing.

  At time T0, as shown in FIG. 5B, the sampling transistor Ms is turned off and the control node NDc is in a floating state. For this reason, as shown in FIG. 4E, the gate voltage Vg of the drive transistor Md decreases at time T0.

[Initialization period (INT)]
Next, the write signal scanning circuit 42 (see FIG. 2) causes the write drive pulse WS (1) to transition from the “L” level to the “H” level at time T1, as shown in FIG. 4 (B1). The first sampling pulse (SP0) is applied to the gate of the sampling transistor Ms.
At this time T1, the discharge period (D-CHG) ends, and from here the initialization period (INT) starts.

In response to the application of the sampling pulse (SP0) at time T1, the sampling transistor Ms is turned on as shown in FIG. As described above, by the time T1, the potential of the video signal Ssig is switched to the data reference potential Vo. Therefore, the sampling transistor Ms samples the data reference potential Vo of the video signal Ssig, and transmits the sampled data reference potential Vo to the gate of the drive transistor Md.
As a result of this sampling operation, as shown in FIG. 4E, the gate voltage Vg of the drive transistor Md that has decreased at the time T0 is converged to the data reference potential Vo.

The sampling pulse (SP0) shown in FIG. 4B1 ends at time T2 when a sufficient time for potential convergence has elapsed from time T1, and the sampling transistor Ms is turned off. Therefore, until the time T5 when the sampling transistor Ms is turned on next time, the gate of the drive transistor Md is in an electrically floating state.
The timing at which the sampling transistor Ms is turned on again at the time T5 is controlled to be substantially the same as the end of the first horizontal period (1H), and within the period of the time T2 to T5, the one horizontal period (1H). The timing is designed so that the video signal pulse (PP) is accommodated (see FIGS. 4A and 4B1).

Looking at this from the sampling pulse (SP0), the duration (time T1 to T2) of the sampling pulse (SP0) for setting the write drive pulse WS (1) to the “H” level is one horizontal period (1H). The first half of the video signal Ssig is within a period (time T0 to T3) in which the data reference potential Vo is taken.
Then, in a state where the sampling transistor Ms is turned off at time T2, the time T4 when the potential fluctuation of the video signal line DTL (j) by the video signal pulse (PP) ends is waited for, and at time T5 thereafter, the data reference A second sampling pulse (SP1) for sampling the potential Vo again is started.
As a result of this control, erroneous sampling of the data potential Vsig of the video signal Ssig at the time T5 when the second sampling pulse (SP1) is raised is avoided.
Note that at the start of the second sampling at time T5, as shown in FIG. 4E, the gate voltage Vg already holds the data reference potential Vo. Therefore, in general, the gate voltage Vg hardly fluctuates even though the second sampling may compensate for a minute loss due to a leak current or the like.

Returning the description on the time axis slightly, the sampling transistor Ms is turned on by applying the first sampling pulse (SP0) at time T1, and as shown in FIG. When the gate voltage Vg of Md converges to the data reference potential Vo, the holding voltage of the holding capacitor Cs decreases in conjunction with this, and becomes “Vo−Vcc_L” (FIG. 4F). This is because the source potential Vs becomes the low potential Vcc_L by the discharge of FIG. 5B, and the holding voltage of the holding capacitor Cs is defined by the gate voltage Vg based on the low potential Vcc_L. That is, in FIG. 5C, when the gate voltage Vg drops to the data reference potential Vo, the holding voltage of the holding capacitor Cs decreases in conjunction with this, and the holding voltage converges to “Vo−Vcc_L”. This holding voltage “Vo−Vcc_L” is the gate-source voltage Vgs itself. If the gate-source voltage Vgs is not larger than the threshold voltage Vth of the drive transistor Md, the threshold correction operation cannot be performed thereafter. Further, the potential relationship is determined so as to satisfy “Vo−Vcc_L> Vth”.
In this way, by preparing the gate voltage Vg and the source potential Vs of the drive transistor Md, preparation for the threshold correction operation is completed.

[First threshold correction period (VTC1)]
After the sampling transistor Ms starts Vo sampling for the second time at time T5, as shown in FIG. 4B2, when the power supply driving pulse DS (1) rises from the low potential Vcc_L to the high potential Vcc_H at time T6, The initialization period (INT) ends, and the first threshold value correction period (VTC1) starts.

Immediately before the start (time T6) of the first threshold correction period (VTC1), since the sampling transistor Ms in the on state is sampling the data reference potential Vo, the gate voltage Vg of the drive transistor Md is a constant data reference. It is in an electrically fixed state at the potential Vo.
In this state, at time T6, the horizontal pixel line drive circuit 41 (see FIG. 2) raises the power supply drive pulse DS (1) from the low potential Vcc_L to the high potential Vcc_H as shown in FIG. 4 (B2). The horizontal pixel line drive circuit 41 holds the potential of the power supply line to the drive transistor Md at the high potential Vcc_H until the start of the processing of the next frame (or field) after the time T6.

The power supply voltage VDD of “Vcc_H−Vcc_L” is applied between the source and drain of the drive transistor Md by the rise of the power supply drive pulse DS (1). Therefore, the drain current Ids flows from the power supply to the driving transistor Md.
The source of the driving transistor Md is charged by the drain current Ids, and the source potential Vs rises as shown in FIG. 4F. Therefore, between the gate and source of the driving transistor Md that has previously taken the value “Vo−Vcc_L”. The voltage Vgs (holding voltage of the holding capacitor Cs) gradually decreases (FIGS. 4E and 4F).

At this time, the source charging speed of the driving transistor Md by the drain current Ids is not so large. The reason will be described with reference to FIG.
As shown in FIG. 6A, since the gate bias voltage applied to the gate voltage Vg of the driving transistor Md is defined by the data reference potential Vo and the bias voltage is not so large, the driving transistor Md is in a shallow ON state. That is, it is turned on in a state where the driving capability is not so large (first reason).
Further, the drain current Ids flows into the holding capacitor Cs. However, since the drain current Ids is also consumed for charging the capacitance Coled. Of the organic light emitting diode OLED, the source potential Vs is hardly increased (second reason).
Furthermore, since the sampling pulse (SP1) needs to be terminated at time T7 before time T8 when the video signal Ssig next transitions to the data potential Vsig (see FIG. 4B1), the charging time of the source potential Vs is required. Is insufficient (third reason).

  If the second sampling pulse (SP1) shown in FIG. 4 (B1) can be sustained for a sufficiently long time exceeding the time T7, the source potential Vs of the driving transistor Md (the anode potential of the organic light emitting diode OLED). As shown in FIG. 8, it rises with time starting from time T6 and converges at “Vo−Vth” (curve CV indicated by the broken line in FIG. 8). That is, when the gate-source voltage Vgs (holding voltage of the holding capacitor Cs) has just reached the threshold voltage Vth of the driving transistor Md, the increase of the source potential Vs should almost end.

[First waiting period (WAT1)]
However, in reality, since the time T7 comes before the convergence point is reached, the duration of the sampling pulse (SP1) ends, whereby the first threshold correction period (VTC1) ends and the first waiting period (WAT1) starts.
Specifically, when the gate-source voltage Vgs of the drive transistor Md becomes Vx1 (> Vth), that is, as shown in FIG. 8, the source potential Vs of the drive transistor Md is changed from the low potential Vcc_L to “Vo−Vx1”. The first threshold value correction period (VTC1) ends at the time point when it rises to "" (time T7). At this time (time T7), the voltage value Vx1 is held in the holding capacitor Cs.

When the first threshold value correction period (VTC1) ends, the sampling transistor Ms is turned off, so that the state in which the gate of the drive transistor Md is electrically fixed at the data reference potential Vo changes to an electrically floating state.
Therefore, after the time T7, when the source potential Vs increases, the potential (Vg) of the floating gate capacitively coupled to the source also increases (FIGS. 4E and 4F). As a result, in this example, at the end point (time T10) of the first waiting period (WAT1), the source potential Vs becomes larger than the convergence target “Vo−Vth” (see FIG. 8), while FIG. As shown in E) and (F), the gate-source voltage Vgs does not shrink.

The first standby period (WAT1) needs to wait for the passage of the video signal pulse (PP) as in the case of the initialization period (INT) described above, and is referred to as a “standby period” in that sense. However, a relatively long standby period such as time T7 to T10 allows the gate voltage Vg to rise, and the convergence of the gate-source voltage Vgs to the threshold voltage Vth does not proceed as described above.
In FIG. 4E, the increase in the gate voltage Vg during the first standby period (WAT1) is represented by “Va1”. If the increase in the source potential Vs that causes the increase in the gate voltage Vg through the coupling capacitor (holding capacitor Cs) by the bootstrap operation is also the same as “Va1”, the source potential Vs is the first standby. It becomes “Vo−Vx1 + Va1” at the end point (time T10) of the period (WAT1) (see FIG. 6B).
Therefore, it is necessary to return the gate potential to the data reference potential Vo, which is the initialization level, and perform threshold voltage correction again.

[Second threshold correction period (VTC2)]
Therefore, in the operation example of the present embodiment, in the next one horizontal period (1H) (time T10 to T15), the first threshold correction period (VTC1) performed in the previous one horizontal period (1H) (time T5 to T10). And a process similar to the first standby period (WAT1), that is, the second threshold correction period (VTC2) and the second standby period (WAT2).
However, at the time T5 when the first threshold value correction period (VTC1) is started, the gate-source voltage Vgs (holding voltage of the holding capacitor Cs) was relatively large as “Vo−Vcc_L”, whereas At time T10 when the two-threshold correction period (VTC2) is started, the holding voltage is reduced to a smaller “Vx1”.

As shown in FIG. 4B1, when the sampling pulse (SP2) rises at time T10 and the sampling transistor Ms is turned on, the gate voltage Vg (= “Vo + Va1”) of the driving transistor Md is lower (data reference potential Vo). Video signal line DTL (j). Therefore, a current corresponding to the difference (Va1) flows from the gate of the drive transistor Md to the video signal line DTL (j), and the gate voltage Vg is forced to the data reference potential Vo as shown in FIG. Is lowered.
The fluctuation of the potential (Va1) at the gate of the driving transistor Md is input to the source of the driving transistor Md via the holding capacitor Cs and the gate-source parasitic capacitance Cgs of the driving transistor Md, and the source potential Vs is pulled down. .
The pull-down amount of the source potential Vs at this time is expressed as “g * Va1” using the capacitive coupling ratio g. Here, the capacitance coupling ratio g is expressed as follows: g = (Cgs + Cs) / (Cgs + Cs + Coled) using the gate-source parasitic capacitance Cgs, the capacitance value (Cs) having the same sign as the holding capacitor Cs, and the capacitance Coled. Of the organic light emitting diode OLED. .) Therefore, the source potential Vs decreases by “g * Va1” from “Vo−Vx1 + Va1” immediately before and becomes “Vo−Vx1 + (1−g) Va1”.
Since the capacitive coupling ratio g takes a value smaller than 1 as is apparent from the definition formula, the change amount “g * Va1” of the source potential Vs is smaller than the change amount (Va1) of the gate voltage Vg.

  If the gate-source voltage Vgs (= “Vx1− (1−g) Va1”) of the drive transistor is larger than the threshold voltage Vth of the drive transistor Md, the drain current Ids is as shown in FIG. Flowing. The drain current Ids tends to flow until the source potential Vs of the drive transistor Md becomes “Vo−Vth” and the drive transistor Md is cut off. However, in the operation example of this embodiment, as shown in FIGS. 4E and 4F, the gate-source voltage Vgs is “Vx2” (however, Vx2 has a size satisfying Vx1> Vx2> Vth). Since the sampling pulse (SP2) ends at the time T12 when the sampling transistor Ms has, the sampling transistor Ms is turned off. The holding voltage of the holding capacitor Cs at time T12 is “Vx2”.

[Second waiting period (WAT2)]
The second waiting period (WAT2) starts from time T12.
In the second standby period (WAT2), as in the previous first standby period (WAT1), the sampling transistor Ms is turned off and the gate voltage Vg is in an electrically floating state. Therefore, in response to the increase in the source potential Vs. The gate voltage Vg also increases (see FIG. 7A).
However, the potential increase effect (bootstrap effect) of the gate voltage Vg is not so large because the gate-source voltage Vgs at the start time is close to the control target “Vth”, which is shown in FIG. 4 (E) and FIG. 4 (F). As can be seen from time T12 to T15, the potential increases of the source potential Vs and the gate voltage Vg are slight.

  More specifically, in the second standby period (WAT2) in FIG. 7A, if the increase in the source potential Vs due to the drain current Ids flowing is “Va2”, the standby period ends (time T15 in FIG. 4). ) Becomes “Vo−Vx2 + Va2”. The increase in the source potential by “Va2” is transmitted to the floating gate via the gate-source parasitic capacitance Cgs and the holding capacitor Cs, and as a result, the gate voltage Vg also increases by substantially the same potential “Va2”. To do. However, the potential increase “Va2” of the gate voltage Vg is much smaller than the potential increase “Va1” in the first standby period (WAT1), as shown in FIG.

[Third threshold correction (VTC3)]
The “main operation” is entered from time T15, and the third threshold value correction (VTC3) starts.
In the third threshold correction (VTC3) (time T15 to T17), processing similar to that in the second threshold correction period (VTC2) is executed.
However, at the time T10 when the second threshold correction period (VTC2) is started, the gate-source voltage Vgs (the holding voltage of the holding capacitor Cs) was relatively large as “Vx1”, whereas the third threshold value At time T15 when the correction period (VTC3) is started, the time period is further reduced to “Vx2”.
Since the basic operation is the repetition of [second threshold correction period (VTC2)], it is omitted. The description of [second threshold correction period (VTC2)] can be applied to the third threshold correction (VTC3) by replacing “Va1” with “Va2” and “Vx1” with “Vx2”. This is also apparent from the comparison between FIG. 6C and FIG.

  However, the difference from the second threshold correction period (VTC2) is that, as shown in FIGS. 4E and 4F, by time T17 when the third threshold correction (VTC3) ends, the drive transistor Md The gate-source voltage Vgs (holding voltage of the holding capacitor Cs) is equal to the threshold voltage Vth. Therefore, the drive transistor Md is cut off when the gate-source voltage Vgs becomes equal to the threshold voltage Vth, and thereafter, the drain current Ids does not flow. At this time, the source potential Vs of the driving transistor Md is “Vo−Vth”.

As described above, the threshold voltage correction is performed a plurality of times (three times in this example) with the standby period interposed therebetween, so that the holding voltage of the storage capacitor Cs converges in a stepped manner with the standby period being constant. The threshold voltage Vth is finally obtained.
If the gate-source voltage of the driving transistor is increased by “Vin”, the gate-source voltage is “Vin + Vth”. Further, a driving transistor having a large threshold voltage Vth and a driving transistor having a small threshold voltage Vth are considered.
The former driving transistor having a larger threshold voltage Vth has a larger gate-source voltage by the amount of the larger threshold voltage Vth, and conversely, the driving transistor having a smaller threshold voltage Vth has a smaller threshold voltage Vth, resulting in a smaller gate-source voltage. Therefore, regarding the threshold voltage Vth, the variation can be canceled by the threshold voltage correction operation, and the same drain current Ids can be caused to flow to the drive transistor at the same data voltage Vin.

Note that in the threshold correction period of three times, that is, in the first threshold correction period (VTC1), the second threshold correction period (VTC2), and the third threshold correction (VTC3), the drain current Ids is exclusively one of the holding capacitors Cs. It is consumed only to flow into the electrode side, one electrode side of the capacitance Coled. Of the organic light emitting diode OLED, and it is necessary to prevent the organic light emitting diode OLED from being turned on. When the anode voltage of the organic light emitting diode OLED is expressed as “Voled.”, Its threshold voltage is expressed as “Vth_oled.”, And its cathode potential is expressed as “Vcath”, the condition for maintaining the organic light emitting diode OLED in the off state is “Voled. ≦ “Vcath + Vth_oled.” Always holds.
Here, when the cathode potential Vcath of the organic light emitting diode OLED is constant at the reference voltage VSS (for example, the ground voltage GND), this equation can always be established when the light emission threshold voltage Vth_oled. Is very large. However, the light emission threshold voltage Vth_oled. Is determined by the manufacturing conditions of the organic light emitting diode OLED, and the light emission threshold voltage Vth_oled. Cannot be increased too much for efficient light emission at a low voltage. Therefore, preferably, the organic light emitting diode OLED is reverse-biased by setting the cathode potential Vcath smaller than the low potential Vcc_L until the threshold correction period of 3 degrees and the mobility correction period described below are completed. It is good to leave.

[Third waiting period (WAT3)]
The above is the description of the threshold voltage correction, but in this operation example, the standby period (third standby period (WAT3)) for “writing & mobility correction” starts. The third standby period (WAT3) is different from the first standby period (WAT1) and the second standby period (WAT2) for the threshold voltage correction so far, and is simply performed at the subsequent “writing & mobility correction”. This is a short waiting period for waiting so that a portion where the potential change of the video signal Ssig is unstable is not erroneously sampled.

As shown in FIG. 4 (B1), when the sampling pulse (SP3) transitions from the “H” level to the “L” level at time T17, the third waiting period (WAT3) starts from here.
In the third standby period (WAT3), as shown in FIG. 4 (A), a video signal pulse (PPx) having a data potential Vsig to be displayed in the pixel circuit 3 (1, j) at a time T18 in the middle. Is supplied to the video signal line DTL (j) as the video signal Ssig (see FIG. 9A). In the video signal Ssig, the difference between the data potential Vsig and the data reference potential Vo corresponds to the data voltage Vin corresponding to the gradation value to be displayed by the pixel circuit. That is, the data potential Vsig is equal to “Vo + Vin”.
The third standby period (WAT3) ends at time T19 when the video signal Ssig has stabilized at the data potential Vsig after a time has elapsed since the potential change performed at time T18.

[Writing & mobility correction period (W & μ)]
From time T19, the writing & mobility correction period (W & μ) starts.
As shown in FIG. 4 (B1), the write pulse (WP) is supplied to the gate of the sampling transistor Ms at time T19 during application of the video signal pulse (PPx) in this operation. Then, as shown in FIG. 9B, the sampling transistor Ms is turned on, and the difference between the data potential Vsig (= Vo + Vin) of the video signal line DTL (j) and the gate voltage Vg (= Vo), that is, The data voltage Vin is input to the gate of the drive transistor Md. As a result, the gate voltage Vg becomes “Vo + Vin”.
When the gate voltage Vg increases by the data voltage Vin, the source potential Vs also increases in conjunction with this. At this time, the data voltage Vin is not transmitted to the source potential Vs as it is, but the source potential Vs rises by the change in the ratio according to the above-described capacitive coupling ratio g, that is, “g * Vin”. Therefore, the source potential Vs after the change is “Vo−Vth + g * Vin”. As a result, the gate-source voltage Vgs of the drive transistor Md becomes “(1−g) Vin + Vth”.

Here, the variation due to the mobility μ will be described.
Although the error due to the mobility μ is included every time the drain current Ids is flowed by the three threshold voltage corrections so far, the error component due to the mobility μ is strictly discussed because the variation of the threshold voltage Vth is large. I didn't. At this time, the voltage indicating only the result is newly described as “Va1” or “Va2” without using the capacitive coupling ratio g, and the complexity due to explaining the variation in mobility is avoided. Because.
On the other hand, as already described, after the threshold voltage correction is strictly performed, the threshold voltage Vth is held in the holding capacitor Cs at that time. The drain current Ids does not vary depending on the magnitude of Vth. For this reason, if the drive transistor Md after the threshold voltage correction is conducted, if the value of the holding voltage (gate-source voltage Vgs) of the holding capacitor Cs varies due to the drive current Id during the conduction, the amount of fluctuation ΔV (which can be positive or negative) is a variation of the mobility μ of the driving transistor Md, more precisely, in addition to the mobility in a pure sense, which is a physical property parameter of the semiconductor material, This reflects the overall variation in factors that affect the current driving force in the structure or manufacturing process.

  Returning to the explanation based on the above, in FIG. 9B, when the sampling transistor Ms is turned on and the data voltage Vin is added to the gate voltage Vg, the driving transistor Md has the data voltage Vin ( A drain current Ids having a magnitude corresponding to (gradation value) is attempted to flow between the source and drain. At this time, the drain current Ids varies depending on the mobility μ, and as a result, the source potential Vs becomes “Vo−Vth + g * Vin + ΔV” obtained by adding the variation ΔV due to the mobility μ to “Vo−Vth + g * Vin”. .

At this time, in order not to cause the organic light emitting diode OLED to emit light, the cathode potential Vcath corresponding to the data voltage Vin, the capacitive coupling ratio g, or the like is satisfied so that “Vs (= Vo−Vth + g * Vin + ΔV) <Vth_oled. + Vcath” is satisfied. It may be set in advance.
If this setting is performed in advance, the organic light emitting diode OLED is reverse-biased and does not emit light because it is in a high impedance state, and exhibits simple capacitance characteristics rather than diode characteristics.
At this time, as long as the above conditional expression is satisfied, the source potential Vs does not exceed the sum of the emission threshold voltage Vth_oled. Of the organic light emitting diode OLED and the cathode potential Vcath, so that the drain current Ids (drive current Id) is A capacitance “C = Cs + Coled. + Cgs” obtained by adding the capacitance value Cs of Cs, the equivalent capacitance value Coled. At the time of reverse bias of the organic light emitting diode OLED, and the parasitic capacitance (denoted as Cgs) existing between the gate and source of the driving transistor Md. Used to charge. As a result, the source potential Vs of the drive transistor Md increases. At this time, since the threshold correction operation of the drive transistor Md is completed, the drain current Ids that the drive transistor Md flows reflects the mobility μ.

As shown by the expression “(1−g) Vin + Vth−ΔV” in FIGS. 4E and 4F, the gate-source voltage Vgs held in the holding capacitor Cs is set to the source potential Vs. Since the added fluctuation amount ΔV is subtracted from the gate-source voltage Vgs (= (1−g) Vin + Vth) after the threshold correction, the fluctuation amount ΔV is held in the holding capacitor Cs so that negative feedback is applied. Therefore, hereinafter, the fluctuation amount ΔV is also referred to as “negative feedback amount”.
This negative feedback amount ΔV can be expressed by an approximate expression of ΔV = t * Ids / (Coled. + Cs + Cgs) because “Coled. >> Cs + Cgs” holds in a state where the organic light emitting diode OLED is reverse-biased. . From this approximate expression, it can be seen that the fluctuation amount ΔV is a parameter that changes in proportion to the fluctuation of the drain current Ids.
From the approximate expression of the negative feedback amount ΔV, the negative feedback amount ΔV added to the source potential Vs is the magnitude of the drain current Ids (this magnitude is positively correlated with the magnitude of the data voltage Vin, that is, the gradation value). The drain current Ids flows, that is, the time (t) from time T19 to time T20 required for mobility correction shown in FIG. 4B1. That is, the larger the gradation value and the longer the time (t), the larger the negative feedback amount ΔV.
Therefore, the mobility correction time (t) is not necessarily constant, and on the contrary, it may be preferable to adjust it according to the drain current Ids (gradation value). For example, when the drain current Ids is close to white display and the drain current Ids is large, the mobility correction time (t) is shortened. Conversely, when the drain current Ids is close to black display and becomes small, the mobility correction time (t) is lengthened. It is good to set to. This automatic adjustment of the mobility correction time according to the gradation value can be realized by providing the function in advance in the write signal scanning circuit 42 shown in FIG.

[Light emission period (LM1)]
When the writing & mobility correction period (W & μ) ends at time T20, the light emission period (LM1) starts.
Since the write pulse (WP) ends at time T20, the sampling transistor Ms is turned off, and the gate of the drive transistor Md is in an electrically floating state.

  By the way, in the writing & mobility correction period (W & μ) before the light emission period (LM1), the drive transistor Md tries to flow the drain current Ids according to the data voltage Vin, but it does not always flow. The reason is that if the current value (Id) flowing through the organic light emitting diode OLED is very small as compared with the current value (Ids) flowing through the drive transistor Md, the sampling transistor Ms is turned on, and therefore the gate voltage of the drive transistor Md This is because Vg is fixed at “Vo + Vin” and the source potential Vs tends to converge to a potential (“Vo + Vin−Vth”) that is lowered by the threshold voltage Vth therefrom. Therefore, no matter how long the mobility correction time (t) is increased, the source potential Vs cannot be a potential exceeding the convergence point. In the mobility correction, the difference in mobility μ is monitored and corrected based on the difference in speed until convergence. For this reason, even when the white display data voltage Vin with the maximum luminance is input, the end point of the mobility correction time (t) is determined before the convergence.

When the light emission period (LM1) starts and the gate of the drive transistor Md becomes floating, the source potential Vs can be further increased. Therefore, the drive transistor Md operates so as to flow the drive current Id corresponding to the input data voltage Vin.
As a result, the source potential Vs (the anode potential of the organic light emitting diode OLED) rises, and eventually the reverse bias state of the organic light emitting diode OLED is canceled, and as shown in FIG. 9C, the drain current Ids becomes the driving current Id. As a result, the organic light emitting diode OLED actually starts to emit light. After a while from the start of light emission, the drive transistor Md is saturated with the drain current Ids corresponding to the input data voltage Vin, and when the drain current Ids (= Id) becomes constant, the organic light emitting diode OLED becomes the data voltage Vin. The light emission state with the corresponding brightness is obtained.

The increase in the anode potential of the organic light emitting diode OLED that occurs from the start of the light emission period (LM1) until the luminance becomes constant is nothing but the increase in the source potential Vs of the drive transistor Md. “ΔVoled.” In the sense of an increase amount of the anode voltage Voled. The source potential Vs of the drive transistor Md is “Vo−Vth + g * Vin + ΔV + ΔVoled.” (See FIG. 4F).
On the other hand, as shown in FIG. 4E, since the gate voltage Vg is in a floating state, the gate voltage Vg rises by the same amount as the increase amount ΔVoled. When the potential Vs is saturated, the gate voltage Vg is also saturated.
As a result, for the gate-source voltage Vgs (holding voltage of the holding capacitor Cs), the mobility correction value (“(1−g) Vin + Vth−ΔV”) is maintained even during the light emission period (LM1).

In the light emission period (LM1), since the drive transistor Md operates as a constant current source, the IV characteristic of the organic light emitting diode OLED changes with time, and the source potential Vs of the drive transistor Md changes accordingly. There is.
However, the holding voltage of the holding capacitor Cs is maintained at “(1−g) Vin + Vth−ΔV” regardless of whether the IV characteristic of the organic light emitting diode OLED changes with time. Since the holding voltage of the holding capacitor Cs includes a component (+ Vth) for correcting the threshold voltage Vth of the driving transistor Md and a component (−ΔV) for correcting the variation due to the mobility μ, the threshold voltage Vth and the movement Even if the degree μ varies between different pixels, the drain current Ids of the drive transistor Md, that is, the drive current Id of the organic light emitting diode OLED is kept constant.

Specifically, as the threshold voltage Vth increases, the drive transistor Md decreases the source potential Vs by the threshold voltage correction component (+ Vth) of the holding voltage so that the drain current Ids (drive current Id) flows more. Increase drain-to-drain voltage. Therefore, the drain current Ids is constant even if the threshold voltage Vth varies.
In addition, when the mobility μ is small and the fluctuation amount ΔV is small, the driving transistor Md has a relatively small decrease amount of the holding voltage due to the mobility correction component (−ΔV) of the holding voltage of the holding capacitor Cs. Therefore, a large source-drain voltage is ensured, and as a result, the drain current Ids (driving current Id) flows more. Therefore, the drain current Ids is constant even when the mobility μ varies.

  From the above, even if the threshold voltage Vth and mobility μ of the drive transistor Md vary between pixels, and even if the characteristics of the drive transistor Md change over time, the organic light emitting diode OLED can be used as long as the data voltage Vin remains the same. The light emission brightness is also kept constant.

<Auxiliary capacitor>
In the write & mobility correction period (W & μ) of the light emission control described above, as shown in FIGS. 4E and 4F, the data voltage Vin written to the gate voltage Vg of the drive transistor Md remains as it is as the holding capacitor. Instead of being added to the holding voltage of Cs, the data voltage “(1-g) Vin” that is lower than the data voltage Vin by (g * Vin) is added to the holding voltage of the holding capacitor Cs. For this reason, a loss of write gain corresponding to the capacitive coupling ratio g occurs, and this causes a desired brightness not to be obtained on the display screen.
The capacitive coupling ratio g is expressed as “g = (Cgs + Cs) / (Cgs + Cs + Coled.)”. A larger denominator is preferable because a loss of write gain is reduced. Therefore, Japanese Patent Laid-Open No. 2007-102046 (Patent Document 1) proposes a pixel circuit configuration in which an auxiliary capacitor Csub is connected in parallel to the organic light emitting diode OLED. When a sufficiently large auxiliary capacitor Csub is added, the capacitive coupling ratio g becomes “g = (Cgs + Cs) / (Cgs + Cs + Coled. + Csub)” and approaches zero, and the write gain is improved accordingly.

  By the way, when the capacitance at the source of the driving transistor Md is increased by mobility correction, the source potential Vs is slowly charged. Since the drive capability of the drive transistor Md is set high, the source potential Vs may be charged too early within a predetermined time (t). If this charging is too early, the rising curve of the source potential Vs is saturated within time (t), and the accuracy of mobility correction is reduced. The addition of the auxiliary capacitor Csub is also desirable in terms of preventing the saturation within the predetermined time and increasing the mobility correction accuracy.

  In Patent Document 1, the auxiliary capacitor Csub is connected between the source of the drive transistor Md and the supply line of the cathode potential Vcath. Usually, the cathode potential Vcath is set to a negative potential that is low enough to reverse bias the organic light emitting diode OLED. However, the cathode potential Vcath is higher than the one electrode of the auxiliary capacitor Csub at the cathode potential Vcath. Fixing at the potential Vcc_H is preferable because the capacitance value (charge storage capability) of the auxiliary capacitor Csub during actual use can be increased. However, if the auxiliary capacitor Csub is connected to the power supply scanning line DSL (i) in the same pixel circuit, the threshold voltage correction is hindered. This is called a prior application).

FIG. 10 shows the pixel circuit of the prior application in two pixels adjacent in the column direction.
The pixel circuit 3 (2, j) illustrated in FIG. 10 is different from the pixel circuit 3 (i, j) illustrated in FIG. 2 in that an auxiliary capacitor Csub is added. The auxiliary capacitor Csub is connected to the source of the driving transistor Md in the pixel circuit 3 (2, j) (hereinafter also referred to as a source node NDs) and the power supply scanning line DSL ( 1). The same applies to the pixel circuit 3 (1, j) one row before. Note that the capacitance Coled. Of the organic light emitting diode OLED is not a circuit element because it is a diode equivalent capacitance at the time of reverse bias, but is described in the circuit on the toilet.

<Other examples of light emission control>
Hereinafter, a problem in the pixel circuit configuration shown in FIG. 10 will be described using another light emission control example shown in FIG.
In the timing charts shown in FIGS. 11A to 11D, the pulse waveforms of the other display lines shown in FIG. 4 are omitted, and the initialization and the first waveform within one horizontal period (1H) are omitted. Although one threshold value correction is performed continuously, this point is not essential and is a control that can be adopted in FIG.
Basic control is common to FIG. 11 and FIG. The symbol “T1 ′” means that it is slightly before the time T1. Further, in FIG. 11, two times indicated at the same position on the time axis, that is, T7 and T8, T9 and T10, T12 and T13, T14 and T15, and T17 and T18 are larger than the time when the number is smaller. It means that it is desirable to be slightly ahead on the time axis.

  In FIG. 11, since the initialization and the first threshold correction are continuously performed within the first one horizontal period (1H), quick discharge is necessary. Therefore, the low potential Vcc_L of the power supply scanning line DSL is normally set to a relatively large negative potential. The high potential Vcc_H is a high positive potential necessary for writing, mobility correction, and light emission. Therefore, when it is necessary to perform rapid discharge as shown in FIG. 11, the pulse peak value (Vcc_H−Vcc_L) of the power supply scanning line DSL may be set large.

<Problem when Csub is set to DSL connection in the previous stage>
FIG. 12A is a diagram focusing on one pixel in FIG. 10, and FIG. 12B is a diagram illustrating 5 pixels from a pixel row (display line) including a pixel focusing on the timing when the light emission time is controlled. It is a figure which shows roughly to the display line before a stage.
Here, the display line including the pixel of interest is referred to as “target display line L (0)”, and the display line whose display is controlled one horizontal period (1H) before the target display line L (0) is referred to as “display line”. L (-1) "is a display line that is displayed and controlled before 2H is" display line L (-2) ", and similarly, a display line that is controlled and displayed before 3H, 4H, and 5H is" display line L ". (−3) ”,“ display line L (−4) ”, and“ display line L (−5) ”.
In this way, the code (i) indicating the row is expanded to 0 or less, and the power supply scanning line DSL (i) and the write scanning line WSL (i) are represented using this code.

Since the times T1, T10, and T15 shown in FIG. 12B correspond to the display control shown in FIG. 11, the processing described with reference to FIG. 4 is executed during this time.
In FIG. 12B, the period during which the power supply scanning line DSL (i) (i = 0, -1, -2, -3, -4, -5) is transitioned to the low potential Vcc_L is the extinguishing time and the high potential. A period of Vcc_H is a light emission (permission) period.
Although not shown in FIG. 12B, the writing scan line WSL (i) takes a binary potential of a high potential Vws_H and a low potential Vws_L (see FIG. 11B2).

In FIG. 13A, the pixel circuit 3 (i, j) in the previous stage is turned off and the pixel circuit 3 (i, j) in the previous stage is emitting light. The potentials of the control node NDc and the source node NDs of i, j) are shown by the equations (1) and (2).
When the power supply scanning line DSL (i−1) power supply line in the previous stage transitions from the high potential Vcc_H to the low potential Vcc_L, the potential fluctuation caused by this potential change is caused by the source node of the driving transistor Md via the auxiliary capacitor Csub. Enter NDs. As can be seen from the equation (1) shown in FIG. 13A, the potential of the node ND at this time is “(Vcc_H−Vcc_L) from the original source potential Vs according to the capacitance ratio of the organic EL capacitor Coled. ) Csub / (Csub + Coled.) ”, And the source potential Vs ′ is lowered. However, the right side of the equation (1) shows a peak of potential fluctuation, and the potential fluctuation converges and disappears with time.

In the pixel circuit 3 (i, j) in the light emitting state, the sampling transistor Ms is turned off by the low potential Vws_L applied to the gate of the sampling transistor Ms, and the gate (control node NDc) of the drive transistor Md is in an electrically floating state. It has become. Therefore, the potential fluctuation generated at the source node NDs is transmitted to the control node NDc via the holding capacitor Cs and the like, and the potential is fluctuated.
The potential of the control node NDc is a gate potential that is lowered by “(Vcc_H−Vcc_L) Csub / (Csub + Coled.)” From the gate voltage Vg already set according to the input data voltage Vin due to the holding characteristics of the holding capacitor Cs. It fluctuates to Vg ′ (minimum value). This potential fluctuation converges and disappears over time.

<Condition of Vws_L>
When the control node potential (gate voltage Vg ′ of the drive transistor Md) that has been subjected to the potential fluctuation in this way is lowered from the gate potential (low potential Vws_L) of the sampling transistor Ms by the threshold voltage Vths of the sampling transistor Ms. The sampling transistor Ms is turned on.
This is shown in equations (3) and (4) of FIGS. 13 (B) and 13 (C).

However, if the source potential of the sampling transistor Ms is the same as the gate potential, no leakage current is generated. However, if the source potential is lower than the gate potential, the off-leakage current increases rapidly to the extent that the image quality is affected even when the source potential is not turned on.
Therefore, if the following expression (5) is satisfied by removing the term of the threshold voltage Vths of the sampling transistor Ms from the right side of the expression (3), a current including a relatively large leakage current and on-current that affects the image quality is satisfied. , Does not flow to the sampling transistor Ms.

Vws_L <Vg− (Vcc_H−Vcc_L) Csub / (Csub + Coled.) (5)

  From the above, the low potential Vws_L of the write scanning line WSL is determined so as to satisfy the above formula (5). The values of the low potential Vws_L and the high potential Vws_H are determined by the write signal scanning circuit 42 shown in FIG. 12 and the like, and in particular, the write signal so that the value of the low potential Vws_L can satisfy the above formula (5). A scanning circuit 42 is configured.

More specifically, the right side of Expression (5) includes five parameters such as Vg, Vcc_H, Vcc_L, Csub, and Coled.
Among these, the value of the high potential Vcc_H is determined from a viewpoint necessary for data writing and mobility correction for a limited time.
The low potential Vcc_L is determined to be a value from the viewpoint of performing rapid discharge by reverse-biasing the organic light emitting diode OLED in a limited time.
The capacitance Coled. Of the organic light emitting diode OLED is a value determined depending on the area of the OLED in the pixel when the production conditions with high efficiency and long life are determined by the development of the organic multilayer film.
The auxiliary capacitor Csub is mainly determined as a value for obtaining a necessary write gain, although it depends on the level of the low potential Vcc_L and the data write time.
The gate voltage Vg can be obtained by sampling the potential range of the video signal line DTL, that is, the range including the data reference potential Vo and the data potential Vsig from black to white. Change in consideration.

As described above, the parameters on the right side of Equation (5) excluding the gate voltage Vg change under various conditions for each process and pattern improvement, but the change width is relatively narrow. As the process and pattern are improved, the values of these parameters are almost fixed.
On the other hand, for the gate voltage Vg, a range in which a value can be accurately obtained is obtained from a potential range that can be taken by the video signal line DTL.
The horizontal pixel line drive circuit 41 can output a low potential Vws_L that always uses equation (5) even if the gate voltage Vg changes to the maximum when the process and pattern are improved, using a fixed parameter. Designed.
Note that the minimum value of the gate voltage Vg is usually set to 0 [V] at the data reference potential Vo in many cases. Therefore, in this case, the low potential Vws_Lh takes a negative value.
From the above, it is possible to prevent not only a large deterioration in image quality due to the sampling transistor Ms being turned on but also a deterioration in image quality due to leakage current, such as black floating.

  A modification in this embodiment will be described.

<Modification 1>
The horizontal pixel line driving circuit 41 uses the determined parameters for each process and pattern improvement, and always considers the threshold voltage Vths of the sampling transistor Ms even if the gate voltage Vg changes to the maximum (3 ) So that the low potential Vws_L can be output.
In this case, since the sampling transistor Ms is not turned on, a large image quality degradation is avoided.

<Modification 2>
The pixel circuit is not limited to that shown in FIGS.
As shown in FIG. 10, the auxiliary capacitor Csub may be connected not to the power supply scanning line DSL in the previous stage but to another power supply scanning line DSL whose display is controlled before that.
In the case shown in FIG. 12B, there is a period in which not only the display line L (−1) but also the display line L (−2) is turned off when the target display line L (0) can emit light. In this case, the auxiliary capacitor Csub may be connected to the power supply scanning line DSL (−2) of the display line L (−2) preceding by two stages.
The turn-off time is arbitrarily determined by the duty ratio of the power supply scanning line DSL, and the range of the stage to which the auxiliary capacitor Csub can be connected is determined accordingly.

<Modification 3>
In the pixel circuit of FIG. 2, the data reference potential Vo is given by sampling the video signal Ssig, but the data reference potential Vo can also be given to the source and gate of the drive transistor Md via another transistor.
In the pixel circuit of FIG. 2, the capacitor is only the holding capacitor Cs. However, another holding capacitor may be provided between the gate of the driving transistor Md and the constant voltage line, for example. The light emitting element is not limited to the organic light emitting diode OLED, and may be another self-light emitting element.

<Modification 4>
A driving method in which the pixel circuit controls light emission and non-light emission of the organic light emitting diode OLED includes a method in which the transistors in the pixel circuit are controlled by a scanning line, and a method in which a power supply voltage supply line is AC driven by a driving circuit (power supply AC Drive method).
The pixel circuit of FIG. 2 or FIG. 13 is an example of the latter power source AC driving method. In this method, the cathode side of the organic light emitting diode OLED may be AC driven to control whether the driving current flows or not. .
On the other hand, in the former method of controlling the light emission control by the scanning line, another transistor is inserted between the drain side of the driving transistor Md or between the source and the organic light emitting diode OLED, and the gate thereof is scanned for power supply driving control. Drive with lines.

<Modification 5>
In the display control shown in FIGS. 4 and 11, the threshold correction period (VTC) is performed by three corrections. However, the correction is performed once or a plurality of times other than three times (initialization in between). The meaning of not pinching) The threshold value may be corrected by processing. Further, display control may be performed in which data is written after mobility correction is performed. In that case, it is possible to apply the present invention to data writing, to apply the present invention to mobility correction, or to apply the present invention to both.

According to this embodiment and its modification, there exist the following effects.
In the pixel circuit configuration as shown in FIG. 10, particularly in the case of black display, the gate potential of the drive transistor Md is lower, so that leakage is likely to occur. The video signal line DTL (j) is always supplied with the data reference potential Vo and the data potential Vsig, and the data potential Vsig is always changing. For this reason, if the expressions (5) and (3) are not satisfied, the video signal line potential leaks to the gate of the drive transistor Md. At this time, the gate-source voltage Vgs of the drive transistor Md becomes a voltage equal to or higher than the black level, which appears as black floating, resulting in a decrease in contrast.
Further, when the sampling transistor Ms is completely turned on, if the data voltage Vin held before that and the data voltage Vin (= Vo + Vsig) of the video signal line DTL are greatly different, the display line becomes streak-like screen noise. As a result, the image quality is greatly reduced.

  In this embodiment, since the low potential Vws_L is determined so that the formula (5) or the formula (3) is always satisfied regardless of the gate voltage Vg, black floating is prevented or suppressed, and high contrast is achieved. It is possible to obtain image quality and prevent further deterioration in image quality.

It is a figure which shows the main structures of the organic electroluminescent display in connection with embodiment of this invention. It is a figure which shows an example of the basic composition of the pixel circuit in connection with embodiment of this invention, and the drive circuit part which controls the pixel circuit. It is a figure which shows the graph and formula showing the characteristic of an organic light emitting diode. It is a timing chart which shows the waveform of the various signals in the display control before applying this invention in connection with embodiment of this invention, and a voltage. It is operation | movement explanatory drawing to Vo sampling in control of FIG. It is operation | movement explanatory drawing to the 2nd threshold value correction | amendment in control of FIG. It is operation | movement explanatory drawing to the 3rd threshold value correction | amendment in control of FIG. It is a graph of the time transition of the source potential concerning the embodiment of the present invention. It is operation | movement explanatory drawing to the light emission period in control of FIG. FIG. 3 is a diagram illustrating a configuration of a pixel circuit according to an example of an embodiment of the present invention and a drive circuit portion that controls the pixel circuit. It is a figure which shows the wiring arrangement | positioning of two adjacent pixel circuits shown in FIG. 10, and an equivalent circuit corresponding to it. In embodiment of this invention, it is a figure for demonstrating transition between the display line of light extinction and light emission. FIG. 5 is a diagram for explaining a potential variation of a pixel circuit due to a potential change of a power supply scanning line, using an expression, related to an embodiment of the present invention. It is the figure which copied the equivalent circuit schematic of the pixel circuit described in node background art (patent document 1), changing a part of reference numerals.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Organic EL display, 2 ... Pixel array, 3 ... Pixel circuit, 4 ... V scanner, 5 ... H scanner, 41 ... Horizontal pixel line drive circuit, 42 ... Write signal scanning circuit, OLED ... Organic light emitting diode, M1 ... Drive Transistor, Ms ... Sampling transistor, Cs ... Holding capacitor, Coled ... Capacitance of organic light emitting diode, Csub ... Auxiliary capacitor, NDc ... Control node, NDs ... Source node, WSL ... Write scan line, DSL ... Power supply scan line, DTL ... Video signal line, Vsig ... Data potential, Vo ... Data reference potential, Vws_L ... Low potential of write scan line, Vcc_H ... High potential of power scan line, Vcc_L ... Low potential of power scan line, Vg ... Gate voltage

Claims (5)

A pixel array in which a plurality of pixel circuits are arranged in a matrix;
A plurality of write scan lines and a plurality of power supply scan lines connecting pixel circuits in the pixel array in a row direction;
A plurality of video signal lines connecting pixel circuits in the pixel array in a column direction;
A drive circuit that controls the potentials of the plurality of write scan lines and the plurality of power supply scan lines, and
Each of the plurality of pixel circuits is
On the other hand, a light emitting element whose applied voltage value changes depending on the potential of the electrode;
A driving transistor connected between the power supply scanning line and the one electrode;
A sampling transistor connected between the video signal line and a control node of the driving transistor and controlled in accordance with a potential of the writing scanning line;
A holding capacitor coupled to the control node;
An auxiliary capacitor connected between the one electrode and a power supply scanning line of another pixel circuit located on one side in the column direction;
Including
The driving circuit corresponds to a value Csub of the auxiliary capacitor, an equivalent capacitance Coled of the light emitting element, a high potential Vcc_H and a low potential Vcc_L of the power source scanning line, and a potential of the video signal line. Depending on the possible range of the gate potential Vg, the following equation:
Vws_L <Vg− (Vcc_H−Vcc_L) Csub / (Csub + Coled.)
A self-luminous display device configured to output a low potential Vws_L that satisfies the above condition to the writing scanning line as a lower potential of a binary potential. The drive circuit sequentially selects a pair of the write scan line and the power scan line corresponding to each of a plurality of pixel rows in a column direction,
The auxiliary capacitor is connected to a power supply scanning line that connects a pixel circuit in another pixel row that is first selected by the drive circuit from a pixel row to which the pixel circuit having the auxiliary capacitor belongs. Self-luminous display device. The self-luminous display device according to claim 1, wherein the low potential Vws_L of the writing scan line is a negative potential having a value satisfying the formula. A video signal in which a data pulse having a data potential whose potential difference from the data reference potential Vo changes corresponding to the display luminance of the pixel is transmitted in the video signal line, and the right side of the equation is the gate potential. 2. The self-luminous display device according to claim 1, wherein a minimum value is obtained when Vg is the data reference potential Vo, and the driving circuit controls the low potential Vws_L to a value lower than the minimum value. Each of a plurality of pixel circuits arranged in a matrix in the pixel array is connected between a light emitting element whose applied voltage value changes depending on the potential of one electrode, and a power source scanning line and one electrode of the light emitting element. A driving transistor; a sampling transistor connected between a control node of the driving transistor and a video signal line and controlled in accordance with a potential of the writing scanning line; a holding capacitor coupled to the control node; A driving method of a self-luminous display device including an electrode and an auxiliary capacitor connected between a power supply scanning line of another pixel circuit located on one side in the column direction,
The drive transistor gate potential Vg corresponds to the value Csub of the auxiliary capacitor, the equivalent capacitance Coled. Of the light emitting element, the high potential Vcc_H and the low potential Vcc_L of the power supply scanning line, and the potential of the video signal line. Depending on the possible range, the following formula:
Vws_L <Vg− (Vcc_H−Vcc_L) Csub / (Csub + Coled.)
A driving method of a self-luminous display device, wherein the sampling transistor is driven by a binary potential of the writing scanning line, in which a low potential Vws_L satisfying the above is defined as a lower potential.

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