JP2009168898A - Self light emitting type display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent potential fluctuation in one electrode of a light emitting element during data writing time, which is caused by potential change in a video signal line. <P>SOLUTION: A pixel circuit 3(i, j) includes: the light emitting element (an organic light emitting diode OLED) in which one electrode is connected to a power scan line DSL via a driving transistor Md, and the other electrode is connected at least between pixels in a row direction by a constant potential line (a cathode line CAL); an auxiliary capacitor connected between the cathode line CAL and the other electrode; a sampling transistor Ms which is connected between the video signal line DTL and a control node NDc of the driving transistor Md; and a holding capacitor Cs. At least part of the power scan line DSL is arranged and overlapped with the cathode line CAL in a plain pattern. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention includes a plurality of pixel circuits and a drive circuit, wherein a video signal line, a power supply scan line, and a write scan line are wired to the plurality of pixel circuits, and each pixel circuit includes a light emitting element, a drive transistor, and a sampling transistor. The present invention relates to a self-luminous display device including a holding capacitor and an auxiliary capacitor.

In recent years, development of self-luminous display devices using organic EL devices as light-emitting elements has become active. An organic EL device has an organic thin film, and utilizes a phenomenon that emits light when an electric field is applied to the organic thin film.
Since the organic EL device is driven with an applied voltage of 10 [V] or less, the power consumption is low. Since the organic EL device is a self-luminous element that emits light by itself, a display device including the organic EL device does not require an illumination unit and can be easily reduced in weight and thickness. Since the response speed of the organic EL device is as high as several [μs], the display device using the organic EL device does not generate an afterimage when displaying a moving image.

  Among self-luminous display devices that use organic EL devices as self-luminous elements, active matrix display devices in which thin film transistors are integrated and formed as driving elements in each pixel are particularly active.

  An active matrix display device having a self-luminous element, wherein an auxiliary capacitor (additional capacitor) is connected to one electrode (anode electrode) of the self-luminous element on the side into which a drive current corresponding to the data potential flows A display device is known (see, for example, Patent Document 1).

In FIG. 13, an equivalent circuit diagram of the basic configuration of the pixel circuit (FIG. 8 of Patent Document 1) is transcribed with a part of reference numerals changed.
The light emitting element is an organic light emitting diode OLED in this example, and in FIG. 13, the organic light emitting diode OLED is indicated by its equivalent capacitance Coled. In addition, the transistor connected between the supply line of the power supply voltage Vdd and the driving transistor (indicated by reference numeral Tr4) shown in FIG. 8 of Patent Document 1 is not necessary depending on the configuration of the pixel circuit. Omitted.

  Since the potential of the other electrode (cathode) of the organic light emitting diode OLED is fixed at the cathode potential Vcath, the voltage applied to the organic light emitting diode OLED is controlled by the potential (anode potential) Va of the one electrode (anode). A supply line of the power supply voltage Vdd can be connected to the anode of the organic light emitting diode OLED via the drive transistor Md. In the drive transistor Md, the magnitude of the drain current Ids is controlled according to the data potential Vsig input to its gate (control node), and thereby the source potential, that is, the anode potential Va of the organic light emitting diode OLED is determined.

A holding capacitor Cs is connected between the gate and source of the driving transistor Md for the purpose of holding the data potential Vsig. A sampling transistor Ms for sampling the data potential Vsig of the video signal is connected between the gate of the drive transistor Md and the video signal line DTL.
The sampling transistor is controlled according to the potential of a write scanning line (not shown) connected to the gate thereof, and is turned on when the write scanning line is activated, and is a video signal line connected to the drain. Are sampled, and the sampled potential is transmitted to the control node of the driving transistor connected to the source.
Here, the video signal has a waveform in which application of a constant reference potential (hereinafter referred to as a data reference potential Vo) and application of a data pulse DP having an arbitrary potential from the data reference potential Vo are repeated. The potential of the data pulse DP is the data potential Vsig, and the data voltage Vin that determines the display gradation corresponds to the peak value of the data pulse DP obtained by subtracting the data reference potential Vo from the data potential Vsig.
A holding capacitor Cs is connected between the gate and source of the driving transistor Md.

In the pixel circuit having such a configuration, the gate-source voltage Vgs of the driving transistor Md becomes the holding voltage of the holding capacitor Cs as it is. In other words, the holding voltage value of the holding capacitor Cs is determined by the magnitude of the potential “Vsig−Va” applied to the gate of the driving transistor with reference to the source potential of the driving transistor (the anode potential Va of the organic light emitting diode OLED). .
Since the drive transistor Md flows a drain current Ids corresponding to the gate-source voltage Vgs, it is necessary to accurately input and hold the data voltage Vin (the peak value of the data pulse DP) to the holding capacitor Cs.

  For this purpose, prior to the input of the data voltage Vin, the potential (anode potential Va) of the source of the drive transistor Md (one electrode of the light emitting element, anode in this example) is initialized by the data reference potential Vo of the video signal. . The data potential Vsig is input to the control node of the drive transistor Md by sampling the data potential Vsig by the sampling transistor Ms.

When the potential of the control node (gate) of the drive transistor Md rises due to the input of the data potential Vsig, the source potential (anode potential Va) of the drive transistor Md also rises from the data reference potential Vo. In order to hold the data voltage Vin in the holding capacitor Cs at 100 [%], it is necessary to make the fluctuation amount of the source potential (anode potential Va) of the driving transistor Md when the data potential Vsig is input almost zero.
However, the value of the current flowing through the drive transistor Md increases due to the input of the data potential Vsig, and the increase in the current value tends to easily increase the source potential (anode potential Va) of the drive transistor Md.

Therefore, in the pixel circuit described in Patent Document 1, an auxiliary capacitor Csub is connected in parallel with the organic light emitting diode OLED for the purpose of increasing the capacitance value connected to the source of the driving transistor.
The drain current Ids charges the combined capacitance of the capacitance Coled. Of the organic light emitting diode OLED, the auxiliary capacitor Csub, and the parasitic capacitance such as the drive transistor Md. If the drain current Ids is increased by the input of the data potential Vsig, and the auxiliary capacitor Csub is large to some extent at this time, the increased amount of the drain current Ids is consumed to charge the combined capacitance so that the anode potential Va hardly increases. Can be. In this case, the “write gain” defined by the ratio between the voltage actually held in the holding capacitor Cs and the desired data voltage Vin is close to “1”.

Thus, the auxiliary capacitor Csub has an effect of increasing the efficiency of data writing (write gain) when the data voltage Vin is written to the pixel circuit.
JP 2007-102046 A

Although not described in detail in Patent Document 1, the constant potential line that fixes the cathode potential of the organic light emitting diode OLED is arranged in the row direction orthogonal to the video signal line DTL. The constant potential line is likely to cause capacitive coupling at a portion intersecting with the video signal line DTL.
Therefore, at the moment when the data pulse DP rises on the video signal line DTL, the potential fluctuation may be superimposed on the constant potential line through the capacitive coupling at the intersection.

  When potential fluctuation occurs in the constant potential line, the potential fluctuation fluctuates the source potential (anode potential Va) of the driving transistor Md via the auxiliary capacitor Csub. The potential fluctuation that occurs in the constant potential line at the moment when the data pulse DP rises on the video signal line DTL, and the potential fluctuation transmitted to the source increases instantly and then decreases, and eventually disappears after the lapse of time defined by a certain time constant. To do.

Since it takes time for the potential fluctuations to converge and disappear, the sampling transistor Ms connected to the gate of the drive transistor Md is turned on with the potential fluctuation remaining, and sampling (writing) of the data potential Vsig is started. There is a case.
In this case, the operation of turning on the driving transistor Md according to the data potential Vsig is started from the source potential where the potential variation remains. For this reason, even when the same data potential Vsig is written, a difference occurs in the data potential after writing between the state where the potential variation remains in the source and the state where the potential variation does not. More specifically, since the data writing time is constant, the source potential at the end of data writing from the state where the potential variation remains in the source is the source potential at the end of data writing that is originally desired when there is no potential variation. Is different. Therefore, a writing error occurs in the data.
If there is a write error, the source potential rises to a level corresponding to the written data potential after the sampling transistor is turned off at the end of writing, and the light emission luminance of the organic light emitting diode OLED according to the level after this rise Is decided. As a result, a difference in light emission luminance between pixels occurs depending on whether there is a writing error.

  Note that data writing can be waited until the potential variation converges, but the magnitude of the potential variation and the time constant that defines the convergence time vary greatly depending on the load capacity of the wiring. For this reason, it is necessary to make the waiting time sufficiently long in order to eliminate the influence of the potential fluctuation in the entire screen. Therefore, if the potential fluctuation is not prevented or suppressed to some extent, a writing time is wasted, which makes timing design in display control of the display device difficult.

  The present invention prevents or suppresses potential fluctuation at the time of data writing in one electrode of a light emitting element caused by a change in potential of a video signal line, thereby enabling the light emitting element to emit light with a desired luminance. A device is provided.

A self-luminous display device according to one embodiment (first embodiment) of the present invention includes a plurality of pixel circuits arranged in a matrix, a write scan line and a power supply scan line respectively connecting pixel circuits in a row direction, Video signal lines connecting pixel circuits in the column direction.
In the pixel circuit, the other electrode is connected at least between the pixels in the row direction by a constant potential line, and the applied voltage value is changed by the potential of one electrode, and the pixel circuit is between the constant potential line and the one electrode. An auxiliary capacitor connected in parallel with the light emitting element, a drive transistor connected between the scan supply line and the one electrode, and a sampling connected between the video signal line and a control node of the drive transistor A transistor and a holding capacitor coupled to the control node.
In the first embodiment, the power supply scanning line is connected to the constant potential line in a layer between the constant potential line arranged along the row direction and the portion of the video signal line intersecting the constant potential line. At least a part of the planar pattern is arranged.

  In a self-luminous display device according to another aspect (second aspect) of the present invention, in addition to the first aspect, in the planar pattern, the power source scanning line is a constant potential line arranged in the row direction. The constant potential line is overlapped with a slightly larger width including the width of.

  The self-luminous display device according to another mode (third mode) of the present invention is the power source scanning line according to the first mode, wherein each gate of the driving transistor and the sampling transistor is formed from a first layer metal. Is formed from the second layer metal one layer above the first layer metal, and the constant potential line arranged along the row direction is formed from the third layer metal one layer above the second layer metal. The video signal line includes a bridge portion formed from the first layer metal at a position intersecting with a constant potential line, and 2 formed from the second layer metal on both sides in the length direction of the bridge portion. One main line portion and a plurality of contacts connecting the bridge portion to each of the two main line portions.

  The self-luminous display device according to another embodiment (fourth embodiment) of the present invention is the same as the first embodiment, except that the gates of the driving transistor and the sampling transistor and the constant potential arranged along the row direction. A line is formed from a first layer metal, the power supply scanning line is formed from a second layer metal one layer higher than the first layer metal, and the video signal line is crossed with a constant potential line. A bridge portion formed from a third layer metal one layer above the second layer metal; two main line portions formed from the second layer metal located on both sides in the length direction of the bridge portion; and the bridge portion And a plurality of contacts connecting each of the two main line portions.

In the self-luminous display devices of the first to fourth embodiments configured as described above, the constant potential lines are arranged even if all or part of them are along the row direction. When a part of the constant potential line is arranged along the row direction, the “constant potential line arranged along the row direction” refers to a portion of the constant potential line along the row direction.
The constant potential line arranged along the row direction intersects with the video signal line in the column direction. At this intersection, a power supply scanning line is arranged in a layer between the constant potential line and the video signal line. The power supply scanning line is at least partially overlapped with the constant potential line arranged in the row direction by a plane pattern.
A driving transistor is connected between the power supply scanning line and one electrode of the light emitting element, and a light emitting element and an auxiliary capacitor are connected in parallel between one electrode and the constant potential line.

In this configuration, when the potential of the video signal line changes, the potential of the power supply scanning line closer in the wiring stacking direction may fluctuate. However, the power supply scanning line is connected to one electrode of the light emitting element through the driving transistor, and the driving transistor has a bias state determined by the potential difference between the potential of one electrode of the light emitting element and the gate potential. Is difficult to be directly transmitted to one electrode of the light emitting element.
A constant potential line is arranged in a layer farther from the video signal line. For this reason, even if a certain amount of potential fluctuation occurs in the power supply scanning line, it is difficult to transmit the potential fluctuation to a farther layer. More specifically, the total load capacity of the power supply scanning line and the constant potential line is very large, and an interlayer insulating film is usually present between each layer. It is rare to be transmitted across. When the layers used are three layers as in the third and fourth embodiments, it is difficult to transmit the potential fluctuation across the two layers, but even if it is transmitted, the fluctuation level is extremely high. small.

Specifically, in the third embodiment, the power supply scanning line is formed from the second metal layer on one layer of the video signal line (the bridge portion formed from the first metal layer), and a constant potential is further formed on the one layer. A line is disposed from the third metal layer.
In the fourth mode, conversely, a constant potential line is formed from the first metal layer, and the power source scanning line and the main line portion of the video signal line are formed on the first layer from the second metal layer, and on the first layer. In addition, a bridge portion of the video signal line is formed from the third metal layer.

  In the third and fourth embodiments, at least the power supply scanning line, the video signal line, and the constant potential line are formed of three metal layers (first to third metal layers), and the first metal layer serves as the gate metal of the transistor. Since it is for forming, a wiring for performing control or inputting a video signal is formed substantially by a two-layer metal.

In the first embodiment, the power supply scanning line at least partially overlaps the constant potential line and the planar pattern. For this reason, the power source scanning line has an effect of shielding the portion of the constant potential line overlapping with the video signal line.
In the second mode, since the power source scanning lines overlap so as to include the entire width of the constant potential line, the shielding action is stronger than that in the first mode.

  In the first to fourth embodiments, the potential fluctuation of the constant potential line is prevented or suppressed as described above. For this reason, the potential fluctuation is prevented or suppressed also in the one electrode of the light emitting element connected to the constant potential line through the auxiliary capacitor so that the potential fluctuation can be transmitted. Since the auxiliary capacitor is provided to increase the capacitance value viewed from one electrode, the capacitance value of the auxiliary capacitor is relatively large, so even if potential fluctuation is transmitted to the constant potential line, the fluctuation is suppressed. Therefore, the potential fluctuation is not transmitted to the one electrode, or even if it is transmitted, the fluctuation is further attenuated.

  When the video signal line changes in potential at the time of data writing, it is usually when the potential of the data pulse having the data potential rises. In this case, the data potential is usually written immediately after the potential of the data pulse rises. However, even in such a case, at the time of writing the data potential, for example, the source node of the driving transistor connected to one electrode of the light emitting element is not subjected to potential fluctuation. Alternatively, it is moderate so as not to be substantially detrimental to potential fluctuations. Therefore, after data writing, the drive transistor, for example, the source node of the drive transistor rises from a predetermined level where there is (almost) no potential fluctuation to a desired potential corresponding to the input data, and the pixel emits light with a desired brightness.

  According to the present invention, it is possible to prevent or suppress potential fluctuation at the time of data writing in one electrode of a light emitting element caused by a change in the potential of the video signal line, thereby allowing the light emitting element to emit light with a desired luminance. It becomes.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings, using an organic EL display having a 2T · 1C type pixel circuit as a main example.

<Overall configuration>
FIG. 1 shows a main configuration of an organic EL display according to an embodiment of the present invention.
The illustrated organic EL display 1 includes a pixel array 2 in which a plurality of pixel circuits (PXLC) 3 (i, j) are arranged in a matrix, a vertical drive circuit (V scanner) 4 that drives the pixel array 2, and a horizontal And a drive circuit (H selector: HSEL) 5.
A plurality of V scanners 4 are provided depending on the configuration of the pixel circuit 3. Here, the V scanner 4 includes a horizontal pixel line drive circuit (DSCN) 41 and a write signal scanning circuit (WSCN) 42. The V scanner 4 and the H selector 5 are a part of the “drive circuit”. The “drive circuit” includes a circuit for supplying a clock signal to the V scanner 4 and the H selector 5, a control circuit (CPU, etc.), and the like. Also includes a circuit (not shown).

The code “3 (i, j)” of the pixel circuit shown in FIG. 1 indicates that the pixel circuit has an address i (i = 1, 2) in the vertical direction (vertical direction) and an address j ( j = 1,2,3). These addresses i and j take integers of 1 or more with the maximum values being “n” and “m”, respectively. Here, for simplification of the figure, a case where n = 2 and m = 3 is shown.
This address notation is similarly applied to the elements, signals, signal lines, voltages, and the like of the pixel circuit in the following description and drawings.

Pixel circuits 3 (1,1) and 3 (2,1) are connected to the video signal line DTL (1) in the vertical direction. Similarly, the pixel circuits 3 (1,2) and 3 (2,2) are connected to the video signal line DTL (2) in the vertical direction, and the pixel circuits 3 (1,3) and 3 (2,3) are vertical. Direction video signal line DTL (3). The video signal lines DTL (1) to DTL (3) are driven by the H selector 5.
The pixel circuits 3 (1,1), 3 (1,2) and 3 (1,3) in the first row are connected to the write scanning line WSL (1). Similarly, the pixel circuits 3 (2,1), 3 (2,2) and 3 (2,3) in the second row are connected to the write scanning line WSL (2). The write scanning lines WSL (1) and WSL (2) are driven by the horizontal pixel line driving circuit 41.
The pixel circuits 3 (1,1), 3 (1,2) and 3 (1,3) in the first row are connected to the power supply scanning line DSL (1). Similarly, the pixel circuits 3 (2,1), 3 (2,2) and 3 (2,3) in the second row are connected to the power supply scanning line DSL (2). The power supply scanning lines DSL (1) and DSL (2) are driven by the write signal scanning circuit.

Any one of the m video signal lines including the video signal lines DTL (1) to DTL (3) will be represented by the symbol “DTL (j) or DTL”. Similarly, any one of the n write scan lines including the write scan lines WSL (1) and WSL (2) is represented by the reference numeral “WSL (i) or WSL”, and the power scan line DSL (1 ), Any one of the n power supply scanning lines including DSL (2) is represented by a symbol “DSL (i) or DSL”.
For the video signal line DTL (j), line-sequential driving in which video signals are discharged all at once in units of display pixel rows (also referred to as display lines), or video is sequentially applied to video signal lines DTL (j) in the same row. Although there is dot sequential driving in which signals are discharged, any driving method may be used in this embodiment.

<Pixel circuit>
FIG. 2 shows a configuration example of the pixel circuit 3 (i, j).
The pixel circuit 3 (i, j) illustrated is a circuit that controls the organic light emitting diode OLED. In addition to the organic light emitting diode OLED, the pixel circuit includes a drive transistor Md and a sampling transistor Ms made of an NMOS type TFT, a holding capacitor Cs, and an auxiliary capacitor Csub.

  Although the organic light emitting diode OLED is not particularly shown, for example, in the case of a top emission type, an anode electrode is first formed on a TFT structure formed on a substrate made of transparent glass or the like, and a hole transport layer, A light emitting layer, an electron transport layer, an electron injection layer, and the like are sequentially deposited to form a laminate that forms an organic multilayer film, and a cathode electrode made of a transparent electrode material is formed on the laminate. The anode electrode is connected to the positive power source, and the cathode electrode is connected to the negative power source.

  When a bias voltage for obtaining a predetermined electric field is applied between the anode and cathode electrodes of the organic light emitting diode OLED, the organic multilayer film emits light when the injected electrons and holes recombine in the light emitting layer. The organic light emitting diode OLED can emit light in each color of red (R), green (G), and blue (B) by appropriately selecting the organic material constituting the organic multilayer film. For example, color display is possible by arranging the light emission of R, G, B in the pixels of each row. Alternatively, R, G, and B may be distinguished by the color of the filter using an organic material that emits white light. A four-color configuration in which W (white) is added in addition to R, G, and B may be used.

The drive transistor Md functions as current control means for controlling the amount of current flowing through the organic light emitting diode OLED to define display gradation.
The drain of the driving transistor Md is connected to the power supply scanning line DSL (i) that controls the supply of the power supply voltage VDD, and the source is connected to the anode of the organic light emitting diode OLED. The anode electrode of the organic light emitting diode OLED corresponds to “one electrode”.

  The sampling transistor Ms is connected between the supply line (video signal line DTL (j)) of the data potential Vsig that determines the pixel gradation and the gate (control node NDc) of the drive transistor Md. One of the source and drain of the sampling transistor Ms is connected to the gate (control node NDc) of the drive transistor Md, and the other is connected to the video signal line DTL (j). A data pulse having a data potential Vsig is supplied to the video signal line DTL (j) from the H selector 5 (see FIG. 1) at a predetermined interval. The sampling transistor Ms samples data at a level to be displayed by the pixel circuit at an appropriate timing in a data potential supply period (data pulse duration time). This is to eliminate the influence on the display image in the transition period where the level is unstable at the front or rear of the data pulse having the desired data potential Vsig to be sampled.

A holding capacitor Cs is connected between the gate (control node) and source (one electrode forming the anode of the organic light emitting diode OLED) of the drive transistor Md.
A cathode line CAL as a “constant potential line” is connected to the other electrode forming the cathode of the organic light emitting diode OLED. An auxiliary capacitor Csub is connected between one electrode (anode) and the other electrode (cathode line CAL) of the organic light emitting diode OLED.
The roles of the holding capacitor Cs and the auxiliary capacitor Csub will be clarified in the description of operation described later.

In FIG. 2, the horizontal pixel line drive circuit 41 supplies a power supply drive pulse DS (i) in which the peak value of the high potential Vcc_H with respect to the low potential Vcc_L becomes the power supply voltage VDD to the drain of the drive transistor Md. Power is supplied when correcting Md or when the organic light emitting diode OLED actually emits light.
Further, the write signal scanning circuit 42 supplies a write drive pulse WS (i) having a relatively short duration to the gate of the sampling transistor Ms to perform sampling control.
The power supply control may be configured such that another transistor is inserted between the drain of the drive transistor Md and the supply line of the power supply voltage VDD, and the gate is controlled by the horizontal pixel line drive circuit 41. (Refer to a modification described later).

  In FIG. 2, one electrode (anode) of the organic light emitting diode OLED is supplied with the power supply voltage VDD from the positive power supply via the drive transistor Md. The other electrode (cathode) of the organic light emitting diode OLED is supplied with a negative cathode potential Vcath from the negative power source via the cathode line CAL.

  Usually, all transistors in the pixel circuit are formed of TFTs. The thin film semiconductor layer in which the TFT channel is formed is made of a semiconductor material such as polycrystalline silicon (polysilicon) or amorphous silicon (amorphous silicon). Polysilicon TFTs can have high mobility, but their characteristic variation is large, so they are not suitable for increasing the screen size of a display device. Therefore, in a display device having a large screen, an amorphous silicon TFT is generally used. However, since it is difficult to form a P-channel TFT in an amorphous silicon TFT, it is desirable that all TFTs be an N-channel type like the pixel circuit 3 (i, j) described above.

Here, the pixel circuit 3 (i, j) described above is an example of a pixel circuit applicable in the present embodiment, that is, a basic configuration example of a two-transistor (2T) / 1-capacitor (1C) type. Therefore, the pixel circuit that can be used in the present embodiment may be a pixel circuit having the pixel circuit 3 (i, j) as a basic configuration and further added with a transistor and a capacitor (refer to a modification described later). In some basic configurations, the holding capacitor Cs is connected between the supply line of the power supply voltage VDD and the gate of the drive transistor Md.
Specifically, some pixel circuits other than the 2T • 1C type that can be employed in the present embodiment will be briefly described in modification examples described later. For example, 4T • 1C type, 4T • 2C type, 5T • 1C type It may be a 3T / 1C type.

In the pixel circuit based on the configuration of FIG. 2, when the organic light emitting diode OLED is reverse-biased at the time of threshold voltage correction or mobility correction, the equivalent capacitance value at the time of reverse biasing of the organic light-emitting diode OLED is maintained, as will be described in detail later. Since it can be made sufficiently larger than the value of the capacitor Cs, the anode of the organic light emitting diode OLED becomes difficult to move in terms of potential, so that the correction accuracy is improved. For this reason, it is desirable to perform correction in a reverse bias state.
The reason why the cathode is connected to the cathode line CAL without grounding the cathode potential Vcath is to perform reverse bias. In order to reverse bias the organic light emitting diode OLED, for example, the cathode potential Vcath is made smaller than the reference potential (low potential Vcc_L) of the power supply driving pulse DS (i). In this example, it is assumed that the cathode potential Vcath is a negative potential.

  At the time of writing data, the capacitance value seen from the anode of the organic light emitting diode OLED may be increased in order to make the anode potential of the organic light emitting diode OLED harder to move and to fix the potential. For this purpose, an auxiliary capacitor Csub is connected to the anode of the organic light emitting diode OLED.

<Display control>
The operation at the time of data writing in the circuit of FIG. 2 will be described together with the threshold voltage and mobility correction operation. A series of these operations is called “display control”.
First, the characteristics of the drive transistor to be corrected and the organic light emitting diode OLED will be described.

A holding capacitor Cs is coupled to the control node NDc of the drive transistor Md shown in FIG. The data potential Vsig, which is the effective potential of the data pulse transmitted through the video signal line DTL (j), is sampled by the sampling transistor Ms, and the potential thus obtained is applied to the control node NDc and held by the holding capacitor Cs. When a predetermined potential is applied to the gate of the drive transistor Md, the drain current Ids is determined according to the gate-source voltage Vgs having a value corresponding to the applied potential.
Here, it is assumed that sampling is performed after the source potential Vs of the drive transistor Md is initialized to the reference potential (data reference potential Vo) of the data pulse. The data potential Vsig after sampling, more precisely, the drain current Ids corresponding to the magnitude of the data voltage Vin defined by the potential difference between the data reference potential Vo and the data potential Vsig flows to the drive transistor Md, which is almost organic. It becomes the drive current Id of the light emitting diode OLED.
Therefore, when the source potential Vs of the driving transistor Md is initialized with the data reference potential Vo, the organic light emitting diode OLED emits light with a luminance corresponding to the data potential Vsig.

FIG. 3 shows a graph of the IV characteristic of the organic light emitting diode OLED and a general formula of the drain current Ids of the drive transistor Md (which is substantially equivalent to the drive current Id of the OLED).
As is well known, the organic light emitting diode OLED changes its IV characteristic as shown in FIG. At this time, in the pixel circuit of FIG. 2, even if the drive transistor Md tries to pass a constant drain current Ids, the applied voltage of the organic light emitting diode OLED increases as can be seen from the graph shown in FIG. Source potential Vs rises. At this time, since the gate of the driving transistor Md is in a floating state, the gate potential rises together with the source potential so that the substantially constant gate-source voltage Vgs is maintained, and the drain current Ids is kept substantially constant. Acts so as not to change the light emission luminance of the organic light emitting diode OLED.

  However, since the threshold voltage Vth and the mobility μ of the driving transistor Md are different for each pixel circuit, the drain current Ids varies according to the equation of FIG. 3, and the data potential Vsig given in the display screen. Even if the two pixels are the same, the light emission luminance differs between the two pixels.

  In the equation of FIG. 3, the symbol “Ids” represents a current flowing between the drain and the source of the drive transistor Md operating in the saturation region. In the drive transistor Md, “Vth” is the threshold voltage, “μ” is the mobility, “W” is the effective channel width (effective gate width), and “L” is the effective channel length (effective gate length). Respectively. “Cox” represents the sum of the unit gate capacitance of the drive transistor Md, that is, the gate oxide film capacitance per unit area, and the fringing capacitance between the source, drain, and gate.

  The pixel circuit having the N-channel type driving transistor Md has an advantage of high driving capability and simplification of the manufacturing process. However, in order to suppress variations in the threshold voltage Vth and the mobility μ, these correction operations can emit light. Must be done prior to bias setting.

Next, the control will be described with reference to FIG. 4. FIG. 4 shows the control before the present invention is applied.
Hereinafter, the period in FIG. 4 is defined, and the entire control will be described in detail along the time axis of FIG.

  4A to 4F are timing charts showing waveforms of various signals and voltages in display control. In this display control, data writing is sequentially performed in units of rows. The pixel circuit 3 (1, j) in the first row is a row to be written (display row), and the pixel circuit 3 (2 in the second row). , j) and the pixel circuit 3 (3, j) in the third row are not write targets (non-display rows) at the time of FIG. For the display line, after data is written by the display control shown in FIG. 4 and described below, the display line moves to the second line and the same display control is performed, and the same display control is performed for the third and second lines. One screen is displayed by repeating four lines,... After the display of one screen, display control for displaying other screens is repeated as many times as necessary.

FIG. 4A is a waveform diagram of the video signal Ssig.
FIGS. 4B1 and 4B2 are waveform diagrams of the write drive pulse WS (1) and the power supply drive pulse DS (1) supplied to the first row to be written. Similarly, FIGS. 4C1 and 4C2 are waveform diagrams and diagrams of the write drive pulse WS (2) and the power supply drive pulse DS (2) supplied to the second row to be non-written. 4 (D1) and FIG. 4 (D2) are waveform diagrams of the write drive pulse WS (3) and the power supply drive pulse DS (3) supplied to the third row to be non-written.
FIG. 4E is a waveform diagram of the gate potential (potential of the control node NDc) of the drive transistor Md in the pixel circuit 3 (1, j) in the first row to be written.
FIG. 4F is a waveform diagram of the source potential of the drive transistor Md (the anode potential of the organic light emitting diode OLED) in the pixel circuit 3 (1, j) in the first row to be written.

[Definition of period]
As shown in the lower part of FIG. 4F, FIG. 4 displays a waveform diagram with a span slightly more than four times as long as one horizontal period (1H) of the NTSC video signal standard. Then, in the final one horizontal period (1H), the final third threshold correction (VTC3), the mobility correction, and the actual data writing (W & μ) are continuously executed (this operation). ). The last three horizontal periods ((1H) × 3) prior to the main operation performed in the last one horizontal period (1H) are completely corrected for initialization and for the final threshold correction. Considering the case where there is not, it is expended to perform threshold correction twice in advance to some extent (preliminary operation).
In the display control as shown in FIG. 4, the resolution of the display image is increasing and the drive frequency of the display panel is very high. At present, from the threshold voltage correction to the data writing in one short horizontal period (1H). In view of the shortage of threshold correction time, the threshold correction is performed in several steps. However, for a small to medium-sized display panel or the like whose driving frequency is not so high, if the time of this operation is sufficient for one horizontal period (1H), if there is one horizontal period (1H) for initialization, the preliminary operation is It may be enough. Of course, the preliminary operation may be two horizontal periods (2H), or four horizontal periods (4H) or more.
When this operation is performed for a certain row, the preliminary operation can be executed in parallel for the next row (and the subsequent rows, etc.). Almost no effect. Rather, it is desirable that the preliminary operation is sufficiently performed in order to surely correct the threshold voltage.

The above is the division of the period viewed on a fixed scale of one horizontal period (1H), but it is also possible to functionally grasp the roughly four horizontal periods described in FIG.
Specifically, as described in the upper part of FIG. 4A, the discharge period (D-CHG) in the chronological order after the light emission period (LM0) of the previous screen (one field or one frame), the initial period The “preliminary operation” is executed through the conversion period (INT), the first threshold correction period (VTC1), the first standby period (WAT1), the second threshold correction period (VTC2), and the second standby period (WAT2). Subsequently, after the third threshold value correction (VTC3), the third standby period (WAT3), the writing & mobility correction period (W & μ), the light emission period of the pixel circuit 3 (1, j) in the first row ( The “main operation” is executed by transitioning to LM1).

[Outline of drive pulse]
Further, in FIG. 4, time display is indicated by symbols “T0” to “T21” at appropriate portions of the waveform diagram. Next, an outline of the video signal and the drive pulse will be described with reference to this time display.
In the write drive pulse WS (1) supplied to the first row, as shown in FIG. 4B1, four sampling pulses (SP0 to SP3) which are inactive at the “L” level and active at the “H” level. ) Appear periodically. At this time, the cycle of the four sampling pulses (SP0 to SP3) is constant throughout the preliminary operation (time T0 to time T15) and the main operation (after time T15). However, the write drive pulse WS (1) in this operation has a waveform in which the write pulse (WP) is superimposed after the fourth sampling pulse (SP3).

On the other hand, the video signal Ssig supplied to m (several hundred to several hundreds) video signal lines DTL (j) (see FIGS. 1 and 2) is m video signal lines in line sequential display. DTL (j) is supplied simultaneously. The signal amplitude (Vin) reflecting the data voltage obtained after sampling the video signal Ssig is the data reference potential Vo that repeatedly appears in the first half of one horizontal period (1H) as shown in FIG. This corresponds to the peak value of the video signal pulse (PP) that repeatedly appears in the latter half of one horizontal period (1H) as a reference. Hereinafter, the signal amplitude (Vin) is referred to as a data voltage Vin.
Of the several video signal pulses (PP) shown in FIG. 4A, the video signal pulse important for the first row is the video signal pulse (PPx) in the main operation that overlaps the write pulse (WP) in time. It is. The peak value from the data reference potential Vo of the video signal pulse (PPx) during this operation corresponds to the gradation value to be displayed (written) in FIG. 4, that is, the magnitude of the data voltage Vin. This gradation value (= Vin) may be the same for each pixel in the first row (in the case of monochromatic display), but usually changes according to the gradation value of the display pixel row. FIG. 4 is mainly for explaining the operation of one pixel in the first row, but the control itself is different except that this display gradation value may be different in other pixels in the same row. This is executed in parallel with the pixel drive control shown.

  The power supply driving pulse DS (1) supplied to the drain (see FIG. 2) of the driving transistor Md is the start (time) of the first first threshold correction period (VTC1) from time T0, as shown in FIG. 4 (B2). T6) It is held at the inactive low potential Vcc_L until immediately before, and transitions to the active high potential Vcc_H almost simultaneously with the start of the first threshold correction period (VTC1) (time T6). The holding of the high potential Vcc_H continues until the light emission period (LM1) ends.

The second row (pixel circuit 3 (2, j)) and the third row (pixel circuit 3 (3, j)) are shown in FIGS. 4C1, 4C2, and 4D1, respectively. ) And FIG. 4D2, each pulse is applied with a delay of one horizontal period (1H).
Specifically, in the period of time T5 to T7 in which the second sampling pulse (SP1) corresponding to the first threshold correction period (VTC1) of the first row is applied, the initialization period ( A first sampling pulse (SP0) corresponding to (INT) is applied.
During this pulse application, that is, at time T6, the power supply driving pulse DS (1) in the first row rises to a high level (power supply potential Vcc_H) and becomes active.

Thereafter, in the period of time T10 to T12 in which the third sampling pulse (SP2) corresponding to the second threshold correction period (VTC2) of the first row is applied, in the second row, from the first row to one horizontal period The second sampling pulse (SP1) is applied with a delay of (1H). In the third row, the first sampling pulse (SP0) is delayed by two horizontal periods ((1H) × 2) from the first row. Is applied.
During this pulse application, that is, at time T11, the power supply driving pulse DS (2) in the second row rises to the high potential Vcc_H and becomes active.

Thereafter, in the period of time T15 to T17 in which the fourth sampling pulse (SP3) corresponding to the third threshold correction period (VTC3) of the first row is applied, in the second row, from the first row to one horizontal period The third sampling pulse (SP2) is applied with a delay of (1H), and in the third row, the second sampling pulse (SP1) is delayed by two horizontal periods ((1H) × 2) from the first row. Is applied.
During this pulse application, that is, at time T16, the power supply driving pulse DS (3) in the third row rises to the high potential Vcc_H and becomes active.

When the pulse application timing design is performed as described above, the preliminary operation for several other rows in which the main operation is performed in parallel after one to several horizontal periods is performed in parallel during the period in which the main operation is performed in a certain row. For this reason, when it is limited to this operation, it is executed seamlessly in units of lines. Therefore, no useless period occurs other than the first few horizontal periods.
Since the display screen usually has hundreds to thousands of rows, the time of one to several horizontal periods during one-screen display is so short that it can be ignored. Therefore, even if the threshold voltage correction is divided into several times, there is substantially no time loss.

Next, a change in the potential of the source and gate of the driving transistor Md shown in FIGS. 4E and 4F and the accompanying operation under the above pulse control for each period shown in FIG. 4A. Explained.
Here, the preliminary operation explanatory diagram of the pixel circuit 3 (1, j) in the first row shown in FIGS. 5A to 7B, the time transition graph of the source potential Vs shown in FIG. The operation explanatory diagram of the pixel circuit 3 (1, j) in the first row shown in FIGS. 9A to 9C and FIG.

[Light emission period of previous screen (LM0)]
For the pixel circuit 3 (1, j) in the first row, the light emission period (LM0) for the screen one field or one frame before the time T0 (hereinafter referred to as the previous screen) is shown in FIG. 4B1. Thus, since the write drive pulse WS (1) is at the “L” level, the sampling transistor Ms is turned off. In addition, as shown in FIG. 4B2, the power supply driving pulse DS (1) is in the application state of the high potential Vcc_H.

  At this time, as shown in FIG. 5A, it is assumed that the organic light emitting diode OLED is in a light emitting state in accordance with the data voltage Vin0 input and held in the gate of the driving transistor Md by the data writing operation of the previous screen. . Since the driving transistor Md is set to operate in the saturation region, the driving current Id (= Ids) flowing through the organic light emitting diode OLED is equal to the gate-source voltage Vgs of the driving transistor Md held in the holding capacitor Cs. Accordingly, the value calculated from the above-described equation shown in FIG. 3 is taken.

[Discharge period (D-CHG)]
In FIG. 4, processing related to a new screen display of line sequential scanning is started from time T0.
At time T0, the horizontal pixel line drive circuit 41 (see FIG. 2) switches the power supply drive pulse DS (1) from the high potential Vcc_H to the low potential Vcc_L as shown in FIG. 4 (B2). In the driving transistor Md, since the potential of the node that has been functioning as the drain is suddenly dropped to the low potential Vcc_L and the potential of the source and the drain is reversed, the node that has been the drain until now is used as the source. A discharge operation is performed in which the node that was the source is the drain, and the potential of the drain (however, the source potential Vs remains in the notation in the drawing) is extracted.
Therefore, as shown in FIG. 5B, a drain current Ids in the opposite direction to that of the current flows in the driving transistor Md. A period during which a reverse current flows through the driving transistor Md is referred to as a “discharge period (D-CHG)” in FIGS. 4 and 5B.

When the discharge period (D-CHG) is started, as shown in FIG. 4F, the source potential Vs (the drain potential in actual operation) of the drive transistor Md is suddenly discharged at the time T0, as shown in FIG. The voltage drops to near the low potential Vcc_L.
At this time, when the low potential Vcc_L is smaller than the sum of the light emission threshold voltage Vth_oled. And the cathode potential Vcath of the organic light emitting diode OLED, that is, “Vcc_L <Vth_oled. + Vcath”, the organic light emitting diode OLED is extinguished.
Note that before the end of the discharge period (D-CHG) (time T1), as shown in FIG. 4A, the potential of the video signal Ssig is lowered from the data potential Vsig to the data reference potential Vo. ing.

  At time T0, as shown in FIG. 5B, the sampling transistor Ms is turned off and the control node NDc is in a floating state. For this reason, as shown in FIG. 4E, the gate voltage Vg of the drive transistor Md decreases at time T0.

[Initialization period (INT)]
Next, the write signal scanning circuit 42 (see FIG. 2) causes the write drive pulse WS (1) to transition from the “L” level to the “H” level at time T1, as shown in FIG. 4 (B1). The first sampling pulse (SP0) is applied to the gate of the sampling transistor Ms.
At this time T1, the discharge period (D-CHG) ends, and from here the initialization period (INT) starts.

In response to the application of the sampling pulse (SP0) at time T1, the sampling transistor Ms is turned on as shown in FIG. As described above, by the time T1, the potential of the video signal Ssig is switched to the data reference potential Vo. Therefore, the sampling transistor Ms samples the data reference potential Vo of the video signal Ssig, and transmits the sampled data reference potential Vo to the gate of the drive transistor Md.
As a result of this sampling operation, as shown in FIG. 4E, the gate voltage Vg of the drive transistor Md that has decreased at the time T0 is converged to the data reference potential Vo.

The sampling pulse (SP0) shown in FIG. 4B1 ends at time T2 when a sufficient time for potential convergence has elapsed from time T1, and the sampling transistor Ms is turned off. Therefore, until the time T5 when the sampling transistor Ms is turned on next time, the gate of the drive transistor Md is in an electrically floating state.
The timing at which the sampling transistor Ms is turned on again at the time T5 is controlled to be substantially the same as the end of the first horizontal period (1H), and within the period of the time T2 to T5, the one horizontal period (1H). The timing is designed so that the video signal pulse (PP) is accommodated (see FIGS. 4A and 4B1).

Looking at this from the sampling pulse (SP0), the duration (time T1 to T2) of the sampling pulse (SP0) for setting the write drive pulse WS (1) to the “H” level is one horizontal period (1H). The first half of the video signal Ssig is within a period (time T0 to T3) in which the data reference potential Vo is taken.
Then, in a state where the sampling transistor Ms is turned off at time T2, the time T4 when the potential fluctuation of the video signal line DTL (j) by the video signal pulse (PP) ends is waited for, and at time T5 thereafter, the data reference A second sampling pulse (SP1) for sampling the potential Vo again is started.
As a result of this control, erroneous sampling of the data potential Vsig of the video signal Ssig at the time T5 when the second sampling pulse (SP1) is raised is avoided.
Note that at the start of the second sampling at time T5, as shown in FIG. 4E, the gate voltage Vg already holds the data reference potential Vo. Therefore, in general, the gate voltage Vg hardly fluctuates even though the second sampling may compensate for a minute loss due to a leak current or the like.

Returning the description on the time axis slightly, the sampling transistor Ms is turned on by applying the first sampling pulse (SP0) at time T1, and as shown in FIG. When the gate voltage Vg of Md converges to the data reference potential Vo, the holding voltage of the holding capacitor Cs decreases in conjunction with this, and becomes “Vo−Vcc_L” (FIG. 4F). This is because the source potential Vs becomes the low potential Vcc_L by the discharge of FIG. 5B, and the holding voltage of the holding capacitor Cs is defined by the gate voltage Vg based on the low potential Vcc_L. That is, in FIG. 5C, when the gate voltage Vg drops to the data reference potential Vo, the holding voltage of the holding capacitor Cs decreases in conjunction with this, and the holding voltage converges to “Vo−Vcc_L”. This holding voltage “Vo−Vcc_L” is the gate-source voltage Vgs itself. If the gate-source voltage Vgs is not larger than the threshold voltage Vth of the drive transistor Md, the threshold correction operation cannot be performed thereafter. Further, the potential relationship is determined so as to satisfy “Vo−Vcc_L> Vth”.
In this way, by preparing the gate voltage Vg and the source potential Vs of the drive transistor Md, preparation for the threshold correction operation is completed.

[First threshold correction period (VTC1)]
After the sampling transistor Ms starts Vo sampling for the second time at time T5, as shown in FIG. 4B2, when the power supply driving pulse DS (1) rises from the low potential Vcc_L to the high potential Vcc_H at time T6, The initialization period (INT) ends, and the first threshold value correction period (VTC1) starts.

Immediately before the start (time T6) of the first threshold correction period (VTC1), since the sampling transistor Ms in the on state is sampling the data reference potential Vo, the gate voltage Vg of the drive transistor Md is a constant data reference. It is in an electrically fixed state at the potential Vo.
In this state, at time T6, the horizontal pixel line drive circuit 41 (see FIG. 2) raises the power supply drive pulse DS (1) from the low potential Vcc_L to the high potential Vcc_H as shown in FIG. 4 (B2). The horizontal pixel line drive circuit 41 holds the potential of the power supply line to the drive transistor Md at the high potential Vcc_H until the start of the processing of the next frame (or field) after the time T6.

The power supply voltage VDD of “Vcc_H−Vcc_L” is applied between the source and drain of the drive transistor Md by the rise of the power supply drive pulse DS (1). Therefore, the drain current Ids flows from the power supply to the driving transistor Md.
The source of the driving transistor Md is charged by the drain current Ids, and the source potential Vs rises as shown in FIG. 4F. Therefore, between the gate and source of the driving transistor Md that has previously taken the value “Vo−Vcc_L”. The voltage Vgs (holding voltage of the holding capacitor Cs) gradually decreases (FIGS. 4E and 4F).

At this time, the source charging speed of the driving transistor Md by the drain current Ids is not so large. The reason will be described with reference to FIG.
As shown in FIG. 6A, since the gate bias voltage applied to the gate voltage Vg of the driving transistor Md is defined by the data reference potential Vo and the bias voltage is not so large, the driving transistor Md is in a shallow ON state. That is, it is turned on in a state where the driving capability is not so large (first reason).
Further, the drain current Ids flows into the holding capacitor Cs. However, since the drain current Ids is also consumed for charging the capacitance Coled. Of the organic light emitting diode OLED, the source potential Vs is hardly increased (second reason).
Furthermore, since the sampling pulse (SP1) needs to be terminated at time T7 before time T8 when the video signal Ssig next transitions to the data potential Vsig (see FIG. 4B1), the charging time of the source potential Vs is required. Is insufficient (third reason).

  If the second sampling pulse (SP1) shown in FIG. 4 (B1) can be sustained for a sufficiently long time exceeding the time T7, the source potential Vs of the driving transistor Md (the anode potential of the organic light emitting diode OLED). As shown in FIG. 8, it rises with time starting from time T6 and converges at “Vo−Vth” (curve CV indicated by the broken line in FIG. 8). That is, when the gate-source voltage Vgs (holding voltage of the holding capacitor Cs) has just reached the threshold voltage Vth of the driving transistor Md, the increase of the source potential Vs should almost end.

[First waiting period (WAT1)]
However, in reality, since the time T7 comes before the convergence point is reached, the duration of the sampling pulse (SP1) ends, whereby the first threshold correction period (VTC1) ends and the first waiting period (WAT1) starts.
Specifically, when the gate-source voltage Vgs of the drive transistor Md becomes Vx1 (> Vth), that is, as shown in FIG. 8, the source potential Vs of the drive transistor Md is changed from the low potential Vcc_L to “Vo−Vx1”. The first threshold value correction period (VTC1) ends at the time point when it rises to "" (time T7). At this time (time T7), the voltage value Vx1 is held in the holding capacitor Cs.

When the first threshold value correction period (VTC1) ends, the sampling transistor Ms is turned off, so that the state in which the gate of the drive transistor Md is electrically fixed at the data reference potential Vo changes to an electrically floating state.
Therefore, after the time T7, when the source potential Vs increases, the potential (Vg) of the floating gate capacitively coupled to the source also increases (FIGS. 4E and 4F). As a result, in this example, at the end point (time T10) of the first waiting period (WAT1), the source potential Vs becomes larger than the convergence target “Vo−Vth” (see FIG. 8), while FIG. As shown in E) and (F), the gate-source voltage Vgs does not shrink.

The first standby period (WAT1) needs to wait for the passage of the video signal pulse (PP) as in the case of the initialization period (INT) described above, and is referred to as a “standby period” in that sense. However, a relatively long standby period such as time T7 to T10 allows the gate voltage Vg to rise, and the convergence of the gate-source voltage Vgs to the threshold voltage Vth does not proceed as described above.
In FIG. 4E, the increase in the gate voltage Vg during the first standby period (WAT1) is represented by “Va1”. If the increase in the source potential Vs that causes the increase in the gate voltage Vg through the coupling capacitor (holding capacitor Cs) by the bootstrap operation is also the same as “Va1”, the source potential Vs is the first standby. It becomes “Vo−Vx1 + Va1” at the end time (time T10) of the period (WAT1) (see FIG. 8B).
Therefore, it is necessary to return the gate potential to the data reference potential Vo, which is the initialization level, and perform threshold voltage correction again.

[Second threshold correction period (VTC2)]
Therefore, in the operation example of the present embodiment, in the next one horizontal period (1H) (time T10 to T15), the first threshold correction period (VTC1) performed in the previous one horizontal period (1H) (time T5 to T10). And a process similar to the first standby period (WAT1), that is, the second threshold correction period (VTC2) and the second standby period (WAT2).
However, at the time T5 when the first threshold value correction period (VTC1) is started, the gate-source voltage Vgs (holding voltage of the holding capacitor Cs) was relatively large as “Vo−Vcc_L”, whereas At time T10 when the two-threshold correction period (VTC2) is started, the holding voltage is reduced to a smaller “Vx1”.

As shown in FIG. 4B1, when the sampling pulse (SP2) rises at time T10 and the sampling transistor Ms is turned on, the gate voltage Vg (= “Vo + Va1”) of the driving transistor Md is lower (data reference potential Vo). Video signal line DTL (j). Therefore, a current corresponding to the difference (Va1) flows from the gate of the drive transistor Md to the video signal line DTL (j), and the gate voltage Vg is forced to the data reference potential Vo as shown in FIG. Is lowered.
The fluctuation of the potential (Va1) at the gate of the driving transistor Md is input to the source of the driving transistor Md via the holding capacitor Cs and the gate-source parasitic capacitance Cgs of the driving transistor Md, and the source potential Vs is pulled down. .
The pull-down amount of the source potential Vs at this time is expressed as “g * Va1” using the capacitive coupling ratio g. Here, the capacitance coupling ratio g is the gate-source parasitic capacitance Cgs, the capacitance value (Cs) having the same sign as the holding capacitor Cs, the capacitance value (Csub) having the same sign as the auxiliary capacitor Csub, and the capacitance of the organic light emitting diode OLED. Using Coled., G = (Cgs + Cs) / (Cgs + Cs + Coled. + Csub). Therefore, the source potential Vs decreases by “g * Va1” from “Vo−Vx1 + Va1” immediately before and becomes “Vo−Vx1 + (1−g) Va1”.
Since the capacitive coupling ratio g takes a value smaller than 1 as is apparent from the definition formula, the change amount “g * Va1” of the source potential Vs is smaller than the change amount (Va1) of the gate voltage Vg.

  If the gate-source voltage Vgs (= “Vx1− (1−g) Va1”) of the drive transistor is larger than the threshold voltage Vth of the drive transistor Md, the drain current Ids is as shown in FIG. Flowing. The drain current Ids tends to flow until the source potential Vs of the drive transistor Md becomes “Vo−Vth” and the drive transistor Md is cut off. However, in the operation example of this embodiment, as shown in FIGS. 4E and 4F, the gate-source voltage Vgs is “Vx2” (however, Vx2 has a size satisfying Vx1> Vx2> Vth). Since the sampling pulse (SP2) ends at the time T12 when the sampling transistor Ms has, the sampling transistor Ms is turned off. The holding voltage of the holding capacitor Cs at time T12 is “Vx2”.

[Second waiting period (WAT2)]
The second waiting period (WAT2) starts from time T12.
In the second standby period (WAT2), as in the previous first standby period (WAT1), the sampling transistor Ms is turned off and the gate voltage Vg is in an electrically floating state. Therefore, in response to the increase in the source potential Vs. The gate voltage Vg also increases (see FIG. 7A).
However, the potential increase effect (bootstrap effect) of the gate voltage Vg is not so large because the gate-source voltage Vgs at the start time is close to the control target “Vth”, which is shown in FIG. 4 (E) and FIG. 4 (F). As can be seen from time T12 to T15, the potential increases of the source potential Vs and the gate voltage Vg are slight.

  More specifically, in the second standby period (WAT2) in FIG. 7A, if the increase in the source potential Vs due to the drain current Ids flowing is “Va2”, the standby period ends (time T15 in FIG. 4). ) Becomes “Vo−Vx2 + Va2”. The increase in the source potential by “Va2” is transmitted to the floating gate via the gate-source parasitic capacitance Cgs and the holding capacitor Cs, and as a result, the gate voltage Vg also increases by substantially the same potential “Va2”. To do. However, the potential increase “Va2” of the gate voltage Vg is much smaller than the potential increase “Va1” in the first standby period (WAT1), as shown in FIG.

[Third threshold correction (VTC3)]
The “main operation” is entered from time T15, and the third threshold value correction (VTC3) starts.
In the third threshold correction (VTC3) (time T15 to T17), processing similar to that in the second threshold correction period (VTC2) is executed.
However, at the time T10 when the second threshold correction period (VTC2) is started, the gate-source voltage Vgs (the holding voltage of the holding capacitor Cs) was relatively large as “Vx1”, whereas the third threshold value At time T15 when the correction period (VTC3) is started, the time period is further reduced to “Vx2”.
Since the basic operation is the repetition of [second threshold correction period (VTC2)], it is omitted. The description of [second threshold correction period (VTC2)] can be applied to the third threshold correction (VTC3) by replacing “Va1” with “Va2” and “Vx1” with “Vx2”. This is also apparent from the comparison between FIG. 6C and FIG.

  However, the difference from the second threshold correction period (VTC2) is that, as shown in FIGS. 4E and 4F, by time T17 when the third threshold correction (VTC3) ends, the drive transistor Md The gate-source voltage Vgs (holding voltage of the holding capacitor Cs) is equal to the threshold voltage Vth. Therefore, the drive transistor Md is cut off when the gate-source voltage Vgs becomes equal to the threshold voltage Vth, and thereafter, the drain current Ids does not flow. At this time, the source potential Vs of the driving transistor Md is “Vo−Vth”.

As described above, the threshold voltage correction is performed a plurality of times (three times in this example) with the standby period interposed therebetween, so that the holding voltage of the storage capacitor Cs converges in a stepped manner with the standby period being constant. The threshold voltage Vth is finally obtained.
If the gate-source voltage of the driving transistor is increased by “Vin”, the gate-source voltage is “Vin + Vth”. Further, a driving transistor having a large threshold voltage Vth and a driving transistor having a small threshold voltage Vth are considered.
The former driving transistor having a larger threshold voltage Vth has a larger gate-source voltage by the amount of the larger threshold voltage Vth, and conversely, the driving transistor having a smaller threshold voltage Vth has a smaller threshold voltage Vth, resulting in a smaller gate-source voltage. Therefore, regarding the threshold voltage Vth, the variation can be canceled by the threshold voltage correction operation, and the same drain current Ids can be caused to flow to the drive transistor at the same data voltage Vin.

Note that in the threshold correction period of three times, that is, in the first threshold correction period (VTC1), the second threshold correction period (VTC2), and the third threshold correction (VTC3), the drain current Ids is exclusively one of the holding capacitors Cs. It is consumed only to flow into one electrode side of the combined capacitance (Coled. + Csub) of the capacitance of the organic light emitting diode OLED and the auxiliary capacitor on the electrode side, and it is necessary to prevent the organic light emitting diode OLED from being turned on. When the anode voltage of the organic light emitting diode OLED is expressed as “Voled.”, Its threshold voltage is expressed as “Vth_oled.”, And its cathode potential is expressed as “Vcath”, the condition for maintaining the organic light emitting diode OLED in the off state is “Voled. ≦ “Vcath + Vth_oled.” Always holds.
Here, when the cathode potential Vcath of the organic light emitting diode OLED is constant at the reference voltage VSS (for example, the ground voltage GND), this equation can always be established when the light emission threshold voltage Vth_oled. Is very large. However, the light emission threshold voltage Vth_oled. Is determined by the manufacturing conditions of the organic light emitting diode OLED, and the light emission threshold voltage Vth_oled. Cannot be increased too much for efficient light emission at a low voltage. Therefore, preferably, the organic light emitting diode OLED is reverse-biased by setting the cathode potential Vcath smaller than the low potential Vcc_L until the threshold correction period of 3 degrees and the mobility correction period described below are completed. It is good to leave.

[Third waiting period (WAT3)]
The above is the description of the threshold voltage correction, but in this operation example, the standby period (third standby period (WAT3)) for “writing & mobility correction” starts. The third standby period (WAT3) is different from the first standby period (WAT1) and the second standby period (WAT2) for the threshold voltage correction so far, and is simply performed at the subsequent “writing & mobility correction”. This is a short waiting period for waiting so that a portion where the potential change of the video signal Ssig is unstable is not erroneously sampled.

As shown in FIG. 4 (B1), when the sampling pulse (SP3) transitions from the “H” level to the “L” level at time T17, the third waiting period (WAT3) starts from here.
In the third standby period (WAT3), as shown in FIG. 4 (A), a video signal pulse (PPx) having a data potential Vsig to be displayed in the pixel circuit 3 (1, j) at a time T18 in the middle. Is supplied to the video signal line DTL (j) as the video signal Ssig (see FIG. 9A). In the video signal Ssig, the difference between the data potential Vsig and the data reference potential Vo corresponds to the data voltage Vin corresponding to the gradation value to be displayed by the pixel circuit. That is, the data potential Vsig is equal to “Vo + Vin”.
The third standby period (WAT3) ends at time T19 when the video signal Ssig has stabilized at the data potential Vsig after a time has elapsed since the potential change performed at time T18.

[Writing & mobility correction period (W & μ)]
From time T19, the writing & mobility correction period (W & μ) starts.
As shown in FIG. 4 (B1), the write pulse (WP) is supplied to the gate of the sampling transistor Ms at time T19 during application of the video signal pulse (PPx) in this operation. Then, as shown in FIG. 9B, the sampling transistor Ms is turned on, and the difference between the data potential Vsig (= Vo + Vin) of the video signal line DTL (j) and the gate voltage Vg (= Vo), that is, The data voltage Vin is input to the gate of the drive transistor Md. As a result, the gate voltage Vg becomes “Vo + Vin”.
When the gate voltage Vg increases by the data voltage Vin, the source potential Vs also increases in conjunction with this. At this time, the data voltage Vin is not transmitted to the source potential Vs as it is, but the source potential Vs rises by the change in the ratio according to the above-described capacitive coupling ratio g, that is, “g * Vin”. Therefore, the source potential Vs after the change is “Vo−Vth + g * Vin”. As a result, the gate-source voltage Vgs of the drive transistor Md becomes “(1−g) Vin + Vth”.

Here, the variation due to the mobility μ will be described.
Although the error due to the mobility μ is included every time the drain current Ids is flowed by the three threshold voltage corrections so far, the error component due to the mobility μ is strictly discussed because the variation of the threshold voltage Vth is large. I didn't. At this time, the voltage indicating only the result is newly described as “Va1” or “Va2” without using the capacitive coupling ratio g, and the complexity due to explaining the variation in mobility is avoided. Because.
On the other hand, as already described, after the threshold voltage correction is strictly performed, the threshold voltage Vth is held in the holding capacitor Cs at that time. The drain current Ids does not vary depending on the magnitude of Vth. For this reason, if the drive transistor Md after the threshold voltage correction is conducted, if the value of the holding voltage (gate-source voltage Vgs) of the holding capacitor Cs varies due to the drive current Id during the conduction, the amount of fluctuation ΔV (which can be positive or negative) is a variation of the mobility μ of the driving transistor Md, more precisely, in addition to the mobility in a pure sense, which is a physical property parameter of the semiconductor material, This reflects the overall variation in factors that affect the current driving force in the structure or manufacturing process.

  Returning to the explanation based on the above, in FIG. 9B, when the sampling transistor Ms is turned on and the data voltage Vin is added to the gate voltage Vg, the driving transistor Md has the data voltage Vin ( A drain current Ids having a magnitude corresponding to (gradation value) is attempted to flow between the source and drain. At this time, the drain current Ids varies depending on the mobility μ, and as a result, the source potential Vs becomes “Vo−Vth + g * Vin + ΔV” obtained by adding the variation ΔV due to the mobility μ to “Vo−Vth + g * Vin”. .

At this time, in order not to cause the organic light emitting diode OLED to emit light, the cathode potential Vcath corresponding to the data voltage Vin, the capacitive coupling ratio g, or the like is satisfied so that “Vs (= Vo−Vth + g * Vin + ΔV) <Vth_oled. + Vcath” is satisfied. It may be set in advance.
If this setting is performed in advance, the organic light emitting diode OLED is reverse-biased and does not emit light because it is in a high impedance state, and exhibits simple capacitance characteristics rather than diode characteristics.
At this time, as long as the above conditional expression is satisfied, the source potential Vs does not exceed the sum of the emission threshold voltage Vth_oled. Of the organic light emitting diode OLED and the cathode potential Vcath, so that the drain current Ids (drive current Id) is The capacitance value Cs of the organic light emitting diode OLED, the equivalent capacitance value Coled at the time of reverse bias, the capacitance value Csub of the auxiliary capacitor, and the parasitic capacitance (denoted as Cgs) existing between the gate source of the drive transistor Md are added. Used to charge the capacity “C = Cs + Coled. + Csub + Cgs”. As a result, the source potential Vs of the drive transistor Md increases. At this time, since the threshold correction operation of the drive transistor Md is completed, the drain current Ids that the drive transistor Md flows reflects the mobility μ.

As shown by the expression “(1−g) Vin + Vth−ΔV” in FIGS. 4E and 4F, the gate-source voltage Vgs held in the holding capacitor Cs is set to the source potential Vs. Since the added fluctuation amount ΔV is subtracted from the gate-source voltage Vgs (= (1−g) Vin + Vth) after the threshold correction, the fluctuation amount ΔV is held in the holding capacitor Cs so that negative feedback is applied. Therefore, hereinafter, the fluctuation amount ΔV is also referred to as “negative feedback amount”.
This negative feedback amount ΔV can be expressed by an approximate expression of ΔV = t * Ids / (Coled. + Csub + Cs + Cgs) because “Coled. + Csub >> Cs + Cgs” holds in a state where the organic light emitting diode OLED is reverse-biased. it can. From this approximate expression, it can be seen that the fluctuation amount ΔV is a parameter that changes in proportion to the fluctuation of the drain current Ids.
From the approximate expression of the negative feedback amount ΔV, the negative feedback amount ΔV added to the source potential Vs is the magnitude of the drain current Ids (this magnitude is positively correlated with the magnitude of the data voltage Vin, that is, the gradation value). The drain current Ids flows, that is, the time (t) from time T19 to time T20 required for mobility correction shown in FIG. 4B1. That is, the larger the gradation value and the longer the time (t), the larger the negative feedback amount ΔV.
Therefore, the mobility correction time (t) is not necessarily constant, and on the contrary, it may be preferable to adjust it according to the drain current Ids (gradation value). For example, when the drain current Ids is close to white display and the drain current Ids is large, the mobility correction time (t) is shortened. Conversely, when the drain current Ids is close to black display and becomes small, the mobility correction time (t) is lengthened. It is good to set to. This automatic adjustment of the mobility correction time according to the gradation value can be realized by providing the function in advance in the write signal scanning circuit 42 shown in FIG.

[Light emission period (LM1)]
When the writing & mobility correction period (W & μ) ends at time T20, the light emission period (LM1) starts.
Since the write pulse (WP) ends at time T20, the sampling transistor Ms is turned off, and the gate of the drive transistor Md is in an electrically floating state.

  By the way, in the writing & mobility correction period (W & μ) before the light emission period (LM1), the drive transistor Md tries to flow the drain current Ids according to the data voltage Vin, but it does not always flow. The reason is that if the current value (Id) flowing through the organic light emitting diode OLED is very small as compared with the current value (Ids) flowing through the drive transistor Md, the sampling transistor Ms is turned on, and therefore the gate voltage of the drive transistor Md This is because Vg is fixed at “Vo + Vin” and the source potential Vs tends to converge to a potential (“Vo + Vin−Vth”) that is lowered by the threshold voltage Vth therefrom. Therefore, no matter how long the mobility correction time (t) is increased, the source potential Vs cannot be a potential exceeding the convergence point. In the mobility correction, the difference in mobility μ is monitored and corrected based on the difference in speed until convergence. For this reason, even when the white display data voltage Vin with the maximum luminance is input, the end point of the mobility correction time (t) is determined before the convergence.

When the light emission period (LM1) starts and the gate of the drive transistor Md becomes floating, the source potential Vs can be further increased. Therefore, the drive transistor Md operates so as to flow the drive current Id corresponding to the input data voltage Vin.
As a result, the source potential Vs (the anode potential of the organic light emitting diode OLED) rises, and eventually the reverse bias state of the organic light emitting diode OLED is canceled, and as shown in FIG. 9C, the drain current Ids becomes the driving current Id. As a result, the organic light emitting diode OLED actually starts to emit light. After a while from the start of light emission, the drive transistor Md is saturated with the drain current Ids corresponding to the input data voltage Vin, and when the drain current Ids (= Id) becomes constant, the organic light emitting diode OLED becomes the data voltage Vin. The light emission state with the corresponding brightness is obtained.

The increase in the anode potential of the organic light emitting diode OLED that occurs from the start of the light emission period (LM1) until the luminance becomes constant is nothing but the increase in the source potential Vs of the drive transistor Md. “ΔVoled.” In the sense of an increase amount of the anode voltage Voled. The source potential Vs of the drive transistor Md is “Vo−Vth + g * Vin + ΔV + ΔVoled.” (See FIG. 4F).
On the other hand, as shown in FIG. 4E, since the gate voltage Vg is in a floating state, the gate voltage Vg rises by the same amount as the increase amount ΔVoled. When the potential Vs is saturated, the gate voltage Vg is also saturated.
As a result, for the gate-source voltage Vgs (holding voltage of the holding capacitor Cs), the mobility correction value (“(1−g) Vin + Vth−ΔV”) is maintained even during the light emission period (LM1).

In the light emission period (LM1), since the drive transistor Md operates as a constant current source, the IV characteristic of the organic light emitting diode OLED changes with time, and the source potential Vs of the drive transistor Md changes accordingly. There is.
However, the holding voltage of the holding capacitor Cs is maintained at “(1−g) Vin + Vth−ΔV” regardless of whether the IV characteristic of the organic light emitting diode OLED changes with time. Since the holding voltage of the holding capacitor Cs includes a component (+ Vth) for correcting the threshold voltage Vth of the driving transistor Md and a component (−ΔV) for correcting the variation due to the mobility μ, the threshold voltage Vth and the movement Even if the degree μ varies between different pixels, the drain current Ids of the drive transistor Md, that is, the drive current Id of the organic light emitting diode OLED is kept constant.

Specifically, as the threshold voltage Vth increases, the drive transistor Md decreases the source potential Vs by the threshold voltage correction component (+ Vth) of the holding voltage so that the drain current Ids (drive current Id) flows more. Increase drain-to-drain voltage. Therefore, the drain current Ids is constant even if the threshold voltage Vth varies.
In addition, when the mobility μ is small and the fluctuation amount ΔV is small, the driving transistor Md has a relatively small decrease amount of the holding voltage due to the mobility correction component (−ΔV) of the holding voltage of the holding capacitor Cs. Therefore, a large source-drain voltage is ensured, and as a result, the drain current Ids (driving current Id) flows more. Therefore, the drain current Ids is constant even when the mobility μ varies.

  From the above, even if the threshold voltage Vth and mobility μ of the drive transistor Md vary between pixels, and even if the characteristics of the drive transistor Md change over time, the organic light emitting diode OLED can be used as long as the data voltage Vin remains the same. The light emission brightness is also kept constant.

The present embodiment is characterized in that the video signal line DTL, the power supply scanning line DSL, and the cathode line CAL are used in the multilayer wiring structure and the pattern is superposed.
In other words, the organic EL display 1 according to the present embodiment has the following: “The power source scanning line DSL is in a layer between the constant potential line such as the cathode line CAL and the video signal line DTL intersecting the constant potential line. The constant potential line and the planar pattern are arranged so as to at least partially overlap.

  Hereinafter, the pattern of the comparative example which does not have this feature and the defect in the display control will be described first, and the cross-section of the wiring portion and the formation example of the planar pattern of this embodiment will be described.

<Comparative example>
FIG. 10 shows a wiring layout in the pixel circuit 3 (i, j) of the comparative example.
In the pixel circuit 3 (i, j), the write scanning line WSL is arranged in the row direction at a position near the pixel boundary on one side in the column direction (vertical direction in FIG. 10). The write scanning line WSL is formed of the same material as the gate metal (GM) of the TFT as the “first layer metal”, for example, a refractory metal such as molybdenum Mo. A TFT layer is disposed on the gate metal (GM) and then flattened by an interlayer insulating film, and wiring is formed on the interlayer insulating film from aluminum (AL) as a “second layer metal”. .
A power supply scanning line DSL and a cathode line CAL are formed of aluminum (AL). The cathode line CAL and the power supply scanning line DSL are formed along the pixel side opposite to the writing scanning line WSL.

  Note that the gate metal (GM) is also used as a lower electrode of the holding capacitor Cs. Aluminum (AL) is also used as a source electrode wiring, a drain electrode wiring of the TFT (driving transistor Md and sampling transistor Ms), and an upper electrode of the holding capacitor Cs.

The video signal line DTL includes a main line portion 14C formed of aluminum (AL) as “second layer metal”, a bridge portion 11C formed of gate metal (GM) as “first layer metal”, and 1st A plurality of contacts 12C and 12D formed from the contacts (1C) are included.
The video signal line DTL intersects the power supply scanning line DSL and the cathode line CAL at the bridge portion 11C.

  As described above, when the cathode line CAL is formed of aluminum (AL) for forming the electrode of the TFT, the lower gate metal (GM) via the relatively thin gate insulating film (not shown) They are coupled by a relatively large parasitic capacitance Cp. Therefore, when the potential of the video signal line DTL changes, strong capacitive coupling occurs through the parasitic capacitance Cp, and as a result, the potential of the cathode line CAL varies greatly.

11A to 11E are timing charts showing waveforms of various signals and voltages in the light emission control of the comparative example.
In FIG. 11, the pulse waveforms of the other display lines shown in FIG. 4 are omitted, and a potential fluctuation waveform of the cathode line CAL is added instead (FIG. 11C). In FIG. 11, the initialization and the first threshold correction are continuously performed within the first one horizontal period (1H). However, this point is not essential, and the control that can be adopted in FIG. It is.
Basic control is common to FIG. 11 and FIG. The symbol “T1 ′” means that it is slightly before the time T1. Further, in FIG. 11, two times indicated at the same position on the time axis, that is, T7 and T8, T9 and T10, T12 and T13, T14 and T15, and T17 and T18 are larger than the time when the number is smaller. It means that it is desirable to be slightly ahead on the time axis.

  As shown in FIG. 11C, potential fluctuations VC1 and VC2 occur in the cathode line CAL each time the video signal pulse PP rises in the video signal line DTL. Since the peak value of the video signal pulse PP differs depending on the magnitude of the input data voltage Vin, the magnitude of the potential change generated in the cathode line CAL is the potential change VC1 (solid line) during black display and the white display. It varies in the range between the potential change VC2 (broken line).

The problem here is the tailing of the potential change that occurs immediately before the write & mobility correction period (W & μ) (time T18).
The potential change VC1 at the time of black display disappears by time T19 when the writing & mobility correction is started, but the potential change VC2 at the time of white display (and the potential change at the time of display of high luminance close to white) is It does not converge after time T19. Therefore, the trailing edge of the potential change VC2 or the like becomes an error component of the source potential Vs shown in FIG. At this time, the gate potential Vg shown in FIG. 11D does not fluctuate because the sampling operation is being performed.
The source potential of the source potential Vs at the end of writing (time T20) becomes prominent as an error in both the source potential Vs and the gate potential Vg after the gate of the drive transistor Md becomes floating at time T20. Therefore, the luminance after the organic light emitting diode OLED emits light is different from a desired value corresponding to the data voltage Vin, and the display quality is deteriorated.

<Configuration of wiring arrangement>
FIG. 12A is a layout diagram of wirings in the pixel circuit according to this embodiment.
The layout shown in FIG. 12A is different from the layout of the comparative example shown in FIG. 10 in that an upper layer of the power supply scanning line DSL formed of aluminum (AL) as “second layer metal” is “ The cathode line CAL formed from the anode metal (AM) as the “third layer metal” is formed so as to be overlapped on the plane pattern.
In the illustrated example, in the planar pattern, the power source scanning line DSL is overlapped with the cathode line CAL with a width that is slightly larger than the width of the cathode line CAL as the “constant potential line” arranged in the row direction.

  FIG. 12B is a cross-sectional view taken along the line AA in FIG. FIG. 12C is a cross-sectional view corresponding to an equivalent circuit portion taken along line BB in FIG. The equivalent circuit portion of the BB line in FIG. 12A includes an anode contact 15A formed from the 2nd contact (2C), and the anode contact 15A indicates a position on the equivalent circuit. The actual position on the plane pattern is not always the position shown in the figure.

A base layer 10 made of an insulating material is formed on a substrate (not shown), a gate metal (GM) is formed on the base layer 10, and this is patterned to form a gate electrode 11A such as a drive transistor Md (FIG. 12 (FIG. C)) and the bridge portion 11C of the video signal line DTL (FIG. 12B) are collectively formed. At this time, the write scan line WSL, the holding capacitor Cs, and the lower electrode of the auxiliary capacitor Csub in FIG. 12A are also simultaneously formed from the same material gate metal (GM).
12B and 12C, a gate insulating film 12 that covers the surfaces of the gate electrode 11A and the bridge portion 11C is formed on the base layer 10.

In FIG. 12C, a TFT layer 13A is formed so as to overlap with the gate electrode 11A. The TFT layer 13A is formed, for example, by depositing a polysilicon or amorphous silicon film and patterning it.
Impurities are introduced into the TFT layer 13A for channel doping or for forming the source (S) and the drain (D).

  A drain line 14A connected to the drain (D) and provided as a branch line of the power supply scanning line DSL, and a source line 14D connected to the source (S) and connected to the upper electrode of the holding capacitor Cs and the auxiliary capacitor Csub (not shown) It is formed by patterning aluminum (AL). At the same time, the main line portion 14C of the video signal line DTL shown in FIG. 12C and the power supply scanning line DSL shown in FIG. 12B are formed of the same aluminum (AL).

A flattening film 15 for flattening the step of aluminum (AL) or the transistor portion is deposited relatively thick, and thereby the transistor and the capacitor are buried in the flattening film 15.
The planarizing film 15 is formed with an anode contact 15A made of a second contact (2C) in the form of a plug of metal or the like. The anode contact 15A is formed on the source line 14D.

An anode electrode AE that is formed on the planarizing film 15 and contacts the end face of the anode contact 15A, a protective film 16 that is formed on the anode electrode AE and has an opening 16A that is slightly smaller than the anode electrode AE, and further covers the protective film 16 The organic multilayer film OML and the cathode electrode CE formed in a blanket shape over the entire area occupied by the pixel are deposited in this order, thereby forming the organic light emitting diode OLED.
The anode electrode AE is made of, for example, an anode metal (AM) as a “third layer metal” mainly composed of silver Ag. At the same time, as shown in FIG. 12B, the cathode line CAL made of the same anode metal (AM) is formed on the planarizing film 15 with a narrower width than the lower power supply scanning line DSL.

According to the above configuration, the cathode line CAL is formed from the “third layer metal”, and the image formed from the lower “first layer metal” by the power source scanning line DSL formed from the “second layer metal”. The cathode line CAL is completely shielded from a part of the signal line DTL (bridge portion 11C). For this reason, the power source scanning line DSL is used as a shield layer, and a shielding effect is obtained that the potential variation in the cathode line CAL is effectively prevented by the potential change of the video signal line DTL.
Due to the shielding effect, potential fluctuations VC1 and VC2 do not occur as shown in FIG. Alternatively, even when the potential change occurs and the generated potential change takes the maximum value during white display according to the data potential Vsig, the image quality is not affected as in the case of black display in FIG. The potential change is suppressed to the extent. As a result, the light emission luminance of the organic light emitting diode OLED is stabilized and high image quality is obtained.

  A modification in this embodiment will be described.

<Modification 1>
The overlap between the power supply scanning line DSL and the cathode line CAL in the planar pattern is not limited to the form shown in FIG. For example, the power supply scanning line DSL and the cathode line CAL may partially overlap in the width direction.

<Modification 2>
Although not particularly shown, the cathode line CAL is formed from a gate metal (GM) which is a “first layer metal”, and the bridge portion 11C of the video signal line DTL is formed from aluminum (AL) which is a “second layer metal”. The main line portion 14 </ b> C may be formed so as to be connected as a so-called upper bridge. In this case, the bridge portion 11C is formed of, for example, an anode metal (AM) that is a “third layer metal”.

<Modification 3>
The cathode line CAL as the “constant potential line” has a frame-like cathode line at the outermost peripheral portion of the pixel array 2 and connects both ends of the cathode line CAL in the row direction. By connecting to the frame-like cathode line, the plurality of row-direction cathode lines CAL may have substantially the same potential.
Alternatively, the cathode line CAL for each row may be connected in the pixel array 2. When the number of connections is maximized, the pattern of the cathode lines CAL may be formed in a lattice shape along pixel boundaries in the row direction and the column direction.

<Modification 4>
The pixel circuit is not limited to those shown in FIGS.
In the pixel circuits of FIGS. 2 and 12, the data reference potential Vo is given by sampling the video signal Ssig, but the data reference potential Vo can also be given to the source and gate of the driving transistor Md via another transistor.
In the pixel circuits of FIGS. 2 and 12, the capacitor is only the holding capacitor Cs. However, another holding capacitor may be provided, for example, between the gate of the driving transistor Md and the constant voltage line. The light emitting element is not limited to the organic light emitting diode OLED, and may be another self-light emitting element.

<Modification 5>
A driving method in which the pixel circuit controls light emission and non-light emission of the organic light emitting diode OLED includes a method in which the transistors in the pixel circuit are controlled by a scanning line, and a method in which a power supply voltage supply line is AC driven by a driving circuit (power supply AC Drive method).
The pixel circuit of FIGS. 2 and 12 is an example of the latter power source AC driving method. In this method, the cathode side of the organic light emitting diode OLED may be AC driven to control whether the driving current flows or not. .
On the other hand, in the former method of controlling the light emission control by the scanning line, another transistor is inserted between the drain side of the driving transistor Md or between the source and the organic light emitting diode OLED, and the gate thereof is scanned for power supply driving control. Drive with lines.

<Modification 6>
In the display control shown in FIGS. 4 and 11, the threshold correction period (VTC) is performed by three corrections. However, the correction is performed once or a plurality of times other than three times (initialization in between). The meaning of not pinching) The threshold value may be corrected by processing. Further, display control may be performed in which data is written after mobility correction is performed.

  According to the embodiment of the present invention and the modification thereof, the potential fluctuation at the time of data writing in one electrode of the light emitting element caused by the change in the potential of the video signal line is prevented or suppressed. Light can be emitted with luminance.

It is a figure which shows the main structures of the organic electroluminescent display in connection with embodiment of this invention. It is a figure which shows an example of the basic composition of the pixel circuit in connection with embodiment of this invention, and the drive circuit part which controls the pixel circuit. It is a figure which shows the graph and formula showing the characteristic of an organic light emitting diode. It is a timing chart which shows the waveform of various signals and voltage in display control concerning the embodiment of the present invention. It is operation | movement explanatory drawing to Vo sampling in control of FIG. It is operation | movement explanatory drawing to the 2nd threshold value correction | amendment in control of FIG. It is operation | movement explanatory drawing to the 3rd threshold value correction | amendment in control of FIG. It is a graph of the time transition of the source potential concerning the embodiment of the present invention. It is operation | movement explanatory drawing to the light emission period in control of FIG. It is a figure which shows arrangement | positioning of the wiring in the pixel circuit concerning the comparative example of embodiment of this invention with an equivalent circuit. It is a timing chart which shows the malfunction in a comparative example in addition to FIG. It is a figure which shows arrangement | positioning and cross-sectional structure of the wiring in the pixel circuit concerning embodiment of this invention. It is the figure which copied the equivalent circuit schematic of the pixel circuit described in background art (patent document 1), changing a part of reference signs.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 1 ... Organic EL display, 2 ... Pixel array, 3 ... Pixel circuit, 4 ... V scanner, 5 ... H scanner, 11A ... Gate electrode, 11C ... Bridge part of video signal line, 12C, 12D ... Contact, 14A ... Drain line , 14C of the video signal line, 14D, source line, 15D, planarizing film, 15A, anode contact, AE, anode electrode, CE, cathode electrode, 41, horizontal pixel line drive circuit, 42, write signal scanning circuit. , OLED ... organic light emitting diode, M1 ... driving transistor, Ms ... sampling transistor, Cs ... holding capacitor, Csub ... auxiliary capacitor, NDc ... control node, NDs ... source node, WSL ... write scan line, DSL ... power supply scan line, DTL: Video signal line, Vsig: Data potential, Vo: Data reference potential

Claims (4)

A plurality of pixel circuits arranged in a matrix;
A write scan line and a power supply scan line respectively connecting the pixel circuits in the row direction;
Video signal lines connecting pixel circuits in the column direction;
Have
The pixel circuit includes:
A light-emitting element in which the other electrode is connected at least between the pixels in the row direction by a constant potential line, and an applied voltage value changes according to the potential of the one electrode;
An auxiliary capacitor connected in parallel with the light emitting element between the constant potential line and the one electrode;
A driving transistor connected between the power supply scanning line and the one electrode;
A sampling transistor connected between the video signal line and a control node of the driving transistor;
A holding capacitor coupled to the control node;
Including
In a layer between the constant potential line arranged along the row direction and the position of the video signal line intersecting the constant potential line, the power scanning line is at least one in a plane pattern with the constant potential line. Self-luminous display device with overlapping parts. 2. The self-luminous display device according to claim 1, wherein in the planar pattern, the power supply scanning line is overlapped with the constant potential line with a width that is slightly larger than a width of the constant potential line arranged in the row direction. Each gate of the driving transistor and the sampling transistor is formed of a first layer metal,
The power supply scanning line is formed from a second layer metal one layer above the first layer metal;
A constant potential line arranged along the row direction is formed from a third layer metal one layer above the second layer metal;
The video signal line includes a bridge portion formed from the first layer metal at a location intersecting with a constant potential line, and two main lines formed from the second layer metal located on both sides in the length direction of the bridge portion. The self-luminous display device according to claim 1, further comprising a plurality of contacts that connect the bridge portion to each of the two main line portions. Each gate of the driving transistor and the sampling transistor, and a constant potential line arranged along the row direction are formed from a first layer metal,
The power supply scanning line is formed from a second layer metal one layer above the first layer metal;
The video signal line includes a bridge portion formed of a third layer metal, which is one layer higher than the second layer metal, at a position intersecting with a constant potential line, and is positioned on both sides in the length direction of the bridge portion. 2. The self-luminous display device according to claim 1, comprising: two main line portions formed of layer metal; and a plurality of contacts connecting the bridge portion to each of the two main line portions.

Images