JP5589903B2 - Inverter circuit and display device - Google Patents

Description

  The present invention relates to an inverter circuit that can be suitably applied to a display device. Moreover, this invention relates to the display apparatus provided with the said inverter circuit.

  The inverter circuit may be formed by combining n-channel and p-channel MOS transistors in one chip, or may be formed by only a single-channel MOS transistor. The latter can reduce the number of processes and is superior to the former in terms of productivity and yield.

  FIG. 22 shows a general inverter circuit composed of only n-channel MOS transistors. A similar circuit is described in Patent Document 1 as a conventional example. The inverter circuit 10 shown in FIG. 22 is configured by connecting two n-channel MOS transistors T10 and T20 in series. The inverter circuit 10 is inserted between a negative voltage line L10 to which the voltage Vss is applied and a positive voltage line L20 to which the voltage Vdd is applied. In the transistor T10, the source is connected to the negative voltage line L10, the drain is connected to the source of the transistor T20, and the gate is connected to the input terminal IN. The transistor T20 has a diode connection in which the gate and the drain are connected to each other. Specifically, in the transistor T20, the source is connected to the drain of the transistor T10, and the gate and the drain are connected to the positive voltage line L20. A connection point C between the transistors T10 and T20 is connected to the output terminal OUT.

JP 2009-188749 A

  In the inverter circuit 10, for example, as shown in FIG. 23, when the voltage Vin of the input terminal IN is Vss, the voltage Vout of the output terminal OUT does not become Vdd, but becomes Vdd−Vth. That is, the voltage Vout at the output terminal OUT includes the threshold voltage Vth of the transistor T20, and the voltage Vout at the output terminal OUT is greatly affected by variations in the threshold voltage Vth of the transistor T20.

  Therefore, for example, as shown in the inverter circuit 20 of FIG. 24, the gate and the drain of the transistor T20 are electrically separated from each other, and a positive voltage Vdd2 (≧ Vdd + Vth) higher than the drain voltage Vdd is applied. It is conceivable to connect a gate to the voltage line L30. Further, for example, a bootstrap type circuit configuration as shown in the inverter circuit 30 of FIG. 25 is conceivable. Specifically, the transistor T30 is inserted between the gate of the transistor T20 and the positive voltage line L2, the gate of the transistor T30 is connected to the positive voltage line L20, and the gate of the transistor T20 and the source of the transistor T30 are connected. A circuit configuration in which a capacitive element C10 is inserted between the connection point D and the connection point C is conceivable.

  However, in any of the circuits of FIGS. 22, 24, and 25, the transistor T10 is used until the voltage Vin at the input terminal IN is high, that is, until the voltage Vout at the output terminal OUT is low. , T20, a current (through current) flows from the positive voltage line L20 side to the negative voltage line L10 side. As a result, power consumption in the inverter circuit also increases.

  The present invention has been made in view of such a problem, and an object thereof is to provide an inverter circuit capable of suppressing power consumption and a display device including the inverter circuit.

The first inverter circuit of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, an input terminal and an output terminal, a capacitor, and a fourth transistor that are of the same channel type. And a power source for inputting a second control signal to the gate of the fifth transistor . Here, the first transistor cuts off the electrical connection between the output terminal and the first voltage line according to the potential difference between the voltage of the input terminal and the voltage of the first voltage line or the corresponding potential difference. ing. The second transistor disconnects the electrical connection between the second voltage line and the output terminal according to the potential difference between the voltage of the source or drain of the fourth transistor and the voltage of the output terminal or the potential difference corresponding thereto. It has become. The third transistor cuts off the electrical connection between the gate of the second transistor and the third voltage line according to the potential difference between the voltage of the input terminal and the voltage of the third voltage line or the corresponding potential difference. ing. The fourth transistor cuts off the electrical connection between the first terminal, which is the source or drain of the fifth transistor, and the gate of the second transistor in response to the first control signal . The fifth transistor cuts off the electrical connection between the fourth voltage line and the first terminal according to the second control signal . The capacitive element is inserted between the gate of the second transistor and the terminal on the output terminal side of the source and drain of the second transistor. The power supply is configured to output a low level voltage as one of the first control signal and the second control signal from before the input terminal voltage rises to before the fall. Furthermore, while the voltage of the input terminal is a high level voltage and the one control signal is a high level voltage, the low level voltage is set to the first control signal and the second control signal. Is output as the other control signal.

  A first display device of the present invention includes a display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix. In addition, a drive unit for driving each pixel is provided. The drive unit includes a plurality of inverter circuits provided for each scanning line, and each inverter circuit includes the same components as the first inverter circuit.

The second inverter circuit of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor that are of the same channel type, a first input terminal , a second input terminal, and a third input terminal. And an output terminal, a capacitive element, and a power source for inputting a first control signal to the gate of the fourth transistor and inputting a second control signal to the gate of the fifth transistor . Here, in the first transistor, the gate is connected to the first input terminal, one of the source and the drain is connected to the first voltage line, and the other of the source and the drain is connected to the output terminal. In the second transistor, the gate is connected to the source or drain of the fourth transistor, one of the source and drain is connected to the second voltage line, and the other of the source and drain is connected to the output terminal. In the third transistor, the gate is connected to the first input terminal, one of the source and the drain is connected to the third voltage line, and the other of the source and the drain is connected to the gate of the second transistor. In the fourth transistor, the gate is connected to the second input terminal , one of the source and drain is connected to the gate of the second transistor, and the other of the source and drain is connected to the source or drain of the fifth transistor. . In the fifth transistor, the gate is connected to the third input terminal , one of the source and drain is connected to the fourth voltage line, and the other of the source and drain is the second transistor of the source and drain of the fourth transistor. Connected to a terminal not connected to the gate. The capacitive element is inserted between the gate of the second transistor and a terminal not connected to the second voltage line among the source and drain of the second transistor. The power supply is configured to output a low level voltage to one of the second input terminal and the third input terminal before the voltage at the first input terminal rises and before it falls. Furthermore, while the voltage at the first input terminal is a high level voltage and the voltage at one input terminal is a high level voltage, the low level voltage is applied to the second input terminal and the second input terminal. The other input terminal of the three input terminals is output.

  A second display device of the present invention includes a display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix. In addition, a drive unit for driving each pixel is provided. The drive unit includes a plurality of inverter circuits provided for each scanning line, and each inverter circuit includes the same components as those of the second inverter circuit.

The third inverter circuit of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor that are of the same channel type, an input terminal, and an output terminal. , And a capacitive element, and a power source that inputs a first control signal to the gate of the fourth transistor and a second control signal to the gate of the fifth transistor . Here, the first transistor cuts off the electrical connection between the gate of the seventh transistor and the first voltage line according to the potential difference between the voltage of the input terminal and the voltage of the first voltage line or the corresponding potential difference. It is like that. The second transistor electrically connects the second voltage line and the gate of the seventh transistor according to the potential difference between the source or drain voltage of the fourth transistor and the gate voltage of the seventh transistor or the corresponding potential difference. It is supposed to be relayed. The third transistor cuts off the electrical connection between the gate of the second transistor and the third voltage line according to the potential difference between the voltage of the input terminal and the voltage of the third voltage line or the corresponding potential difference. ing. The fourth transistor cuts off the electrical connection between the first terminal, which is the source or drain of the fifth transistor, and the gate of the second transistor in response to the first control signal . The fifth transistor cuts off the electrical connection between the fourth voltage line and the first terminal according to the second control signal . The sixth transistor cuts off the electrical connection between the output terminal and the fifth voltage line according to the potential difference between the voltage of the input terminal and the voltage of the fifth voltage line or the potential difference corresponding thereto. The seventh transistor cuts off the electrical connection between the sixth voltage line and the output terminal in accordance with the potential difference between the gate voltage of the seventh transistor and the voltage at the output terminal or the corresponding potential difference. Yes. The capacitive element is inserted between the gate of the second transistor and the terminal on the output terminal side of the source and drain of the second transistor. The power supply is configured to output a low level voltage as one of the first control signal and the second control signal from before the input terminal voltage rises to before the fall. Furthermore, while the voltage of the input terminal is a high level voltage and the one control signal is a high level voltage, the low level voltage is set to the first control signal and the second control signal. Is output as the other control signal.

  A third display device of the present invention includes a display unit including a plurality of scanning lines arranged in a row, a plurality of signal lines arranged in a column, and a plurality of pixels arranged in a matrix. In addition, a drive unit for driving each pixel is provided. The drive unit includes a plurality of inverter circuits provided for each scanning line, and each inverter circuit includes the same components as the third inverter circuit.

The fourth inverter circuit of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor that are of the same channel type, a first input terminal , 2 input terminals, 3rd input terminals and output terminals, a capacitive element, and a power source for inputting the first control signal to the gate of the fourth transistor and inputting the second control signal to the gate of the fifth transistor It is. Here, in the first transistor, the gate is connected to the first input terminal, one of the source and the drain is connected to the first voltage line, and the other of the source and the drain is connected to the gate of the seventh transistor. . In the second transistor, the gate is connected to the source or drain of the fourth transistor, one of the source and drain is connected to the second voltage line, and the other of the source and drain is connected to the gate of the seventh transistor. . In the third transistor, the gate is connected to the first input terminal, one of the source and the drain is connected to the third voltage line, and the other of the source and the drain is connected to the gate of the second transistor. In the fourth transistor, the gate is connected to the second input terminal , one of the source and drain is connected to the gate of the second transistor, and the other of the source and drain is connected to the source or drain of the fifth transistor. . In the fifth transistor, the gate is connected to the third input terminal , one of the source and drain is connected to the fourth voltage line, and the other of the source and drain is the second transistor of the source and drain of the fourth transistor. Connected to a terminal not connected to the gate. In the sixth transistor, the gate is connected to the first input terminal, one of the source and the drain is connected to the fifth voltage line, and the other of the source and the drain is connected to the output terminal. In the seventh transistor, the gate is connected to a terminal not connected to the second voltage line of the source and drain of the second transistor, one of the source and drain is connected to the sixth voltage line, and the other of the source and drain is Is connected to the output terminal. The capacitive element is inserted between the gate of the second transistor and a terminal not connected to the second voltage line among the source and drain of the second transistor. The power supply is configured to output a low level voltage to one of the second input terminal and the third input terminal before the voltage at the first input terminal rises and before it falls. Furthermore, while the voltage at the first input terminal is a high level voltage and the voltage at the one input terminal is a high level voltage, the low level voltage is changed to the second input terminal and Output is performed as the other input terminal of the third input terminals.

  A fourth display device of the present invention includes a display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix. In addition, a drive unit for driving each pixel is provided. The drive unit includes a plurality of inverter circuits provided for each scanning line, and each inverter circuit includes the same components as the fourth inverter circuit.

  In the first to fourth inverter circuits and the first to fourth display devices of the present invention, the fourth transistor and the fifth transistor connected between the gate of the second transistor and the fourth voltage line, By the on / off operation of the third transistor connected between the gate of the transistor and the third voltage line, the first transistor and the second transistor are prevented from being turned on simultaneously over the period, or the voltage of the input terminal is raised. It can be turned on at the same time only when it is lowered. Thus, in the present invention, the through current can be controlled by the on / off operation of the third transistor, the fourth transistor, and the fifth transistor.

  According to the first to fourth inverter circuits and the first to fourth display devices of the present invention, the through current is controlled by the on / off operation of the third transistor, the fourth transistor, and the fifth transistor. Power consumption can be reduced.

It is a circuit diagram showing an example of the inverter circuit which concerns on one embodiment of this invention. FIG. 2 is a waveform diagram illustrating an example of input / output signal waveforms of the inverter circuit of FIG. 1. FIG. 2 is a circuit diagram for explaining an example of the operation of the inverter circuit of FIG. 1. FIG. 4 is a circuit diagram for explaining an example of an operation following FIG. 3. FIG. 5 is a circuit diagram for explaining an example of an operation following FIG. 4. FIG. 6 is a circuit diagram for explaining an example of an operation following FIG. 5. FIG. 7 is a circuit diagram for explaining an example of an operation following FIG. 6. FIG. 8 is a circuit diagram for explaining an example of an operation following FIG. 7. FIG. 4 is a circuit diagram illustrating another example of an input signal in the inverter circuit of FIG. 1. FIG. 10 is a waveform diagram illustrating another example of input / output signal waveforms of the inverter circuit of FIGS. 1 and 9. FIG. 11 is a circuit diagram illustrating an example of operation of the inverter circuit of FIG. 10. FIG. 12 is a circuit diagram for explaining an example of an operation following FIG. 11. FIG. 6 is a circuit diagram illustrating a modification of the inverter circuit of FIG. 1. FIG. 10 is a circuit diagram illustrating a modification of the inverter circuit of FIG. 9. It is a circuit diagram for demonstrating an example of operation | movement of the inverter circuit of FIG. FIG. 16 is a circuit diagram for explaining an example of an operation following FIG. 15. It is a schematic block diagram of the display apparatus which is an example of the application example of the inverter circuit which concerns on the said embodiment and its modification. FIG. 18 is a circuit diagram illustrating an example of a writing line driving circuit and a pixel circuit in FIG. 17. It is a wave form diagram showing an example of a waveform of a synchronizing signal, and an example of a signal waveform outputted to a writing line. FIG. 18 is a circuit diagram illustrating an example of an inverter circuit included in the write line driving circuit of FIG. 17. FIG. 21 is a waveform diagram illustrating an example of input / output signal waveforms of the inverter circuit of FIG. 20. It is a circuit diagram showing an example of the conventional inverter circuit. FIG. 23 is a waveform diagram illustrating an example of input / output signal waveforms of the inverter circuit of FIG. 22. It is a circuit diagram showing the other example of the conventional inverter circuit. It is a circuit diagram showing the other example of the conventional inverter circuit.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the invention will be described in detail with reference to the drawings. The description will be given in the following order.

1. Embodiment (5Tr1C inverter circuit)
2. Modified example (7Tr1C inverter circuit)
3. Application example (display device)

<1. Embodiment>
[Constitution]
FIG. 1 shows an example of the overall configuration of an inverter circuit 1 according to an embodiment of the present invention. The inverter circuit 1 outputs a pulse signal (for example, FIG. 2D) obtained by substantially inverting the signal waveform (for example, FIG. 2A) of the pulse signal input to the input terminal IN from the output terminal OUT. . The inverter circuit 1 is preferably formed on amorphous silicon or an amorphous oxide semiconductor, and includes, for example, five identical channel-type transistors T1 to T5. The inverter circuit 1 includes one capacitive element C1, three input terminals IN1, IN2, IN3, and one output terminal OUT in addition to the five transistors T1 to T5, and has a circuit configuration of 5Tr1C. It has become.

  The transistor T1 corresponds to a specific example of the “first transistor” of the present invention, the transistor T2 corresponds to a specific example of the “second transistor” of the present invention, and the transistor T3 corresponds to the “third transistor” of the present invention. This corresponds to a specific example. The transistor T4 corresponds to a specific example of the “fourth transistor” of the present invention, and the transistor T5 corresponds to a specific example of the “fifth transistor” of the present invention. The capacitive element C1 corresponds to a specific example of “a capacitive element” of the invention. The input terminal IN1 corresponds to a specific example of the “first input terminal” of the present invention, the input terminal IN2 corresponds to a specific example of the “second input terminal” of the present invention, and the input terminal IN3 corresponds to the “first input terminal” of the present invention. This corresponds to a specific example of “third input terminal”.

  The transistors T1 to T5 are thin film transistors (TFTs) of the same channel type, for example, n-channel MOS (Metal Oxide Semiconductor) type thin film transistors (TFTs). The on-resistance of the transistor T1 is smaller than the on-resistance of the transistor T2. The on-resistance of the transistor T1 is preferably sufficiently smaller than the on-resistance of the transistor T2.

  For example, the transistor T1 is connected to the output terminal OUT and the low voltage in accordance with the potential difference (or potential difference corresponding thereto) between the voltage of the input terminal IN1 (hereinafter referred to as “input voltage Vin”) and the voltage Vss of the low voltage line L1. The electrical connection with the line L1 is cut off. The gate of the transistor T1 is electrically connected to the input terminal IN1. The source or drain of the transistor T1 is electrically connected to the low voltage line L1, and the terminal not connected to the low voltage line L1 among the source and drain of the transistor T1 is electrically connected to the output terminal OUT.

  The transistor T2 includes a voltage at a terminal (hereinafter referred to as “terminal A”) that is not connected to the transistor T5, of the source or drain of the transistor T4, and a voltage at the output terminal OUT (hereinafter referred to as “output voltage Vout”). The electrical connection between the high voltage line L2 and the output terminal OUT is cut off according to the potential difference (or potential difference corresponding thereto). The gate of the transistor T2 is electrically connected to the terminal A of the transistor T4. The source or drain of the transistor T2 is electrically connected to the output terminal OUT, and the terminal not connected to the output terminal OUT among the source and drain of the transistor T2 is electrically connected to the high voltage line L2.

  The transistor T3 cuts off the electrical connection between the gate of the transistor T2 and the low voltage line L1 in accordance with the potential difference (or potential difference corresponding thereto) between the input voltage Vin and the voltage of the low voltage line L1. Yes. The gate of the transistor T3 is electrically connected to the input terminal IN1. The source or drain of the transistor T3 is electrically connected to the low voltage line L1, and the terminal not connected to the low voltage line L1 among the source and drain of the transistor T3 is electrically connected to the gate of the transistor T2. . That is, the transistors T1 and T3 are connected to the same voltage line (specifically, the low voltage line L1). Accordingly, the terminal on the low voltage line L1 side of the transistor T1 and the terminal on the low voltage line L1 side of the transistor T3 have the same potential.

  The transistor T4 has an electrical connection between the source or drain of the transistor T5 (hereinafter referred to as “terminal B”) and the gate of the transistor T2 in response to a control signal Vc1 input to the gate of the transistor T4 via the input terminal IN2. The connection is to be broken. The gate of the transistor T4 is electrically connected to the input terminal IN2. A terminal A of the transistor T4 is electrically connected to the gate of the transistor T2, and a terminal different from the terminal A among the source and drain of the transistor T4 is electrically connected to the source or drain of the transistor T5.

  The transistor T5 is electrically connected to a terminal different from the terminal A among the high voltage line L3 and the source and drain of the transistor T4 according to the control signal Vc2 input to the gate of the transistor T5 via the input terminal IN3. Is supposed to be cut off. The gate of the transistor T5 is electrically connected to the input terminal IN3. The source or drain of the transistor T5 is electrically connected to the high voltage line L3. The terminal B of the transistor T5 is electrically connected to a terminal different from the terminal A among the source and drain of the transistor T4.

  The low voltage line L1 corresponds to a specific example of “first voltage line” and “third voltage line” of the present invention. The high voltage line L2 corresponds to a specific example of the “second voltage line” of the present invention, and the high voltage line L3 corresponds to a specific example of the “fourth voltage line” of the present invention. The terminal B of the transistor T5 corresponds to a specific example of “first terminal” of the present invention.

  The high voltage lines L2 and L3 are connected to a power supply (not shown) that outputs a higher voltage (constant voltage) than the voltage of the low voltage line L1. The voltage of the high voltage line L2 is a high level voltage Vdd when the inverter circuit 1 is driven, and the voltage of the high voltage line L3 is a high level voltage Vdd when the inverter circuit 1 is driven. . The voltage of the high voltage line L3 may be the same as the voltage of the high voltage line L2, or is higher than the voltage of the high voltage line L2 (for example, a voltage higher than the high level voltage Vdd). Also good. Further, when the voltages of the high voltage lines L2 and L3 are equal to each other, the high voltage lines L2 and L3 may be configured by a common voltage line. On the other hand, the low voltage line L1 is connected to a power supply (not shown) that outputs a voltage (constant voltage) lower than the voltages of the high voltage lines L2 and L3. During the driving, the low level voltage Vss (<Vdd) is obtained.

  The input terminal IN2 is connected to a power source S1 (not shown) that outputs a predetermined pulse signal. The input terminal IN3 is connected to a power source S2 (not shown) that outputs a predetermined pulse signal. For example, as shown in FIG. 2B, the power supply S1 outputs the low-level voltage Vss as the control signal Vc1 for a predetermined period from before the input voltage Vin rises to before it falls. It has become. In FIG. 2B, the power source S1 outputs the low level voltage Vss as the control signal Vc1 for a longer time than the time during which the input voltage Vin is continuously at the high level voltage Vdd. The case where it becomes is illustrated. Further, for example, as shown in FIG. 2B, the power source S1 outputs a high level voltage Vdd as the control signal Vc1 during a period other than the above.

  On the other hand, for example, as shown in FIG. 2C, the power source S2 is connected to the high level voltage Vdd and the low level at a cycle shorter than the time during which the input voltage Vin is continuously at the high level voltage Vdd. A pulse signal in which the level voltage Vss is alternately repeated is output as the control signal Vc2.

  For example, as shown in FIG. 2C, the power source S2 is controlled so that the transistors T4 and T5 are not simultaneously turned on during the period in which the input voltage Vin is at the high level voltage Vdd. The signal Vc2 is output. Specifically, for example, as shown in FIG. 2C, the power source S2 has the input voltage Vin at a high level voltage Vdd and the control signal Vc1 applied to the input terminal IN2 is high. During the period when the level voltage is Vdd, the low level voltage Vss is output as the control signal Vc2. The “period in which the input voltage Vin is at the high level voltage Vdd” refers to a period from when the input voltage Vin rises to when it falls.

  Further, for example, as shown in FIG. 2C, the power supply S2 outputs the control signal Vc2 so that the period during which the high-level voltage Vdd is output is out of the time when the input voltage Vin falls. It has become. Specifically, for example, as shown in FIG. 2C, the power source S2 outputs the high-level voltage Vdd as the control signal Vc2 immediately after the input voltage Vin falls.

  The capacitive element C1 is inserted between the gate of the transistor T2 and a terminal (that is, a terminal on the output terminal OUT side) that is not connected to the high voltage line L2 among the source and drain of the transistor T2. The capacitance of the capacitor C1 is such that when a falling voltage is input to the input terminal IN1 and the transistors T1 and T3 are turned off, the gate of the transistor T2 is a voltage higher than Vss + Vth2 and higher than Vdd−Vth4. It is a value that can be charged. Vth2 is the threshold voltage of the transistor T2, and Vth4 is the threshold voltage of the transistor T4.

  By the way, in the relationship with the conventional inverter circuit (specifically, the inverter circuit 20 in FIG. 22), the inverter circuit 1 includes a control element and a capacitive element C1 between the output stage transistors T1 and T2 and the input terminal IN1. Is equivalent to the one inserted. Here, the control element includes transistors T3, T4, and T5. This control element controls on / off of the transistors T1, T2 in the output stage by the on / off operation of the transistors T3, T4, T5 based on the input voltage Vin and the control signals Vc1, Vc2. Specifically, the control element alternately turns on the transistors T1 and T2 so that the transistors T1 and T2 in the output stage do not turn on simultaneously during the entire period. Further, the control element turns off the transistor T2 at the same time as the input voltage Vin rises, and turns on the transistor T2 immediately after the input voltage Vin falls.

[Operation]
Next, an example of the operation of the inverter circuit 1 will be described with reference to FIGS. 3 to 8 are circuit diagrams illustrating an example of a series of operations of the inverter circuit 1.

  First, as shown in FIG. 3, in the period t1, the input voltage Vin is the low level voltage Vss, and the transistors T1 and T3 are turned off. In the period t1, a high level voltage Vdd is applied to the input terminal IN2 as the control signal Vc1. Further, in the period t1, a pulse signal in which the high level voltage Vdd and the low level voltage Vss are alternately repeated in a short cycle is applied to the input terminal IN3 as the control signal Vc2.

  At this time, as shown in FIG. 3, since the gate potential of the transistor T2 becomes Vx and Vx is higher than Vdd + Vth2, the transistor T2 is turned on, and Vdd is output as the output voltage Vout (details will be described later). Further, since Vx is larger than Vdd−Vth4 and almost no current flows from the gate of the transistor T2 to the transistor T4, the potential of each node hardly changes.

  Next, as shown in FIG. 4, the voltage of the input terminal IN2 changes from the high level voltage Vdd to the low level voltage Vss (that is, falls), and shifts from the period t1 to the period t2. Accordingly, the transistor T4 is turned off, so that the potential of each node does not change even if the voltage of the input terminal IN3 changes to the high level voltage Vdd or the low level voltage Vss. The output voltage Vout remains at Vdd.

  Next, as shown in FIG. 5, the input voltage Vin changes from the low level voltage Vss to the high level voltage Vdd (that is, rises), and shifts from the period t2 to the period t3. As a result, the transistors T1 and T3 are turned on, and the gate of the transistor T2 and the output terminal OUT are charged to Vss. As a result, the gate-source voltage Vgs2 of the transistor T2 becomes 0V, and the transistor T2 is turned off (when Vth2 is greater than 0V). Further, during the period t3, the voltage at the input terminal IN3 changes to the high level voltage Vdd or changes to the low level voltage Vss. However, since the transistor T4 is off, the gate potential of the transistor T2 is changed. Does not change. That is, in the period t3, no through current flows from the high voltage line L2 to the low voltage line L1.

  After a certain period of time, as shown in FIG. 6, when the input voltage Vin is the high level voltage Vdd and the voltage of the input terminal IN3 is the low level voltage Vss, the voltage of the input terminal IN2 Changes from the low-level voltage Vss to the high-level voltage Vdd (that is, rises), and shifts from the period t3 to the period t4. Accordingly, the transistor T4 is turned on, and the potential at the connection point between the transistor T4 and the transistor T5 is charged to Vss. At this time, since the voltage of the input terminal IN3 is the low level voltage Vss, no through current flows at this time.

  Next, as shown in FIG. 7, the input voltage Vin changes from the high level voltage Vdd to the low level voltage Vss (that is, falls), and shifts from the period t4 to the period t5. Thus, the transistors T1 and T3 are turned off, but the potential of each node does not change.

  Further, as shown in FIG. 8, the voltage at the input terminal IN3 changes from the low level voltage Vss to the high level voltage Vdd (that is, rises), and shifts from the period t5 to the period t6. As a result, the gate potential of the transistor T2 starts to gradually rise from the low level voltage Vss via the transistors T4 and T5, and when the gate potential of the transistor T2 exceeds Vss + Vth2, the voltage Vgs2 becomes larger than the threshold voltage Vth2. . As a result, the transistor T2 is turned on, a current flows from the high voltage line L2, and the source voltage (that is, the output voltage Vout) of the transistor T2 starts to rise.

  At this time, since the capacitive element C1 is connected between the gate and source of the transistor T2, the gate voltage of the transistor T2 also rises as the source voltage increases. When the gate voltage of the transistor T2 becomes higher than Vdd−Vth4, the transistor T4 is turned off, and the gate voltage of the transistor T2 continues to rise only by the rise of the source voltage via the capacitor C1. Finally, the gate voltage of the transistor T2 becomes Va, and the high level voltage Vdd is output as the output voltage Vout.

  As described above, in the inverter circuit 1 according to the present embodiment, the pulse signal (for example, FIG. 2B) obtained by substantially inverting the signal waveform (for example, FIG. 2A) of the pulse signal input to the input terminal IN. ) Is output from the output terminal OUT.

[effect]
Incidentally, for example, the conventional inverter circuit 10 as shown in FIG. 22 has a single-channel circuit configuration in which two n-channel MOS transistors T10 and T20 are connected in series. In the inverter circuit 10, for example, as shown in FIG. 23, when the input voltage Vin is Vss, the output voltage Vout does not become Vdd but Vdd−Vth. That is, the output voltage Vout includes the threshold voltage Vth of the transistor T20, and the output voltage Vout is greatly affected by variations in the threshold voltage Vth of the transistor T2.

  Therefore, for example, as shown in the inverter circuit 20 of FIG. 24, the gate and the drain of the transistor T20 are electrically separated from each other, and a high voltage to which a voltage Vss2 (= Vdd + Vth) higher than the drain voltage Vdd is applied. It is conceivable to connect a gate to the wiring L30. Further, for example, a bootstrap type circuit configuration as shown in the inverter circuit 30 of FIG. 25 is conceivable.

  However, in any of the circuits of FIGS. 22, 24, and 25, until the input voltage Vin is high, that is, until the output voltage Vout is low, through the transistors T10 and T20, A current (through current) flows from the high voltage wiring L20 side toward the low voltage wiring L10 side. As a result, power consumption in the inverter circuit also increases.

  On the other hand, in the inverter circuit 1 of the present embodiment, the transistors T4 and T5 connected between the gate of the transistor T2 and the high voltage line L3 and the gate of the transistor T2 and the low voltage line L1 are connected. By the on / off operation with the transistor T3, the transistors T1 and T2 can be prevented from being simultaneously turned on over the entire period. As described above, in this embodiment, since no through current is generated over the entire period, the power consumption can be reduced as compared with the inverter circuits illustrated in FIGS. 22, 24, and 25.

<2. Modification>
[Modification 1]
In the above embodiment, the control signal Vc1 is applied to the input terminal IN2, and the control signal Vc2 is applied to the input terminal IN3. For example, as shown in FIG. The control signal Vc2 may be applied to the terminal IN2, and the control signal Vc1 may be applied to the input terminal IN3. Even in this case, since no through current is generated over the entire period, the power consumption can be kept low as in the case of the above embodiment.

[Modification 2]
In the above embodiment, the control signal Vc2 is input to the input terminal IN3 so that the period during which the high-level voltage Vdd is output deviates from the time when the input voltage Vin falls. The control signal Vc2 may be input to the input terminal IN3 so that the period during which the input voltage Vin falls includes the time when the input voltage Vin falls. For example, as shown in FIG. 10, the high-level voltage Vdd may be input to the input terminal IN3 as the control signal Vc2 immediately before the input voltage Vin falls. For example, although not shown, the high level voltage Vdd may be input to the input terminal IN3 as the control signal Vc2 at the same time when the input voltage Vin falls. That is, there may be a slight period (hereinafter referred to as “overlap period”) in which the voltages of the input terminals IN1, IN2, and IN3 are both at the high level voltage Vdd. The operation during the overlap period will be described below.

  As shown in FIG. 11, the voltage at the input terminal IN3 changes from the low level voltage Vss to the high level voltage Vdd during the period t4 when both the voltages at the input terminals IN1 and IN2 are at the high level voltage Vdd. (I.e., rising), the period transitions from the period t4 to the period t7. At this time, since the voltages of the input terminals IN2 and IN3 are both the high level voltage Vdd, the transistors T4 and T5 are both turned on. Therefore, a current flows from the high voltage line L3 to the low voltage line L1 via the transistors T3, T4, and T5, and the gate potential of the transistor T2 becomes Vb. At this time, since Vb is larger than Vss + Vth2, the transistor T2 is also turned on, and a current flows from the high voltage line L2 to the low voltage line L1 via the transistors T1 and T2. As a result, the output voltage Vout changes from the low level voltage Vss to Vss + ΔV. However, when the on-resistance of the transistor T1 is sufficiently smaller than the on-resistance of the transistor T2, ΔV≈0.

  Immediately thereafter, the input voltage Vin changes from the high level voltage Vdd to the low level voltage Vss (that is, falls), and shifts from the period t7 to the period t8. Thereby, the transistors T1 and T3 are turned off. Here, since the voltage Vgs2 between the gate and the source of the transistor T2 is equal to or higher than the threshold voltage Vth2, a current flows from the high voltage line L2, as shown in FIG. As a result, the gate voltage of the transistor T2 rises due to the increase of the source voltage via the capacitive element C1 in addition to the writing by the transistors T4 and T5 (in the figure, it rises by ΔV2), and finally the high level voltage Vdd. Is output as the output voltage Vout. Thus, when the output voltage Vout changes from the low level voltage Vss to the high level voltage Vdd, the transient of the output voltage Vout can be accelerated by setting the gate voltage of the transistor T2 high in advance. . As a result, the inverter circuit 1 can be operated at high speed.

[Modification 3]
In the second modification, as shown in FIG. 11, a through current flows through the transistors T1 and T2 for a short period from immediately before the input voltage Vin falls to immediately after it falls. In general, since an inverter circuit is often used as a buffer for driving a load, the size of the transistor forming the output stage is designed to be large (that is, the resistance is designed to be small). Therefore, when a through current flows through the transistors T1 and T2 as shown in FIG. 11, the through current may become very large although it is a short time.

  Therefore, for example, as shown in FIGS. 13 and 14, it is preferable that transistors T6 and T7 are further provided in the output stage of the inverter circuit 1 shown in FIGS.

  In this case, the transistor T2 has a voltage difference between the high voltage line L4 and the gate of the transistor T7 in accordance with a potential difference (or a corresponding potential difference) between the source or drain voltage of the transistor T4 and the gate voltage of the transistor T7. The electrical connection is cut off. In the transistor T2, the gate is connected to the source or drain of the transistor T4. In the transistor T2, one of the source and the drain is connected to the high voltage line L4, and the other of the source and the drain is connected to the gate of the transistor T7.

  The transistor T6 cuts off the electrical connection between the output terminal OUT and the low voltage line L1 according to the potential difference (or potential difference corresponding thereto) between the voltage of the input terminal IN1 and the voltage of the low voltage line L1. ing. In the transistor T6, the gate is connected to the input terminal IN1. In the transistor T6, one of the source and the drain is connected to the low voltage line L1, and the other of the source and the drain is connected to the output terminal OUT.

  The transistor T7 cuts off the electrical connection between the high voltage line L2 and the output terminal OUT in accordance with the potential difference (or potential difference corresponding thereto) between the gate voltage of the transistor T7 and the voltage of the output terminal OUT. It has become. In the transistor T7, the gate is connected to a terminal not connected to the high voltage line L2 among the source and drain of the transistor T2. In the transistor T7, one of the source and the drain is connected to the high voltage line L2, and the other of the source and the drain is connected to the output terminal OUT.

  The high voltage line L4 is connected to a power supply (not shown) that outputs a higher voltage (constant voltage) than the voltage of the high voltage line L2. The voltage of the high voltage line L2 is Vcc when the inverter circuit 1 is driven. Note that the voltage Vcc of the high voltage line L3 is preferably higher than Vdd + Vth7. Vth7 is a threshold voltage of the transistor T7.

  The transistor T6 corresponds to a specific example of “sixth transistor” of the present invention, and the transistor T7 corresponds to a specific example of “seventh transistor” of the present invention. The high voltage line L2 corresponds to a “sixth voltage line” of the present invention, and the high voltage line L4 corresponds to a specific example of a “second voltage line” of the present invention.

  15 and 16 show an example of the operation of the inverter circuit 1 when the above-described overlap period is provided in this modification.

  As shown in FIG. 15, the voltage at the input terminal IN3 changes from the low level voltage Vss to the high level voltage Vdd during the period t4 when both the voltages at the input terminals IN1 and IN2 are at the high level voltage Vdd. (I.e., rising), the period t4 is shifted to the period t7. As a result, a current flows from the high voltage line L3 to the low voltage line L1 via the transistors T3, T4, and T5, and the gate potential of the transistor T2 becomes Vb. At this time, since Vb is larger than Vss + Vth2, the transistor T2 is turned on, and a current flows from the high voltage line L2 to the low voltage line L1 via the transistors T1 and T2. As a result, the output voltage Vout changes from the low level voltage Vss to Vss + ΔV. However, when the on-resistance of the transistor T1 is sufficiently smaller than the on-resistance of the transistor T2, ΔV≈0. Further, since ΔV is smaller than the threshold voltage of the transistor T7 and the transistor T7 is not turned on, no through current flows in the final stage.

  Immediately thereafter, the input voltage Vin changes from the high level voltage Vdd to the low level voltage Vss (that is, falls), and shifts from the period t7 to the period t8. Thereby, the transistors T1, T3, and T6 are turned off. Here, since the gate-source voltage Vgs2 of the transistor T2 is equal to or higher than the threshold voltage Vth2, a current flows from the high voltage line L4 as shown in FIG. As a result, the gate voltage of the transistor T2 increases due to the increase of the source voltage via the capacitive element C1 in addition to the writing by the transistors T4 and T5 (in the drawing, it increases by ΔV2). As a result of the rise in the gate voltage of the transistor T2, the gate voltage of the transistor T7 finally becomes the high level voltage Vdd. At this time, when the gate-source voltage of the transistor T7 becomes equal to or higher than the threshold voltage Vth7, the transistor T7 is turned on, and accordingly, the high-level voltage Vdd is output as the output voltage Vout.

  Incidentally, the transient of the gate voltage of the transistor T7 can be accelerated by setting the gate-source voltage Vgs2 of the transistor T2 to be equal to or higher than the threshold voltage Vth2. Further, since the transient of the transistor T7 is accelerated, the transient of the output voltage Vout can be also accelerated. Therefore, the inverter circuit 1 can be operated at high speed.

  Further, since transistors T6 and T7 that do not flow through current are provided at the subsequent stage of the inverter circuit 1, it is possible to prevent the through current from increasing when a load is connected to the output terminal OUT of the inverter circuit 1. be able to. Further, when no overlap period is provided, it is possible to eliminate the through current over the entire period.

<3. Application example>
FIG. 17 illustrates an example of the overall configuration of the display device 100 which is an example of an application example of the inverter circuit 1 according to the embodiment and the modification thereof. The display device 100 includes, for example, a display panel 110 and a drive circuit 120 that drives the display panel 110. The display panel 110 corresponds to a specific example of the “display unit” of the present invention, and the drive circuit 120 corresponds to a specific example of the “drive unit” of the present invention.

(Display panel 110)
The display panel 110 has a display area 110A in which a plurality of display pixels 114 are two-dimensionally arranged, and each display pixel 114 is driven by a drive circuit 120 to display an image on the display area 110A. is there. Each display pixel 114 includes three pixels 113R, 113G, and 113B adjacent to each other. Hereinafter, the pixel 113 is appropriately used as a general term for the pixels 113R, 113G, and 113B.

  The pixel 113R includes an organic EL element 111R and a pixel circuit 112. The pixel 113G includes an organic EL element 111G and a pixel circuit 112. The pixel 113B includes an organic EL element 111B and a pixel circuit 112. The organic EL element 111R is an organic EL element that emits red light, the organic EL element 111G is an organic EL element that emits green light, and the organic EL element 111B is an organic EL element that emits blue light. Hereinafter, the organic EL element 111 is appropriately used as a general term for the organic EL elements 111R, 111G, and 111B.

  FIG. 18 illustrates an example of a circuit configuration in the display area 110 </ b> A together with an example of a writing line driving circuit 124 described later. In the display area 110 </ b> A, a plurality of pixel circuits 112 are two-dimensionally arranged in pairs with the individual organic EL elements 111. Each pixel circuit 112 includes, for example, a drive transistor T100 that controls a current flowing through the organic EL element 111, a write transistor T200 that writes the voltage of the signal line DTL into the drive transistor T100, and a storage capacitor Cs. 2Tr1C circuit configuration. The drive transistor T100 and the write transistor T200 are formed of, for example, an n-channel MOS thin film transistor (TFT). The drive transistor T100 or the write transistor T200 may be, for example, a p-channel MOS type TFT.

  In display area 110A, a plurality of write lines WSL are arranged in rows, and a plurality of signal lines DTL are arranged in columns. The write line WSL corresponds to a specific example of “scan line” of the present invention. In the display area 110A, a plurality of power supply lines PSL (members to which power supply voltage is supplied) are further arranged in rows along the write lines WSL. One organic EL element 111 is provided near the intersection of each signal line DTL and each write line WSL. Each signal line DTL is connected to an output end of a signal line drive circuit 123 described later and one of a drain electrode and a source electrode of the write transistor T200. Each write line WSL is connected to an output terminal of a write line drive circuit 124 described later and a gate electrode of the write transistor T200. Each power supply line PSL is connected to an output terminal of a power supply line drive circuit 125 described later and one of a drain electrode and a source electrode of the drive transistor T100. Of the drain electrode and the source electrode of the writing transistor T200, the electrode not connected to the signal line DTL is connected to the gate electrode of the driving transistor T100 and one end of the storage capacitor Cs. Of the drain electrode and the source electrode of the driving transistor T100, the electrode not connected to the power supply line PSL and the other end of the storage capacitor Cs are connected to the anode electrode (not shown) of the organic EL element 111. The cathode electrode of the organic EL element 111 is connected to the ground line GND, for example.

(Drive circuit 120)
Next, each circuit in the drive circuit 120 will be described with reference to FIGS. 17, 18, and 19. FIG. 19 shows an example of the waveform of the synchronization signal and an example of a voltage waveform output from the drive circuit 120 to each write line WSL. The drive circuit 120 includes a timing generation circuit 121, a video signal processing circuit 122, a signal line drive circuit 123, a write line drive circuit 124, and a power supply line drive circuit 125. The drive circuit 120 also includes various power sources (specifically, power sources connected to the low voltage line L1, the high voltage lines L2, L3, L4, and the like) in the above-described embodiment and modifications thereof.

  The timing generation circuit 121 controls the video signal processing circuit 122, the signal line drive circuit 123, the write line drive circuit 124, and the power supply line drive circuit 125 to operate in conjunction with each other. The timing generation circuit 121 outputs a control signal 121A to each circuit described above, for example, in response to (in synchronization with) the synchronization signal 120B input from the outside.

  The video signal processing circuit 122 performs predetermined correction on the video signal 120 </ b> A input from the outside, and outputs the corrected video signal 122 </ b> A to the signal line driving circuit 123. Examples of the predetermined correction include gamma correction and overdrive correction.

  In response to (in synchronization with) the input of the control signal 121A, the signal line driver circuit 123 applies the video signal 122A input from the video signal processing circuit 122 to each signal line DTL and writes it to the pixel 113 to be selected. Is. Note that writing refers to applying a predetermined voltage to the gate of the driving transistor T100.

  The signal line driver circuit 123 includes, for example, a shift register (not shown), and includes a buffer circuit (not shown) for each stage corresponding to each column of the pixels 113. The signal line driving circuit 123 can output, for example, two types of voltages (Vofs, Vsig) to each signal line DTL in response to (in synchronization with) the input of the control signal 121A. Specifically, the signal line driver circuit 123 sequentially applies two types of voltages (Vofs, Vsig) to the pixel 113 selected by the write line driver circuit 124 via the signal line DTL connected to each pixel 113. To supply.

  Here, the offset voltage Vofs has a constant voltage value regardless of the value of the signal voltage Vsig. The signal voltage Vsig is a voltage value corresponding to the video signal 122A. The minimum voltage of the signal voltage Vsig is a voltage value lower than the offset voltage Vofs, and the maximum voltage of the signal voltage Vsig is a voltage value higher than the offset voltage Vofs.

  The write line driving circuit 124 includes, for example, a shift register (not shown), and includes a buffer circuit 2 for each stage corresponding to each row of the pixels 113. The buffer circuit 2 includes a plurality of the inverter circuits 1 described above, and outputs a pulse signal having substantially the same phase as the pulse signal input to the input terminal from the output terminal. The write line driving circuit 124 can output two types of voltages (Vdd, Vss) to each write line WSL in response to (in synchronization with) the input of the control signal 121A. Specifically, the write line drive circuit 124 supplies two types of voltages (Vdd, Vss) to the drive target pixel 113 via the write line WSL connected to each pixel 113, and the write transistor T200. Is to control. For example, as shown in FIG. 19, when a clock ck and a scan pulse sp are input as the control signal 121A, the write line driving circuit 124 has a peak value Vdd for a plurality of write lines WSL. Thus, a voltage Vs (i) including a pulse having a width of 2H (1 ≦ i ≦ N, i and N are positive integers) is sequentially output while shifting the phase of the pulse by 1H.

  Here, the voltage Vdd has a value equal to or higher than the ON voltage of the write transistor T200. The voltage Vdd is, for example, a voltage value output from the write line driving circuit 124 during threshold correction, mobility correction, and light emission operation. The voltage Vss is lower than the on-voltage of the write transistor T200 and lower than the voltage Vdd.

  The power supply line driving circuit 125 includes a shift register (not shown), for example, and includes a buffer circuit (not shown) for each stage corresponding to each row of the pixels 113, for example. The power supply line driving circuit 125 can output two types of voltages (VccH and VccL) in response to (in synchronization with) the input of the control signal 121A. Specifically, the power supply line drive circuit 125 supplies two types of voltages (VccH and VccL) to the drive target pixel 113 via the power supply line PSL connected to each pixel 113, and the organic EL element 111. Light emission and quenching are controlled.

  Here, the voltage VccL is a voltage value lower than a voltage obtained by adding the threshold voltage of the organic EL element 111 and the voltage of the cathode of the organic EL element 111. The voltage VccH is a voltage value equal to or higher than the sum of the threshold voltage of the organic EL element 111 and the cathode voltage of the organic EL element 111.

  In the display device 100, the pixel circuit 112 is controlled to be turned on / off in each pixel 113, and a driving current is injected into the organic EL element 111 of each pixel 113, whereby holes and electrons are recombined to emit light, Light is extracted outside. As a result, an image is displayed in the display area 110 </ b> A of the display panel 110.

  By the way, in this application example, for example, the buffer circuit 2 in the write line drive circuit 124 includes a plurality of the inverter circuits 1 described above. Thereby, since there is almost no through current flowing in the buffer circuit 2, the power consumption of the buffer circuit 2 can be suppressed.

  In this application example, the write line driver circuit 124 turns off the transistor T4 or the transistor T5 so that the transistor T4 or the transistor T5 is turned off for a time equal to the time during which the voltage at the input terminal IN1 is continuously high. A control signal may be input to the gate. In this case, the write line driving circuit 124, for example, as shown in FIGS. 20 and 21, the signal (output voltage Vout) output from the output terminal OUT of the inverter circuit 1 provided for each write line WSL. (I) = Vs (i)) (or a signal corresponding thereto) is output to the write line WSL. The write line driving circuit 124 further outputs a signal (output voltage Vout (i−1)) output from the output terminal OUT of the inverter circuit 1 provided corresponding to the (i−1) th write line WSL. Alternatively, an inverted signal obtained by inverting the corresponding signal) may be input to the gate of the transistor T4 included in the inverter circuit 1 provided corresponding to the i-th write line WSL. Although not shown, the write line drive circuit 124 inputs the above inverted signal to the gate of the transistor T5 included in the inverter circuit 1 provided corresponding to the i-th write line WSL. It may be.

  In this case, it is not necessary to separately provide a circuit for generating a control signal to be input to the gate of the transistor T4 or the transistor T5, so that the circuit configuration of the display device 100 can be simplified. When the inverted signal is input to the gate of the transistor T4 or transistor T5 included in the inverter circuit 1 provided corresponding to the i-th write line WSL, instead of the circuit shown in FIG. The circuit described in FIG. 13 or FIG. 14 may be used.

  The present invention has been described with the embodiment, the modification, and the application example. However, the present invention is not limited to the embodiment and the like, and various modifications can be made.

  For example, in the application example described above, the inverter circuit 1 according to each of the above-described embodiments and modifications thereof is used in the output stage of the write line drive circuit 124, but instead of the output stage of the write line drive circuit 124. The output stage of the power supply line driving circuit 125 may be used, or the output stage of the power supply line driving circuit 125 may be used together with the output stage of the write line driving circuit 124.

  Note that when the inverter circuit 1 according to each of the above-described embodiments and modifications thereof is used in the output stage of the power supply line driving circuit 125, for example, a power supply (not shown) that outputs the voltage VccL to the low voltage line L1. And a power source (not shown) that outputs a voltage VccH to the high voltage lines L2 and L3, and a power source (a power that outputs a voltage higher than the voltage VccH) to the high voltage line L4. (Not shown) may be connected.

  DESCRIPTION OF SYMBOLS 1,20,30,40 ... Inverter circuit, 2 ... Buffer circuit, 100 ... Display apparatus, 110 ... Display panel, 110A ... Display area, 111, 111R, 111G, 111B ... Organic EL element, 112 ... Pixel circuit, 113, 113R, 113G, 113B ... pixels, 114 ... display pixels, 120 ... drive circuit, 120A, 122A ... video signal, 120B ... synchronization signal, 121 ... timing generation circuit, 121A ... control signal, 122 ... video signal processing circuit, 123 ... Signal line drive circuit, 124 ... write line drive circuit, 125 ... power supply line drive circuit, A, B ... terminal, C, D ... connection point, C1 ... capacitance element, Cs ... retention capacitor, DTL ... signal line, GND ... Ground line, IN1, IN2, IN3 ... input terminal, L1 ... low voltage line, L2, L3, L4 ... high voltage line, OUT ... output terminal, PSL ... electric Line, S1, S2 ... Power source, t1-t8 ... Period, T1-T7, T10, T20, T30 ... Transistor, T100 ... Drive transistor, T200 ... Write transistor, Vc1, Vc2 ... Control signal, Vcc, VccH, VccL, Vdd , Vss ... voltage, Vgs2 ... gate-source voltage, Vin ... input voltage, Vofs ... offset voltage, Vout ... output voltage, Vsig ... signal voltage, Vth, Vth2, Vth4, Vth5, Vth7 ... threshold voltage, WSL ... Barbed wire.

Claims (15)

A first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor of the same channel type;
Input and output terminals;
A capacitive element ;
A power source that inputs a first control signal to the gate of the fourth transistor and a second control signal to the gate of the fifth transistor ;
The first transistor disconnects the electrical connection between the output terminal and the first voltage line according to a potential difference between the voltage of the input terminal and the voltage of the first voltage line or a corresponding potential difference. And
The second transistor has an electrical connection between the second voltage line and the output terminal according to a potential difference between a voltage at the source or drain of the fourth transistor and a voltage at the output terminal or a corresponding potential difference. Have come to refuse,
The third transistor cuts off the electrical connection between the gate of the second transistor and the third voltage line according to a potential difference between the voltage of the input terminal and the voltage of the third voltage line or a corresponding potential difference. Is supposed to
The fourth transistor is configured to cut off an electrical connection between the first terminal, which is the source or drain of the fifth transistor, and the gate of the second transistor in response to the first control signal .
The fifth transistor is adapted to cut off an electrical connection between the fourth voltage line and the first terminal in response to the second control signal .
The capacitive element is inserted between the gate of the second transistor and the terminal on the output terminal side of the source and drain of the second transistor ,
The power supply outputs a low-level voltage as one of the first control signal and the second control signal from before the voltage of the input terminal rises to before it falls. Furthermore, while the voltage at the input terminal is a high level voltage and the one control signal is at a high level voltage, the low level voltage is changed to the first control signal and An inverter circuit configured to output the other control signal of the second control signals . A first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor of the same channel type;
A first input terminal, a second input terminal, a third input terminal and an output terminal;
A capacitive element ;
A power source that inputs a first control signal to the gate of the fourth transistor and a second control signal to the gate of the fifth transistor ;
In the first transistor, a gate is connected to the first input terminal, one of a source and a drain is connected to a first voltage line, and the other of the source and the drain is connected to the output terminal,
In the second transistor, a gate is connected to a source or a drain of the fourth transistor, one of the source and the drain is connected to a second voltage line, and the other of the source and the drain is connected to the output terminal,
In the third transistor, a gate is connected to the first input terminal, one of a source and a drain is connected to a third voltage line, and the other of the source and the drain is connected to a gate of the second transistor,
In the fourth transistor, the gate is connected to the second input terminal, one of the source and drain is connected to the gate of the second transistor, and the other of the source and drain is connected to the source or drain of the fifth transistor. And
In the fifth transistor, the gate is connected to the third input terminal, one of the source and the drain is connected to the fourth voltage line, and the other of the source and the drain is the second of the source and the drain of the fourth transistor. Connected to a terminal not connected to the gate of two transistors,
The capacitive element is inserted between the gate of the second transistor and a terminal not connected to the second voltage line among the source and drain of the second transistor ,
The power supply outputs a low-level voltage to one of the second input terminal and the third input terminal from before the voltage at the first input terminal rises to before it falls. Furthermore, while the voltage of the first input terminal is a high level voltage and the voltage of the one input terminal is a high level voltage, the low level voltage is An inverter circuit configured to output as the other input terminal of the second input terminal and the third input terminal . A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor of the same channel type;
Input and output terminals;
A capacitive element ;
A power source that inputs a first control signal to the gate of the fourth transistor and a second control signal to the gate of the fifth transistor ;
The first transistor interrupts electrical connection between the gate of the seventh transistor and the first voltage line according to a potential difference between the voltage of the input terminal and the voltage of the first voltage line or a potential difference corresponding thereto. Is supposed to
The second transistor has a voltage difference between a source voltage or a drain voltage of the fourth transistor and a gate voltage of the seventh transistor or a corresponding potential difference between the second voltage line and the gate of the seventh transistor. The traditional connection is interrupted,
The third transistor cuts off the electrical connection between the gate of the second transistor and the third voltage line according to a potential difference between the voltage of the input terminal and the voltage of the third voltage line or a corresponding potential difference. Is supposed to
The fourth transistor is configured to cut off an electrical connection between the first terminal, which is the source or drain of the fifth transistor, and the gate of the second transistor in response to the first control signal .
The fifth transistor is adapted to cut off an electrical connection between the fourth voltage line and the first terminal in response to the second control signal .
The sixth transistor may disconnect the electrical connection between the output terminal and the fifth voltage line according to a potential difference between the voltage of the input terminal and the voltage of the fifth voltage line or a corresponding potential difference. And
The seventh transistor interrupts the electrical connection between the sixth voltage line and the output terminal according to a potential difference between the gate voltage of the seventh transistor and the voltage of the output terminal or a potential difference corresponding thereto. And
The capacitive element is inserted between the gate of the second transistor and the terminal on the output terminal side of the source and drain of the second transistor ,
The power supply outputs a low-level voltage as one of the first control signal and the second control signal from before the voltage of the input terminal rises to before it falls. Furthermore, while the voltage at the input terminal is a high level voltage and the one control signal is at a high level voltage, the low level voltage is changed to the first control signal and An inverter circuit configured to output the other control signal of the second control signals . A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor of the same channel type;
A first input terminal, a second input terminal, a third input terminal and an output terminal;
A capacitive element ;
A power source that inputs a first control signal to the gate of the fourth transistor and a second control signal to the gate of the fifth transistor ;
In the first transistor, a gate is connected to the first input terminal, one of a source and a drain is connected to a first voltage line, and the other of the source and the drain is connected to a gate of the seventh transistor,
In the second transistor, the gate is connected to the source or drain of the fourth transistor, one of the source and drain is connected to the second voltage line, and the other of the source and drain is connected to the gate of the seventh transistor. And
In the third transistor, a gate is connected to the first input terminal, one of a source and a drain is connected to a third voltage line, and the other of the source and the drain is connected to a gate of the second transistor,
In the fourth transistor, the gate is connected to the second input terminal, one of the source and drain is connected to the gate of the second transistor, and the other of the source and drain is connected to the source or drain of the fifth transistor. And
In the fifth transistor, the gate is connected to the third input terminal, one of the source and the drain is connected to the fourth voltage line, and the other of the source and the drain is the second of the source and the drain of the fourth transistor. Connected to a terminal not connected to the gate of two transistors,
In the sixth transistor, a gate is connected to the first input terminal, one of a source and a drain is connected to a fifth voltage line, and the other of the source and the drain is connected to the output terminal,
In the seventh transistor, a gate is connected to a terminal not connected to the second voltage line among a source and a drain of the second transistor, and one of the source and the drain is connected to a sixth voltage line. The other of which is connected to the output terminal,
The capacitive element is inserted between the gate of the second transistor and a terminal not connected to the second voltage line among the source and drain of the second transistor ,
The power supply outputs a low-level voltage to one of the second input terminal and the third input terminal from before the voltage at the first input terminal rises to before it falls. Furthermore, while the voltage of the first input terminal is a high level voltage and the voltage of the one input terminal is a high level voltage, the low level voltage is An inverter circuit configured to output as the other input terminal of the second input terminal and the third input terminal . The inverter circuit according to any one of claims 1 to 4, wherein the first voltage line and the third voltage line are at the same potential. The inverter circuit according to claim 5, wherein the second voltage line and the fourth voltage line have the same potential. The inverter circuit according to claim 6, wherein the second voltage line and the fourth voltage line are connected to a power supply that outputs a voltage higher than the voltages of the first voltage line and the third voltage line. The inverter circuit according to claim 5, wherein an on-resistance of the first transistor is smaller than an on-resistance of the second transistor. A display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix;
And a driving unit for driving each pixel,
The drive unit is
A plurality of inverter circuits provided for each of the scanning lines ;
A power source for driving the plurality of inverter circuits ,
The inverter circuit is
A first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor of the same channel type;
A first input terminal and an output terminal;
A capacitive element,
The first transistor cuts off an electrical connection between the output terminal and the first voltage line according to a potential difference between the voltage of the first input terminal and the voltage of the first voltage line or a corresponding potential difference. And
The second transistor has an electrical connection between the second voltage line and the output terminal according to a potential difference between a voltage at the source or drain of the fourth transistor and a voltage at the output terminal or a corresponding potential difference. Have come to refuse,
The third transistor electrically connects the gate of the second transistor and the third voltage line according to the potential difference between the voltage of the first input terminal and the voltage of the third voltage line or the corresponding potential difference. It is supposed to be relayed,
The fourth transistor electrically connects the first terminal, which is the source or drain of the fifth transistor, and the gate of the second transistor according to a first control signal input to the gate of the fourth transistor. It is supposed to be relayed,
The fifth transistor cuts off the electrical connection between the fourth voltage line and the first terminal in response to a second control signal input to the gate of the fifth transistor.
The capacitive element is inserted between the gate of the second transistor and the terminal on the output terminal side of the source and drain of the second transistor ,
The power supply is configured to input a first control signal to the gate of the fourth transistor and to input a second control signal to the gate of the fifth transistor,
The power supply outputs a low-level voltage as one of the first control signal and the second control signal from before the voltage at the first input terminal rises to before the voltage falls. Furthermore, while the voltage of the first input terminal is a high level voltage and the one control signal is a high level voltage, the low level voltage is changed to the first level. A display device configured to output one control signal and the other control signal of the second control signal . A display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix;
And a driving unit for driving each pixel,
The drive unit is
A plurality of inverter circuits provided for each of the scanning lines ;
A power source for driving the plurality of inverter circuits ,
The inverter circuit is
A first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor of the same channel type;
A first input terminal, a second input terminal, a third input terminal and an output terminal;
A capacitive element,
In the first transistor, a gate is connected to the first input terminal, one of a source and a drain is connected to a first voltage line, and the other of the source and the drain is connected to the output terminal,
In the second transistor, a gate is connected to a source or a drain of the fourth transistor, one of the source and the drain is connected to a second voltage line, and the other of the source and the drain is connected to the output terminal,
In the third transistor, a gate is connected to the first input terminal, one of a source and a drain is connected to a third voltage line, and the other of the source and the drain is connected to a gate of the second transistor,
In the fourth transistor, the gate is connected to the second input terminal, one of the source and drain is connected to the gate of the second transistor, and the other of the source and drain is connected to the source or drain of the fifth transistor. And
In the fifth transistor, the gate is connected to the third input terminal, one of the source and the drain is connected to the fourth voltage line, and the other of the source and the drain is the second of the source and the drain of the fourth transistor. Connected to a terminal not connected to the gate of two transistors,
The capacitive element is inserted between the gate of the second transistor and a terminal not connected to the second voltage line among the source and drain of the second transistor ,
The power supply is configured to input a first control signal to the gate of the fourth transistor and to input a second control signal to the gate of the fifth transistor,
The power supply outputs a low-level voltage to one of the second input terminal and the third input terminal from before the voltage at the first input terminal rises to before it falls. Furthermore, while the voltage of the first input terminal is a high level voltage and the voltage of the one input terminal is a high level voltage, the low level voltage is A display device configured to output as the other input terminal of the second input terminal and the third input terminal . A display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix;
And a driving unit for driving each pixel,
The drive unit is
A plurality of inverter circuits provided for each of the scanning lines ;
A power source for driving the plurality of inverter circuits ,
The inverter circuit is
A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor of the same channel type;
A first input terminal and an output terminal;
A capacitive element,
The first transistor electrically connects the gate of the seventh transistor and the first voltage line according to a potential difference between the voltage of the first input terminal and the voltage of the first voltage line or a corresponding potential difference. It is supposed to be relayed,
The second transistor has a voltage difference between a source voltage or a drain voltage of the fourth transistor and a gate voltage of the seventh transistor or a corresponding potential difference between the second voltage line and the gate of the seventh transistor. The traditional connection is interrupted,
The third transistor electrically connects the gate of the second transistor and the third voltage line according to the potential difference between the voltage of the first input terminal and the voltage of the third voltage line or the corresponding potential difference. It is supposed to be relayed,
The fourth transistor cuts off the electrical connection between the first terminal, which is the source or drain of the fifth transistor, and the gate of the second transistor in accordance with a control signal input to the gate of the fourth transistor. Is supposed to
The fifth transistor cuts off the electrical connection between the fourth voltage line and the first terminal in accordance with a control signal input to the gate of the fifth transistor,
The sixth transistor cuts off an electrical connection between the output terminal and the fifth voltage line according to a potential difference between the voltage of the first input terminal and the voltage of the fifth voltage line or a corresponding potential difference. And
The seventh transistor interrupts the electrical connection between the sixth voltage line and the output terminal according to a potential difference between the gate voltage of the seventh transistor and the voltage of the output terminal or a potential difference corresponding thereto. And
The capacitive element is inserted between the gate of the second transistor and the terminal on the output terminal side of the source and drain of the second transistor ,
The power supply is configured to input a first control signal to the gate of the fourth transistor and to input a second control signal to the gate of the fifth transistor,
The power supply outputs a low-level voltage as one of the first control signal and the second control signal from before the voltage at the first input terminal rises to before the voltage falls. Furthermore, while the voltage of the first input terminal is a high level voltage and the one control signal is a high level voltage, the low level voltage is changed to the first level. A display device configured to output one control signal and the other control signal of the second control signal . A display unit including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix;
And a driving unit for driving each pixel,
The drive unit is
A plurality of inverter circuits provided for each of the scanning lines ;
A power source for driving the plurality of inverter circuits ,
The inverter circuit is
A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor of the same channel type;
A first input terminal, a second input terminal, a third input terminal and an output terminal;
A capacitive element,
In the first transistor, a gate is connected to the first input terminal, one of a source and a drain is connected to a first voltage line, and the other of the source and the drain is connected to a gate of the seventh transistor,
In the second transistor, the gate is connected to the source or drain of the fourth transistor, one of the source and drain is connected to the second voltage line, and the other of the source and drain is connected to the gate of the seventh transistor. And
In the third transistor, a gate is connected to the first input terminal, one of a source and a drain is connected to a third voltage line, and the other of the source and the drain is connected to a gate of the second transistor,
In the fourth transistor, the gate is connected to the second input terminal, one of the source and drain is connected to the gate of the second transistor, and the other of the source and drain is connected to the source or drain of the fifth transistor. And
In the fifth transistor, the gate is connected to the third input terminal, one of the source and the drain is connected to the fourth voltage line, and the other of the source and the drain is the second of the source and the drain of the fourth transistor. Connected to a terminal not connected to the gate of two transistors,
In the sixth transistor, a gate is connected to the first input terminal, one of a source and a drain is connected to a fifth voltage line, and the other of the source and the drain is connected to the output terminal,
In the seventh transistor, a gate is connected to a terminal not connected to the second voltage line among a source and a drain of the second transistor, and one of the source and the drain is connected to a sixth voltage line. The other of which is connected to the output terminal,
The capacitive element is inserted between the gate of the second transistor and a terminal not connected to the second voltage line among the source and drain of the second transistor ,
The power supply is configured to input a first control signal to the gate of the fourth transistor and to input a second control signal to the gate of the fifth transistor,
The power supply outputs a low-level voltage as one of the first control signal and the second control signal from before the voltage of the input terminal rises to before it falls. Furthermore, while the voltage at the input terminal is a high level voltage and the one control signal is at a high level voltage, the low level voltage is changed to the first control signal and A display device configured to output the other control signal of the second control signals . The power source turns on or off one of the fourth transistor and the fifth transistor in a cycle shorter than the time during which the voltage at the first input terminal is continuously high, and The other of the four transistors and the fifth transistor is turned off for a time longer than a time during which the voltage at the first input terminal is continuously high. The display device described. The power source turns on or off one of the fourth transistor and the fifth transistor in a cycle shorter than the time during which the voltage at the first input terminal is continuously high, and The other transistor of the four transistors and the fifth transistor is turned off for a time equal to a time during which the voltage at the first input terminal is continuously high. Display device. The drive section may have a said inverter circuit for each of the scanning lines,
The power source is configured to output a signal output from an output terminal of each inverter circuit or a signal corresponding thereto to the scanning line, and i−1 (1 ≦ i ≦ N, where N is a positive integer. ) An inverter provided in correspondence with the i-th scanning line is a signal output from the output terminal of the inverter circuit provided corresponding to the scanning line in the stage or an inverted signal obtained by inverting the corresponding signal. The display device according to claim 14 , wherein the display device is input to a gate of a fourth transistor or a fifth transistor of the circuit.

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