JPS59161921A - Asynchronous boot strap buffer circuit device - Google Patents

Abstract

PURPOSE:To secure the excellent driving capacity with no deterioration of speed by separating an input (output of the preceding stage) from a load transistor after detecting that the input level reaches the prescribed value and turning on a switching transistor. CONSTITUTION:The level of an output point A of the preceding stage 11 rises up and exceeds the threshold level of a transistor TRT17, the TRT17 is turned on. However a TRT15 is not turned on and therefore the potential is high at a point D with no effect given to the following stage. Then the input potential rises up, and TRT15 and T17 are turned on. When the input potential reaches the value VA which is decided by the inverter ratio between the TRT15 and T17, the potential of the point D drops suddenly to turn off a TRT13 and to raises up the potential of a point E. In this case, a TRT11 which is turned on to increase the potential of the point B is turned off to cut off an input (load C11 of the preceding stage). Thus the feedback efficiency is increased to raise suddenly the potential of the point E.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a completely statically operated asynchronous Poot-strap buffer circuit device.

(Prior Art) Conventionally, semiconductor circuit devices such as memory and logic using an asynchronous circuit system have been equipped with a buffer circuit device of an asynchronous type, that is, a completely Static type Poot-Strapp circuit devices are widely used.

FIG. 1 shows a conventional statically operated Poot strap buffer circuit device. In this Figure 1, 1
is a front-stage drive circuit whose output point A is connected to the drain of an enhanced type transistor T1 which acts as a switch gate.

The gate of this transistor T1 is connected to the power supply voltage Vcc, and the source is connected to the connection point B, ie, the gate of the enhancement type transistor T2. The drain of the transistor T2 is connected to the power supply voltage Vcc, and the source is connected to the output point and to the drain of an enhancement type transistor T3. Capacitor C3 is connected.

Furthermore, a capacitor (load capacitance) C4 is connected between the output point and ground. The source of transistor T3 is grounded.

On the other hand, the output point A of the front-stage drive circuit 1 is the transistor T1
In addition to the enhancement type transistor T
It is connected to gate 5. The drain of transistor T5 is connected to the source and gate of depletion type transistor T4, the connection point being C, which is connected to the gate of transistor T3. The drain of the transistor T4 is connected to the power supply voltage Vcc, and the source of the transistor T5 is grounded.

Note that C1 is the output load capacitance of the front-stage drive circuit 1, which is connected between the point A and the ground, and C2 is the stray capacitance at the connection point B. Further, all of the above transistors are MOS transistors.

The operation of the conventional static operation type Putot-Strap-Nocket circuit device configured as described above will be explained. First, when the output point A of the front-stage drive circuit 1 is at a low level, the transistor T1 is in a conductive state, so the connection point B
also becomes a low level, and the transistor T2 becomes non-conductive.

Further, the transistor T5 also becomes non-conductive, and since the transistor T4 is a depletion type transistor, the connection point C becomes the power supply voltage Vcc, and the transistor T
3 is in a conductive state. Therefore, the output point becomes a low level.

On the other hand, when the output point A of the pre-stage drive circuit 1 rises from a low level to a high level, the waveforms of each part are as shown in FIG.

Hereinafter, explanation will be given with reference to this waveform diagram.

First, the voltage at the output point A of the front-stage drive circuit 1 is shown in Fig. 2(a).
As shown in FIG.
As shown in FIG. 2(b), the transistor T2 becomes conductive from time t2 when the threshold value VT of the transistor T2 is exceeded.

On the other hand, the potential at output point A is the threshold value V of transistor T5.
Time exceeding T1. , the transistor T5 conducts,
The potential at the connection point C begins to fall as shown in FIG. 2(e). Then, the time 1. when the potential of this connection point C becomes lower than the threshold value VT of the transistor T3. From transistor T
3 is non-conductive, and the potential at the output point is the transistor T2.
As a result of charging from , the voltage rises as shown in FIG.

Until time t4 when the potential at the connection point B reaches the potential Vcc and the potential at the output point A of the pre-stage drive circuit I reaches the potential Vcc - VT, the transistor T1 is conductive, so the voltage increase at the connection point ΔV1 is the sum of capacitors c1 and C2 and the Poot strap capacitor c3.03/
(C1+C2+C3)×/Iv1° bamboo transistor T
It is fed back to the second gate.

After time t4, transistor T1 becomes non-conductive, so the potential increase ΔV2 at the output point is reduced by C3/(C
2+C3) XΔv2 is fed back to the gate potential of transistor T2.

Therefore, the potential increase at the output point is promoted by the two-stage feedback, and the driving ability of the buffer circuit is improved.

However, in such a conventional device, when trying to improve the driving ability of the buffer circuit, if the load capacitance ttc1 of the front stage driving circuit 1 is relatively large, the rise characteristic of the output point from time t3 to t4 is Because of this, it is necessary to increase the capacitance of the Poot-strap capacitor C3, which is equivalent to increasing the load capacitance C1 of the front-stage drive circuit 1, and also increases the load on the transistor T2. .

Furthermore, in order to improve the effectiveness of the Poot Strap, time t! Since it is necessary to leave a sufficient gap between and t3,
It is necessary to lower the drive ability of transistor T5.

Since this requires an inverter ratio between the transistor T4 and the transistor T5, the drive capability of the transistor T4 is lowered, and the discharge capability of the transistor T3 at the output point is lowered.

This means that the time required for the output point to transition from a high level to a low level increases. Therefore, in conventional devices, attempts are made to increase the driving ability of the buffer circuit, that is, the putot strap efficiency. When doing so, speed was sacrificed.

(Object of the Invention) The present invention has been made to eliminate the above-mentioned drawbacks of the conventional art, and provides an asynchronous Poot-Strap buffer circuit device that can obtain excellent driving performance without sacrificing speed. The purpose is to

(Structure of the Invention) The asynchronous Putt-Strapp-no-Future circuit device of the present invention drives an inverting circuit having an input detection level function by a front-stage drive circuit, and a switch circuit is driven by the output of the inverting circuit. This switch circuit cuts off the first input level of the buffer circuit and the output load of the preceding stage drive circuit, and also controls the second human power level of the buffer circuit.

(Embodiments) Hereinafter, embodiments of the asynchronous Poot-Strap buffer circuit device of the present invention will be described with reference to the drawings. FIG. 3 is a circuit diagram of one embodiment. In this FIG. 3, 11 is a front-stage drive circuit, its output point A is connected to the drain of an enhancement type transistor T11 (switch ink circuit), and its source is connected to a connection point B, that is, an enhancement type transistor T11 (switch ink circuit). - Connected to the gate of type transistor T12 (first input of the buffer circuit).

The Drake of the transistor T12 is connected to the power supply voltage Vcc, the source is connected to the output point E, and the drain of the enhancement type transistor T13 is connected between the output point E and the connection point 3. Strap capacitor C13 is connected.

Furthermore, a capacitor (load capacitance) C14 is connected between the output point E and the ground. The source of transistor T13 is grounded.

On the other hand, the output point A of the front-stage drive circuit 11 is the transistor 11
In addition, an enforcement type transistor T
15 and enhancement type transistor T
It is connected to 17 gates.

The drain of transistor T15 is connected to the connection point and is connected to the depletion type transistor T1.
Connected to the gate and source of 4.

The source of transistor T15 is connected to the drain of transistor T17, which is further connected to the source of enhancement type transistor T16. This connection point is C. The source of transistor T17 is grounded. →The drain of the run raster T16 is connected to the power supply voltage Vcc, and the gate is connected to the connection point.

Further, this connection point is connected to the gate of the transistor T11 and the gate of the transistor T13 (second input of the buffer circuit).

Transistor T14. T15. T16 and T17 constitute an inverter (inversion circuit), and this inverter has an input level detection function.

Note that C1l is the output load capacitance of the front-stage drive circuit 11, which is connected between the output point A and the ground, and C12 is the stray capacitance at the connection point B. Also, all the above transistors are M5S)
It is a rangister.

Next, the operation of the asynchronous Poot-Strap buffer circuit device of the invention constructed as described above will be explained. First, when the output point A of the front-stage drive circuit 11 is at a low level, the gate inputs of the transistors T15 and T17 are also at a low level, and the transistors T15 and T17 become non-conductive.
Since 4 is a depletion type transistor, the connection point becomes high level (Vcc voltage), and transistors T11, T13, and T16 become conductive.

Therefore, the potential of the connection point Cit Vcc -vt becomes low level through the transistor Tll, the transistor T13 becomes conductive, and the charge accumulated in the capacitor C14 is transferred through the transistor T13. is discharged, and the output point E becomes a low level.

On the other hand, when the output point A of the pre-stage drive circuit 11 rises from a low level to a high level, the waveforms of the various parts become as shown in FIG. Hereinafter, explanation will be given with reference to this waveform diagram.

First, as shown in FIG. 4(a), the potential at the output point A of the front-stage drive circuit gradually rises, and exceeds the threshold value VT of the transistor T17 at the time 1. Then, the transistor T17 becomes conductive, and accordingly, the potential at the connection point C starts to fall as shown in Fig. 34 (C).

However, since the connection point C is at a high level (VCC voltage), the transistor T16 is conductive, and the potential drop at the connection point C is slow due to the transistor T16.

The potential at the output point A further increases, and at time t3 when the potential difference between the gate and source of the transistor T15 exceeds the threshold value VT of the transistor T15, the potential at the connection point begins to drop.

If the potential at the output point A at this time is VA, then VA can be arbitrarily determined at a potential equal to or higher than the threshold value of the transistor T17, depending on the inoctor ratio of the transistor T16 and the transistor T17.

Therefore, transistor T14. T15. The instantaneous output voltage composed of T16 and 'l'17, that is, the potential at the output point A where the potential at the connection point begins to drop, can be arbitrarily determined to be above the threshold VT of the transistor T17. .

This means that transistor T14. T15. It can be said that the inno (-) composed of T16 and T17 has an input level detection function.

Furthermore, the potentials at the connection point C and the connection point D are equal to or higher than the threshold value VT of the VA75f transistor T17, and the potential at the connection point D
(7) Since the voltage at the LIT level is self-returning to the gate of the transistor T16, the potential at the low voltage connection point rapidly decreases, and as shown in Fig. 4(d), the potential at the low voltage connection point exhibits a node-like constant voltage characteristic overnight. shows.

On the other hand, the potential at the connection point B rises to almost the same level as the output point A of the preceding stage drive circuit 11 until time t, and the potential at the connection point B increases as shown in FIG. T12
From the time t2 when the threshold value VT is exceeded, the transistor T1
2 is in a conductive state.

However, until time t4 when the potential at the connection point reaches the threshold value VT of the transistor T13, the transistor T13 remains conductive and the potential at the output point E remains at a low level.

After time t4, transistor T13 becomes non-conductive, and the potential at output point E rises as shown in FIG. 4(e) due to charging from transistor T12. At this time, the potential increase Av at the output point E causes the transistor Tll to become non-conductive, so the capacitor C12 and the Poot-strap capacitor C13 alone are used to increase the potential by C13/(C12+C1
3) XΔV is fed back to the gate potential of transistor T12.

In this way, when the potential at the output point E increases, the transistor Tll becomes non-conductive, and the floating capacitance 1c12 at the connection point B increases.
is very small compared to the Poot-strap capacitor C13, and the potential at the output point E is the same as that of the transistor T12.
The rate of feedback to the gate potential of E is very high 9, which also promotes an increase in the potential of output point E.

Also, the potential at the connection point begins to drop, the transistor T
Since the gate potential of the transistor T15 and the transistor T17, that is, the potential of the output point A of the pre-stage drive circuit 11 can be set independently of the threshold voltage VT of the transistor T15 and the transistor T17, the gate potential of the transistor T12, that is, the potential of the connection point B The potential has risen sufficiently, and the feedback efficiency by the Putt-Strap Innotor is very good.

Furthermore, since there is no need to reduce the drive capability of the transistor T14, the discharge capability of the output point E by the transistor T13 does not decrease, and the time required for the output point E to transition from a high level to a low level does not increase.

As is clear from the description of the embodiments above, the asynchronous poot strap (sofa circuit device) of the present invention
The first input level of the buffer circuit and the output load of the output of the preceding stage drive circuit are cut off through a switch circuit that is controlled on and off by the output of an inverting circuit having an input detection level function. By controlling the second human power level, excellent driving performance can be obtained without sacrificing speed.

(Effects of the Invention) As described above, according to the asynchronous bootstrap buffer circuit device of the present invention, the output of the inverting circuit having the input detection level function controls the on/off switching circuit to buffer the Since the first human power level of the circuit and the output load of the front-stage drive circuit are cut off, and the second human power level of the buffer circuit is controlled, excellent driving performance can be obtained.

Accordingly, it can be used as a word line buffer circuit device of a memory device, an output buffer circuit device, or a buffer circuit device in various logic LSI devices.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional static operation type bootstrap buffer circuit device, and FIGS. 2(a) to 2(d) show the static operation type boot strap buffer circuit device of FIG. A waveform diagram for explaining the operation, FIG. 3 is a circuit diagram showing an embodiment of the asynchronous bootstrap buffer circuit device of the present invention, and FIG.
4(a) to 4(e) are waveform diagrams for explaining the operation of the asynchronous bootstrap/balance circuit device, respectively. 11... Previous stage drive circuit, Tll to T17... Transistor, C1l... Output load capacitance, C12... Stray capacitance, C13... Boot strap capacitor,
C14... Capacitor. Figure 2 tl t2 13 t* Figure 3111 Figure 4 t, t2 t3t4 Procedural amendment (method) % formula % 1 Indication of the case Patent application No. 1983-35867 2 Name of the invention Asynchronous bootstrap buffer circuit device 3 Relationship with the case of the person making the amendment Patent applicant (0291 Oki Electric Industry Co., Ltd. 5 Date of amendment order June 28, 1983 (shipment date)
6 Subject of amendment As shown in the appendix, Figure 2 Figure 4 Procedural amendment January 1, 1982 Kazuo Wakasugi, Commissioner of the Japanese Patent Office 1, Indication of the case 1988 4 "Y Permit No. 35867 2
, Name of the invention Asynchronous boot strug buffer circuit device 3, Relationship with the case of the person making the amendment Patent Applicant (029) Oki Boki Kogyo Co., Ltd. 4, Agent 5, Date of amendment order Showa year, month, Tadashi spontaneously )
and Drawing 7, Contents of the Amendment As shown in Attachment 7, Contents of the Amendment ■) "U-Static" at the end of page 3 of the specification is corrected to "Static." 2) FI page 8 l, line a, r Drake' is corrected to 'drain'. 3) On page 9, line 3, "Star IIJ is corrected to ``Star T11." 4) Page 11, line 5 [Figure 4 (a) J is changed to “Figure 4 (a)”
I am corrected. 5) Correct the drawing number 4 and figure in the attached sheet.

Claims (1)

[Claims] a front-stage drive circuit; an inverting circuit driven by the output of the front-stage drive circuit and having an input level detection function; and a second circuit having a Poot-strap function and first and second input ends.
an amplifier circuit whose input terminal is connected to the output terminal of the inverting circuit; and an amplifier circuit connected between the output terminal of the pre-stage drive circuit and the first input terminal of the amplifier circuit, and turned on by the inverting circuit;
An asynchronous Poot Strap buffer circuit device comprising a switching circuit which is controlled to be off and cuts off the output load of the preceding stage drive circuit and the buffer circuit.