JPS63208321A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the noises of an output circuit and to prevent it from malfunctioning by providing a feedback path between the output terminal of an output circuit and the gate of an output MOSFET provided between the output terminal of the output terminal and the ground potential of the circuit. CONSTITUTION:Serial type MOSFETs Q3 and Q4 are provided between the corresponding output terminals D0-Dn of data output buffers DOB0-DOBn are provided between the output terminals of the gates of output MOSFETs Q2 provided between the ground potential of the circuits and output terminals. The FETs Q3 and Q4 turn on simultaneously for only a specific time when corresponding FETs Q2 are turned on. Consequently, the output signals of output terminals corresponding to the FETs Q3 and Q4 are fed back negatively to the FETs Q3 and Q4 for only the specific time and their amplification factors are suppressed low. Consequently, noises on a ground potential line are suppressed to prevent other data output buffers and data input buffers which are arranged nearby from malfunctioning.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and is applicable to, for example, a semiconductor integrated circuit device having a plurality of output circuits (output sofas) that are activated at the same time. It is about effective techniques.

[Conventional technology]

There are semiconductor integrated circuit devices such as gate array integrated circuits that have a plurality of output circuits that are activated simultaneously. There is also a bush-pull type output path used in such output circuits.

For the above bush-pull type output circuit, for example, 1
979, United States, Rohhart E. Krieger Publishers <n
orhEprTE, Kprec[! u puBLrs
uIh+; co-MPANY) issued rMO3 integrated circuit (MOS INTEGRA-TED CIRCUI)
TS) J, pages 246 to 249.

[Problem that the invention seeks to solve]

FIG. 4 shows an example of a circuit diagram of a standard tri-state output circuit, including the bush-pull output circuit described above. This output circuit has an output control signal φo
Each data output buffer, including fi+1 data output buffers DOBO to DOBn that are activated simultaneously according to M.O.
Contains SFETQB and Q9, respectively. Output MOSFE
The gates of TQ8 and Q9 are supplied with an internal signal selectively formed according to the corresponding inverted output data signal 7-pon and the output control signal φoe.

In other words, the output MOSFET QB has the output control signal φoe
is set to high level and the corresponding inverted output data signal DoO
When ~Don is set to the low level of logic "1", it is selectively turned on, and a high level output signal is sent to the corresponding output terminal. At this time, the output MOSFET Q8 forms a source follower circuit with the output MOSFET Q9 as a load. On the other hand, the output MOSFET Q9 is selectively turned on when the output control signal φoe is set to high level and the corresponding inverted output data signal DoO~m is set to the high level of logic "0", and the corresponding output terminal Sends a low level output signal to

At this time, the output MOSFETQ9 is
A source-grounded amplifier circuit with Q8 as a load is configured.

By the way, the data output buffers DOBO to DOBn are coupled with resistive, inductive, and capacitive loads coupled to the output signal line via the data output terminals Do to Dn. In addition, the data output buffer DOBO~DO
The ground potential of the circuit is supplied to Bn via a ground potential line GND, and a resistive load R is similarly supplied to this ground potential line GND.
s and an inductive load LS are coupled. Furthermore, as semiconductor integrated circuit devices including the above-described output circuits operate at higher speeds, there is a tendency to increase the size of output MOSFETs and reduce their conductance, that is, on-resistance.

Therefore, when a plurality of data output buffers are brought into operation at the same time, a plurality of output MOSFETs are turned on all at once, causing a sudden change in current in the power supply voltage line and the ground potential line GND. This change is particularly important for the ground potential line G
In the ND, this current change significantly generates noise due to the parasitic inductance Ls. That is, the output M of the data output buffer y D OB O to D OB n
By turning on the OSFETs Q8 all at once, the load capacitances coupled to each output signal line are discharged all at once, and the discharge current flows to the ground potential line GND. Therefore, noise is generated in the ground potential line GND as follows: ΔV=LsxIg/Δt, where LS is the parasitic inductance and Ig is the ground potential line current. This noise on the ground potential line GND causes malfunctions of other output circuits, input circuits, etc. disposed nearby.

In addition, in order to deal with this, the inventors of the present invention first output M
An attempt was made to suppress changes in the output signal by slowing down the rise of the output data signal supplied to the gate of the OSFET. However, in the case of the output MOSFET Q7 that forms the source follower circuit, the effect can be obtained because its amplification factor is approximately 1, but the output MOSFET Q7
In the case of ETQ9, since its amplification factor is large, the change in the output signal after exceeding the threshold is still in a sharp state, and it has been found that no effect can be obtained.

Furthermore, the inventors of the present application considered adding a mirror capacitance C as shown by the dotted line in FIG. However, this resulted in an impediment to higher integration.

An object of the present invention is to provide a semiconductor integrated circuit device that includes an output circuit that reduces noise and prevents malfunctions without reducing layout efficiency.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows. That is,
between the output terminal and the gate of an output MOSFET provided between the output terminal of the output circuit and the ground potential of the circuit,
A feedback path is provided that is selectively formed when the output MOSFET is turned on.

[For production]

According to the above means, the amplification factor of the output MOSFET provided between the output terminal and the ground potential of the circuit is reduced due to the negative feedback effect via the feedback path, and the amplification factor of the output MOSFET provided between the output terminal and the ground potential of the circuit is reduced.
By making the output data signal supplied to the gate of the SFET somewhat more gradual, changes in the output signal can be made more gradual, reducing noise on the ground potential line and preventing malfunctions of other circuits placed nearby. It can be prevented.

[Embodiment 1] FIG. 1 shows a circuit diagram of an embodiment of a tri-state output circuit of a gate array integrated circuit to which the present invention is applied. Each circuit element in the figure is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using a known CMO3 integrated circuit manufacturing technique. In the figures below, all MOSFETs described are N-channel O3FETs.

The gate array integrated circuit of this embodiment includes n+1 data output buffers DOBO to DOBn. Corresponding inverted output data signals DoO to [)on are supplied to these data output buffers from other circuits of the gate array integrated circuit (not shown), respectively. The data output buffers DOB O-DOBn are simultaneously activated in accordance with an output control signal φOe supplied from a timing control circuit (not shown), and output corresponding inverted output data signals DoO-D via data output terminals Do-Dn.

Send out an output signal according to T.

In FIG. 1, the output control signal φoe is the Nant gate circuit NAG1 of the data output buffers DOBO to DOBn.
are commonly supplied to one input terminal of the Further, the output control signal φoe is inverted by the inverter circuit N1 and then commonly supplied to one input terminal of the NOR gate circuit N0GI of the data output buffers DOBO to DOBn.

The other input terminals of the NOR gate circuit N0G1 and the NAND gate circuit NAG1 of the data output buffers DOBO to DOBn are connected in common, and the corresponding inverted output data signals ■τ]- to Don are respectively supplied. These inverted output data signals 500 to DOn are set to a high level when the data to be output is a logic "0", and are set to a low level when the data to be output is a logic "1".

From the above, data output buffer DOB O~DO
The output signal of the NOR gate N0GI of Bn is the inverted output data signal 10τ corresponding to the output control signal φoe at a high level, that is, the output signal of the inverter circuit Nl at a low level.
When ~Don is at low level, that is, logic "1", it is set to high level. In addition, the data output buffer DOBO~D
When the output control signal φoe is at high level and the corresponding inverted output data signals DoO to Don are at high level, that is, logic "0", the output signal of OBn (Nando game) NAGI is
It is considered to be low level.

Although not particularly limited, between the power supply voltage Vcc of each data output buffer and the ground potential line GND of the circuit, there are two N-channel type output MOSFETs QI (first output MOSFET) and Q2 (second output MOSFET), respectively.
ET) are provided in series configuration. Output MOS FET
The commonly connected drains of Q1 and Q2 are coupled to corresponding data output terminals DO-D7, respectively. Among these, the output signal of the NOR gate N0G1 is supplied to the gate of the output MOSFET QI. Therefore, when the output signal of the NOR gate circuit NOG1 becomes high level, the output MOSFET QI changes to the output control signal φ.
When the signal oe is at a high level and the corresponding inverted output data signals DoO to Do7T are at logic "1", they are respectively turned on. As a result, data output terminals DO to D7
A high-level output signal such as the power supply voltage Vcc is sent out through the corresponding output MOSFET QI.

On the other hand, the inverted signal of the output signal of the NAND game NAG 1 by the inverter circuit N2 is supplied to the gate of the output MOSFET Q2 of each data output bumper. Although not particularly limited, between the gates of these output MOSFETs Q2 and the corresponding data output terminals DO-D7, a series-type N-channel MOSFET Q3 (third MOSFET
SFET) and Q4 (fourth MOS FET) are provided.

An inverted signal from the inverter circuit N3 of the Nant gate circuit NAG1 is supplied to the gate of the MOSFET Q3. Further, a delayed signal of the output signal ' of the Nant gate circuit NAGL by the inverter circuits N4 and N5 is supplied to the gate of the MOSFET Q4. Here, the MOSFETs forming the inverter circuit N2 are designed to have a slightly smaller conductance than the MOSFETs forming the inverter circuit N3. Furthermore, the sizes of the MOSFETs constituting the inverter circuits N4 and N5 are designed so that their delay times are, for example, several nanoseconds (ns).

FIG. 2 shows the data output buffers 7DOBO to D in FIG.
A signal waveform diagram of each part of OBn is shown. Based on this signal waveform diagram and Figure 1 above, the data output buffer DOBO
An outline of the operation when the logic "0" is output from ~DOBn will be explained.

In the non-selected state of the gate array integrated circuit, the output control signal φoe is set to a low level, and the Nant gate circuit NA
The output signal n1 of G1 becomes high level. This results in
The output signals n2 and ns of the inverter circuits N2 and N3 both become low level, and the MOSFET Q3 is turned off. On the other hand, since the output signal of the Nant gate circuit NAGl is set to high level, the output signal n5 of the inverter circuit N5 becomes high level, and MOSFET Q4 is turned on.

The gate array integrated circuit is in the selected state and the output control signal φ
When Oe is at a high level and the corresponding inverted output data signal 170,000~robi is at a logic "0" high level, the output signal n1 of the Nant gate circuit NAG1 becomes a low level. As a result, first of all, a relatively large size MOSF
The output signal n3 of the inverter circuit N3 constituted by ET becomes high level, and after a slight delay, the output signal n3 of the inverter circuit N3 becomes high level.
The output signal n2 becomes a logic high level. Furthermore, after a slight delay, the output signal n5 of the inverter circuit N5 changes from high level to low level. When the output signal n3 of the inverter circuit N3 becomes high level, the MOSFET Q3 is turned on, and when the output signal n5 of the inverter circuit N5 becomes low level, the MOSFET Q4 is turned off. Therefore, the output M
Data output terminals DO to Dn corresponding to OSFETQ2 are brought into a short termination state via MOSFETQ3 and Q4. Therefore, the output signals of the corresponding data output terminals DO to Dn are negatively fed back to the gate of MOSFETQ2, and the MOS
The amplification factor of FETQ2 is temporarily reduced. Therefore, the output signals output to the data output terminals DO to Dn are output from the inverter circuit N2, which has a relatively small driving capacity.
According to the characteristics of , it is pulled down to a low level relatively slowly.

The time period during which the gate of the output MOSFET Q2 and the corresponding data output terminals DO to Dn are short-circuited is from when the output signal n3 of the inverter circuit N3 becomes high level until the time when the output signal n5 of the inverter circuit N5 becomes low level. It becomes almost the same as the time Tf. This short circuit time Tf is
Conductance of MOSFETs forming inverter circuit N3 and MOSs forming inverter circuits N4 and N5
Determined by the FET conductance. As mentioned above, this short circuit time Tf is only about several nanoseconds.

As described above, in the data output buffers DOBO to DOB of the gate array integrated circuit of this embodiment, the gate of the output MOSFET provided between the corresponding data output terminal D O-D n and the ground potential of the circuit and the output Series MOSFETs Q3 and Q4 are provided between the terminal and the terminal. These MOSFETs Q3 and Q4 are simultaneously turned on for a predetermined time when the corresponding output MOSFET Q2 is turned on. This allows MOSF
The output signal of the corresponding data output terminal is negatively fed back to the gate of ETQ2 for the predetermined period of time, and its amplification factor is kept low. Therefore, since the output signal of the data output terminal is gently pulled out, noise on the ground potential line GND is suppressed, and malfunctions of other data output buffers and data buffer sofas arranged in the vicinity are prevented.

[Embodiment 2] FIG. 3 shows a circuit diagram of another embodiment of the output circuit of a gate array integrated circuit to which the present invention is applied. In the figure, the data output buffer DOBO of the output circuits is shown as an example. Other data output buffers DOB not shown
1 to DOBn have the same configuration as the data output buffer DOBO. Further, in the following description, the description of the same parts as in FIG. 1 will be omitted.

In FIG. 3, the data output buffer DO of this embodiment is
BO is the output MOSFET Q1 and Q of the embodiment of FIG.
2 (first output M
OSFET) and Q6 (second output MOSFET). Furthermore, output signals of a NOR gate circuit N0G2 and an inverter circuit N6 corresponding to the NOR gate circuit N0GI and inverter circuit N2 in FIG. 1 are supplied to the gates of these output MOSFETs Q5 and Q6, respectively. The Nantes gate circuit NAG2 corresponds to the Nantes gate circuit NAGI in FIG.

An inverted output data signal D is connected between the gate of the output MOSFET Q6 and the corresponding data output terminal DO.
N-channel feedback MOSFETQ that receives oO?
(fifth MOSFET) is provided.

Feedback MOSFET Q7 has the corresponding inverted output data signal DoO logic "0" regardless of the output control signal φoe.
is selectively turned on when the signal is at a high level. As a result, when the inverted output data signal DoO is set to high level and the output MOSFET Q6 is turned on, M
The gate of OSFETQ6 has a corresponding data output terminal D.
The output signal of o is negatively fed back and its amplification factor is reduced. Therefore, the output signal of the data output terminal DO is pulled out relatively slowly, and noise on the ground potential line GND is suppressed.

In this embodiment, since the output signal of the inverter circuit N6 becomes high level when the MOSFET Q6 is turned on, the high level output MOSFET of the inverter circuit N6
A through current flows through ET and output MOSFET Q6. Therefore, this embodiment can be said to be an effective method when the amount of negative feedback is small, that is, when the conductance of the feedback MOSFET Q7 is relatively small, since the circuit tank configuration is simple. .

As shown in the above embodiment, when the present invention is applied to an output circuit of a semiconductor integrated circuit device such as a gate array integrated circuit, the following effects can be obtained. That is, (11) between the gate of the output MOSFET provided between the output terminal of the output circuit and the ground potential of the circuit and the above output terminal, when the output MOSFET is turned on, there is a By providing the feedback MOSFET, it is possible to selectively reduce the amplification factor of the output MOSFET provided between the output terminal and the ground potential of the circuit.

(2) In the above item (1), the output MOSFET is connected between the gate of the output MOSFET and the corresponding output terminal.
By providing two MOS FETs that are simultaneously turned on for a predetermined period of time when the ET is turned on,
The effect of reducing the amplification factor of the output MOSFET while preventing through current can be obtained.

(3) With the above (1) and (2), the level change of the output signal of the output terminal can be made relatively gradual,
This provides the effect of suppressing noise from the ground potential line and the like.

(4) The above items (11 to (3)) provide the effect of preventing malfunctions of other output circuits, input circuits, etc. disposed close to the output circuit.

(5) Feedback MOSFET in items (1) and (2) above
can be formed within a relatively small area on a semiconductor substrate, so an effect can be obtained that it can be realized without sacrificing layout efficiency.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the data output buffers of FIGS. 1 and 3 are MO8FETQI and Q
5 may be replaced with a P-channel MOSFET. Furthermore, in this embodiment, each data output buffer is a tri-state output buffer sofa, but a CMO in which two output MOSFETs are turned on in a complementary manner
It may also be an S buffer or the like. Output MOSFET QI
Alternatively, the feedback path provided between the gate of Q5 and the corresponding output terminal may be a resistor made of polysilicon, for example, or a P-channel MOSFET. In addition, in FIG. 1, inverter circuits N4 and N5
The delay circuit configured by is not limited to this. Furthermore, the specific circuit configuration of the output circuit shown in FIGS. 1 and 3 can take various embodiments.

In the above description, the invention made by the present inventor was mainly applied to the output circuit of a data 1-array integrated circuit, which is the background field of application, but the invention is not limited to this, for example, It can also be applied to various semiconductor storage devices and various microcomputers. The present invention is applicable to a semiconductor integrated circuit device having a plurality of output circuits that are activated at least simultaneously.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a feedback path is selectively formed between the output terminal and the gate of the output MOSFET provided between the output terminal of the output circuit and the ground potential of the circuit when the output MOSFET is turned on. By providing the output M O provided between the output terminal and the ground potential of the circuit
The amplification factor of the SFET can be selectively reduced, suppressing noise from ground potential lines, etc., without sacrificing layout efficiency, and reducing noise from other output circuits and inputs placed close to the output circuit. This can prevent malfunctions of circuits, etc.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a tri-state output circuit to which the present invention is applied, FIG. 2 is a timing diagram for explaining the operation of the tri-state output circuit of FIG. 1, and FIG. 4 is a circuit diagram showing another embodiment of a tri-state output circuit to which the present invention is applied, and FIG. 4 is a circuit diagram showing an example of a conventional tri-state output circuit. DOBO~DOB7...Data output buffer, Q1~
Q9...N channel MOSFET, N0GI-~N
0G3...Nor gate circuit, NAG1~NAG3...
・Nando game 1・Circuit, N1~NB... Inverter circuit, C... Miller capacitance, R8... Parasitic resistance, Ls...
...parasitic inductance. Figure 1 Figure 2

Claims (1)

[Claims] 1. A first device provided between the output terminal and the power supply voltage of the circuit.
a plurality of outputs including an output MOSFET, a second output MOSFET provided between the output terminal and the ground potential of the circuit, and a feedback path provided between the output terminal and the gate of the second output MOSFET. A semiconductor integrated circuit device comprising a circuit. 2. The feedback path is composed of third and fourth N-channel MOSFETs connected in series, and the third MOSFET is normally in an off state and the second output MOSFET is in an on state. The fourth MOSFET is normally turned on, the second output MOSFET is turned on, and then turned off after a predetermined time has elapsed. A semiconductor integrated circuit device according to claim 1. 3. The above feedback path is an N-channel type fifth MOSFE.
2. The semiconductor integrated circuit device according to claim 1, wherein the fifth MOSFET has an inverted signal supplied to the gate of the fifth MOSFET.