JP2011228755A - Stacked semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a heat cycle test on a stacked semiconductor device.SOLUTION: The stacked semiconductor device 1 includes a first semiconductor element 5 bonded on a circuit board 2. The first semiconductor element 5 is electrically connected to an electrode part 4 of the circuit board 2 through a first bonding wire 7. A second semiconductor element is bonded on the first semiconductor element 5 through a second adhesive layer (insulating adhesive layer) 9 whose thickness is 50 μm or more. The second adhesive layer 9 consists of an insulation resin layer of which a glass transition temperature is 135°C or higher, a linear expansion coefficient is 100 ppm or lower at the glass transition temperature or lower, and an elastic modulus at room temperature is 500 MPa to 2 GPa.

Description

  The present invention relates to a stacked semiconductor device configured by stacking a plurality of semiconductor elements.

  2. Description of the Related Art In recent years, a stacked multichip package in which a plurality of semiconductor elements are stacked and sealed in a single package has been put into practical use in order to realize miniaturization and high-density mounting of semiconductor devices. In a stacked multichip package, a plurality of semiconductor elements are sequentially stacked on a circuit board via an adhesive layer. The electrode pad of each semiconductor element is electrically connected to the electrode portion of the circuit board via a bonding wire. By stacking such a laminate with a sealing resin, a stacked multichip package is formed.

  In a stacked multi-chip package, when semiconductor elements having the same shape or semiconductor elements larger than the lower stage side are stacked on the upper stage side, the bonding wires of the lower stage semiconductor element and the upper stage semiconductor element may come into contact with each other. For this reason, it is important to prevent the occurrence of insulation failure or short circuit due to the contact of the bonding wire. Therefore, the thickness of the adhesive layer for bonding the semiconductor elements is increased to, for example, 50 to 150 μm, and the bonding wire of the lower semiconductor element is taken into the adhesive layer to contact the upper semiconductor element. It is performed so that it may not (for example, refer patent documents 1-3).

  By the way, the resin material constituting the adhesive layer generally has a larger coefficient of linear expansion than the Si wafer constituting the semiconductor element. For this reason, when a thermal cycle is applied to a stacked semiconductor device such as a stacked multichip package, the thermal stress (residual tensile stress) based on the difference in the linear expansion coefficient between the adhesive layer and the semiconductor element is a semiconductor. There is a possibility that the semiconductor element may crack due to the thermal stress acting on the element. In particular, in a stacked semiconductor device to which a thick adhesive layer having a spacer function as described above is applied, stress concentration occurs on the end surface of the semiconductor element when a thermal cycle test is performed to evaluate reliability. There is a problem that cracks are likely to occur due to this stress concentration.

JP 2001-308262 A JP 2002-222913 A Japanese Patent Laid-Open No. 2004-072009

  An object of the present invention is to provide a stacked semiconductor device having improved reliability for a thermal cycle test.

  A stacked semiconductor device according to an aspect of the present invention is bonded to a first semiconductor element bonded on a circuit substrate and an insulating adhesive layer having a thickness of 50 μm or more on the first semiconductor element. A first bonding wire for electrically connecting the second semiconductor element formed, the first semiconductor element and the electrode portion of the circuit base material, and a connection side end to the first semiconductor element A first bonding wire having a portion taken into the insulating adhesive layer, a second bonding wire for electrically connecting the second semiconductor element and the electrode portion of the circuit substrate, A sealing resin that seals the first and second semiconductor elements together with the first and second bonding wires, and the insulating adhesive layer has a glass transition temperature of 135 ° C. or more and a glass transition The linear expansion coefficient below the temperature is 100p With m or less, a normal temperature elastic modulus is characterized in that it consists of an insulating resin layer is not more than 2GPa least 500 MPa.

  According to the stacked semiconductor device according to the aspect of the present invention, since the linear expansion coefficient of the insulating adhesive layer with respect to the temperature applied in the thermal cycle test is reduced, in the case where a thick insulating adhesive layer is used. It is also possible to improve the reliability for the thermal cycle test.

It is sectional drawing which shows the structure of the laminated semiconductor device by one Embodiment of this invention. FIG. 10 is a cross-sectional view showing a modification of the stacked semiconductor device shown in FIG. 1. It is a figure which shows an example of the result of having measured the influence which the linear expansion coefficient of the 2nd adhesive bond layer in a laminated semiconductor device has on the surface tensile stress value of a semiconductor element at the time of a thermal cycle test (-55 degreeC-125 degreeC). An example of the result of measuring the influence of the thickness of the second adhesive layer and the thickness of the semiconductor element on the surface tensile stress value of the semiconductor element during the thermal cycle test (−55 ° C. to 125 ° C.) in the stacked semiconductor device is shown. FIG. It is a figure which shows the defect generation rate (cumulative defect rate) in the thermal cycle test of the laminated semiconductor device of a comparative example.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In addition, although embodiment of this invention is described based on drawing below, those drawings are provided for illustration and this invention is not limited to those drawings.

  FIG. 1 is a cross-sectional view showing the configuration of a stacked semiconductor device having a stacked multichip structure according to an embodiment of the present invention. A stacked semiconductor device 1 shown in FIG. 1 has a circuit substrate 2 for mounting elements. The circuit substrate 2 for element mounting may be any element that can mount a semiconductor element and has a circuit. As such a circuit base material 2, a circuit board in which a circuit is formed on the surface or inside of an insulating substrate or a semiconductor substrate, or a base material in which an element mounting portion such as a lead frame and a circuit portion are integrated is used. be able to.

  A stacked semiconductor device 1 shown in FIG. 1 has a circuit board 2 as an element mounting circuit base. As the substrate constituting the circuit board 2, substrates made of various materials such as a resin substrate, a ceramic substrate, an insulating substrate such as a glass substrate, or a semiconductor substrate can be applied. Examples of the circuit board to which the resin substrate is applied include a general multilayer copper-clad laminate (multilayer printed wiring board). External connection terminals 3 such as solder bumps are provided on the lower surface side of the circuit board 2.

  An electrode portion 4 electrically connected to the external connection terminal 3 via, for example, an inner layer wiring (not shown) is provided on the upper surface side which is an element mounting surface of the circuit board 2. The electrode part 4 becomes a wire bonding part. The first semiconductor element 5 is bonded to the element mounting surface (upper surface) of the circuit board 2 through the first adhesive layer 6. For the first adhesive layer 6, a general die attach material (die attach film or the like) is used. The first electrode pad 5 a provided on the upper surface side of the first semiconductor element 5 is electrically connected to the electrode portion 4 of the circuit board 2 through the first bonding wire 7.

  On the first semiconductor element 5, a second semiconductor element 8 is bonded via a second adhesive layer 9. The second semiconductor element 8 has, for example, a shape that is the same as or larger than that of the first semiconductor element 5. The second adhesive layer 9 is softened or melted at the heating temperature (bonding temperature) when the second semiconductor element 8 is bonded, and a part of the first bonding wire 7 (connection with the electrode pad 5a) is formed therein. The first semiconductor element 5 and the second semiconductor element 8 are bonded together while taking in the side end portion. Accordingly, an insulating adhesive is used for the second adhesive layer 9 in order to ensure insulation of the first bonding wire 7.

  The connection-side end of the first bonding wire 7 with the electrode pad 5a is taken into the second adhesive layer 9 made of an insulating adhesive layer, thereby preventing contact with the second semiconductor element 8. Has been. That is, the first bonding wire 7 is separated from the lower surface of the second semiconductor element 8 based on the thickness of the insulating adhesive layer 9, whereby the first bonding wire 7 and the second semiconductor element 8 are separated. Insulation failure and short-circuiting due to contact with are prevented. Thus, the second adhesive layer also has a function as a spacer, and an insulating resin layer having a thickness of 50 μm or more is applied to obtain such a function.

  When the thickness of the insulating resin layer constituting the second adhesive layer 9 is 50 μm or less, the first bonding wire 7 is likely to come into contact with the second semiconductor element 8, and the occurrence rate of insulation failure, short circuit, etc. Becomes higher. Although it depends on the wire diameter and the like, the thickness of the second adhesive layer 9 is more preferably 70 μm or more. As a specific example when the diameter of the bonding wire 7 is 25 μm, an insulating adhesive layer 9 having a thickness of 75 μm or 85 μm can be cited. Note that, if the second adhesive layer 9 is too thick, the thickness of the stacked semiconductor device 1 is hindered. Therefore, the thickness of the second adhesive layer 9 is preferably 150 μm or less.

  In order to satisfactorily capture a part of the first bonding wire 7 at the time of bonding, the second adhesive layer 9 preferably has a viscosity at the bonding temperature (viscosity at bonding) of 1 kPa · s or more and less than 100 kPa · s. . If the viscosity at the time of adhesion of the second adhesive layer 9 is less than 1 kPa · s, the second adhesive layer 9 is too soft and the adhesive may protrude from the element end face. On the other hand, if the viscosity at the time of adhesion of the second adhesive layer 9 is 100 kPa · s or more, the first bonding wire 7 may be deformed or poorly connected. The adhesion viscosity of the second adhesive layer 9 is more preferably in the range of 1 to 50 kPa · s, and further preferably in the range of 1 to 20 kPa · s.

  In FIG. 1, the contact between the first bonding wire 7 and the second semiconductor element 8 is suppressed based on the thickness of the second adhesive layer 9. In addition to this, as shown in FIG. 2, the first layer 9 a that softens or melts at the bonding temperature of the second semiconductor element 8, and the layer shape is maintained with respect to the bonding temperature of the second semiconductor element 8. Alternatively, the second adhesive layer 9 in which the second layer 9b is laminated may be applied. The first layer 9 a is formed on the first semiconductor element 5 side and functions as an adhesive layer for the second semiconductor element 8. The second layer 9b is formed on the second semiconductor element 8 side, and functions as an insulating layer that prevents the first bonding wire 7 and the second semiconductor element 8 from contacting each other.

  In this way, the first bonding is performed by forming the second layer (insulating layer) 9b whose layer shape is maintained with respect to the bonding temperature of the second semiconductor element 8 on the second semiconductor element 8 side. It is possible to more reliably prevent the occurrence of insulation failure and short circuit due to the contact between the wire 7 and the second semiconductor element 8. Further, the adhesion between the first semiconductor element 5 and the second semiconductor element 8 can be satisfactorily realized by the first layer 9a. The adhesive layer 9 having such a two-layer structure can be formed, for example, by laminating adhesive resin sheets having different viscosities at the time of adhesion, or by sequentially applying an adhesive resin composition.

  In the adhesive layer 9 having a two-layer structure, the second layer 9b preferably has a viscosity at the time of adhesion of 100 kPa · s or more. If the viscosity at the time of adhesion of the second layer 9b is less than 100 kPa · s, the contact prevention function of the first bonding wire 7 may not be sufficiently exhibited. The adhesion viscosity of the second layer 9b is more preferably 200 kPa · s or more. However, since the function as the bonding layer is impaired when the viscosity is too high, the adhesion viscosity of the second layer (insulating layer) 9b is preferably less than 1000 kPa · s. As described above, the viscosity at the time of adhesion of the first layer (adhesive layer) is preferably 1 kPa · s or more and less than 100 kPa · s.

  Further, the distance between the first semiconductor element 5 and the second semiconductor element 8 is such that a metal material, a resin material, or the like is formed on an electrode pad that is not used for connection of the first semiconductor element 5, that is, a non-connection pad. A stud pump made of may be formed and maintained. Such a configuration can also effectively prevent contact between the first bonding wire 7 and the second semiconductor element 8. The height of the stud pump is set to be higher than the height of the first bonding wire 7. The second semiconductor element 8 prevents the contact with the first bonding wire 7 because the stud bump functions as a spacer and does not descend below the second semiconductor element 8. The stud pumps may be installed at only one place, but are preferably installed at three or more places passing through the center of gravity of the first semiconductor element 5.

  The second semiconductor element 8 bonded on the first semiconductor element 5 through the second adhesive layer 9 has the second electrode pad 8a provided on the upper surface side thereof connected to the second bonding wire 10. Via the electrode part 4 of the circuit board 2. The first and second semiconductor elements 5 and 8 stacked and arranged on the circuit board 2 are sealed with a sealing resin 11 such as an epoxy resin, for example, thereby stacking a stacked multichip package structure. A type semiconductor device 1 is configured. 1 and 2, the structure in which two semiconductor elements 5 and 8 are stacked has been described. However, the number of stacked semiconductor elements is not limited to this, and may be three or more. Needless to say.

  The second adhesive layer 9 described above (in the case of the two-layer structure, each layer 9a, 9b) has an insulation having a glass transition temperature of 135 ° C. or more and a linear expansion coefficient of 100 ppm or less in a temperature range of the glass transition temperature or less. It consists of a resin layer. That is, a polymer material such as an insulating resin constituting the insulating adhesive layer 9 is generally glassy at a low temperature, and rubbery (and liquid) when the glass transition temperature (glass transition point Tg) is exceeded. And the linear expansion coefficient increases rapidly. Therefore, when the glass transition temperature of the insulating resin layer constituting the second adhesive layer 9 is equal to or lower than the temperature applied in the thermal cycle test, the linear expansion coefficient of the adhesive layer 9 increases rapidly during the thermal cycle test. As a result, the difference in coefficient of linear expansion from the semiconductor elements 5 and 8 further increases.

  When the difference in linear expansion coefficient between the adhesive layer 9 and the semiconductor elements 5 and 8 increases, the thermal stress (tensile stress) acting on the semiconductor elements 5 and 8 also increases based on the difference. Since tensile stress concentrates on the surface of the end portion of the semiconductor element 5, cracks and cracks are likely to occur in the semiconductor element 5 due to this stress concentration. A thermal cycle test of a semiconductor device is generally performed in a temperature range of −55 ° C. to 125 ° C. Accordingly, the thermal transition (+ 10 ° C.) is set to the glass transition temperature of the insulating resin layer constituting the adhesive layer 9 and the high temperature side temperature (125 ° C.) at the time of the thermal cycle test for generating the tensile stress in the semiconductor elements 5 and 8. By setting the applied temperature (135 ° C.) or higher, it is possible to suppress an increase in the difference in linear expansion coefficient between the adhesive layer 9 and the semiconductor elements 5 and 8 during the thermal cycle test.

  Further, the tensile stress acting on the semiconductor elements 5 and 8 during the thermal cycle test is affected by a specific value of the linear expansion coefficient below the glass transition temperature of the insulating resin layer constituting the adhesive layer 9. That is, even if the glass transition temperature of the insulating resin layer is 135 ° C. or higher, if the value of the linear expansion coefficient below the glass transition temperature is large, the tensile stress acting on the semiconductor elements 5 and 8 increases, thereby Cracks and the like are likely to occur in 5 and 8. Therefore, the adhesive layer 9 is composed of an insulating resin layer having a linear expansion coefficient not higher than the glass transition temperature and not higher than 100 ppm. FIG. 3 shows an example of the relationship between the coefficient of linear expansion below the glass transition temperature of the insulating resin layer and the tensile stress acting on the semiconductor element (Si chip) during the thermal cycle test (−55 ° C. to 125 ° C.).

  As is apparent from FIG. 3, it can be seen that the tensile stress acting on the semiconductor element increases as the linear expansion coefficient of the insulating resin layer increases. In general, cracks tend to occur when the tensile stress acting on a semiconductor element exceeds 300 MPa. In other words, if the linear expansion coefficient of the insulating resin layer constituting the adhesive layer 9 is 100 ppm or less, it is possible to suppress cracks that occur in the semiconductor elements 5 and 8 during the thermal cycle test. The tensile stress acting on the semiconductor elements 5 and 8 varies depending on the thickness thereof, and the tensile stress increases as the thickness of the semiconductor elements 5 and 8 decreases. Furthermore, for example, when the semiconductor elements 5 and 8 having a thickness of 70 μm or less are applied, the linear expansion coefficient of the insulating resin layer constituting the adhesive layer 9 is more preferably 70 ppm or less.

  FIG. 4 shows the results of measuring the influence of the thickness of the semiconductor element and the adhesive layer on the surface tensile stress value of the semiconductor element (Si chip) during the thermal cycle test (−55 ° C. to 125 ° C.). As apparent from FIG. 4, the surface tension stress value of the semiconductor elements 5 and 8 increases as the thickness of the adhesive layer (insulating resin layer) 9 increases, and the surface decreases as the thickness of the semiconductor elements 5 and 8 decreases. The tensile stress value increases. Therefore, when the stacked semiconductor device 1 is composed of the semiconductor elements 5 and 8 having a thickness of 70 μm or less, it is more preferable that the linear expansion coefficient of the insulating resin layer is 70 ppm or less.

  As described above, the second adhesive layer 9 is made of an insulating resin layer having a glass transition temperature of 135 ° C. or higher and a linear expansion coefficient of 100 ppm or lower, further 70 ppm or lower. Since the difference in coefficient of linear expansion between the adhesive layer 9 and the semiconductor elements 5 and 8 during the cycle test is reduced, it is possible to reduce the thermal stress (tensile stress) acting on the semiconductor elements 5 and 8. Thereby, cracks, cracks, and the like generated in the semiconductor elements 5 and 8 during the thermal cycle test can be suppressed. That is, the reliability of the stacked semiconductor device 1 with respect to the thermal cycle test can be increased. Such an effect of improving the reliability with respect to the heat cycle is particularly effective when the semiconductor elements 5 and 8 having a thickness of 70 μm or less are applied.

  The insulating resin layer that constitutes the second adhesive layer 9 is preferably composed of a thermosetting resin such as an epoxy resin, a silicone resin, a polyimide resin, an acrylic resin, or a bismaleimide resin. In applying such a thermosetting insulating resin, the molecular weight of the main chain, the degree of polymerization, the degree of crosslinking, the type and amount of side chain substituents, the type and amount of additives (for example, plasticizers) in the resin composition, The glass transition temperature of the adhesive layer (insulating resin layer) 9 can be adjusted by the kind and amount of the curing agent and the crosslinking agent. Furthermore, the linear expansion coefficient of the insulating resin layer can be controlled by adjusting the content of an inorganic filler such as silica in the insulating resin composition.

  Thus, based on the type, structure, polymerization conditions, and type and amount of additive of the thermosetting insulating resin, the glass transition temperature is set to 135 ° C. or higher, and the linear expansion coefficient below the glass transition temperature is set to 100 ppm. The adhesive resin layer 9 between the semiconductor elements 5 and 8 is configured with an insulating resin layer adjusted to the following (further 70 ppm or less). When the adhesive layer 9 having a two-layer structure is applied, the above conditions are satisfied. The second adhesive layer 9 is formed by, for example, attaching an adhesive sheet to the back surface of a semiconductor wafer or applying an adhesive resin composition (application resin composition) and then cutting them together with the semiconductor wafer. Is done. Alternatively, a piece of adhesive sheet may be supplied between the first semiconductor element 5 and the second semiconductor element 8 so as to function as the second adhesive layer 9. The method for supplying the adhesive layer 9 is not particularly limited.

  The second adhesive layer 9 preferably has a cured elastic modulus (room temperature elastic modulus) of 500 MPa to 2 GPa. When the elastic modulus of the second adhesive layer (cured resin layer) 9 after curing is less than 500 MPa, the bending of the second semiconductor element 8 in the wire bonding step increases, and cracks or the like occur in the second semiconductor element 8. Is likely to occur. If the elastic modulus of the second adhesive layer 9 after curing exceeds 2 GPa, the productivity of the second semiconductor element 8 and the stacked semiconductor device 1 may be reduced. In such a range, it was confirmed that the elastic modulus of the adhesive layer 9 does not affect the surface tensile stress values of the semiconductor elements 5 and 8 during the thermal cycle test.

  The stacked semiconductor device 1 of the above-described embodiment is manufactured as follows, for example. First, the first semiconductor element 5 is bonded onto the circuit board 2 using the first adhesive layer 6. Subsequently, a wire bonding step is performed to electrically connect the electrode portion 4 of the circuit board 2 and the electrode pad 5 a of the first semiconductor element 5 with the first bonding wire 7. Next, the second semiconductor element 8 is bonded onto the first semiconductor element 5 using the second adhesive layer 9.

  In carrying out the bonding process of the second semiconductor element 8, the second adhesive layer 9 is divided into the second semiconductor elements 8 in advance, for example, as an adhesive sheet bonding layer or an adhesive resin composition coating layer. It is formed on the back surface of the semiconductor wafer before being processed. These are cut (diced) together with the semiconductor wafer into individual pieces. Next, the separated second semiconductor element 8 is held by a mounting tool, and after being aligned with the first semiconductor element 5 placed on the mounting stage, the second semiconductor element 8 is lowered, and the second adhesive layer 9 is pressed against the first semiconductor element 5. At this time, the second adhesive layer 9 is heated and softened or melted using at least one of the mounting stage and the mounting tool, and further heated and cured.

  Since the second adhesive layer 9 has such a thickness that a part of the first bonding wire 7 (the end on the connection side with the first semiconductor element 5) can be taken into the second adhesive layer 9, the first bonding layer 9 Contact between the wire 7 and the second semiconductor element 8 can be suppressed. Thereafter, a wire bonding step is performed on the second semiconductor element 8 to electrically connect the electrode portion 4 of the circuit board 2 and the electrode pad 8 a of the second semiconductor element 8 with the second bonding wire 10. Further, the first and second semiconductor elements 5 and 8 are sealed with the sealing resin 11 together with the bonding wires 7 and 10 and the like, whereby the stacked semiconductor device 1 shown in FIGS. 1 and 2 is manufactured. The

  As a specific example of the above-described embodiment, a laminated semiconductor in which a semiconductor element 5 and 8 having a thickness of 60 μm is bonded with an epoxy resin adhesive having a glass transition temperature of 155 ° C. and a linear expansion coefficient equal to or lower than the glass transition temperature of 70 ppm. 100 devices (Examples) were produced. The thickness of the adhesive layer was 85 μm. When such a 100 stacked semiconductor devices were subjected to a thermal cycle test of −55 ° C. × 20 min → normal temperature (25 ° C.) × 20 min → 125 ° C. × 20 min as one cycle, generation of cracks after 500 cycles The rate was 0%. On the other hand, a laminated semiconductor device (comparative example) manufactured using an epoxy resin adhesive having a glass transition temperature of 155 ° C. and a linear expansion coefficient equal to or lower than the glass transition temperature of 120 ppm has a crack generation rate of 55 after 500 cycles. Rose to%. FIG. 5 shows a Weibull chart of the cumulative defect rate in the thermal cycle test (TCT) of the stacked semiconductor device of the comparative example.

  As described above, the stacked semiconductor device 1 according to the embodiment of the present invention is excellent in reliability with respect to the thermal cycle test. The present invention is not limited to a stacked semiconductor device using wire bonding connection for connecting semiconductor elements, but can also be applied to a stacked semiconductor device using flip-chip connection. The present invention can also be applied to a stacked semiconductor device in which the thickness of the insulating adhesive layer that insulates the periphery of the flip chip connecting portion is increased to 50 μm or more. In this case, the semiconductor element, the insulating adhesive layer, It is possible to obtain the effect of suppressing the occurrence of cracks and the like based on the difference between the linear expansion coefficients, and the improvement effect of the reliability of the stacked semiconductor device based thereon.

  The present invention is not limited to the above-described embodiments, and may be applied to various stacked semiconductor devices in which a plurality of semiconductor elements are bonded using an insulating adhesive layer having a thickness of 50 μm or more. Can do. Such a stacked semiconductor device is also included in the present invention. The embodiments of the present invention can be expanded or modified within the scope of the technical idea of the present invention, and the expanded and modified embodiments are also included in the technical scope of the present invention.

  DESCRIPTION OF SYMBOLS 1 ... Multilayer type semiconductor device, 2 ... Circuit board, 4 ... Electrode part, 5 ... 1st semiconductor element, 6 ... 1st adhesive layer, 7 ... 1st bonding wire, 8 ... 2nd semiconductor element, DESCRIPTION OF SYMBOLS 9 ... 2nd adhesive bond layer, 9a ... 1st layer (adhesion layer), 9b ... 2nd layer (insulating layer), 10 ... 2nd bonding wire, 11 ... sealing resin.

Claims (5)

A first semiconductor element adhered on a circuit substrate;
A second semiconductor element adhered on the first semiconductor element via an insulating adhesive layer having a thickness of 50 μm or more;
A first bonding wire for electrically connecting the first semiconductor element and the electrode portion of the circuit base material, wherein a connection side end with the first semiconductor element is in the insulating adhesive layer A first bonding wire incorporated in
A second bonding wire for electrically connecting the second semiconductor element and the electrode portion of the circuit substrate;
A sealing resin for sealing the first and second semiconductor elements together with the first and second bonding wires;
The insulating adhesive layer is composed of an insulating resin layer having a glass transition temperature of 135 ° C. or more and a linear expansion coefficient of 100 ppm or less and a normal temperature elastic modulus of 500 MPa or more and 2 GPa or less. A feature of a stacked semiconductor device. The stacked semiconductor device according to claim 1,
The stacked semiconductor device according to claim 1, wherein the first bonding wire is separated from the lower surface of the second semiconductor element based on the thickness of the insulating adhesive layer. The stacked semiconductor device according to claim 1,
The insulating adhesive layer is disposed on the first semiconductor element side, disposed on the second semiconductor element side, and a first layer that softens or melts at a bonding temperature of the second semiconductor element. And a second layer in which the layer shape is maintained with respect to the bonding temperature of the second semiconductor element. The stacked semiconductor device according to claim 1, wherein:
The stacked semiconductor device, wherein the second semiconductor element has a thickness of 70 μm or less. The stacked semiconductor device according to claim 1, wherein:
The insulating layer has a viscosity at a bonding temperature of the second semiconductor element of 1 kPa · s or more and less than 100 kPa · s.

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