JP2005303267A - Stack-type electronic components - Google Patents

Stack-type electronic components Download PDF

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JP2005303267A
JP2005303267A JP2005048236A JP2005048236A JP2005303267A JP 2005303267 A JP2005303267 A JP 2005303267A JP 2005048236 A JP2005048236 A JP 2005048236A JP 2005048236 A JP2005048236 A JP 2005048236A JP 2005303267 A JP2005303267 A JP 2005303267A
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electronic component
bonding wire
semiconductor element
adhesive layer
resin
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JP4203031B2 (en
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Atsushi Yoshimura
淳 芳村
Tadanori Okubo
忠宣 大久保
Yoshiaki Sugizaki
吉昭 杉崎
Susumu Harada
享 原田
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a stack-type electronic component having a plurality of electronic components, such as semiconductor elements, mounted in a stacked construction, adapted to suppress creation of bubbles attributed to unfilled voids of resin below wires to prevent defective insulation and short circuit caused by a touch between an electronic component on the upper layer side and the bonding wire of the electronic component on the lower layer side. <P>SOLUTION: The stack-type semiconductor device 1 is provided with: a first semiconductor element 5 adhered onto a circuit board 2 through a first adhesive layer 6; and a second semiconductor element 8 adhered onto the first semiconductor element 5 through a second adhesive layer 9. The underspace below a first bonding wire 7 connected to the first semiconductor element 5 is filled with insulative resin 11 having a viscosity ranging from 1 Pa s or more to less than 1000 Pa s under filled-up conditions or with light-hardening insulative resin. The first and second semiconductor elements 5 and 8 are adhered together through an insulative resin layer 9 having a viscosity ranging from 1 kPas or more to less than 100 kPas under adhering conditions. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は複数個の電子部品を積層して構成した積層型電子部品に関する。   The present invention relates to a laminated electronic component configured by laminating a plurality of electronic components.

近年、半導体装置の小型化や高密度実装化等を実現するために、1つのパッケージ内に複数の半導体素子（半導体チップ）を積層して封止したスタック型マルチチップパッケージが実用化されている。スタック型マルチチップパッケージにおいては、複数の半導体素子が回路基板上にダイアタッチ材等の接着剤を介して順に積層されている。各半導体素子の電極パッドは、回路基板の電極部とボンディングワイヤを介して電気的に接続されている。そして、このような積層構造体を封止樹脂でパッケージングすることによって、スタック型マルチチップパッケージが構成される。   In recent years, in order to realize miniaturization and high-density packaging of semiconductor devices, a stacked multichip package in which a plurality of semiconductor elements (semiconductor chips) are stacked and sealed in one package has been put into practical use. . In a stacked multichip package, a plurality of semiconductor elements are sequentially stacked on a circuit board via an adhesive such as a die attach material. The electrode pad of each semiconductor element is electrically connected to the electrode portion of the circuit board via a bonding wire. A stacked multichip package is configured by packaging such a laminated structure with a sealing resin.

上記したようなスタック型マルチチップパッケージにおいて、上段側の半導体素子が下段側の半導体素子より小さい場合には、下段側の半導体素子のボンディングワイヤに上段側の半導体素子が干渉することはない。しかし、このような構成では適用可能な半導体素子が大幅に制限されることから、同形状の半導体素子同士や上段側が下段側より大きい半導体素子まで適用範囲を広げることが進められている。ここで、同形状の半導体素子同士や上段側に下段側より大形状の半導体素子を積層する場合には、下段側の半導体素子のボンディングワイヤと上段側の半導体素子とが接触するおそれがある。このため、ボンディングワイヤの接触による絶縁不良やショート等の発生を防止することが重要となる。   In the stacked multichip package as described above, when the upper semiconductor element is smaller than the lower semiconductor element, the upper semiconductor element does not interfere with the bonding wire of the lower semiconductor element. However, since applicable semiconductor elements are greatly limited in such a configuration, the application range is being extended to semiconductor elements having the same shape or to semiconductor elements whose upper side is larger than the lower side. Here, when semiconductor elements having a larger shape than the lower stage side are stacked on the upper side or the semiconductor elements having the same shape, there is a possibility that the bonding wire of the lower side semiconductor element and the upper side semiconductor element come into contact with each other. For this reason, it is important to prevent the occurrence of insulation failure or short circuit due to the contact of the bonding wire.

そこで、下段側の半導体素子に接続されたボンディングワイヤの高さより上段側の半導体素子の下面が高くなるように厚さを設定したスペーサを、上下の半導体素子間に配置することが行われている（例えば特許文献１，２参照）。半導体素子間にスペーサを配置した構造では、スペーサで形成した空間内にボンディングワイヤを配置すると共に、このボンディングワイヤが配置された空間を接着剤樹脂等で封止する必要がある。この際、ボンディングワイヤが配置された空間に充填する樹脂量が不十分であると、ワイヤ下部に樹脂の未充填部が生じやすいという問題がある。   Therefore, a spacer whose thickness is set so that the lower surface of the upper semiconductor element is higher than the height of the bonding wire connected to the lower semiconductor element is disposed between the upper and lower semiconductor elements. (For example, refer to Patent Documents 1 and 2). In a structure in which spacers are arranged between semiconductor elements, it is necessary to arrange bonding wires in a space formed by the spacers and seal the space in which the bonding wires are arranged with an adhesive resin or the like. At this time, if the amount of resin to be filled in the space in which the bonding wires are arranged is insufficient, there is a problem that an unfilled portion of the resin is likely to occur in the lower portion of the wire.

また、スペーサを用いることなく、半導体素子間にボンディングワイヤの接触を防止する空間を形成することも行われている。例えば、特許文献３には半導体素子間を接着する絶縁性接着剤層の厚さを、ボンディングワイヤの高さより厚くした半導体装置が記載されている。ボンディングワイヤの一部は絶縁性接着剤層内に配置される。特許文献４には下段側の半導体素子上に絶縁用樹脂層と固定用樹脂層を順に形成した後、上段側の半導体素子を配置して固定した構造が記載されている。さらに、特許文献５には上段側の半導体素子の裏面を絶縁処理することにより、ボンディングワイヤと半導体素子との接触による絶縁不良やショート等を防ぐことが記載されている。
特開2003-179200号公報 特開2003-218316号公報 特開2004-072009号公報 特開平08-288455号公報 特開2004-193363号公報 In addition, a space for preventing contact of a bonding wire is formed between semiconductor elements without using a spacer. For example, Patent Document 3 describes a semiconductor device in which the thickness of an insulating adhesive layer for bonding between semiconductor elements is larger than the height of a bonding wire. A portion of the bonding wire is disposed within the insulating adhesive layer. Patent Document 4 describes a structure in which an insulating resin layer and a fixing resin layer are sequentially formed on a lower semiconductor element, and then an upper semiconductor element is arranged and fixed. Further, Patent Document 5 describes that insulation failure or short-circuit due to contact between the bonding wire and the semiconductor element is prevented by performing an insulation treatment on the back surface of the upper semiconductor element.
JP 2003-179200 A JP 2003-218316 A JP 2004-072009 Japanese Unexamined Patent Publication No. 08-288455 JP 2004-193363 A

上述したように、半導体素子間にスペーサを配置した構造を有する半導体装置は、ボンディングワイヤの下部空間に樹脂の未充填部が生じやすいという問題を有している。ワイヤ下部の樹脂の未充填部には、その後の樹脂モールド工程においても樹脂を充填することが困難であることから、樹脂の未充填部に起因する気泡が残存することになる。半導体装置内に気泡が発生すると、吸湿や半田リフロー等に対する信頼性試験で気泡を起点とした剥離やリーク等が生じやすくなり、半導体装置の信頼性が損なわれる。樹脂の未充填部の発生を防ぐ手法としては、低粘度の接着剤樹脂を使用したり、接着剤樹脂の充填量を増加させることが考えられる。しかし、これらの場合には素子端面からの樹脂のはみ出し（ブリード）や樹脂の上方への這い上がり等の問題が生じる。   As described above, a semiconductor device having a structure in which spacers are arranged between semiconductor elements has a problem that an unfilled portion of resin is likely to occur in the lower space of the bonding wire. In the unfilled portion of the resin below the wire, it is difficult to fill the resin even in the subsequent resin molding process, so that bubbles resulting from the unfilled portion of the resin remain. If bubbles are generated in the semiconductor device, peeling or leaking from the bubbles is likely to occur in a reliability test for moisture absorption, solder reflow, etc., and the reliability of the semiconductor device is impaired. As a technique for preventing the unfilled portion of the resin from occurring, it is conceivable to use a low-viscosity adhesive resin or increase the filling amount of the adhesive resin. However, in these cases, problems such as bulging of the resin from the end face of the element and scooping up of the resin occur.

一方、半導体素子間の空間を接着剤層で維持する構造（スペーサを省いた構造）においては、高粘度の接着剤樹脂を使用して接着剤層の形状を保持する必要がある。このように高粘度の接着剤樹脂を使用すると、上述したワイヤ下部の樹脂未充填部がさらに発生しやすくなる。特に、スペーサを用いることなく複数の半導体素子を積層した半導体装置においては、接着剤層がスペーサと封止樹脂の機能を兼ねるため、形状の維持と充填性の向上を両立させることは困難である。   On the other hand, in a structure in which a space between semiconductor elements is maintained by an adhesive layer (a structure in which a spacer is omitted), it is necessary to maintain the shape of the adhesive layer using a high-viscosity adhesive resin. When a high-viscosity adhesive resin is used in this way, the above-described resin unfilled portion below the wire is more likely to occur. In particular, in a semiconductor device in which a plurality of semiconductor elements are stacked without using a spacer, the adhesive layer serves as both a spacer and a sealing resin. .

上述したように、従来のスタック型マルチチップパッケージ構造を適用した半導体装置においては、ボンディングワイヤの下部に樹脂の未充填部が生じやすく、この樹脂未充填部が気泡として残存することで半導体装置の信頼性を低下させるという問題がある。特に、スペーサを用いていない半導体装置では、ボンディングワイヤの接触を防止する層形状を保持した上で、接着剤樹脂の充填性を向上させることが困難となっている。このような問題は複数の半導体素子を積層した半導体装置に限らず、各種の電子部品を積層してパッケージングした積層型電子部品においても同様に生じている。   As described above, in the semiconductor device to which the conventional stack type multichip package structure is applied, an unfilled portion of the resin is likely to be formed below the bonding wire, and the unfilled portion of the resin remains as bubbles, thereby There is a problem of reducing reliability. In particular, in a semiconductor device that does not use a spacer, it is difficult to improve the filling property of the adhesive resin while maintaining a layer shape that prevents contact of the bonding wire. Such a problem occurs not only in a semiconductor device in which a plurality of semiconductor elements are stacked, but also in a stacked electronic component in which various electronic components are stacked and packaged.

本発明はこのような課題に対処するためになされたもので、ボンディングワイヤ下部の樹脂未充填部に起因する気泡の発生を抑制した上で、下段側の電子部品のボンディングワイヤと上段側の電子部品との接触に基づく絶縁不良やショート等の発生を防止する空間を維持することを可能にした積層型電子部品を提供することを目的としている。   The present invention has been made to cope with such a problem, and suppresses the generation of bubbles caused by the resin unfilled portion below the bonding wire, and then bonds the bonding wire of the lower electronic component to the upper electronic component. It is an object of the present invention to provide a multilayer electronic component that can maintain a space that prevents the occurrence of insulation failure and short circuit due to contact with the component.

本発明の一態様に係る積層型電子部品は、電極部を有する基板と、前記電極部に第１のボンディングワイヤを介して接続された第１の電極パッドを有し、前記基板上に第１の接着層を介して接着された第１の電子部品と、前記電極部に第２のボンディングワイヤを介して接続された第２の電極パッドを有し、前記第１の電子部品上に第２の接着層を介して接着された第２の電子部品とを具備し、前記第２の接着層は、前記第１の電子部品と前記第１のボンディングワイヤとの間の空間に充填された第１の絶縁性樹脂と、前記第１の電子部品と前記第２の電子部品とを接着するように配置され、前記第１の絶縁性樹脂とは異なる弾性率を有する第２の絶縁性樹脂とを有することを特徴としている。   A multilayer electronic component according to an aspect of the present invention includes a substrate having an electrode portion, a first electrode pad connected to the electrode portion via a first bonding wire, and a first electrode on the substrate. And a second electrode pad connected to the electrode portion via a second bonding wire, and the second electronic pad is connected to the second electronic pad on the first electronic component. A second electronic component bonded via an adhesive layer, wherein the second adhesive layer fills a space between the first electronic component and the first bonding wire. A first insulating resin, and a second insulating resin disposed to adhere the first electronic component and the second electronic component, and having a different elastic modulus from the first insulating resin; It is characterized by having.

本発明の他の態様に係る積層型電子部品は、電極部を有する基板と、前記電極部に第１のボンディングワイヤを介して接続された第１の電極パッドを有し、前記基板上に第１の接着層を介して接着された第１の電子部品と、前記電極部に第２のボンディングワイヤを介して接続された第２の電極パッドを有し、前記第１の電子部品上に第２の接着層を介して接着された第２の電子部品とを具備し、前記第２の接着層は前記第１の電子部品と前記第１のボンディングワイヤとの間の空間に充填され、充填時粘度が1Pa・s以上1000Pa・s未満の範囲の第１の絶縁性樹脂と、前記第１の電子部品と前記第２の電子部品とを接着するように配置され、接着時粘度が1kPa・s以上100kPa・s以下の範囲の第２の絶縁性樹脂とを有することを特徴としている。   A multilayer electronic component according to another aspect of the present invention includes a substrate having an electrode portion, a first electrode pad connected to the electrode portion via a first bonding wire, and a first electronic pad on the substrate. A first electronic component bonded via an adhesive layer, and a second electrode pad connected to the electrode portion via a second bonding wire, and the first electronic component is formed on the first electronic component. A second electronic component bonded via an adhesive layer, and the second adhesive layer is filled in a space between the first electronic component and the first bonding wire. The first insulating resin having a viscosity at the time of 1 Pa · s or more and less than 1000 Pa · s and the first electronic component and the second electronic component are arranged to be bonded, and the viscosity at the time of bonding is 1 kPa · and a second insulating resin in a range of s to 100 kPa · s.

本発明のさらに他の態様に係る積層型電子部品は、電極部を有する基板と、前記電極部に第１のボンディングワイヤを介して接続された第１の電極パッドを有し、前記基板上に第１の接着層を介して接着された第１の電子部品と、前記電極部に第２のボンディングワイヤを介して接続された第２の電極パッドを有し、前記第１の電子部品上に第２の接着層を介して接着された第２の電子部品とを具備し、前記第２の接着層は前記第１の電子部品と前記第１のボンディングワイヤとの間の空間に充填された光硬化型絶縁性樹脂と、前記第１の電子部品と前記第２の電子部品とを接着するように配置され、接着時粘度が1kPa・s以上100kPa・s以下の範囲の熱硬化型絶縁性樹脂とを有することを特徴としている。   A multilayer electronic component according to still another aspect of the present invention includes a substrate having an electrode portion, and a first electrode pad connected to the electrode portion via a first bonding wire, on the substrate. A first electronic component bonded via a first adhesive layer; and a second electrode pad connected to the electrode portion via a second bonding wire, the first electronic component being on the first electronic component A second electronic component bonded via a second adhesive layer, and the second adhesive layer is filled in a space between the first electronic component and the first bonding wire Thermosetting insulating resin that is arranged to adhere the photocurable insulating resin, the first electronic component, and the second electronic component, and has a viscosity in the range of 1 kPa · s to 100 kPa · s. And a resin.

本発明の態様に係る積層型電子部品においては、第１の電子部品と第１のボンディングワイヤとの間の空間に充填時粘度が1Pa・s以上1000Pa・s未満の絶縁性樹脂や光硬化型絶縁性樹脂を予め充填している。このため、第１の電子部品と第２の電子部品との接着に高粘度の絶縁性樹脂を使用して接着層の形状を保持した上で、ボンディングワイヤ下部の樹脂未充填部に起因する気泡の発生等を抑制することができる。従って、積層型電子部品の信頼性や製造歩留まり等を高めることが可能となる。   In the multilayer electronic component according to the aspect of the present invention, an insulating resin or photo-curing type having a filling viscosity in the space between the first electronic component and the first bonding wire of 1 Pa · s or more and less than 1000 Pa · s. Insulating resin is filled in advance. For this reason, after maintaining the shape of the adhesive layer using a high-viscosity insulating resin for bonding the first electronic component and the second electronic component, air bubbles caused by the resin unfilled portion below the bonding wire Can be suppressed. Therefore, it is possible to improve the reliability and manufacturing yield of the multilayer electronic component.

以下、本発明を実施するための形態について、図面を参照して説明する。なお、以下では本発明の実施形態を図面に基づいて述べるが、それらの図面は図解のために提供されるものであり、本発明はそれらの図面に限定されるものではない。   Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In addition, although embodiment of this invention is described below based on drawing, those drawings are provided for illustration and this invention is not limited to those drawings.

図１は本発明の積層型電子部品をスタック型マルチチップ構造の半導体装置に適用した第１の実施形態の構成を模式的に示す断面図である。同図に示す半導体装置１は、素子搭載用の基板２を有している。素子搭載用基板２は電子部品を搭載することが可能で、かつ回路を有するものであればよい。このような基板２としては、絶縁基板や半導体基板等の表面や内部に回路を形成した回路基板、あるいはリードフレームのような素子搭載部と回路部とを一体化した基板等を用いることができる。   FIG. 1 is a cross-sectional view schematically showing a configuration of a first embodiment in which a multilayer electronic component of the present invention is applied to a semiconductor device having a stacked multichip structure. A semiconductor device 1 shown in FIG. 1 has a substrate 2 for mounting elements. The element mounting board 2 only needs to be capable of mounting electronic components and have a circuit. As such a substrate 2, a circuit substrate in which a circuit is formed on or inside an insulating substrate or a semiconductor substrate, or a substrate in which an element mounting portion and a circuit portion such as a lead frame are integrated can be used. .

図１に示す半導体装置１は、素子搭載用基板として回路基板２を有している。回路基板２を構成する基板には、樹脂基板、セラミックス基板、ガラス基板等の絶縁基板、あるいは半導体基板等、各種の材料からなる基板を適用することができる。樹脂基板を適用した回路基板としては、一般的な多層銅張積層板（多層プリント配線板）等が挙げられる。このような回路基板２の下面側には、半田バンプ等の外部接続端子３が設けられている。   A semiconductor device 1 shown in FIG. 1 has a circuit board 2 as an element mounting board. As the substrate constituting the circuit board 2, substrates made of various materials such as a resin substrate, a ceramic substrate, an insulating substrate such as a glass substrate, or a semiconductor substrate can be applied. Examples of the circuit board to which the resin substrate is applied include a general multilayer copper-clad laminate (multilayer printed wiring board). External connection terminals 3 such as solder bumps are provided on the lower surface side of the circuit board 2.

回路基板２の素子搭載面となる上面側には、外部接続端子３と例えば内層配線（図示せず）を介して電気的に接続された電極部４が設けられている。電極部４はワイヤボンディング部となるものである。このような回路基板２の素子搭載面（上面）には、第１の電子部品として第１の半導体素子５が第１の接着層６を介して接着されている。第１の接着層６には一般的なダイアタッチ材（ダイアタッチフィルム等）が用いられる。第１の半導体素子５の上面側に設けられた第１の電極パッド（図示せず）は、第１のボンディングワイヤ７を介して回路基板２の電極部４と電気的に接続されている。   An electrode portion 4 electrically connected to the external connection terminal 3 via, for example, an inner layer wiring (not shown) is provided on the upper surface side which is an element mounting surface of the circuit board 2. The electrode part 4 becomes a wire bonding part. A first semiconductor element 5 as a first electronic component is bonded to the element mounting surface (upper surface) of the circuit board 2 through a first adhesive layer 6. A general die attach material (die attach film or the like) is used for the first adhesive layer 6. A first electrode pad (not shown) provided on the upper surface side of the first semiconductor element 5 is electrically connected to the electrode portion 4 of the circuit board 2 through a first bonding wire 7.

さらに、第１の半導体素子５上には第２の電子部品として第２の半導体素子８が第２の接着層９を介して接着されている。第２の半導体素子８は第１の半導体素子５と同形またはそれより大形の形状を有している。第２の半導体素子８の上面側に設けられた第２の電極パッド（図示せず）は、第２のボンディングワイヤ１０を介して回路基板２の電極部４と電気的に接続されている。   Further, a second semiconductor element 8 as a second electronic component is bonded onto the first semiconductor element 5 via a second adhesive layer 9. The second semiconductor element 8 has the same shape as the first semiconductor element 5 or a shape larger than that. A second electrode pad (not shown) provided on the upper surface side of the second semiconductor element 8 is electrically connected to the electrode portion 4 of the circuit board 2 through the second bonding wire 10.

第１の半導体素子５と第１のボンディングワイヤ７との間の空間には、図２の拡大図に示すように、充填時粘度が1Pa・s以上1000Pa・s未満の範囲の第１の絶縁性樹脂１１が充填されている。なお、符号１２は第１の半導体素子５の上面側に設けられた第１の電極パッドである。第２の接着層９は第１の絶縁性樹脂１１の充填部を除いて、接着時粘度が1kPa・s以上100kPa・s以下の第２の絶縁性樹脂（接着剤樹脂）により構成されている。すなわち、第１の半導体素子５と第２の半導体素子８とは、主として第２の絶縁性樹脂からなる第２の接着層９を介して接着されている。   In the space between the first semiconductor element 5 and the first bonding wire 7, as shown in the enlarged view of FIG. 2, a first insulation having a filling viscosity in the range of 1 Pa · s to less than 1000 Pa · s. Resin 11 is filled. Reference numeral 12 denotes a first electrode pad provided on the upper surface side of the first semiconductor element 5. The second adhesive layer 9 is composed of a second insulating resin (adhesive resin) having a viscosity at the time of bonding of 1 kPa · s to 100 kPa · s except for the filling portion of the first insulating resin 11. . That is, the first semiconductor element 5 and the second semiconductor element 8 are bonded via the second adhesive layer 9 mainly made of the second insulating resin.

第１の絶縁性樹脂１１は、第１のボンディングワイヤ７を第１の半導体素子５の電極パッドにボンディングした後、第２の半導体素子８の接着工程に先立って、第１の半導体素子５と第１のボンディングワイヤ７との間の空間に充填されたものである。このように、予め第１の半導体素子５と第１のボンディングワイヤ７との間の空間に、第１の絶縁性樹脂１１を充填しておくことによって、ワイヤ下部の樹脂未充填部に基づく気泡の発生等を確実に防ぐことができる。   The first insulating resin 11 is bonded to the first semiconductor element 5 prior to the bonding process of the second semiconductor element 8 after bonding the first bonding wire 7 to the electrode pad of the first semiconductor element 5. The space between the first bonding wire 7 is filled. In this way, by previously filling the space between the first semiconductor element 5 and the first bonding wire 7 with the first insulating resin 11, bubbles based on the resin unfilled portion below the wire. Can be reliably prevented.

さらに、ワイヤ下部の樹脂未充填部の発生を懸念する必要がないため、第２の接着層９を主として構成する第２の絶縁性樹脂には、その形状（設定した層厚等）を維持することが可能な高粘度の接着剤樹脂を適用することができる。これによって、第２の接着層（第２の絶縁性樹脂層）９に第１および第２の半導体素子５、８間の空間を保持する機能を良好に付与することが可能となる。このような高粘度の第２の絶縁性樹脂から主としてなる第２の接着層９によれば、第１のボンディングワイヤ７が第２の半導体素子８に接触して絶縁不良やショート等が発生することを再現性よく抑制することができる。   Furthermore, since it is not necessary to worry about the occurrence of a resin unfilled portion below the wire, the shape (the set layer thickness, etc.) of the second insulating resin mainly constituting the second adhesive layer 9 is maintained. It is possible to apply a high viscosity adhesive resin that can be used. As a result, it is possible to satisfactorily give the second adhesive layer (second insulating resin layer) 9 the function of maintaining the space between the first and second semiconductor elements 5 and 8. According to the second adhesive layer 9 mainly composed of such a high-viscosity second insulating resin, the first bonding wire 7 comes into contact with the second semiconductor element 8 to cause insulation failure, short circuit, or the like. This can be suppressed with good reproducibility.

第１の絶縁性樹脂１１は、例えば図３に示すように、第１の半導体素子５と第１のボンディングワイヤ７との間の空間毎に充填する。図３に示す第１の絶縁性樹脂１１は、例えば絶縁性樹脂ペーストを順にポッティングすることによって、第１の半導体素子５と第１のボンディングワイヤ７との間の空間にそれぞれ充填することができる。このような第１の絶縁性樹脂１１の充填構造は、第１のボンディングワイヤ７の形成ピッチが比較的広い場合に有効であり、第２の接着層９の体積計算が容易であるというような利点がある。   For example, as shown in FIG. 3, the first insulating resin 11 is filled in each space between the first semiconductor element 5 and the first bonding wire 7. The first insulating resin 11 shown in FIG. 3 can be filled in the space between the first semiconductor element 5 and the first bonding wire 7 by sequentially potting an insulating resin paste, for example. . Such a filling structure of the first insulating resin 11 is effective when the formation pitch of the first bonding wires 7 is relatively wide, and the volume calculation of the second adhesive layer 9 is easy. There are advantages.

第１の絶縁性樹脂１１は図４に示すように、第１の半導体素子５と第１のボンディングワイヤ７との間の空間全体を繋ぐように充填してもよい。図４に示す第１の絶縁性樹脂１１は、例えば絶縁性樹脂ペーストをスクリーン印刷することによって、第１の半導体素子５と第１のボンディングワイヤ７との間の空間全体に充填することができる。このような第１の絶縁性樹脂１１の充填構造は、第１のボンディングワイヤ７の形成ピッチが比較的狭い場合に有効であり、第１のボンディングワイヤ７の変形防止に対しても効果を示す。   As shown in FIG. 4, the first insulating resin 11 may be filled so as to connect the entire space between the first semiconductor element 5 and the first bonding wire 7. The first insulating resin 11 shown in FIG. 4 can be filled in the entire space between the first semiconductor element 5 and the first bonding wire 7, for example, by screen printing an insulating resin paste. . Such a filling structure of the first insulating resin 11 is effective when the formation pitch of the first bonding wires 7 is relatively narrow, and also has an effect for preventing deformation of the first bonding wires 7. .

第１の絶縁性樹脂１１は、第１の半導体素子５と第１のボンディングワイヤ７との間の空間に充填するものであるため、そのような空間への良好な充填性を確保する上で、充填時粘度が1Pa・s以上1000Pa・s未満の絶縁性樹脂が用いられる。第１の絶縁性樹脂１１の充填時粘度が1000Pa・s以上であると、第１の半導体素子５と第１のボンディングワイヤ７との間の空間への充填性が低下して未充填部が発生しやすくなる。第１の絶縁性樹脂１１の充填時粘度は充填性を高めるために500Pa・s以下とすることが好ましい。一方、第１の絶縁性樹脂１１の充填時粘度が1Pa・s未満であると、逆に軟らかすぎることで未充填部が発生したり、また周囲へのはみ出し（ブリード）等が生じるおそれがある。第１の絶縁性樹脂１１の充填時粘度は10〜50Pa・sの範囲であることがより好ましい。   Since the first insulating resin 11 fills the space between the first semiconductor element 5 and the first bonding wire 7, in order to ensure a good fillability in such a space. An insulating resin having a viscosity at the time of filling of 1 Pa · s or more and less than 1000 Pa · s is used. When the filling viscosity of the first insulating resin 11 is 1000 Pa · s or more, the filling property into the space between the first semiconductor element 5 and the first bonding wire 7 is lowered, and the unfilled portion is formed. It tends to occur. The viscosity at the time of filling of the first insulating resin 11 is preferably 500 Pa · s or less in order to improve the filling property. On the other hand, when the viscosity of the first insulating resin 11 is less than 1 Pa · s, there is a possibility that an unfilled portion may be generated due to being too soft, and that protrusion (bleed) or the like to the surroundings may occur. . The viscosity of the first insulating resin 11 when filled is more preferably in the range of 10 to 50 Pa · s.

上述したような充填時粘度を有する第１の絶縁性樹脂１１には、例えばエポキシ樹脂やシリコーン樹脂等の熱硬化性樹脂が用いられる。充填時粘度は第１の絶縁性樹脂１１を構成する熱硬化性樹脂組成物の組成等で調整してもよいし、また充填工程における第１の半導体素子５の温度（例えば加熱温度）で調整することも可能である。上記した空間に充填した熱硬化性樹脂からなる第１の絶縁性樹脂１１は、第２の半導体素子８の接着工程前に熱処理を施して硬化させてもよいし、また第２の半導体素子８を接着する第２の接着層９の硬化処理時に同時に硬化させてもよい。   For the first insulating resin 11 having the above-described filling viscosity, for example, a thermosetting resin such as an epoxy resin or a silicone resin is used. The viscosity at the time of filling may be adjusted by the composition of the thermosetting resin composition constituting the first insulating resin 11, or may be adjusted by the temperature (for example, heating temperature) of the first semiconductor element 5 in the filling step. It is also possible to do. The first insulating resin 11 made of the thermosetting resin filled in the space may be cured by heat treatment before the bonding process of the second semiconductor element 8, or the second semiconductor element 8 may be cured. May be cured at the same time as the curing process of the second adhesive layer 9 for adhering.

第１の絶縁性樹脂１１の充填部を除く第２の接着層９には、第１のボンディングワイヤ７の配置領域となる層形状が維持されるように、接着時粘度が1kPa・s以上100kPa・s以下の第２の絶縁性樹脂が用いられる。第２の絶縁性樹脂の接着時粘度が100kPa・sを超えると硬すぎて、第１のボンディングワイヤ７を良好に層内に取り込むことができない。このため、第１のボンディングワイヤ７を押し潰してしまうおそれがある。一方、第２の絶縁性樹脂の接着時粘度が1kPa・s未満であると軟らかすぎて、第１のボンディングワイヤ７が第２の半導体素子８に接触したり、また樹脂が素子端面からはみ出すおそれがある。第２の絶縁性樹脂の接着時粘度は1〜50kPa・sの範囲であることがより好ましく、さらには1〜20kPa・sの範囲であることが望ましい。   The second adhesive layer 9 excluding the filled portion of the first insulating resin 11 has a viscosity at the time of adhesion of 1 kPa · s or more and 100 kPa so that the layer shape serving as the arrangement region of the first bonding wire 7 is maintained. A second insulating resin of s or less is used. If the viscosity at the time of adhesion of the second insulating resin exceeds 100 kPa · s, it is too hard to satisfactorily take the first bonding wire 7 into the layer. For this reason, there exists a possibility that the 1st bonding wire 7 may be crushed. On the other hand, if the viscosity of the second insulating resin is less than 1 kPa · s, the first bonding wire 7 may come into contact with the second semiconductor element 8 or the resin may protrude from the end face of the element. There is. The adhesion viscosity of the second insulating resin is more preferably in the range of 1 to 50 kPa · s, and further preferably in the range of 1 to 20 kPa · s.

第２の接着層９を主として構成する第２の絶縁性樹脂には、例えばエポキシ樹脂のような熱硬化性樹脂が用いられる。熱硬化性樹脂の接着時粘度は、熱硬化性樹脂組成物の組成等で調整してもよいし、また接着工程における加熱温度で調整することも可能である。図５はエポキシ樹脂からなるダイアタッチ材の粘度特性の一例を示している。図５に示す粘度特性を有するダイアタッチ材は、接着時温度を約70〜160℃の範囲とすることで接着時粘度を100kPa・s以下とすることができる。また、接着時温度を約90〜140℃の範囲とすることで接着時粘度を50kPa・s以下とすることができる。   For the second insulating resin mainly constituting the second adhesive layer 9, for example, a thermosetting resin such as an epoxy resin is used. The viscosity at the time of adhesion of the thermosetting resin may be adjusted by the composition of the thermosetting resin composition or the like, or may be adjusted by the heating temperature in the bonding step. FIG. 5 shows an example of viscosity characteristics of a die attach material made of an epoxy resin. The die attach material having the viscosity characteristics shown in FIG. 5 can have a viscosity at the time of bonding of 100 kPa · s or less by setting the temperature at the time of bonding to a range of about 70 to 160 ° C. Moreover, the viscosity at the time of adhesion can be 50 kPa * s or less by making the temperature at the time of adhesion into the range of about 90-140 degreeC.

また、第２の絶縁性樹脂で第２の接着層９を形成する際に、例えば熱硬化性樹脂組成物の乾燥温度を適宜に調整することによっても、接着工程の加熱温度に対して適度な粘度を有する第２の接着層（第２の絶縁性樹脂層）９を得ることができる。ここで言う乾燥温度とは、例えば熱硬化性樹脂組成物を第２の半導体素子８の裏面に塗布した後、この樹脂塗膜を半硬化状態（Ｂステージ状態）とするための温度を示すものである。半硬化状態の熱硬化性樹脂層は、半硬化させた温度（乾燥温度）以上に加熱することで軟化もしくは溶融させることができるため、乾燥温度と接着時の加熱温度とを適宜に調整することで、所望の接着時粘度を得ることができる。   Further, when the second adhesive layer 9 is formed with the second insulating resin, for example, by appropriately adjusting the drying temperature of the thermosetting resin composition, it is appropriate for the heating temperature of the bonding step. A second adhesive layer (second insulating resin layer) 9 having a viscosity can be obtained. The drying temperature as used herein refers to a temperature at which, for example, a thermosetting resin composition is applied to the back surface of the second semiconductor element 8 and then the resin coating film is brought into a semi-cured state (B stage state). It is. The semi-cured thermosetting resin layer can be softened or melted by heating to a temperature above the semi-cured temperature (drying temperature), so the drying temperature and the heating temperature at the time of adhesion should be adjusted appropriately. Thus, a desired viscosity at the time of adhesion can be obtained.

第１の絶縁性樹脂１１および第２の絶縁性樹脂層９は、第１の半導体素子５と第２の半導体素子８とを接着すると共に、半導体素子５、８間を封止する樹脂層を構成するものである。上述したように、第２の接着層９を主として構成する第２の絶縁性樹脂には高粘度の樹脂を用いており、第１の絶縁性樹脂１１には低粘度の樹脂を用いている。このような絶縁性樹脂の硬化前の粘度特性の違いに基づいて、第２の接着層９は弾性率が異なる2種類の絶縁性樹脂で構成されている。すなわち、第１の絶縁性樹脂１１は硬化前の低粘度特性に基づいて低弾性率を有する。一方、第２の絶縁性樹脂９は硬化前の高粘度特性に基づいて高弾性率（第１の絶縁性樹脂１１より高い弾性率）を有する。   The first insulating resin 11 and the second insulating resin layer 9 are a resin layer that bonds the first semiconductor element 5 and the second semiconductor element 8 and seals between the semiconductor elements 5 and 8. It constitutes. As described above, a high-viscosity resin is used for the second insulating resin mainly constituting the second adhesive layer 9, and a low-viscosity resin is used for the first insulating resin 11. Based on the difference in viscosity characteristics of the insulating resin before curing, the second adhesive layer 9 is composed of two types of insulating resins having different elastic moduli. That is, the first insulating resin 11 has a low elastic modulus based on the low viscosity characteristic before curing. On the other hand, the second insulating resin 9 has a high elastic modulus (an elastic modulus higher than that of the first insulating resin 11) based on the high viscosity characteristics before curing.

上述したように、弾性率が異なる2種類の絶縁性樹脂で第２の接着層９を構成することによって、ワイヤ下部の樹脂未充填部に基づく気泡の発生等を防いだ上で、封止樹脂層を兼ねる第２の接着層９に第１および第２の半導体素子５、８間の空間を保持する機能を良好に付与することができる。なお、ここで言う弾性率が異なる2種類の絶縁性樹脂とは、あくまでも硬化後の弾性率自体が異なるものであればよく、材質的には同材質の絶縁性樹脂であってもよい。   As described above, by forming the second adhesive layer 9 with two types of insulating resins having different elastic moduli, it is possible to prevent the generation of bubbles based on the resin unfilled portion below the wire, and the sealing resin. The function of maintaining the space between the first and second semiconductor elements 5 and 8 can be favorably imparted to the second adhesive layer 9 that also serves as a layer. Here, the two types of insulating resins having different elastic moduli are not limited as long as they have different elastic moduli themselves after curing, and may be insulating resins of the same material.

そして、回路基板２上に積層、配置された第１および第２の半導体素子５、８を、例えばエポキシ樹脂のような封止樹脂１３を用いて封止することによって、スタック型マルチチップパッケージ構造の半導体装置１が構成される。なお、図１では2個の半導体素子５、８を積層した構造について説明したが、半導体素子の積層数はこれに限られるものではなく、3個もしくはそれ以上であってもよいことは言うまでもない。3個以上の半導体素子を積層して半導体装置を構成する場合、半導体素子間に存在するボンディングワイヤの下部空間には低粘度の絶縁性樹脂を予め充填する。   The first and second semiconductor elements 5 and 8 stacked and arranged on the circuit board 2 are sealed using a sealing resin 13 such as an epoxy resin, for example, so that a stacked multichip package structure is formed. The semiconductor device 1 is configured. Although the structure in which two semiconductor elements 5 and 8 are stacked is described in FIG. 1, the number of stacked semiconductor elements is not limited to this, and it goes without saying that the number may be three or more. . When a semiconductor device is configured by stacking three or more semiconductor elements, a low-viscosity insulating resin is filled in advance in the lower space of the bonding wire existing between the semiconductor elements.

上述した実施形態の半導体装置１は、例えば以下のようにして作製される。まず、回路基板２上に第１の接着層６を用いて第１の半導体素子５を接着する。続いて、ワイヤボンディング工程を実施して、第１のボンディングワイヤ７で回路基板２の電極部４と第１の半導体素子５の電極パッドとを電気的に接続する。次いで、第１の半導体素子５と第１のボンディングワイヤ７との間の空間に、充填時粘度が1Pa・s以上1000Pa・s未満の範囲の第１の絶縁性樹脂１１を充填する。第１の絶縁性樹脂１１は上述したように各空間毎にポッティングして充填してもよいし、また空間全体を繋ぐように印刷して充填してもよい。第１の絶縁性樹脂１１には必要に応じて硬化処理を施す。   The semiconductor device 1 according to the above-described embodiment is manufactured as follows, for example. First, the first semiconductor element 5 is bonded onto the circuit board 2 using the first adhesive layer 6. Subsequently, a wire bonding step is performed to electrically connect the electrode portion 4 of the circuit board 2 and the electrode pad of the first semiconductor element 5 with the first bonding wire 7. Next, the first insulating resin 11 having a filling viscosity of 1 Pa · s or more and less than 1000 Pa · s is filled in the space between the first semiconductor element 5 and the first bonding wire 7. As described above, the first insulating resin 11 may be filled by potting in each space, or may be printed and filled so as to connect the entire space. The first insulating resin 11 is subjected to a curing process as necessary.

次に、第１の半導体素子５を接着した回路基板２を加熱ステージ上に載置する。一方、下面側に第２の接着層（第２の絶縁性樹脂層）９を形成した第２の半導体素子８を実装ツールで保持する。実装ツールは例えば半導体素子８の吸着保持手段と加熱機構とを備えている。実装ツールに保持された第２の半導体素子８を、第１の半導体素子５に対して位置合せした後に下降させ、第２の接着層９を第１の半導体素子５に押し当てる。この際、加熱ステージおよび実装ツールの少なくとも一方を用いて第２の接着層（第２の絶縁性樹脂層）９を加熱し、その粘度が1〜100kPa・sの範囲となるように調整する。加熱形態は第２の接着層９の接着時粘度や接着速度等を考慮して適宜に選択することができる。   Next, the circuit board 2 to which the first semiconductor element 5 is bonded is placed on the heating stage. On the other hand, the second semiconductor element 8 having the second adhesive layer (second insulating resin layer) 9 formed on the lower surface side is held by a mounting tool. The mounting tool includes, for example, a suction holding unit for the semiconductor element 8 and a heating mechanism. The second semiconductor element 8 held by the mounting tool is lowered after being aligned with the first semiconductor element 5, and the second adhesive layer 9 is pressed against the first semiconductor element 5. At this time, the second adhesive layer (second insulating resin layer) 9 is heated using at least one of a heating stage and a mounting tool, and the viscosity is adjusted to be in the range of 1 to 100 kPa · s. The heating mode can be appropriately selected in consideration of the viscosity at the time of bonding of the second adhesive layer 9 and the bonding speed.

第２の接着層（第２の絶縁性樹脂層）９はその接着時粘度に基づいて、第１および第２の半導体素子５、８間の空間を保持する機能を有しているため、第１のボンディングワイヤ７と第２の半導体素子８との接触を抑制することができる。このような状態で第２の接着層（第２の絶縁性樹脂層）９を硬化させることによって、第１のボンディングワイヤ７の下部空間に樹脂未充填部が生じることを防止しつつ、第１のボンディングワイヤ７と第２の半導体素子８との接触による絶縁不良やショート等の発生をより有効に抑制することができる。これらによって、信頼性や動作特性等をより一層向上させたスタック型マルチチップパッケージ構造の半導体装置１を実現することが可能となる。   The second adhesive layer (second insulating resin layer) 9 has a function of holding the space between the first and second semiconductor elements 5 and 8 based on the viscosity at the time of adhesion. The contact between the first bonding wire 7 and the second semiconductor element 8 can be suppressed. By curing the second adhesive layer (second insulating resin layer) 9 in such a state, the first unfilled portion is prevented from occurring in the lower space of the first bonding wire 7 while the first It is possible to more effectively suppress the occurrence of insulation failure and short circuit due to contact between the bonding wire 7 and the second semiconductor element 8. As a result, it is possible to realize a semiconductor device 1 having a stacked multichip package structure in which reliability, operating characteristics, and the like are further improved.

上述した実施形態の半導体装置１は、接着時粘度が1〜100kPa・sの範囲の第２の接着層９で第１のボンディングワイヤ７と第２の半導体素子８との接触を抑制している。これに加えて、例えば図６に示すように、第２の半導体素子８の下面、すなわち第１の半導体素子５との接着面（積層面）に絶縁層１４を形成してもよい。第２の半導体素子８の下面側に絶縁層１４を設けることによって、第１のボンディングワイヤ７と第２の半導体素子８との接触に伴う絶縁不良やショート等の発生をより確実に防止することができる。絶縁層１４には接着温度に対して耐熱性を有する絶縁性樹脂等が用いられる。   In the semiconductor device 1 according to the above-described embodiment, the contact between the first bonding wire 7 and the second semiconductor element 8 is suppressed by the second adhesive layer 9 having a viscosity at the time of bonding of 1 to 100 kPa · s. . In addition to this, for example, as shown in FIG. 6, an insulating layer 14 may be formed on the lower surface of the second semiconductor element 8, that is, on the adhesive surface (laminated surface) with the first semiconductor element 5. By providing the insulating layer 14 on the lower surface side of the second semiconductor element 8, it is possible to more reliably prevent the occurrence of insulation failure, short circuit or the like due to the contact between the first bonding wire 7 and the second semiconductor element 8. Can do. For the insulating layer 14, an insulating resin having heat resistance with respect to the bonding temperature is used.

第２の半導体素子８の下面に絶縁層１４を設ける場合には、例えば図７に示すように、第１のボンディングワイヤ７を積極的に絶縁層１４と当接させ、これによって第１のボンディングワイヤ７を回路基板２側に変形させるようにしてもよい。すなわち、絶縁層１４は単に第１のボンディングワイヤ７と第２の半導体素子８との接触に伴うショート等を抑制するだけでなく、第１のボンディングワイヤ７を積極的に回路基板２側に変形させる層として利用することができる。このように、絶縁層１４を利用して第１のボンディングワイヤ７を回路基板２側に変形させることによって、半導体装置１のより一層の薄型化を実現することが可能となる。   When the insulating layer 14 is provided on the lower surface of the second semiconductor element 8, for example, as shown in FIG. 7, the first bonding wire 7 is positively brought into contact with the insulating layer 14, thereby the first bonding. The wire 7 may be deformed to the circuit board 2 side. In other words, the insulating layer 14 not only suppresses a short circuit caused by the contact between the first bonding wire 7 and the second semiconductor element 8, but also positively deforms the first bonding wire 7 to the circuit board 2 side. It can be used as a layer to be made. As described above, by using the insulating layer 14 to deform the first bonding wire 7 toward the circuit board 2, the semiconductor device 1 can be further reduced in thickness.

ここで、図７および図８を参照して、第１のボンディングワイヤ７の変形に基づく半導体装置１の薄型化について述べる。図７は第１のボンディングワイヤ７を絶縁層１４に当接させて積極的に変形させた場合の例を示す図である。図８は第１のボンディングワイヤ７が絶縁層１４に当接していない場合の例を示す図である。第１の半導体素子５の直上における第１のボンディングワイヤ７の最大高さｈの許容範囲が60±15μmであるとする。図８に示すように、絶縁層１４が単に絶縁不良やショート等の発生を防止する機能しか有していない場合には、第２の接着層９の厚さｔ2はワイヤ高さｈの許容範囲（60±15μm）における上限値（60＋15＝75μm）に設定する必要がある。 Here, referring to FIG. 7 and FIG. 8, the thinning of the semiconductor device 1 based on the deformation of the first bonding wire 7 will be described. FIG. 7 is a view showing an example in which the first bonding wire 7 is brought into contact with the insulating layer 14 and positively deformed. FIG. 8 is a diagram illustrating an example in which the first bonding wire 7 is not in contact with the insulating layer 14. It is assumed that the allowable range of the maximum height h of the first bonding wire 7 immediately above the first semiconductor element 5 is 60 ± 15 μm. As shown in FIG. 8, when the insulating layer 14 has only a function of preventing the occurrence of an insulation failure or a short circuit, the thickness t 2 of the second adhesive layer 9 is an allowable value for the wire height h. It is necessary to set the upper limit value (60 + 15 = 75 μm) in the range (60 ± 15 μm).

これに対して、図７ではワイヤ高さｈの標準値である60μmを超えるボンディングワイヤを、第２の半導体素子８の下面に設けた絶縁層１４に当接させて回路基板２側に変形させている。すなわち、第２の接着層９の厚さｔ1をワイヤ高さｈの標準値である60μmに設定し、実際のワイヤ高さｈを60−15μm（45〜60μm）の範囲としている。このように、第１のボンディングワイヤ７を構成する複数本のワイヤのうち、少なくとも一部（この例ではワイヤ高さｈの標準値を超えたボンディングワイヤ）を積極的に絶縁層１４に当接させて変形させることによって、ワイヤ高さｈの許容範囲によらずに、第２の接着層９の厚さｔ1を設定することができる。従って、図８に示した装置構造に比べて、半導体装置１の厚さをより一層薄型化することが可能となる。 On the other hand, in FIG. 7, a bonding wire exceeding the standard value of 60 μm for the wire height h is brought into contact with the insulating layer 14 provided on the lower surface of the second semiconductor element 8 and deformed to the circuit board 2 side. ing. That is, the thickness t 1 of the second adhesive layer 9 is set to 60 μm, which is a standard value of the wire height h, and the actual wire height h is set to a range of 60-15 μm (45-60 μm). As described above, at least a part of the plurality of wires constituting the first bonding wire 7 (in this example, the bonding wire exceeding the standard value of the wire height h) is positively brought into contact with the insulating layer 14. Thus, the thickness t 1 of the second adhesive layer 9 can be set regardless of the allowable range of the wire height h. Therefore, the thickness of the semiconductor device 1 can be further reduced as compared with the device structure shown in FIG.

第２の接着層９の厚さｔ1をワイヤ高さｈの標準値（60μm）に設定した構成はあくまでも一例であり、第２の接着層９の厚さｔ1はこれに限られるものではない。第２の接着層９の厚さｔ1は、ワイヤ高さｈの標準値（60μm）以下の範囲で適宜に設定することができる。例えば、ワイヤ高さｈの許容範囲（60±15μm）における下限値（60−15＝45μm）に設定することも可能である。このような構成によれば、実際のワイヤ高さｈは45μmで一定となり、半導体装置１をさらに薄型化することができる。なお、第２の接着層９の厚さｔ1はワイヤ高さｈの下限値以下とすることも可能であるが、この場合にはボンディングワイヤ７の変形度合いが増大して接続不良等が発生しやすくなる。このため、第２の接着層９の厚さｔ1はワイヤ高さｈの許容範囲内で設定することが好ましい。 Configuration setting the thickness t 1 of the second adhesive layer 9 to the wire height standard value of h (60 [mu] m) is only an example, the thickness t 1 of the second adhesive layer 9 is limited to this Absent. The thickness t 1 of the second adhesive layer 9 can be appropriately set within the range of the standard value (60 μm) or less of the wire height h. For example, it is possible to set the lower limit value (60−15 = 45 μm) in the allowable range (60 ± 15 μm) of the wire height h. According to such a configuration, the actual wire height h is constant at 45 μm, and the semiconductor device 1 can be further thinned. Note that the thickness t 1 of the second adhesive layer 9 can be set to be equal to or less than the lower limit value of the wire height h, but in this case, the degree of deformation of the bonding wire 7 is increased, resulting in poor connection or the like. It becomes easy to do. For this reason, it is preferable to set the thickness t 1 of the second adhesive layer 9 within an allowable range of the wire height h.

第２の半導体素子８の下面側に設ける絶縁層１４は、例えば第２の接着層９の接着時温度に対する耐熱性と第１のボンディングワイヤ７を変形させることが可能な強度とを有する絶縁性樹脂により構成され、その具体的な材料については特に限定されるものではない。絶縁層１４の具体的な構成材料としては、ポリイミド樹脂、シリコーン樹脂、エポキシ樹脂、アクリル樹脂等の熱硬化性樹脂が挙げられる。このような絶縁性樹脂からなる絶縁層１４は、例えば樹脂フィルムの接着や樹脂組成物の塗布・硬化等により形成することができる。また、樹脂フィルムを適用して絶縁層１４を形成する場合、絶縁層１４を構成する樹脂フィルムに第２の接着層９となる第２の絶縁性樹脂層を形成した2層構造のフィルムを用いることも可能である。   The insulating layer 14 provided on the lower surface side of the second semiconductor element 8 is, for example, an insulating material having heat resistance to the bonding temperature of the second adhesive layer 9 and strength capable of deforming the first bonding wire 7. It is comprised with resin and the specific material is not specifically limited. Specific examples of the constituent material of the insulating layer 14 include thermosetting resins such as polyimide resin, silicone resin, epoxy resin, and acrylic resin. The insulating layer 14 made of such an insulating resin can be formed, for example, by adhesion of a resin film or application / curing of a resin composition. When the insulating layer 14 is formed by applying a resin film, a film having a two-layer structure in which a second insulating resin layer that becomes the second adhesive layer 9 is formed on the resin film that forms the insulating layer 14 is used. It is also possible.

図７に示した半導体装置１は、例えば以下のようにして作製される。まず、図９（ａ）に示すように、回路基板２上に第１の接着層６を用いて第１の半導体素子５を接着する。続いて、ワイヤボンディング工程を実施して、第１のボンディングワイヤ７で回路基板２の電極部４と第１の半導体素子５の電極パッドとを電気的に接続する。次いで、第１のボンディングワイヤ７と第１の半導体素子５との間の空間に第１の絶縁性樹脂１１を充填する。第１の絶縁性樹脂１１の充填工程は前述した通りである。   The semiconductor device 1 shown in FIG. 7 is manufactured as follows, for example. First, as shown in FIG. 9A, the first semiconductor element 5 is bonded onto the circuit board 2 using the first adhesive layer 6. Subsequently, a wire bonding step is performed to electrically connect the electrode portion 4 of the circuit board 2 and the electrode pad of the first semiconductor element 5 with the first bonding wire 7. Next, the first insulating resin 11 is filled in the space between the first bonding wire 7 and the first semiconductor element 5. The filling process of the first insulating resin 11 is as described above.

次に、図９（ｂ）に示すように、第１の半導体素子５を接着搭載した回路基板２を加熱ステージ２１上に載置する。一方、下面側に絶縁層１４および第２の接着層９を順に形成した第２の半導体素子８を実装ツール２２で保持する。実装ツール２２は例えば半導体素子８の吸着保持手段と加熱機構とを備えている。次いで、実装ツール２２に保持された第２の半導体素子８を、第１の半導体素子５に対して位置合せした後に下降させ、第２の接着層９を第１の半導体素子５に押し当てる。この際、加熱ステージ２１および実装ツール２２の少なくとも一方を用いて第２の接着層９を加熱し、その粘度が1〜100kPa・sの範囲となるように調整する。第２の接着層９の厚さは、例えばワイヤ高さｈの標準値もしくはそれ以下に設定しておく。   Next, as shown in FIG. 9B, the circuit board 2 on which the first semiconductor element 5 is bonded and mounted is placed on the heating stage 21. On the other hand, the mounting tool 22 holds the second semiconductor element 8 in which the insulating layer 14 and the second adhesive layer 9 are sequentially formed on the lower surface side. The mounting tool 22 includes, for example, a suction holding unit for the semiconductor element 8 and a heating mechanism. Next, the second semiconductor element 8 held by the mounting tool 22 is moved down after being aligned with the first semiconductor element 5, and the second adhesive layer 9 is pressed against the first semiconductor element 5. At this time, the second adhesive layer 9 is heated using at least one of the heating stage 21 and the mounting tool 22 and adjusted so that the viscosity is in the range of 1 to 100 kPa · s. The thickness of the second adhesive layer 9 is set to a standard value of the wire height h or less, for example.

第２の接着層９の厚さをワイヤ高さｈの標準値に設定した場合、第２の接着層９を第１の半導体素子５に押し付ける過程で、標準値に対してプラス側の高さを有する第１のボンディングワイヤ７は絶縁層１４と接触して回路基板２側に変形する（図９（ｃ））。実装ツール２２による第２の半導体素子８の第１の半導体素子５への押付け力（荷重）は、第１のボンディングワイヤ７の変形能や変形させるワイヤの本数等を考慮して適宜に設定する。例えば、直径25μmのボンディングワイヤを10μm変形させるのに7gの荷重が必要であるとした場合、接着時の荷重は［（変形に要する荷重（例えば7g））×（ワイヤ本数）×1.2倍）］程度とすることが好ましい。このような状態で第２の接着層９を例えば加熱して硬化させる。   When the thickness of the second adhesive layer 9 is set to the standard value of the wire height h, in the process of pressing the second adhesive layer 9 against the first semiconductor element 5, the height on the plus side with respect to the standard value is set. The first bonding wire 7 having a contact with the insulating layer 14 is deformed to the circuit board 2 side (FIG. 9C). The pressing force (load) of the second semiconductor element 8 to the first semiconductor element 5 by the mounting tool 22 is appropriately set in consideration of the deformability of the first bonding wire 7, the number of wires to be deformed, and the like. . For example, if a 7 g load is required to deform a bonding wire with a diameter of 25 μm to 10 μm, the load during bonding is [(load required for deformation (for example, 7 g)) × (number of wires) × 1.2 times]] It is preferable to set the degree. In this state, the second adhesive layer 9 is cured by heating, for example.

上述したように、第２の接着層９を第１の半導体素子５に押し付ける過程で、第１のボンディングワイヤ７の少なくとも一部を絶縁層１４に当接させて回路基板２側に変形させることによって、第１のボンディングワイヤ７の高さをいずれもワイヤ高さｈの標準値以下に揃えることができる。言い換えると、第１のボンディングワイヤ７の高さはいずれも第２の接着層９の厚さ以下となるため、第２の接着層９の厚さに基づいて半導体装置１全体をより一層薄型化することが可能となる。また、第１のボンディングワイヤ７と第２の半導体素子８との絶縁は絶縁層１４により維持されるため、絶縁不良やショート等が生じることもない。これらによって、より一層の薄型化と信頼性の向上を両立させたスタック型マルチチップパッケージ構造の半導体装置１を実現することが可能となる。   As described above, in the process of pressing the second adhesive layer 9 against the first semiconductor element 5, at least a part of the first bonding wire 7 is brought into contact with the insulating layer 14 and deformed to the circuit board 2 side. Thus, the heights of the first bonding wires 7 can be all equal to or less than the standard value of the wire height h. In other words, since the height of the first bonding wire 7 is less than or equal to the thickness of the second adhesive layer 9, the entire semiconductor device 1 is further thinned based on the thickness of the second adhesive layer 9. It becomes possible to do. Further, since the insulation between the first bonding wire 7 and the second semiconductor element 8 is maintained by the insulating layer 14, an insulation failure or a short circuit does not occur. As a result, it is possible to realize a semiconductor device 1 having a stacked multichip package structure in which further reduction in thickness and improvement in reliability are achieved.

第１のボンディングワイヤ７の第２の半導体素子８との接触による絶縁不良やショート等の発生は、図１０に示すように、第１のボンディングワイヤ７の外周面に設けた絶縁被覆層１５によっても防ぐことができる。絶縁被覆層１５は、例えば第１のボンディングワイヤ７の第２の半導体素子８との接触部に、熱硬化性の絶縁性樹脂等を吹付けや滴下等で塗布し、この絶縁性樹脂の塗布層を硬化させることにより形成することができる。   As shown in FIG. 10, the occurrence of insulation failure or short-circuit due to contact of the first bonding wire 7 with the second semiconductor element 8 is caused by the insulating coating layer 15 provided on the outer peripheral surface of the first bonding wire 7. Can also prevent. The insulating coating layer 15 is applied, for example, by spraying or dropping a thermosetting insulating resin or the like on the contact portion of the first bonding wire 7 with the second semiconductor element 8, and applying the insulating resin. It can be formed by curing the layer.

さらに、第１のボンディングワイヤ７の少なくとも一部は、絶縁被覆層１５を介して第２の半導体素子８に当接させ、この第２の半導体素子８との当接に基づく荷重の付加により回路基板２側に変形させることができる。第１のボンディングワイヤ７の変形度合い、それによるワイヤ高さ等については、絶縁層１４を適用した場合と同様とされる。このような構成によっても、第１のボンディングワイヤ７の高さを一定の値（例えばワイヤ高さｈの標準値から下限値の範囲の値）以下に揃えることができる。従って、半導体装置１全体をより一層薄型化することが可能となる。   Further, at least a part of the first bonding wire 7 is brought into contact with the second semiconductor element 8 through the insulating coating layer 15, and a circuit is applied by applying a load based on the contact with the second semiconductor element 8. The substrate 2 can be deformed. The degree of deformation of the first bonding wire 7 and the resulting wire height are the same as when the insulating layer 14 is applied. Even with such a configuration, the height of the first bonding wire 7 can be made equal to or less than a certain value (for example, a value in the range from the standard value to the lower limit value of the wire height h). Therefore, the entire semiconductor device 1 can be further reduced in thickness.

第１の半導体素子５と第２の半導体素子８との間の距離は、例えば図１１に示すように、第１の半導体素子５の接続に使用されていない電極パッド、すなわち非接続パッド（ノンコネクションパッド）上に、金属材料や樹脂材料等からなるスタッドパンプ１６を形成して維持するようにしてもよい。スタッドパンプ１６は第１のボンディングワイヤ７と第２の半導体素子８との接触に伴う絶縁不良やショート等の抑制に対して有効に機能するものである。スタッドパンプ１６の設置箇所は1箇所でもよいが、第１の半導体素子５の重心を通る3箇所以上に設置することが好ましい。   For example, as shown in FIG. 11, the distance between the first semiconductor element 5 and the second semiconductor element 8 is an electrode pad that is not used for connection of the first semiconductor element 5, that is, a non-connected pad (non-connected pad). A stud pump 16 made of a metal material, a resin material, or the like may be formed and maintained on the connection pad). The stud pump 16 functions effectively for suppressing insulation failure and short circuit caused by contact between the first bonding wire 7 and the second semiconductor element 8. Although the installation location of the stud pump 16 may be one, it is preferable to install it at three or more locations that pass through the center of gravity of the first semiconductor element 5.

非接続パッドは気泡の発生原因になる。従って、非接続パッド上に設けられたスタッドパンプ１６は気泡の抑制に対しても効果を発揮する。第１の半導体素子５と第１のボンディングワイヤ７との間の空間に第１の絶縁性樹脂１１を充填する際に、非接続パッドを第１の絶縁性樹脂１１で埋めるようにしてもよい。これによっても、非接続パッドに起因する気泡の発生を抑制することができる。さらに、半導体素子の表面にヒューズ部が存在する場合、ヒューズ部も気泡の発生原因になる。第１の絶縁性樹脂１１はヒューズ部の充填に対しても適用することができる。ヒューズ部は接続パッドに比べて小さいため、ジェット方式等を適用して第１の絶縁性樹脂１１を充填することが好ましい。   Unconnected pads cause bubbles. Therefore, the stud pump 16 provided on the non-connected pad is also effective for suppressing bubbles. When filling the space between the first semiconductor element 5 and the first bonding wire 7 with the first insulating resin 11, the non-connecting pad may be filled with the first insulating resin 11. . Also by this, generation | occurrence | production of the bubble resulting from a non-connecting pad can be suppressed. Furthermore, when a fuse portion exists on the surface of the semiconductor element, the fuse portion also causes bubbles. The first insulating resin 11 can also be applied to the filling of the fuse portion. Since the fuse portion is smaller than the connection pad, it is preferable to fill the first insulating resin 11 by applying a jet method or the like.

次に、本発明の第２の実施形態について、図１２および図１３を参照して説明する。なお、前述した第１の実施形態と同一部分には同一符号を付し、その説明を一部省略する。図１２に示す半導体装置３０は、前述した第１の実施形態と同様に、回路基板２上に第１の半導体素子５が第１の接着層６を介して接着されている。第１の半導体素子５の電極パッドは、第１のボンディングワイヤ７を介して回路基板２の電極部４と電気的に接続されている。第１の半導体素子５上には第２の半導体素子８が、接着時粘度が1kPa・s以上100kPa・s以下の熱硬化型絶縁性樹脂からなる第２の接着層９を介して接着されている。第２の接着層９は第１の実施形態における第２の絶縁性樹脂と同様である。   Next, a second embodiment of the present invention will be described with reference to FIGS. The same parts as those in the first embodiment described above are denoted by the same reference numerals, and description thereof is partially omitted. In the semiconductor device 30 shown in FIG. 12, the first semiconductor element 5 is bonded to the circuit board 2 via the first adhesive layer 6 as in the first embodiment described above. The electrode pad of the first semiconductor element 5 is electrically connected to the electrode portion 4 of the circuit board 2 via the first bonding wire 7. A second semiconductor element 8 is bonded onto the first semiconductor element 5 via a second adhesive layer 9 made of a thermosetting insulating resin having a viscosity during bonding of 1 kPa · s to 100 kPa · s. Yes. The second adhesive layer 9 is the same as the second insulating resin in the first embodiment.

第１の半導体素子５と第１のボンディングワイヤ７との間の空間には、例えば紫外線硬化型絶縁性樹脂のような光硬化型絶縁性樹脂３１が充填・硬化されている。光硬化型絶縁性樹脂３１は、例えば紫外線硬化型アクリル樹脂組成物を充填して硬化させたものである。紫外線硬化型アクリル樹脂組成物は、反応基としてアクリロイル基を有するプレポリマーやモノマーと光重合開始剤とを含有し、紫外線照射により硬化するものである。紫外線硬化型アクリル樹脂組成物等は、紫外線が照射された部分のみが硬化するため、塗布後の形状を容易に安定させることができる。   A space between the first semiconductor element 5 and the first bonding wire 7 is filled and cured with a photocurable insulating resin 31 such as an ultraviolet curable insulating resin. The photocurable insulating resin 31 is, for example, one that is filled and cured with an ultraviolet curable acrylic resin composition. The ultraviolet curable acrylic resin composition contains a prepolymer or monomer having an acryloyl group as a reactive group and a photopolymerization initiator, and is cured by ultraviolet irradiation. Since the ultraviolet curable acrylic resin composition or the like is cured only at the portion irradiated with ultraviolet rays, the shape after application can be easily stabilized.

このような光硬化型絶縁性樹脂３１は、第１のボンディングワイヤ７を第１の半導体素子５の電極パッドにボンディングした後、第２の半導体素子８の接着工程に先立って、第１の半導体素子５と第１のボンディングワイヤ７との間の空間に充填し、さらに紫外線等の光を照射して硬化させたものである。光硬化型絶縁性樹脂３１は、例えば図１３に示すように、第１の半導体素子５と第１のボンディングワイヤ７との間の空間毎に充填し、さらに紫外線等の所望の光を照射して硬化させることが好ましい。   Such a photocurable insulating resin 31 is formed by bonding the first bonding wire 7 to the electrode pad of the first semiconductor element 5 and then bonding the first semiconductor element 8 prior to the bonding process of the second semiconductor element 8. The space between the element 5 and the first bonding wire 7 is filled and further cured by irradiation with light such as ultraviolet rays. For example, as shown in FIG. 13, the photocurable insulating resin 31 is filled in each space between the first semiconductor element 5 and the first bonding wire 7 and further irradiated with desired light such as ultraviolet rays. It is preferable to cure.

このように、予め第１の半導体素子５と第１のボンディングワイヤ７との間の空間に光硬化型絶縁性樹脂３１を充填して硬化させることによって、ワイヤ下部の樹脂未充填部に基づく気泡の発生等を確実に防ぐことができる。さらに、ワイヤ下部の樹脂未充填部の発生を懸念する必要がないため、第２の接着層９にはその形状（設定した層厚等）を維持し得るような高粘度の接着剤樹脂を適用することができる。これによって、第２の接着層９に第１および第２の半導体素子５、８間の空間を保持する機能を良好に付与することが可能となる。これらによって、信頼性や動作特性等を向上させたスタック型マルチチップパッケージ構造の半導体装置３０を実現することが可能となる。   As described above, the space between the first semiconductor element 5 and the first bonding wire 7 is filled with the photocurable insulating resin 31 and cured in advance, so that the bubbles based on the resin unfilled portion below the wire. Can be reliably prevented. Furthermore, since there is no need to worry about the occurrence of a resin-unfilled portion below the wire, a high-viscosity adhesive resin that can maintain its shape (set layer thickness, etc.) is applied to the second adhesive layer 9 can do. As a result, it is possible to satisfactorily give the second adhesive layer 9 the function of maintaining the space between the first and second semiconductor elements 5 and 8. As a result, it is possible to realize a semiconductor device 30 having a stacked multichip package structure with improved reliability, operating characteristics, and the like.

熱硬化型絶縁性樹脂からなる第２の接着層９と光硬化型絶縁性樹脂３１とは、それらの硬化形態の違いに基づいて弾性率が異なる。第１の半導体素子５と第１のボンディングワイヤ７との間の空間に光硬化型絶縁性樹脂２１を充填した場合においても、弾性率が異なる2種類の絶縁性樹脂で接着層（樹脂封止層）を構成することができる。このような弾性率が異なる2種類の絶縁性樹脂で構成された樹脂層によっても、ワイヤ下部の樹脂未充填部の発生を防いだ上で、第１のボンディングワイヤ７と第２の半導体素子８との接触による絶縁不良やショート等を有効に抑制することができる。   The second adhesive layer 9 made of the thermosetting insulating resin and the photocurable insulating resin 31 have different elastic moduli based on the difference in their curing forms. Even when the space between the first semiconductor element 5 and the first bonding wire 7 is filled with the photocurable insulating resin 21, the adhesive layer (resin sealing) is made of two types of insulating resins having different elastic moduli. Layer). The resin layer composed of two types of insulating resins having different elastic moduli also prevents the resin unfilled portion below the wire from being generated, and the first bonding wire 7 and the second semiconductor element 8. It is possible to effectively suppress insulation failure and short-circuit due to contact with each other.

なお、第２の実施形態による半導体装置３０においても、第１の実施形態と同様に、第２の半導体素子８の裏面側に絶縁層を形成したり、また第１のボンディングワイヤ７の外周面に絶縁被覆層を形成することができる。さらに、これら絶縁層や絶縁被覆層を利用して、第１のボンディングワイヤ７を回路基板２側に変形させることも有効である。また、第１の半導体素子５と第２の半導体素子８との間の距離を、スタッドパンプで維持するようにしてもよい。スタッドパンプの形成は、第１のボンディングワイヤ７と第２の半導体素子８との接触に伴う絶縁不良やショート等の抑制に対して有効である。   In the semiconductor device 30 according to the second embodiment, an insulating layer is formed on the back surface side of the second semiconductor element 8 and the outer peripheral surface of the first bonding wire 7 as in the first embodiment. An insulating coating layer can be formed on the substrate. Furthermore, it is also effective to deform the first bonding wire 7 to the circuit board 2 side using these insulating layers and insulating coating layers. Further, the distance between the first semiconductor element 5 and the second semiconductor element 8 may be maintained by a stud pump. The formation of the stud pump is effective for suppressing insulation failure and short-circuit caused by contact between the first bonding wire 7 and the second semiconductor element 8.

次に、本発明の第３の実施形態について、図１４、図１５および図１６を参照して説明する。図１４は本発明の積層型電子部品を半導体装置に適用した第３の実施形態の構成を模式的に示す断面図である。なお、前述した第１および第２の実施形態と同一部分には同一符号を付し、その説明を一部省略する。同図に示す半導体装置４０は、第１の電子部品としての半導体素子４１と第２の電子部品としてのパッケージ部品４２とを積層したものであり、これらによりスタック型パッケージ構造が構成されている。このように、積層型電子部品を構成する電子部品は半導体素子単体（ベアチップ）に限らず、予め半導体素子をパッケージングした部品であってもよい。さらに、半導体素子４１やパッケージ部品４２等の半導体部品に限らす、一般的な回路部品等の電子部品であってもよい。   Next, a third embodiment of the present invention will be described with reference to FIG. 14, FIG. 15, and FIG. FIG. 14 is a cross-sectional view schematically showing a configuration of a third embodiment in which the multilayer electronic component of the present invention is applied to a semiconductor device. In addition, the same code | symbol is attached | subjected to the same part as 1st and 2nd embodiment mentioned above, and the description is partially omitted. A semiconductor device 40 shown in FIG. 1 is formed by stacking a semiconductor element 41 as a first electronic component and a package component 42 as a second electronic component, and a stack type package structure is configured by these. As described above, the electronic component constituting the multilayer electronic component is not limited to a single semiconductor element (bare chip), but may be a component in which a semiconductor element is packaged in advance. Furthermore, it may be an electronic component such as a general circuit component, not limited to a semiconductor component such as the semiconductor element 41 or the package component 42.

図１４に示す半導体装置４０は、前述した実施形態と同様に、回路基板２上に第１の電子部品としての半導体素子４１が第１の接着層６を介して接着されている。半導体素子４１の電極パッドは、第１のボンディングワイヤ７を介して回路基板２の電極部４と電気的に接続されている。半導体素子４１上には第２の電子部品としてのパッケージ部品４２が、接着時粘度が1kPa・s以上100kPa・s以下の絶縁性樹脂からなる第２の接着層９を介して接着されている。半導体素子４１と第１のボンディングワイヤ７との間の空間には、充填時粘度が1Pa・s以上1000Pa・s未満の絶縁性樹脂（第１の実施形態）、または光硬化型絶縁性樹脂（第２の実施形態）からなる絶縁性樹脂４３が充填されている。   In the semiconductor device 40 shown in FIG. 14, the semiconductor element 41 as the first electronic component is bonded to the circuit board 2 via the first adhesive layer 6 as in the above-described embodiment. The electrode pad of the semiconductor element 41 is electrically connected to the electrode portion 4 of the circuit board 2 through the first bonding wire 7. A package component 42 as a second electronic component is bonded onto the semiconductor element 41 via a second adhesive layer 9 made of an insulating resin having a viscosity at the time of bonding of 1 kPa · s to 100 kPa · s. In the space between the semiconductor element 41 and the first bonding wire 7, an insulating resin having a filling viscosity of 1 Pa · s or more and less than 1000 Pa · s (first embodiment), or a photocurable insulating resin ( Insulating resin 43 made of the second embodiment is filled.

パッケージ部品４２は、回路基板４４上に第１の半導体素子４５と第２の半導体素子４６とを順に積層した構造を有し、かつ予め封止樹脂４７でパッケージングしたものである。第１の半導体素子４５は回路基板４４上に接着剤層４８を介して接着されており、同様に第２の半導体素子４６は第１の半導体素子４５上に接着剤層４９を介して接着されている。なお、符号５０は受動部品である。このようなパッケージ部品４２は、回路基板４４が上方となるように半導体素子４１上に積層されている。さらに、回路基板４４の裏面側に設けられた電極パッド５１は、第２のボンディングワイヤ１０を介して回路基板２の電極部４と電気的に接続されている。   The package component 42 has a structure in which a first semiconductor element 45 and a second semiconductor element 46 are sequentially stacked on a circuit board 44 and is previously packaged with a sealing resin 47. The first semiconductor element 45 is bonded to the circuit board 44 via an adhesive layer 48, and similarly, the second semiconductor element 46 is bonded to the first semiconductor element 45 via an adhesive layer 49. ing. Reference numeral 50 denotes a passive component. Such a package component 42 is laminated on the semiconductor element 41 so that the circuit board 44 is on the upper side. Furthermore, the electrode pad 51 provided on the back side of the circuit board 44 is electrically connected to the electrode portion 4 of the circuit board 2 through the second bonding wire 10.

そして、回路基板２上に積層、配置された半導体素子４１およびパッケージ部品４２を、例えばエポキシ樹脂のような封止樹脂１３を用いて封止することによって、スタック型パッケージ構造を有する半導体装置４０が構成されている。このような半導体装置４０においても、第１のボンディングワイヤ７の下部空間に樹脂未充填部が生じることを防止することができる。さらに、第１のボンディングワイヤ７とパッケージ部品４２とが過度に接触することで、第１のボンディングワイヤ７に接続不良等が生じることを抑制することができる。これらによって、信頼性や動作特性等をより一層向上させた半導体装置４０を実現することが可能となる。   Then, the semiconductor device 41 and the package component 42 stacked and arranged on the circuit board 2 are sealed using a sealing resin 13 such as an epoxy resin, so that the semiconductor device 40 having a stack type package structure is obtained. It is configured. Even in such a semiconductor device 40, it is possible to prevent the resin-unfilled portion from occurring in the lower space of the first bonding wire 7. Furthermore, it is possible to prevent the first bonding wire 7 from being defectively connected due to excessive contact between the first bonding wire 7 and the package component 42. As a result, it is possible to realize the semiconductor device 40 with further improved reliability, operating characteristics, and the like.

半導体素子４１とパッケージ部品４２との積層構造は、例えば図１５に示すように、回路基板２上に配置した2個の半導体素子４１、４１の上に、パッケージ部品４２を積層するようにしてもよい。このような積層構造は半導体素子４１のサイズがパッケージ部品４２と大きく異なる場合に有効である。また、パッケージ部品４２は図１６に示すように、回路基板４４を下方にして積層することも可能である。この場合、第２のボンディングワイヤ１０は回路基板４４の上面側に設けられた電極パッド５１に接続される。なお、第３の実施形態においても第１および第２の実施形態と同様に種々の変形が可能である。   For example, as shown in FIG. 15, the stacked structure of the semiconductor element 41 and the package component 42 may be formed by stacking the package component 42 on the two semiconductor elements 41, 41 arranged on the circuit board 2. Good. Such a laminated structure is effective when the size of the semiconductor element 41 is significantly different from that of the package component 42. Further, as shown in FIG. 16, the package component 42 can be laminated with the circuit board 44 facing downward. In this case, the second bonding wire 10 is connected to the electrode pad 51 provided on the upper surface side of the circuit board 44. In the third embodiment, various modifications can be made as in the first and second embodiments.

なお、本発明は上記した各実施形態に限定されるものではなく、複数の電子部品を積層して搭載した各種の積層型電子部品に適用することができる。そのような積層型電子部品についても、本発明に含まれるものである。また、本発明の実施形態は本発明の技術的思想の範囲内で拡張もしくは変更することができ、この拡張、変更した実施形態も本発明の技術的範囲に含まれるものである。   In addition, this invention is not limited to each above-mentioned embodiment, It can apply to the various laminated type electronic components which laminated | stacked and mounted the several electronic component. Such a multilayer electronic component is also included in the present invention. The embodiments of the present invention can be expanded or modified within the scope of the technical idea of the present invention, and the expanded and modified embodiments are also included in the technical scope of the present invention.

本発明の積層型電子部品を半導体装置に適用した第１の実施形態の構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of 1st Embodiment which applied the multilayer electronic component of this invention to the semiconductor device. 図１に示す半導体装置の要部を拡大して示す断面図である。FIG. 2 is an enlarged cross-sectional view showing a main part of the semiconductor device shown in FIG. 1. 図１に示す半導体装置における第１の絶縁性樹脂の充填形態の一構成例を示す平面図である。FIG. 3 is a plan view illustrating a configuration example of a filling form of a first insulating resin in the semiconductor device illustrated in FIG. 1. 図１に示す半導体装置における第１の絶縁性樹脂の充填形態の他の構成例を示す平面図である。It is a top view which shows the other structural example of the filling form of the 1st insulating resin in the semiconductor device shown in FIG. 本発明の実施形態による半導体装置に適用可能な絶縁性樹脂（接着剤樹脂）の粘度特性の一例を示す図である。It is a figure which shows an example of the viscosity characteristic of insulating resin (adhesive resin) applicable to the semiconductor device by embodiment of this invention. 図１に示す半導体装置の一変形例を示す断面図である。FIG. 10 is a cross-sectional view showing a modification of the semiconductor device shown in FIG. 1. 図６に示す半導体装置の要部を拡大して示す断面図である。FIG. 7 is an enlarged cross-sectional view showing a main part of the semiconductor device shown in FIG. 6. 図７との比較として示した半導体装置の要部拡大断面図である。FIG. 8 is an enlarged cross-sectional view of a main part of the semiconductor device shown as a comparison with FIG. 7. 図７に示す半導体装置の要部製造工程を示す断面図である。FIG. 8 is a cross-sectional view showing a main part manufacturing process of the semiconductor device shown in FIG. 7. 図１に示す半導体装置の他の変形例を示す断面図である。FIG. 10 is a cross-sectional view showing another modification of the semiconductor device shown in FIG. 1. 図１に示す半導体装置のさらに他の変形例を示す断面図である。FIG. 10 is a cross-sectional view showing still another modification of the semiconductor device shown in FIG. 1. 本発明の積層型電子部品を半導体装置に適用した第２の実施形態の構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of 2nd Embodiment which applied the multilayer electronic component of this invention to the semiconductor device. 図１２に示す半導体装置における光硬化型絶縁性樹脂の充填・硬化形態の一構成例を示す平面図である。It is a top view which shows one structural example of the filling and hardening form of the photocurable insulating resin in the semiconductor device shown in FIG. 本発明の積層型電子部品を半導体装置に適用した第３の実施形態の構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of 3rd Embodiment which applied the multilayer electronic component of this invention to the semiconductor device. 図１４に示す半導体装置の一変形例を示す断面図である。FIG. 15 is a cross-sectional view showing a modification of the semiconductor device shown in FIG. 14. 図１４に示す半導体装置の他の変形例を示す断面図である。FIG. 15 is a cross-sectional view showing another modification of the semiconductor device shown in FIG. 14.

符号の説明Explanation of symbols

１，３０，４０…半導体装置、２…回路基板、４…電極部、５…第１の半導体素子、６…第１の接着層、７…第１のボンディングワイヤ、８…第２の半導体素子、９…第２の接着層、１０…第２のボンディングワイヤ、１１…第１の絶縁性樹脂、１３…封止樹脂、１４…絶縁層、１５…絶縁被覆層、１６…スタッドバンプ、３１…光硬化型絶縁性樹脂、４１，４４，４６…半導体素子、４２…パッケージ部品。   DESCRIPTION OF SYMBOLS 1,30,40 ... Semiconductor device, 2 ... Circuit board, 4 ... Electrode part, 5 ... 1st semiconductor element, 6 ... 1st adhesion layer, 7 ... 1st bonding wire, 8 ... 2nd semiconductor element , 9 ... second adhesive layer, 10 ... second bonding wire, 11 ... first insulating resin, 13 ... sealing resin, 14 ... insulating layer, 15 ... insulating coating layer, 16 ... stud bump, 31 ... Photo-curable insulating resin, 41, 44, 46... Semiconductor element, 42.

Claims (5)

電極部を有する基板と、
前記電極部に第１のボンディングワイヤを介して接続された第１の電極パッドを有し、前記基板上に第１の接着層を介して接着された第１の電子部品と、
前記電極部に第２のボンディングワイヤを介して接続された第２の電極パッドを有し、前記第１の電子部品上に第２の接着層を介して接着された第２の電子部品とを具備し、
前記第２の接着層は、前記第１の電子部品と前記第１のボンディングワイヤとの間の空間に充填された第１の絶縁性樹脂と、前記第１の電子部品と前記第２の電子部品とを接着するように配置され、前記第１の絶縁性樹脂とは弾性率が異なる第２の絶縁性樹脂とを有することを特徴とする積層型電子部品。 A substrate having an electrode part;
A first electronic component having a first electrode pad connected to the electrode portion via a first bonding wire, and bonded to the substrate via a first adhesive layer;
A second electronic component having a second electrode pad connected to the electrode portion via a second bonding wire and bonded to the first electronic component via a second adhesive layer; Equipped,
The second adhesive layer includes a first insulating resin filled in a space between the first electronic component and the first bonding wire, the first electronic component, and the second electron. A multilayer electronic component comprising: a second insulating resin which is arranged so as to adhere to a component and has a different elastic modulus from the first insulating resin. 電極部を有する基板と、
前記電極部に第１のボンディングワイヤを介して接続された第１の電極パッドを有し、前記基板上に第１の接着層を介して接着された第１の電子部品と、
前記電極部に第２のボンディングワイヤを介して接続された第２の電極パッドを有し、前記第１の電子部品上に第２の接着層を介して接着された第２の電子部品とを具備し、
前記第２の接着層は、前記第１の電子部品と前記第１のボンディングワイヤとの間の空間に充填され、充填時粘度が1Pa・s以上1000Pa・s未満の範囲の第１の絶縁性樹脂と、前記第１の電子部品と前記第２の電子部品とを接着するように配置され、接着時粘度が1kPa・s以上100kPa・s以下の範囲の第２の絶縁性樹脂とを有することを特徴とする積層型電子部品。 A substrate having an electrode part;
A first electronic component having a first electrode pad connected to the electrode portion via a first bonding wire, and bonded to the substrate via a first adhesive layer;
A second electronic component having a second electrode pad connected to the electrode portion via a second bonding wire and bonded to the first electronic component via a second adhesive layer; Equipped,
The second adhesive layer is filled in a space between the first electronic component and the first bonding wire, and has a first insulating property with a filling viscosity of 1 Pa · s or more and less than 1000 Pa · s. A resin and a second insulating resin that is disposed so as to bond the first electronic component and the second electronic component and has a viscosity at the time of bonding of 1 kPa · s to 100 kPa · s. A multilayer electronic component characterized by 電極部を有する基板と、
前記電極部に第１のボンディングワイヤを介して接続された第１の電極パッドを有し、前記基板上に第１の接着層を介して接着された第１の電子部品と、
前記電極部に第２のボンディングワイヤを介して接続された第２の電極パッドを有し、前記第１の電子部品上に第２の接着層を介して接着された第２の電子部品とを具備し、
前記第２の接着層は、前記第１の電子部品と前記第１のボンディングワイヤとの間の空間に充填された光硬化型絶縁性樹脂と、前記第１の電子部品と前記第２の電子部品とを接着するように配置され、接着時粘度が1kPa・s以上100kPa・s以下の範囲の熱硬化型絶縁性樹脂とを有することを特徴とする積層型電子部品。 A substrate having an electrode part;
A first electronic component having a first electrode pad connected to the electrode portion via a first bonding wire, and bonded to the substrate via a first adhesive layer;
A second electronic component having a second electrode pad connected to the electrode portion via a second bonding wire and bonded to the first electronic component via a second adhesive layer; Equipped,
The second adhesive layer includes a photocurable insulating resin filled in a space between the first electronic component and the first bonding wire, the first electronic component, and the second electron. A multilayer electronic component comprising: a thermosetting insulating resin which is disposed so as to adhere to a component and has a viscosity at the time of adhesion of 1 kPa · s to 100 kPa · s. 請求項１ないし請求項３のいずれか１項記載の積層型電子部品において、
前記第１および第２の電子部品は半導体素子および半導体素子を含むパッケージ部品から選ばれる少なくとも1種からなることを特徴とする積層型電子部品。 In the multilayer electronic component according to any one of claims 1 to 3,
The multilayer electronic component according to claim 1, wherein the first and second electronic components are at least one selected from a semiconductor device and a package component including the semiconductor device. 請求項１ないし請求項４のいずれか１項記載の積層型電子部品において、
前記第１のボンディングワイヤは、前記第２の電子部品の前記第１の電子部品との接着面に設けられた絶縁層、または前記第１のボンディングワイヤの外周面に設けられた絶縁被覆層を介して、前記第２の電子部品と当接して前記基板側に変形していることを特徴とする積層型電子部品。 In the multilayer electronic component according to any one of claims 1 to 4,
The first bonding wire includes an insulating layer provided on an adhesive surface of the second electronic component with the first electronic component, or an insulating coating layer provided on an outer peripheral surface of the first bonding wire. A laminated electronic component that is in contact with the second electronic component and is deformed to the substrate side.
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