JP5493311B2 - Semiconductor wafer dicing method and semiconductor device manufacturing method using the same - Google Patents

Description

  The present invention relates to a semiconductor wafer dicing method and a semiconductor device manufacturing method using the same.

  Conventionally, wire bonding connection is known as a method of connecting a semiconductor chip to a mounting substrate. However, in recent years, with the downsizing and thinning of electronic devices, there is an increasing demand for downsizing and thinning of semiconductor devices on which semiconductor chips are mounted. Therefore, instead of the conventional wire bonding connection, attention is focused on flip chip connection in which a semiconductor chip is directly connected to a mounting substrate by forming bumps (projection electrodes) on the semiconductor chip.

  For flip chip connection, there are a method of metal bonding using solder, tin or the like, a method of metal bonding by applying ultrasonic vibration, a method of maintaining mechanical contact using the shrinkage force of resin, and the like. From the viewpoint of ensuring reliability, in particular, mounting using solder is frequently used in semiconductor devices used in the above-described electronic devices.

  On the other hand, in the flip chip connection, the stress concentration on the connection part due to the difference in thermal expansion coefficient between the semiconductor chip and the mounting substrate becomes a problem. Such stress concentration can lead to breakage of the connecting portion and can be a factor of reducing connection reliability. Therefore, conventionally, the gap between the semiconductor chip and the mounting substrate has been sealed by injecting a liquid resin utilizing a capillary phenomenon.

In such a conventional sealing method, for example, the pitch of the semiconductor chip is becoming narrower and the gap between the semiconductor chip and the substrate is becoming narrower, such as COF (Chip On Film) which is a mounting package of the liquid crystal driver IC. Then, it may be difficult to inject the liquid resin. Therefore, in order to deal with the problem of liquid resin injection, a method of providing a sealing paste or film resin on the semiconductor chip or mounting substrate in advance and simultaneously sealing the connection has been developed. Studies on suitable sheet-like resin compositions and the like are underway (see Patent Documents 1 to 5).
JP 2004-349561 A Japanese Patent Laid-Open No. 2000-10082 JP 2003-142529 A JP 2001-332520 A JP 2005-28734 A

  By the way, in the manufacturing process of the semiconductor device described above, in order to cope with the thinning of the semiconductor device and the multi-layer stacking of the semiconductor chips, a grinding process called back grind processing in the state of the semiconductor wafer or the semiconductor after the thinning is performed. A process of dicing the wafer into individual chips is included. For this reason, when sealing is performed simultaneously with connection by providing a sealing resin, it is required to improve workability in each process and sufficiently ensure the productivity of the semiconductor device.

  In addition, the demand for thinning semiconductor wafers is becoming stricter. Therefore, there is a need for a technique for reducing damage to a semiconductor wafer whose mechanical strength is reduced due to thinning as much as possible and preventing cracking and chipping during dicing.

  The present invention has been made to solve the above problems, and it is possible to ensure sufficient productivity, and to suppress the occurrence of cracks and chipping of the semiconductor wafer during dicing, and a method for dicing the semiconductor wafer. It is an object of the present invention to provide a method for manufacturing a used semiconductor device.

  In order to solve the above-mentioned problems, a semiconductor wafer dicing method according to the present invention is a support tape fixing in which a first support tape is attached and fixed to a semiconductor wafer having a protruding electrode on a circuit surface. A step of forming a groove portion on the circuit surface along the dicing pattern in a state of being fixed to the first support tape, and a resin layer forming an insulating resin layer on the circuit surface so as to embed the protruding electrode Forming process, wafer thinning process in which the semiconductor wafer is ground and thinned from the opposite side so that the groove is exposed after the first support tape is peeled off, and the second support is provided on the surface of the insulating resin layer. After the tape is pasted and fixed, the insulating resin layer is cut along the dicing pattern by extending the second support tape in the in-plane direction, and the semiconductor wafer is divided into a plurality of semiconductor chips. It is characterized with the resin layer cutting step of, further comprising a.

  In this semiconductor wafer dicing method, after forming a groove portion on the circuit surface of the semiconductor wafer along the dicing pattern, the semiconductor wafer is thinned by grinding from the opposite surface side so that the groove portion is exposed. Disconnect. Further, after the semiconductor wafer is cut, the supporting tape attached to the surface of the insulating resin layer is stretched, and the insulating resin layer is cut by the stretching force. In this method, since semiconductor chips having an insulating resin layer on the circuit surface can be collectively formed by dicing, the workability is excellent compared with the case where the insulating resin layer is individually provided on the semiconductor chip. Moreover, by forming a groove in advance on the circuit surface of the semiconductor wafer, damage to the semiconductor wafer during dicing can be reduced, and the occurrence of cracks and chips can be suppressed.

  The semiconductor wafer dicing method according to the present invention includes a support tape fixing step of attaching and fixing a first support tape to the opposite surface of the circuit surface to a semiconductor wafer having a protruding electrode on the circuit surface; A groove portion forming step of forming a groove portion on the circuit surface along the dicing pattern in a state of being fixed to the support tape, a resin layer forming step of forming an insulating resin layer on the circuit surface so as to embed the protruding electrode, After peeling the support tape of 1, the second support tape is attached and fixed to the surface of the insulating resin layer, and the semiconductor wafer is ground and thinned from the opposite surface side so that the groove is exposed. A step of cutting the insulating resin layer along the dicing pattern by extending the second support tape in the in-plane direction, and dividing the semiconductor wafer into a plurality of semiconductor chips; and It is characterized by comprising.

  In this semiconductor wafer dicing method, after forming a groove portion on the circuit surface of the semiconductor wafer along the dicing pattern, the semiconductor wafer is thinned by grinding from the opposite surface side so that the groove portion is exposed. Disconnect. Further, after the semiconductor wafer is cut, the supporting tape attached to the surface of the insulating resin layer is stretched, and the insulating resin layer is cut by the stretching force. In this method, since semiconductor chips having an insulating resin layer on the circuit surface can be collectively formed by dicing, the workability is excellent compared with the case where the insulating resin layer is individually provided on the semiconductor chip. Moreover, by forming a groove in advance on the circuit surface of the semiconductor wafer, damage to the semiconductor wafer during dicing can be reduced, and the occurrence of cracks and chips can be suppressed. In addition, since the semiconductor wafer is thinned with the support tape attached to the surface of the insulating resin layer, grinding dust during dicing is prevented from adhering to the insulating resin layer without requiring special treatment. it can. This contributes to prevention of insulation failure caused by adhesion of grinding scraps and generation of voids.

  Further, it is preferable to use a resin having a light transmittance of 10% or more for visible light as a material for forming the insulating resin layer. In this way, when a reference mark for alignment for each semiconductor chip is provided on the circuit surface of the semiconductor wafer, the reference mark can be easily recognized through the insulating resin layer. Therefore, it is possible to improve the alignment workability when mounting the semiconductor chip.

  Further, it is preferable to use a resin that does not cause foaming of resin at the connection temperature as a material for forming the insulating resin layer. In this case, since the generation of voids in the insulating resin layer can be suppressed during the mounting of the semiconductor chip, the connection reliability can be improved.

  In the resin layer forming step, it is preferable to form an insulating resin layer on the circuit surface by laminating a film-like resin composition. In this case, high workability can be ensured by using a film-like resin composition that is easy to handle.

  Moreover, it is preferable that an insulating resin layer contains a polyimide resin, an epoxy resin, and a hardening | curing agent. In this case, high heat resistance of the insulating resin layer and high connection reliability after sealing can be ensured.

  Also, the method for manufacturing a semiconductor device according to the present invention includes the step of peeling the second support tape from the semiconductor chip separated by the above-described semiconductor wafer dicing method, and then mounting it on the surface of the insulating resin layer in the semiconductor chip. The substrate is pressed and heated at a predetermined connection temperature to electrically connect the protruding electrode of the semiconductor chip and the electrode of the mounting substrate, and the insulating resin between the circuit surface of the semiconductor chip and the surface of the mounting substrate It is characterized by comprising a substrate mounting process for sealing with a layer.

  In this method of manufacturing a semiconductor device, after forming a groove on the circuit surface of the semiconductor wafer along the dicing pattern, the semiconductor wafer is thinned by grinding the semiconductor wafer from the opposite surface side so that the groove is exposed. Disconnect. Further, after the semiconductor wafer is cut, the supporting tape attached to the surface of the insulating resin layer is stretched, and the insulating resin layer is cut by the stretching force. In this method, since semiconductor chips having an insulating resin layer on the circuit surface can be collectively formed by dicing, the workability is excellent compared with the case where the insulating resin layer is individually provided on the semiconductor chip. Moreover, by forming a groove in advance on the circuit surface of the semiconductor wafer, damage to the semiconductor wafer during dicing can be reduced, and the occurrence of cracks and chips can be suppressed.

  According to the present invention, productivity can be sufficiently ensured, and the occurrence of cracks and chipping of a semiconductor wafer during dicing can be suppressed.

  Hereinafter, preferred embodiments of a semiconductor wafer dicing method and a semiconductor device manufacturing method according to the present invention will be described in detail with reference to the drawings.

  The semiconductor wafer dicing method and the semiconductor device manufacturing method are applied to COF (Chip On Film) mounting of a driver IC for a liquid crystal display (LCD), for example. First, as shown in FIG. 1, a semiconductor wafer 1 is prepared. The semiconductor wafer 1 has a disk shape with a thickness of about 600 μm to 725 μm, for example. On the circuit surface S1 of the semiconductor wafer 1, a plurality of protruding electrodes 2 formed by, for example, gold plating are provided at a predetermined pitch. In addition, a dicing pattern used for dicing the semiconductor wafer 1 and a reference mark for aligning the protruding electrode 2 with an electrode 15 of the mounting substrate 12 described later are formed on the circuit surface S1 (both are not present). (Illustrated).

  Next, as shown in FIG. 2, a dicing tape (first support tape) 4 is attached to the surface S2 opposite to the circuit surface S1 of the semiconductor wafer 1, and the semiconductor wafer 1 is fixed on the dicing tape 4 (support tape). Fixing process). A metal wafer ring 5 surrounding the semiconductor wafer 1 is fixed on the dicing tape 4. The wafer ring 5 functions as a fixing jig for the semiconductor wafer 1 during dicing. As the dicing tape 4, a tape whose adhesive layer has a reduced adhesive strength by heating or ultraviolet irradiation is used.

  Subsequently, a groove portion 41 is formed in the circuit surface S1 of the semiconductor wafer 1 along the dicing pattern (groove portion forming step). In the groove forming process, as shown in FIG. 3, the semiconductor wafer 1 fixed to the dicing tape 4 is placed on the stage 8 of the dicing apparatus with the circuit surface S1 facing upward. Then, after recognizing the dicing pattern, the semiconductor wafer 1 is half-cut with a dicing blade to form the groove 41. The depth of the groove 41 to be formed is made larger than the desired thickness of the semiconductor chip 10. For example, when manufacturing the semiconductor chip 10 having a thickness of 100 μm, the depth of the groove 41 is set to 100 μm or more.

  After the formation of the groove portion 41, the semiconductor wafer 1 is peeled from the dicing tape 4, and as shown in FIG. 4, the insulating resin layer 3 is formed on the circuit surface S1 of the semiconductor wafer 1 so as to embed the protruding electrodes 2 (resin Layer forming step). The insulating resin layer 3 is a layer used for sealing between the surface of the semiconductor chip 10 and the surface of the mounting substrate 12 (see FIG. 11), and the thickness of the insulating resin layer 3 is, for example, that of the protruding electrode 2 It is preferable that the height and the height of the electrode 15 of the mounting substrate 12 are approximately the same.

  Insulating resin layer 3 is preferably formed, for example, by bonding a film-like resin with a roll laminator or a vacuum laminator from the viewpoint of ensuring workability. In addition, the insulating resin layer 3 may be formed, for example, by applying a resin varnish by spin coating and drying it, or by applying a resin varnish or pasty resin by a printing method and drying it. May be.

  As a material for forming the insulating resin layer 3, a resin composition having transparency to visible light is selected so that the reference mark formed on the circuit surface S 1 of the semiconductor wafer 1 can be recognized through the insulating resin layer 3. Is done. The light transmittance of the insulating resin layer 3 is preferably 10% or more with respect to light having a wavelength of 555 nm, which is visible light, for example. As the material for forming the insulating resin layer 3, a resin composition that does not cause resin foaming at the connection temperature (for example, 300 ° C. or higher) between the semiconductor chip 10 and the mounting substrate 12 is selected.

  More specifically, the insulating resin layer 3 includes a thermosetting component and its curing agent. Examples of the thermosetting component include epoxy resin, bismaleimide resin, polyamide resin, polyimide resin, triazine resin, cyanoacrylate resin, phenol resin, unsaturated polyester resin, melamine resin, urea resin, benzoxazine resin, polyurethane resin, poly Examples include isocyanate resins, furan resins, resorcinol resins, xylene resins, benzoguanamine resins, diallyl phthalate resins, silicone resins, polyvinyl butyral resins, siloxane-modified epoxy resins, siloxane-modified polyamideimide resins, and acrylate resins. Of these thermosetting components, epoxy resin, benzoxazine resin, siloxane-modified epoxy resin, and siloxane-modified polyamideimide resin are particularly preferable from the viewpoint of heat resistance. These resins can be used alone or as a mixture of two or more.

  Examples of the curing agent include phenol resin, aliphatic amine, alicyclic amine, aromatic polyamine, polyamide, aliphatic acid anhydride, alicyclic acid anhydride, aromatic acid anhydride, dicyandiamide, and organic acid dihydrazide. , Boron trifluoride amine complexes, imidazoles, tertiary amines, organic peroxides and the like. These can be used alone or as a mixture of two or more. Of the combination of thermosetting component and curing agent, epoxy resin and phenol resin, and epoxy resin and imidazole are particularly preferable from the viewpoints of heat resistance and shape retention.

  The insulating resin layer 3 may contain a thermoplastic component. Examples of the thermoplastic component include polyester resin, polyether resin, polyamide resin, polyamideimide resin, polyimide resin, polyacrylate resin, polyvinyl butyral resin, polyurethane resin, phenoxy resin, polyacrylate resin, polybutadiene, acrylonitrile butadiene copolymer, Examples include acrylonitrile butadiene rubber styrene resin, styrene butadiene copolymer, and acrylic acid copolymer. These can be used alone or in combination of two or more. Of these thermoplastic components, polyimide resins and phenoxy resins are particularly preferable from the viewpoints of heat resistance and film formability.

  Furthermore, the insulating resin layer 3 may contain an inorganic filler for reducing the thermal expansion. The filler type, particle size, and blending amount of the inorganic filler are appropriately selected so that the light transmittance for visible light does not fall below 10%. In addition, the insulating resin layer 3 may contain additives such as a curing accelerator, a silane coupling agent, a titanium coupling agent, an antioxidant, a leveling agent, and an ion trapping agent. These may be used alone or in combination of two or more. A compounding quantity is suitably selected for every additive.

  After the formation of the insulating resin layer 3, the semiconductor wafer 1 is ground and thinned from the opposite surface S2 side (wafer thinning step). In the wafer thinning process, first, as shown in FIG. 5, a back grind tape 42 is attached to the surface of the insulating resin layer 3. Next, as shown in FIG. 6, the semiconductor wafer fixed to the back grind tape 42 is placed on the stage 6 of the grinding apparatus with the opposite surface S2 opposite to the circuit surface S1 facing upward. Then, the grinding wheel 7 is pressed against the opposite surface S2 of the semiconductor wafer 1, and the semiconductor wafer 1 is thinned so that the groove 41 is exposed on the opposite surface S2 side. Finally, the semiconductor wafer 1 is thinned so that the thickness becomes, for example, about 50 μm to 550 μm. The back grind tape 42 is not necessarily used.

  After the wafer thinning step, the insulating resin layer 3 is cut along the dicing pattern, and the semiconductor wafer 1 is separated into a plurality of semiconductor chips 10 (resin layer cutting step). In the resin layer cutting step, first, as shown in FIG. 7, a dicing tape (second support tape) 43 is attached to the opposite surface S <b> 2 of the semiconductor wafer 1, and the semiconductor wafer 1 is fixed on the dicing tape 43.

  At this time, the back grind tape 42 is preferably peeled off from the surface of the insulating resin layer 3 after the dicing tape 43 is fixed. Similarly to the case of FIG. 2, the metal wafer ring 5 surrounding the semiconductor wafer 1 is fixed on the dicing tape 43 and the wafer ring 5 is fixed to the fixing jig 32 of the pickup device. Then, as shown in FIG. 8, the push-up jig 33 is pushed up from the dicing tape 43 side toward the semiconductor wafer 1, and the dicing tape 43 is isotropically extended in the in-plane direction.

  The insulating resin layer 3 is cut at a position corresponding to the groove 41 by the force of the dicing tape 43 extending, and the semiconductor wafer 1 is separated into a plurality of semiconductor chips 10 along the dicing pattern. The size of the semiconductor chip 10 is not particularly limited, but the COF of the liquid crystal display driver IC has a rectangular size of, for example, 1 mm to 3 mm × 10 mm to 25 mm. Thereafter, the dicing tape 43 is irradiated with ultraviolet rays to cure the adhesive layer, and the semiconductor chip 10 is peeled from the dicing tape 43.

  Next, the separated semiconductor chip 10 is aligned with the mounting substrate 12 (alignment process). In the alignment step, first, the semiconductor chip 10 is picked up by a pickup device and is adsorbed on the bottom surface of the alignment head 13 so that the circuit surface S1 faces downward as shown in FIG. Next, the alignment head 13 is transferred onto the stage 14 of the alignment apparatus.

  The mounting substrate 12 is placed in advance on the stage 14 of the alignment apparatus so that the circuit surface S3 faces upward. On the circuit surface S3 of the mounting substrate 12, for example, a plurality of electrodes 15 in which a copper surface is tin-plated and a reference mark (not shown) corresponding to the reference mark on the semiconductor chip 10 side are formed. The relative positional relationship between the reference mark formed on the reference numeral 12 and the reference mark on the semiconductor chip 10 side is defined. Then, by using the recognition camera 16, the two reference marks are recognized, the position of the alignment head 13 or the stage 14 is adjusted so as to match the prescribed positional relationship, and the protruding electrode 2 of the semiconductor chip 10 is mounted. Alignment with the electrode 15 of the substrate 12 is performed.

  After the alignment step, the semiconductor chip 10 and the mounting substrate 12 are temporarily fixed (temporary fixing step). In the temporary fixing step, as shown in FIG. 10, the alignment head 13 is lowered, the mounting substrate 12 is pressed against the surface of the insulating resin layer 3 in the semiconductor chip 10, and heating is performed at a temperature lower than the connection temperature. . The heating temperature at this time should just be the temperature which the insulating resin layer 3 shows adhesiveness, for example, is set in the range of 40 to 100 degreeC. Thereby, the semiconductor chip 10 and the mounting substrate 12 are fixed with a strength that does not cause misalignment.

  Next, the protruding electrode 2 of the semiconductor chip 10 is connected to the electrode 15 of the mounting substrate 12 (substrate mounting process). In the substrate mounting process, first, the temporarily fixed semiconductor chip 10 and the mounting substrate 12 are placed on the stage 18 of the connection device. Then, as shown in FIG. 11, heating is performed at a connection temperature of about 300 ° C. while pressing the mounting substrate 12 against the surface of the insulating resin layer 3 in the semiconductor chip 10 by the connection head 17.

  Thereby, the protruding electrode 2 of the semiconductor chip 10 and the electrode 15 of the mounting substrate 12 are electrically connected, and the insulating resin layer 3 is melted by heating, so that the circuit surface S1 of the semiconductor chip 10 and the mounting substrate 12 are The space between the surfaces is sealed with the insulating resin layer 3. In heating the insulating resin layer 3, either the connection head 17 or the stage 18 may be heated. Moreover, in order to advance the hardening of the insulating resin layer 3 after melting, a treatment with a heating oven or the like may be performed.

  As described above, in the method of manufacturing a semiconductor device according to this embodiment, after forming the groove portion 41 on the circuit surface S1 of the semiconductor wafer 1 along the dicing pattern, the semiconductor wafer 1 is opposed so that the groove portion 41 is exposed. The semiconductor wafer 1 is cut by grinding and thinning from the surface S2 side. In addition, after cutting the semiconductor wafer 1, the dicing tape 43 attached to the surface of the insulating resin layer 3 is stretched, and the insulating resin layer 3 is cut by the stretching force to thereby cut the semiconductor wafer 1 into a plurality of semiconductor chips 10. It is divided into pieces.

  In this method, since the semiconductor chip 10 having the insulating resin layer on the circuit surface S1 can be collectively formed by dicing, the workability is superior to the case where the insulating resin layer 3 is individually provided on the semiconductor chip 10. . Further, by forming the groove portion 41 in advance on the circuit surface S1 of the semiconductor wafer 1, damage to the semiconductor wafer 1 during dicing can be reduced, and generation of cracks and chips can be suppressed.

  In the present embodiment, as a pre-process of the substrate mounting process, the alignment process of aligning the protruding electrode 2 of the semiconductor chip 10 with the electrode 15 of the mounting substrate 12 and the mounting of the semiconductor chip 10 after the alignment process are performed. A temporary fixing step of temporarily fixing the substrate 12. When alignment and connection are performed in the same process, the insulating resin layer 3 continues to be heated at about 300 ° C. at the time of alignment, and the curing of the insulating resin layer 3 may proceed due to thermal history. There is. On the other hand, in this embodiment, by separating the alignment step and the substrate mounting step, it is possible to suppress the curing of the insulating resin layer 3 during the alignment, and the semiconductor chip 10 and the mounting substrate can be suppressed. 12 can be suitably connected.

  In the present embodiment, a resin having a light transmittance of 10% or more for visible light is used as a material for forming the insulating resin layer 3. Therefore, the alignment reference mark provided on the circuit surface S1 of the semiconductor wafer 1 through the insulating resin layer 3 can be easily recognized. Therefore, the workability of the alignment between the semiconductor chip 10 and the mounting substrate 12 can be improved.

  In the present embodiment, as a material for forming the insulating resin layer 3, a resin that does not cause foaming at the connection temperature is used. Thereby, when the semiconductor chip 10 and the mounting substrate 12 are connected, generation of voids in the insulating resin layer 3 can be suppressed, so that connection reliability can be improved.

  The present invention is not limited to the above embodiment. For example, in the wafer thinning process, as shown in FIG. 12, after the dicing tape 4 (see FIG. 3) used in the groove forming process is peeled off, another dicing tape (second support) is formed on the surface of the insulating resin layer 3. (Tape) 43 may be attached and fixed, and the semiconductor wafer 1 may be ground and thinned from the opposite surface S2 side so that the groove 41 is exposed.

  In this case, in the resin layer cutting step subsequent to the wafer thinning step, the wafer ring 5 is fixed on the dicing tape 43 and the wafer ring 5 is fixed to the fixing jig 32 of the pickup device as shown in FIG. The pushing jig 33 is pushed up from the dicing tape 43 side toward the semiconductor wafer 1 and the dicing tape 43 is isotropically extended in the in-plane direction, thereby cutting the insulating resin layer 3.

  Also in this method, since the semiconductor chip 10 having the insulating resin layer 3 on the circuit surface S1 can be collectively formed by dicing as in the above-described embodiment, the insulating resin layer 3 is individually provided on the semiconductor chip 10 and Compared with workability. Further, by forming the groove portion 41 in advance on the circuit surface S1 of the semiconductor wafer 1, damage to the semiconductor wafer 1 during dicing can be reduced, and generation of cracks and chips can be suppressed. Furthermore, since the semiconductor wafer 1 is thinned with the dicing tape 43 attached to the surface of the insulating resin layer 3, grinding waste during dicing adheres to the insulating resin layer 3 without requiring any special treatment. Can be prevented. This contributes to prevention of insulation failure caused by adhesion of grinding scraps and generation of voids.

  For example, as a modification after the alignment step, as shown in FIG. 14, the semiconductor chip 10 is placed on the stage 14 of the alignment apparatus so that the circuit surface S1 faces upward, and the electrode 21 is positioned downward. A polyimide substrate 22 having a high light transmittance with respect to visible light is disposed directly above the semiconductor chip 10 so that the reference mark of the semiconductor chip 10 and the polyimide substrate 22 are aligned by the recognition camera 16 disposed above the polyimide substrate 22. A reference mark may be recognized.

  In this case, in the subsequent temporary fixing step, as shown in FIG. 15, the pressure head 23 is pressed from the upper surface side of the polyimide substrate 22, and the pressure head 23 or the stage 14 is heated at 40 ° C. to 100 ° C., for example. Then, in the substrate mounting process, as shown in FIG. 16, the temporarily fixed semiconductor chip 10 and the polyimide substrate 22 are placed on the stage 18 of the connection device, and the insulating resin layer 3 in the semiconductor chip 10 is connected by the connection head 17. Heating is performed at a predetermined connection temperature while pressing the polyimide substrate 22 against the surface. The connection temperature is set to exceed 278 ° C., which is the eutectic temperature of gold and tin. For example, the stage 18 is heated at 350 ° C. to 450 ° C., and the connection head 17 is heated at 50 ° C. to 150 ° C. Such a connection method can be applied by handling the polyimide substrate 22 by a reel-to-reel method.

It is a figure which shows the 1st process of the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. It is a figure which shows a support tape fixing process. It is a figure which shows a groove part formation process. It is a figure which shows the resin layer formation process. It is a figure which shows a wafer thinning process. FIG. 6 is a diagram showing a step subsequent to FIG. 5. It is a figure which shows the resin layer cutting process. FIG. 8 is a diagram showing a step subsequent to FIG. 7. It is a figure which shows the positioning process. It is a figure which shows a temporary fixing process. It is a figure which shows a board | substrate mounting process. It is a figure which shows the modification of a wafer thinning process. It is a figure which shows the modification of a resin layer cutting process. It is a figure which shows the modification of an alignment process. It is a figure which shows the modification of a temporary fixing process. It is a figure which shows the modification of a board | substrate mounting process.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor wafer, 2 ... Projection electrode, 3 ... Insulating resin layer, 4 ... Dicing tape (support tape), 9 ... Infrared camera, 10 ... Semiconductor chip, 12 ... Mounting substrate, 13 ... Electrode, 41 ... Groove part, 43 ... dicing tape (second support tape), L ... laser beam, S1 ... circuit surface, S2 ... opposite surface.

Claims (2)

A support tape fixing step of attaching and fixing a first support tape on the opposite surface of the circuit surface to a semiconductor wafer having protruding electrodes on the circuit surface;
A groove forming step of forming a groove on the circuit surface along a dicing pattern in a state of being fixed to the first support tape;
A resin layer forming step of forming an insulating resin layer on the circuit surface so as to embed the protruding electrodes;
A wafer thinning step in which, after peeling off the first support tape, the semiconductor wafer is ground and thinned from the opposite surface side so that the groove portion is exposed;
After affixing and fixing a second support tape to the opposite surface, the insulating resin layer is cut along the dicing pattern by extending the second support tape in an in-plane direction, and the semiconductor And a resin layer cutting step for dividing the wafer into a plurality of semiconductor chips. A support tape fixing step of attaching and fixing a first support tape on the opposite surface of the circuit surface to a semiconductor wafer having protruding electrodes on the circuit surface;
A groove forming step of forming a groove on the circuit surface along a dicing pattern in a state of being fixed to the first support tape;
A resin layer forming step of forming an insulating resin layer on the circuit surface so as to embed the protruding electrodes;
A wafer thinning step in which, after peeling off the first support tape, the semiconductor wafer is ground and thinned from the opposite surface side so that the groove portion is exposed;
After affixing and fixing a second support tape to the opposite surface, the insulating resin layer is cut along the dicing pattern by extending the second support tape in an in-plane direction, and the semiconductor And a resin layer cutting step for dividing the wafer into a plurality of semiconductor chips.

Images