JP2011223454A - Multi-lane transmission method and system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide multi-lane transmission that differs in OTUk, an arbitrary number of lanes of an optical transport unit (OTU) kV having arbitrary digit number, and a volume for each lane.SOLUTION: A transmission side device sets the number of logic lanes and provides a logic lane marker corresponding to the number of the logic lanes to an optical transport unit (OTU) frame. If the number of blocks runs short because the OTU block cannot be divided equally, the OTU frame is divided into blocks after having provided dummy bytes, while if the blocks cannot be distributed equally to the logic lanes, the divided blocks with dummy blocks are provided and transmitted to a receiving side device. The receiving side device identifies the logic lanes with a logic lane marker after receiving each lane signal and removes the dummy blocks provided to the frame for linking the blocks and removes the dummy bytes provided to the frame of a signal for reproducing the original OTU frame.

Description

  The present invention relates to a multilane transmission method and system, and more particularly, to a multilane transmission method and system for transmitting a single signal through a plurality of physical lanes.

  Data traffic is increasing rapidly as the use of the Internet expands. In order to support such traffic, transmission capacity has been increased, and transmission capacity of transmission devices supporting backbone networks has been increasing. As one of the technologies supporting the increase in capacity, there is a multilane transmission technology as shown in FIG. The multi-lane transmission system shown in FIG. 1 includes a frame generation unit 11, a forward error correction (FEC) encoding unit 12, a transmission side device 10 including a distribution unit 13, a combining unit 21, an FEC decoding unit 22, and frame processing. A receiving-side device 20 including the unit 23. This system is intended to increase the capacity by transferring single data from the transmission side device 10 to the reception side device 20 using a plurality of lanes (see, for example, Non-Patent Documents 1 and 2).

  For example, a large capacity transmission of 100 Gbit / s is possible by handling transmissions at a speed of 10 Gbit / s per lane collectively for 10 lanes. Since the operation speed per lane can be reduced by using a plurality of lanes, specifications such as the operation speed required for optical components and electronic components are relaxed, and as a result, a low-cost system can be realized. It becomes possible.

  A specific example of multilane transmission is OTUk (k = 3, 4) multilane transmission defined in Annex C of ITU-T recommendation G.709 “Interfaces for Optical Transport Networks (OTN)”. G.709 Annex C defines an OTUk multilane transmission method using 40 Gbit / s, 100 Gbit / s Ethernet (40 GbE, 100 GbE) optical modules based on multilane transmission.

  Hereinafter, the operation principle of Annex C will be described.

  First, the head area (FAS: frame alignment signal) of the OTU frame shown in FIG. 16 is used as a mark, and the OTU frame is divided into blocks of 16 bytes as shown in FIG. 17, and then OTU4 (OTU3). Enables multi-lane transmission by distributing those blocks to 20 (4) logical lanes. 18 shows OTU3 multilane transmission (4 logical lanes) and OTU4 multilane transmission (20 logical lanes) according to G.709 Annex C. As shown in the figure, in block distribution to a plurality of lanes, FAS appears in each logical lane by changing the distribution start lane for each frame (lane rotation).

  FIG. 19 and FIG. 20 show the overhead used for skew detection that is actually lane identification and delay between lanes. Each channel recognizes the start position of the frame by checking the FAS overhead byte (FAS OH byte) in which a fixed bit pattern is stored. Further, during multi-lane transmission of OTU4, 240 numbers from 0 to 239 are sequentially assigned to the FAS OH byte 6 by the distribution unit 13 of the transmission side apparatus 10 and distributed to each logical lane.

For example,
-FAS OH byte 6 = "0" in logical lane 0;
-FAS OH byte 6 = "1" in logical lane 1;
-FAS OH byte 6 = "2" in logical lane 2;
・
・
-FAS OH byte 6 = "19" in logical lane 19;
Next, return to logical lane 0 again-FAS OH byte 6 = "20" in logical lane 0;
-FAS OH byte 6 = "21" in logical lane 1;
-FAS OH byte 6 = "22" in logical lane 2;
・
・
-FAS OH byte 6 = "239" in logical lane 19;
Grant as follows. If a number up to "239" is assigned, it will return to "0" again.

  On the receiving side, the remainder obtained by dividing the value of FAS OH byte 6 received for each logical lane by the number of logical lanes 20 is the number for identifying each logical lane.

  Since the number of numbers to be assigned is 240 which is a multiple of the number of logical lanes 20 (numbers to be assigned are 0 to 239), in the above example, for example, logical lane “0” always has a remainder of “0”. “1” always has a remainder of “1”, etc., and can be distinguished from other logical lanes.

  After distributing the OTUk frame to a plurality of logical lanes, multi-lane transmission is performed by bit-multiplexing the plurality of logical lanes as necessary to match the number of physical lanes actually used. For example, when OTU4 is transmitted in 4 physical lanes, 20 physical lanes are bit-multiplexed by 5 logical lanes as shown in FIG. 21, thereby generating 4 physical lanes and performing multilane transmission.

"Interfaces for the Optical Transport Network (OTN)", March 2003, ITU-T Recommendation G.709 / Y.1331 "Interfaces for the optical transport network (OTN) Amendment 3", April 2009, ITU-T G709 / Y.1331 Amendment 3

  Several problems arise when trying to realize multi-lane transmission using G.709 Amendment 3, Annex C above.

First, there is a problem that only the standard OTUk frame can be supported. G.709 defines a frame structure of 4 rows and 4080 digits (4 × 4080 = 16320 bytes) as an OTUk frame. One frame is divided into 1020 blocks every 16 bytes and distributed to logical lanes. Currently, 20 logical lanes and 4 logical lanes are divisors of 1020 (= 2 ² × 3 × 5 × 17), so that blocks can be evenly distributed to each logical lane, enabling multi-lane transmission. Yes. However, blocks cannot be evenly distributed for logical lane numbers other than a divisor of 1020. Also, in high-speed transmission, an error correction code having a redundancy different from the standard is often used, and in that case, the number of digits of the OTU frame is different from the standard (referred to as an OTUkV frame). At that time, OTUkV frames may not be divided into 16-byte blocks, and blocks may not be evenly distributed to each logical lane. Therefore, any OTUkV signal should be supported. I can't.

  Second, there is a problem that multi-lane transmission with an arbitrary number of lanes cannot be supported. In the method defined in G.709 Annex C, OTU4 is defined as 20 logical lanes and OTU3 is defined as 4 logical lanes, and physical lanes are generated by bit-multiplexing logical lanes. Therefore, the number of physical lanes that can be handled is limited to a divisor of the number of logical lanes. That is, in the case of OTU4, it is possible to correspond to the physical lanes 20, 10, 5, 4, 2 which are divisors of the logical lane number 20, and in the case of OTU3, 4,2 physical lanes which are divisors of 4. Can be supported. Therefore, it cannot be transmitted with an arbitrary number of lanes.

  Third, there is a problem that multi-lane transmission with different lane capacities cannot be supported. The method specified in G.709 Annex C assumes that the bit rate of each lane is the same. This is because each logical lane has the same bit rate, and a physical lane is generated by bit-multiplexing the same number of logical lanes. Therefore, for example, a 100 Gbit / s signal cannot be transmitted in multilane at 40 Gbit / s × 2 and 10 Gbit / s × 2.

  The present invention has been made in view of the above points, and enables multi-lane transmission of OTUk and an arbitrary number of OTUkV lanes having an arbitrary number of digits, and capacity for each OTUkV and an OTUkV lane having an arbitrary number of digits. It is an object to provide a multilane transmission method and system capable of different multilane transmissions.

  FIG. 1 is a principle configuration diagram of the present invention.

The present invention (Claim 1) includes a transmission side apparatus that transmits a single signal using a plurality of physical lanes using an OTU frame (OTUk or OTUkV) defined in Annex C of OTN (Optical Transport Network), and A multilane transmission system having a receiving side device for combining received frames,
The transmission side device 100
Logical lane marker assigning means 130 for setting the number of logical lanes according to the number of physical lanes and assigning a logical lane marker corresponding to the number of logical lanes for identifying the logical lane to the overhead area of the OTU frame;
A block dividing unit 140 for dividing the OTU frame into blocks after adding dummy bytes to the OTU frame when the OTU frame cannot be evenly divided into blocks and there are insufficient bytes;
A block distribution means 150 for distributing a block divided by assigning a dummy block to the logical lane when the block cannot be evenly distributed to the logical lane;
With
The receiving side device 200
Logical lane identification means 210 for identifying a logical lane by a logical lane marker after receiving a signal of each lane;
Block combining means 220 for combining the blocks by removing the dummy blocks attached to the signal frame;
Frame reproducing means 230 for removing the dummy bytes attached to the signal frame and reproducing the original OTU frame.

The present invention (Claim 2) is the multi-lane transmission system according to Claim 1,
Make the number of physical lanes the same as the number of logical lanes.

The present invention (Claim 3) is the multi-lane transmission system according to Claim 1,
The block dividing means 140 includes means for adding dummy columns in units of columns to the OTU frame.

The present invention (Claim 4) is the multi-lane transmission system according to Claim 1,
The transmission-side apparatus 100 includes physical lane generation means for generating a physical lane by multiplexing an arbitrary number of lanes among a plurality of logical lanes connected to the block distribution means 150.

  FIG. 2 is a diagram for explaining the principle of the present invention.

According to the present invention (Claim 5), a transmission side apparatus that transmits a single signal using an OTU frame (OTUk or OTUkV) defined by Annex C of OTN (OTUk or OTUkV) through a plurality of physical lanes, and a received frame are combined. A multilane transmission method in a multilane transmission system having a receiving side device,
In the sending device:
A logical lane marker assigning unit sets the number of logical lanes according to the number of physical lanes, and assigns a logical lane marker corresponding to the number of logical lanes for identifying the logical lane to the overhead area of the OTU frame (step 1). )When,
A block dividing step (step 2) for dividing the OTU frame into blocks after adding dummy bytes to the OTU frame when the OTU frame cannot be equally divided into blocks by the block distribution means and the bytes are insufficient;
A block distribution step (step 3) for distributing a block divided by assigning a dummy block to the logical lane and transmitting the block to the logical lane when the block distribution means cannot evenly distribute the block to the logical lane;
And
In the receiving device:
A logical lane identifying step (step 4) for identifying a logical lane by a logical lane marker after receiving a signal of each lane by the logical lane identifying means;
A block combining step (step 5) in which the block combining means removes the dummy block attached to the signal frame and combines the blocks;
A frame reproduction step (step 6) is performed in which the dummy byte added to the frame of the signal is removed by the frame reproduction means to reproduce the original OTU frame.

The present invention (Claim 6) is the multi-lane transmission method according to Claim 5,
Make the number of physical lanes the same as the number of logical lanes.

Further, the present invention (Claim 7) is the block dividing step of Claim 5,
Add a dummy column to the OTU frame for each column.

The present invention (Claim 8) is the multi-lane transmission method according to Claim 5,
A physical lane is generated by multiplexing an arbitrary number of lanes among a plurality of logical lanes connected to the block distribution means of the transmission side apparatus.

  In the present invention, when the number of logical lanes is set according to the number of physical lanes and the OTU frame is divided into blocks, if the logical lanes cannot be evenly distributed, dummy bytes are used. If there are not enough blocks when distributing, a dummy block is used to enable multi-lane transmission of any number of lanes of OTUk and OTUkV having an arbitrary number of digits.

  In addition, by generating a physical lane by multiplexing some logical lanes and generating a physical lane without multiplexing other logical lanes, the capacity of each OTUk and OTUkV lane having an arbitrary number of digits can be increased. Enable different multi-lane transmissions.

It is a principle block diagram of this invention. It is a figure for demonstrating the principle of this invention. 1 is a basic configuration diagram of a multilane transmission system according to a first embodiment of the present invention. It is a flowchart of operation | movement of the multilane transmission system in the 1st Embodiment of this invention. This is an example in which the logical lane and the physical lane are the same in the first embodiment of the present invention (when OTU4 is transmitted to 7 physical lanes). It is an example of the lane marker in the 1st Embodiment of this invention. It is an example of block division of the OTU4 frame in the first exemplary embodiment of the present invention. It is an example of block distribution to the logical lane in the 1st Embodiment of this invention. It is an example of block division of the OTU4V frame (non-standard FEC assumption, for example, the number of columns 4100) in the second embodiment of the present invention. It is an example of block distribution to the logical lane in the 2nd Embodiment of this invention. It is an example of the block division | segmentation of the OTU4V frame (4150 columns) in the 3rd Embodiment of this invention. It is an example of block distribution to the logical lane in the 3rd Embodiment of this invention. It is an additional example of the column unit in the 4th Embodiment of this invention. It is an example of unequal capacity multilane transmission in the sixth embodiment of the present invention (when OTUflex (10TS) is transmitted at 10G × 1, 25G × 2 multilane). It is a basic block diagram of the conventional multilane transmission system. OTU frame structure. This is a block division method of an OTU frame at the time of multi-lane transmission according to G.709 Annex C. This is a lane rotation method in multi-lane transmission according to G.709 Annex C. This is the overhead used for deskew and lane identification in the case of 20 logical lanes. This is the overhead used for deskew and lane identification in the case of 4 logical channels. This is an example of logical lane and physical lane (when OTU4 is transmitted in 4 physical lanes (* OTU4 is 20 logical lanes)) in multi-lane transmission according to G.709 Annex C.

  Embodiments of the present invention will be described below with reference to the drawings.

[First embodiment]
In the present embodiment, a case where a standard frame is transmitted in multilane with an arbitrary number of lanes will be described, and a case where a dummy block is used when a block cannot be evenly distributed to logical lanes will be described.

  FIG. 3 is a basic configuration diagram of the multilane transmission system according to the first embodiment of the present invention, and FIG. 4 is a flowchart of the operation of the multilane transmission system according to the first embodiment of the present invention.

  The multilane transmission system shown in the figure includes a transmission side device 100 and a reception side device 200.

  The transmission-side apparatus 100 includes a frame generation unit 110, an FEC (Forward Error Correction) encoding unit 120, a logical lane marker addition unit 130, a block division unit 140, and a block distribution unit 150.

  The frame generation unit 110 of the transmission side device 100 receives a signal from another device and generates an ODUk signal (step 101). The FEC encoding 120 adds an error correction code to the ODUk signal to generate an OTUk signal (step 102). The logical lane marker adding unit 130 adds a logical lane marker to the overhead area of the OTUk signal (step 103). The block dividing unit 140 divides the OTUk frame into a plurality of blocks (step 104). At that time, if it is not possible to divide the bytes of one block without excess or deficiency, dummy bytes corresponding to the number of bytes less than one block are assigned. The block distribution unit 150 distributes the divided blocks to a plurality of logical lanes (step 105). At that time, if the blocks cannot be evenly distributed, a shortage of dummy blocks is added so that the blocks can be evenly distributed. Thereafter, multi-lane transmission is performed using the physical lane (step 106).

  The receiving-side apparatus 200 includes a logical lane identifying unit 210, a block combining unit 220, a frame reproducing unit 230, an FEC decoding unit 240, and a frame processing unit 250.

  The logical lane identification unit 210 of the receiving apparatus 200 generates a logical lane from the received physical lane signal (step 201), and then detects the logical lane marker to recognize the number of the own lane (step). 202). The block combiner 220 eliminates the skew between the logical lanes (step 203), removes the dummy blocks added thereafter (step 204), and transfers the blocks transmitted on the plurality of logical lanes in the original order. Join side by side (step 205). The frame reproducing unit 230 removes the dummy byte added from the combined block and reproduces the original OTUk frame (step 206).

  Below, the main components among the above-described configurations will be specifically described.

  Here, as an example, a case where an OTU4 signal (4 rows, 4080 digits) is transmitted in 7 lanes by multilane transmission is shown.

  FIG. 5 shows an example in which the logical lane and the physical lane are the same in the first embodiment of the present invention (when OTU4 is transmitted to 7 physical lanes). The logical lane generation unit in the figure corresponds to the block division unit 140 and the block distribution unit 150 in FIG. Also, the physical lane termination portion corresponds to the block combining portion 220 in FIG.

  As shown in the figure, in order to realize 7 physical lanes, the same number of 7 logical lanes as the number of physical lanes are used. In order to make it possible to identify seven logical lanes, the logical lane marker assigning unit 130 of the transmission-side apparatus 100 sequentially sets seven values from 0 to 6 as logical lane markers (LLM) to frames as shown in FIG. Give. Or it is good also as giving the value of the number of multiples of seven.

  Thereafter, the block dividing unit 140 divides one frame into 16-byte blocks and divides them into 1020 blocks (4080 × 4/16 = 1020) as shown in FIG. When the block distribution unit 150 distributes 1020 blocks to 7 logical lanes in a round robin manner, 1020 blocks cannot be evenly distributed as shown in FIG. 8, and the blocks of “lane 5” and “lane 6” Is lacking. By using two dummy blocks there, it is possible to distribute evenly. For example, all the bits in the dummy block are set to “0”.

  In the receiving device 200, the logical lane identifying unit 210 identifies each logical lane from the logical lane marker, the block combining unit 220 removes the dummy block, and combines the data of each logical lane to reproduce the OTU4 frame. To do.

  In the above example, the number of logical lanes is the same as the number of physical lanes. However, the number of logical lanes may be a multiple of the number of physical lanes. In that case, it is necessary to match the value of the logical lane marker with the number of logical lanes.

[Second Embodiment]
In this embodiment, a case where a dummy block is used when a non-standard frame is subjected to multi-lane transmission with an arbitrary number of lanes and a block cannot be equally distributed to logical lanes will be described.

  The configurations of the transmission side device and the reception side device in the present embodiment are the same as those shown in FIG. 3 of the first embodiment described above.

  In the present embodiment, OTU4V 4 physical lane transmission is shown. Assuming the use of non-standard FEC, in this embodiment, a case will be described in which the number of columns is 4100 columns instead of the standard 4080 columns.

  Four logical lanes are used to realize four physical lane transmission. The logical lane marker assigning unit 130 of the transmission-side apparatus 100 sequentially assigns four values from 0 to 3 to the frame as logical lane markers (LLM) to enable identification of the four logical lanes. Thereafter, as shown in FIG. 9, when the number of columns is 4100, the block dividing unit 140 divides one frame into 16 byte blocks and divides the OTU4V frame into 1025 blocks (4100 × 4/16).

  Next, when the block distribution unit 150 distributes the 1025 blocks to the four logical lanes in a round robin manner, the 1025 blocks cannot be evenly distributed as shown in FIG. Three blocks in “lane 3” are insufficient. Therefore, it is possible to distribute evenly by using three dummy blocks. For example, all the bits in the dummy block are set to “0”.

  In the receiving-side apparatus 200, the logical lane identifying unit 210 identifies each logical lane from the logical lane marker, the block combining unit 220 removes the dummy block, and combines the data of each logical lane to generate an OTU4V frame. Reproduce.

If the bit error rate at the time of logical lane identification is extremely bad (for example, BER = 10 ^-2 ) due to the high performance of the FEC used, it is possible to use a combination of the following error tolerance improvement methods. It is. As the error tolerance improvement method, in a transmission method in which a single signal is distributed and combined in a plurality of lanes by a transmission / reception unit,
Add an error correction code for the bit string used for lane identification and skew detection;
・ Error correction using the error correction code at the time of combination;
Perform bit pattern verification using a smaller number of bits than specified in the OTN recommendation in the bit string used for lane identification and skew detection when combining;
Allow bit errors for bit strings used for lane identification and skew detection when combined;
There is a method of improving error tolerance by performing the above.

[Third Embodiment]
In the present embodiment, a case will be described in which dummy blocks and dummy bytes are used when a block cannot be evenly distributed to logical lanes when performing non-standard frame multi-lane transmission with an arbitrary number of lanes.

  The configurations of the transmission side device and the reception side device in the present embodiment are the same as those shown in FIG. 3 of the first embodiment described above.

  In this embodiment, OTU4V 5 physical lane transmission is shown. Assuming the use of non-standard FEC, the case of using 4150 columns instead of the standard 4080 columns will be described. Five logical lanes are used to realize five physical lane transmission.

  The logical lane marker assigning unit 130 sequentially assigns five values from 0 to 4 to the frame as logical lane markers (LLM) to enable identification of five logical lanes. Thereafter, the block dividing unit 140 divides the OTU4V frame into 16-byte blocks as shown in FIG. At this time, 4150 × 4/16 = 1037.5 blocks, and an OTU4V frame having 4150 columns cannot be divided into 16-byte blocks without excess or deficiency of bytes, and 8 bytes remain halfway. Therefore, 8 dummy bytes are added and divided into 1038 blocks. The dummy bytes are all set to “0”, for example. After that, if the block distribution unit 150 distributes 1038 blocks to 5 logical lanes in a round robin manner, the 1038 blocks cannot be distributed evenly as shown in FIG. 12, and “lane 3” and “lane 4” Two blocks are insufficient. By using two dummy blocks there, it is possible to distribute evenly. For example, all the bits in the dummy block are set to “0”.

  In the receiving-side apparatus 200, the logical lane identifying unit 210 identifies each logical lane from the logical lane marker, the block combining unit 220 removes the dummy block and the dummy byte, and combines the data of each logical lane. Play OTU4V frame.

[Fourth Embodiment]
In the present embodiment, a case will be described in which a dummy column is used when performing multi-lane transmission with an arbitrary number of lanes. The configurations of the transmission side device and the reception side device in the present embodiment are the same as those shown in FIG. 3 of the first embodiment described above.

In the above embodiment, in the logical lane marker assigning unit 130, dummy bytes and dummy blocks are added as a minimum so that blocks can be evenly distributed to each logical lane. However, as shown in FIG. A dummy column is added so that the block division unit 140 can divide the block into bytes without excess or deficiency, or the block distribution unit 150 can evenly distribute the blocks to the logical lane without excess or deficiency. Or you may be able to do both.
[Fifth Embodiment]
Although the above embodiment has been described using a specific number of columns and logical lanes, this embodiment shows an example in a more general form. The configurations of the transmission side device and the reception side device in the present embodiment are the same as those shown in FIG. 3 of the first embodiment described above.

In the present embodiment, an example of the number of dummy bytes and the number of dummy blocks required when the number of logical lanes is L and the number of OTUkV rows is 4 columns is shown. When trying to divide OTUkV into 16-byte blocks, the number of blocks in the OTUkV frame is 4 C.
B = 4 C / 16 = C / 4
It is expressed. However, since it may not be divisible by 16 bytes, B ′ obtained by rounding up B is the minimum number of blocks to be used.

B '= ceiling (B)
Here, ceiling (x) indicates a function for rounding up x. In order to generate B 'blocks, it is necessary to add dummy bytes, and the number D_byte is obtained by subtracting the number of bytes of the OTUkV frame from the total number of bytes of the minimum used block.
D_byte = 16 * B '-4C
It becomes. If B ′ blocks are to be evenly distributed to the L logical lanes, the number of blocks cannot be divided by the number of logical lanes depending on the number of lanes, so it is necessary to add a dummy block by the block distributing unit 150. The number of blocks B '' after adding a dummy block is
B '' = ceiling (B '/ L) * L
It becomes. The number of dummy blocks D_block required at that time is
D_block = B ''-B '
It is represented by Therefore, by using the required number of dummy bytes D_byte and the required number of dummy blocks D_block, the OTUkV signal with an arbitrary number of columns is divided into 16-byte blocks without excess or shortage of bytes, and the divided blocks are evenly distributed to each logical lane. As a result, multi-lane transmission with an arbitrary number of lanes becomes possible. The calculation results for the case of C = 4250 and L = 1-10 are shown.

以上，ブロックサイズが、１６バイトの例を示したがブロックサイズを変更することも可能である。その際も上に示したような考え方でダミーバイトやダミーブロックを付加することでマルチレーン伝送が可能となる。

The example in which the block size is 16 bytes has been described above, but the block size can be changed. Even in that case, multi-lane transmission is possible by adding dummy bytes and dummy blocks based on the concept described above.

[Sixth Embodiment]
In this embodiment, unequal capacity multilane transmission will be described. The configurations of the transmission side device and the reception side device in the present embodiment are the same as those shown in FIG. 3 of the first embodiment described above.

In the following, an example of unequal capacity multi-lane transmission of an ODUflex signal (12.5 Gbit / s, 10 tributary slots) using one 10G signal and two 1.25G signals is shown. Considering 1.25G as one unit, first distribute ODUflex frames to 10 logical lanes. As the method for dividing and distributing the ODUflex frame, the methods described in the first to fifth embodiments can be used. In addition,
ODUflex is one of ODUs, and an ODU frame is obtained by removing a column in which an error correction code is stored from an OTU frame. After that, as shown in FIG. 14, 8 of the 10 logical lanes are bit-multiplexed and 10G physical lanes are transmitted, and the remaining two logical lanes are transmitted as they are through the two 1.25G physical lanes to obtain 10G × 1, 1.25G × 2 unequal capacity multi-lane transmission is possible.

  This method is applicable to, for example, ODU-XC (cross connect) using a plurality of switches having different granularities such as 10G granularity and 1.25G granularity, and 100G client signal transfer using 10G and 40G wavelengths.

  In addition, the operation | movement of each element in the said 1st-6th embodiment shown in said FIG. 3 is constructed | assembled as a program, installed in the computer utilized as a transmission side apparatus and a reception side apparatus, or made to perform, or a network It is possible to circulate through.

  In addition, the constructed program can be stored in a portable storage medium such as a hard disk, a flexible disk, or a CD-ROM, and can be installed or distributed in a computer.

  The present invention is not limited to the above-described embodiments, and various modifications and applications can be made within the scope of the claims.

  In the above embodiments, application to multi-lane long-distance transmission has been mainly described. However, the application destination of the present invention is not limited to long-distance transmission. It can also be applied to parallel transmission and cross-connect devices with limited input port signal speed.

DESCRIPTION OF SYMBOLS 100 Transmission side apparatus 110 Frame generation part 120 FEC encoding part 130 Logical lane marker provision means, Logical lane marker provision part 140 Block division means, Block division part 150 Block distribution means, Block distribution part 200 Reception side apparatus 210 Logical lane identification means, logic Lane identifying unit 220 Block combining unit, block combining unit 230 Frame reproducing unit, frame reproducing unit 240 FEC decoding unit 250 Frame processing unit

Claims (8)

OTN (Optical Transport Network) interface recommendation G.709 Amendment 3 (2009/4) Annex C of OTU frame (OTUk or OTUkV) stipulated in Annex C Transmits a single signal over multiple physical lanes And a multilane transmission system having a receiving side device for combining received frames,
The transmitting device is:
Logical lane marker giving means for setting the number of logical lanes according to the number of physical lanes and giving a logical lane marker corresponding to the number of logical lanes for identifying the logical lane to the overhead area of the OTU frame;
A block dividing means for dividing the OTU frame into blocks after giving a dummy byte to the OTU frame when the OTU frame cannot be evenly divided into blocks and there are insufficient bytes;
If the block cannot be evenly distributed to the logical lane, block distribution means for distributing the block divided by assigning a dummy block to the logical lane;
With
The receiving side device
Logical lane identification means for identifying a logical lane by the logical lane marker after receiving the signal of each lane;
Block combining means for removing the dummy blocks attached to the signal frame and combining the blocks;
Frame reproduction means for reproducing the original OTU frame by removing dummy bytes attached to the frame of the signal;
A multi-lane transmission system comprising: The multi-lane transmission system according to claim 1, wherein the number of physical lanes and the number of logical lanes are the same. The block dividing means includes
2. The multilane transmission system according to claim 1, further comprising means for adding a dummy column in units of columns to the OTU frame. The transmitting device is:
The multi-lane transmission according to claim 1, further comprising physical lane generation means for generating a physical lane by multiplexing an arbitrary number of lanes among a plurality of logical lanes connected to the block distribution means. system. OTN (Optical Transport Network) interface recommendation G.709 Amendment 3 (2009/4) Annex C of OTU frame (OTUk or OTUkV) stipulated in Annex C Transmits a single signal over multiple physical lanes And a multilane transmission method in a multilane transmission system having a receiving side device for combining received frames,
In the transmission side device,
A logical lane marker providing step for setting the number of logical lanes according to the number of physical lanes by the logical lane marker providing means, and assigning a logical lane marker corresponding to the number of logical lanes for identifying the logical lane to the overhead area of the OTU frame;
When the block distribution means cannot evenly divide the OTU frame into blocks and there are insufficient bytes, a block dividing step of dividing the OTU frame into blocks after adding dummy bytes to the OTU frame;
If the block distribution means cannot distribute the blocks evenly to the logical lanes, a block distribution step of distributing the blocks divided by assigning dummy blocks to the logical lanes and transmitting them to the receiving side device;
And
In the receiving device,
A logical lane identification step of identifying a logical lane by the logical lane marker after receiving a signal of each lane by the logical lane identification means;
A block combining step of combining the blocks by removing the dummy blocks attached to the frame of the signal by the block combining means;
A frame playback step of playing back the original OTU frame by removing dummy bytes attached to the frame of the signal by frame playback means;
A multilane transmission method comprising: 6. The multilane transmission method according to claim 5, wherein the number of physical lanes and the number of logical lanes are the same. In the block dividing step,
6. The multilane transmission method according to claim 5, wherein dummy columns are added to the OTU frame in units of columns. In the transmission side device,
6. The multi-lane transmission method according to claim 5, wherein a physical lane is generated by multiplexing an arbitrary number of lanes among a plurality of logical lanes connected to the block distribution unit.

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