JP6461299B1 - Frame transmitting apparatus and frame receiving apparatus - Google Patents

Abstract

A frame transmission apparatus capable of realizing a small data transfer processing delay is provided.
A frame transmitting apparatus for distributing and outputting data of a frame containing a client signal to n logical lanes in units of m-byte blocks, and for identifying a position of the distributed logical lane The data array conversion unit that inputs the data of the frame to which the frame is assigned as a parallel signal, distributes the data to the logical lane in blocks, and the data that changes the position of the logical lane to which the frame is distributed according to the marker value A rotation unit, and the data array conversion unit sequentially stores the input frame data in a plurality of memories in synchronization with the processing clock, and when the m × n byte frame data is stored, The data allocation of multiple memories is arranged in parallel so that the data of blocks divided in units of m bytes from the beginning of the data of the same frame is allocated Instead and outputs.
[Selection] Figure 5

Description

  The present invention relates to a transmission technique for a frame storing digital data, and more particularly to a frame transmission apparatus and a frame reception apparatus that distribute a frame to a plurality of logical lanes and transmit the frame in parallel.

  In the current backbone communication network, "ITU-T G.709 / Y.1331" recommended by the International Telecommunication Union-Telecommunication Standardization Sector (ITU-T), an international standardization organization. Is widely used. This optical transmission standard is also called “Optical Transport Network” (OTN). It is a supervisory control system, Ethernet (registered trademark) and synchronous digital hierarchy, which is conscious of wavelength division multiplexing (WDM) signal management. It defines bit rates, mapping methods, etc. for accommodating various client signals such as (Synchronous Digital Hierarchy, SDH) and transmitting them transparently. (See Non-Patent Document 1)

  FIG. 1 is a diagram for explaining the structure of an OTN frame. Note that the overhead of storing address information and various monitoring signals used when transmitting data is added to the beginning of the various frames that make up the OTN frame, but in the following, the overhead is abbreviated as OH and stored in OH. Information and signals transmitted in this manner will be abbreviated as OH information. The OPUk frame 110 includes a payload area 112 in which a client signal 100 such as Ethernet (registered trademark) or SDH is accommodated, and an OPUk (Optical Channel Payload Unit-k) OH 114 that is OH that provides accommodation information of the client signal. The The ODUk frame 110 is configured with an ODUk (Optical Channel Data Unit-k) OH 124 which is an OH that provides (stores) signals for end-to-end path monitoring and performance monitoring. Is done. The ODUk frame 120 provides (stores) signals for maintenance and operation functions necessary for transmission of an optical channel, which is signal transmission between 3R playback (Re-amplification, reshaping, and retiming) points. Transport Unit-k) OH 134 and a code 136 for providing a forward error correction (FEC) function are added to form an OTUk frame 130.

  FIG. 2A is a diagram for explaining the structure of the OTUk frame described in FIG. 1 in more detail. Frame synchronization (FA) OH230 is defined in the first to seventh columns of the first row of the OTUk frame, and OTUk OH134 is defined in the subsequent 8th to 14th columns of the first row. ODUk OH124 is defined in the 1st to 14th columns of the 2nd to 4th rows. The OPUk OH 114 is defined in the 15th to 16th columns of the 1st to 4th rows, and the payload 112 is defined in the 17th to 3824th columns of the 1st to 4th rows. An OTUk FEC code 136 is defined in the 3825 to 4080 columns of the first to fourth rows.

  FIG. 2B illustrates a specific structure of the FA OH 230 in the OTUk frame. The first 6 bytes of FA OH (the first row to the sixth column of the OTUk frame) are defined as a frame alignment signal (FAS) 232. The FAS 232 is used to detect the head of the OTUk frame when receiving the transmitted OTUk frame 130. Of the 6 bytes of the FAS, the first to third bytes are named OA1, respectively, and “1111 0110” bits are fixedly assigned to each of them. The 4th to 6th bytes of the FAS are named OA2, and all of them are fixedly assigned "0010 1000" bits. One byte following the FAS 232 of the FA OH 230 (the first row and the seventh column of the OTUk frame) is defined as a multiframe alignment signal (MFAS) 234. The MFAS is equivalent to a counter, and the MFAS value (MFAS value) is incremented and added each time one OTUk frame 130 is generated. When the MFAS value reaches 255 ("1111 1111" in the bit string), it returns to 0 ("0000 0000") and is incremented again.

  Annex C of ITU-T G.709 / Y.1331 discloses a method for transmitting an OTUk frame (k = 3,4) divided into a plurality of physical lanes. For example, an OTU4 frame is distributed to 20 logical lanes by interleaving in units of 16 bytes. Then, by simply bit-multiplexing five logical lanes, 20 logical lanes are multiplexed into four physical lanes and transmitted.

  FIG. 3 is a diagram for explaining logical lane distribution of OTU4. With reference to FIG. 3, the logical lane distribution of OTU4 will be described more specifically. As shown in FIG. 3A, the OTU4 frame shown in FIG. 2A is divided into 1020 groups of 16 bytes starting from FAS. The divided first 16-byte unit (described as “1:16 (FAS)” in FIG. 3A) includes FAS. Each 16-byte unit of the OTU4 frame is distributed in a round-robin manner to 20 logical lanes from Lane 0 to Lane 19 as shown in FIG. By repeating this distribution 51 times every 320 bytes (= 16 bytes × 20 logical lanes), one entire OTU4 frame is distributed to 20 logical lanes.

  Distribution of OTU4 frames to 20 logical lanes (also referred to as “lane allocation”) is rotated on OTU4 frame boundaries. That is, in the lane allocation of the second OTU4 frame, the first 16-byte unit including the FAS is assigned to Lane1 and the next 16-byte unit (from the 17th to the 17th) as in the 52nd distribution shown in FIG. 32 bytes) is assigned to Lane2, the 19th 16-byte unit (289th to 304th bytes) is assigned to Lane19, and the 20th 16-byte unit (305th to 320th bytes) is assigned to Lane0. In the lane allocation of the third OTU4 frame, the first 16-byte unit including FAS is rotated so as to be allocated to Lane2. In the lane allocation of the 20th OTU4 frame, rotation is performed so that the first 16-byte unit including FAS is allocated to Lane19. Then, in the lane allocation of the 21st OTU4 frame, returning to the original, the first 16 byte unit is allocated to Lane0.

  The third OA2 byte (6th column of the first row) of the OTU4 frame is borrowed as a logical lane marker (Logical Lane Marker, LLM) used as a marking mechanism for lane allocation (as described later, a temporary value) Is rewritten and later written back to "00101000"). The LLM is sequentially incremented from 0 to 239 for each OTU4 frame. The OTU4 frame in which the remainder when the LLM value is divided by 20 (represented as “LLM MOD 20”) is 0 is lane-assigned so that the first 16-byte unit including FAS is Lane0. The OTU4 frame in which LLM MOD 20 is 1 is assigned a lane so that the first 16-byte unit including FAS is Lane1. Similarly, the OTU4 frame in which LLM MOD 20 is m (m is an integer from 0 to 19) is lane-assigned so that the first 16-byte unit including FAS is Lane m. LLM MOD 20 acts as an identifier for lane assignment.

  In this way, in Annex C of ITU-T G.709 / Y.1331, when distributing OTU4 frames to 20 logical lanes by interleaving in units of 16 bytes, the lane arrangement is rotated according to the LLM value, Since the position of the FAS used for synchronization can be distributed to all the logical lanes Lane0 to Lane19, frame synchronization can be performed in any logical lane, and skew removal between logical lanes is possible.

  As for the OTU3 frame, one OTU3 frame is divided into 16-byte units as shown in FIG. 3A, but the number of logical lanes is 4, and the value of the lower 2 bits of the MFAS is used for identifying the lane allocation. Used.

  FIG. 4 is a diagram illustrating the configuration of a conventionally known device that distributes and transmits OTUk frames to logical lanes (see, for example, Patent Document 1). The transmission apparatus (frame transmission apparatus) 400 includes a frame generation unit 410, an LLM addition unit 422, a block division unit 424, a block distribution unit 426, and a bit multiplexing unit 430. The LLM adding unit 422, the block dividing unit 424, and the block distributing unit 426 constitute a lane allocation unit 420. The receiving device (frame receiving device) 600 includes a logical lane restoring unit 610, a logical lane identifying unit 622, a block combining unit 624, a frame reproducing unit 626, and a frame processing unit 630. The logical lane identifying unit 622, the block combining unit 624, and the frame reproducing unit 626 constitute a lane combining unit 620. The transmission device 400 and the reception device 600 are coupled by a transmission line such as an optical fiber.

  The frame generation unit 410 of the transmission device 400 generates the OTUk frame 130 by accommodating the client signal. The LLM adding unit 422 adds a logical lane marker (LLM) to the OH area 230 of the OTUk frame. The block division unit 424 divides the OTUk frame 130 into a plurality of blocks each composed of 16 bytes. The block distribution unit 426 distributes the divided blocks to 20 logical lanes based on the LLM. The bit multiplexing unit 430 generates a signal of 4 physical lanes by bit-multiplexing the signal of 20 logical lanes and outputs the signal to the transmission path.

  The logical lane restoration unit 610 of the receiving device 600 generates a signal of 20 logical lanes by bit interleaving the received signals of the 4 physical lanes. The logical lane identification unit 622 detects the LLM from each logical lane and recognizes the number of the own lane. The block combining unit 524 uses the FAS 232 present in each logical lane to eliminate the skew between the logical lanes, and then arranges and connects the blocks transmitted in the plurality of logical lanes in the original order. The frame playback unit 626 removes the LLM from the combined block, writes it back to the original OA2 value (“0010 1000” bits), and plays back the OTUk frame 130. The frame processing unit 630 extracts and restores the client signal from the reproduced OTUk frame.

JP 2011-223454 A

International Telecommunication Union, “Interfaces for the optical transport network,” Recommendation ITU-T G.709 / Y.1331, February 2012

  Patent Document 1 discloses that the block distribution unit 426 of the lane allocation unit 420 distributes the divided blocks to 20 logical lanes, but does not disclose the specific processing contents. Further, Patent Document 1 discloses that the block combining unit 624 of the lane combining unit 620 arranges blocks transmitted in a plurality of logical lanes in the original order and combines the specific processing contents. Not disclosed.

  The present invention has been made in view of the above, and an object of the present invention is to divide an OTUk frame into blocks that are division units, and to distribute less data when outputting to a plurality of logical lanes in units of blocks. An object of the present invention is to provide a frame transmission device and a frame reception device capable of realizing a transfer processing delay.

  In order to achieve such an object, according to a first aspect of the present invention, data of a frame accommodating a client signal is divided into blocks each of m bytes (m is a positive number), and n (n Is a frame transmission device that distributes and outputs to positive logical lanes.

  A frame transmission apparatus according to an embodiment includes a LLM adding unit that adds a marker for identifying a position of a logical lane to which a frame is distributed to a header of the frame, and outputs data of the frame to which the marker is added as a parallel signal. The data of the frame output by the LLM adding unit is input as a parallel signal, the data of the input frame is distributed to logical lanes in units of blocks, and the frame is distributed according to the marker value. And a data rotation unit for changing the position of the logical lane.

  The data array conversion unit according to an embodiment can hold m × n bytes of data, which is the product of the block size and the number of logical lanes, and is equal to the amount of data input to the data array conversion unit with one processing clock. A data holding unit having a plurality of memories capable of holding data is provided. The data array conversion unit sequentially holds the input frame data in a plurality of memories in synchronization with the processing clock, and when the m × n byte frame data is held, the start of the input frame data To rearrange the data arrangement of the plurality of memories so that the data of the blocks divided in units of m bytes are arranged in parallel.

  The second aspect of the present invention is that n (where n is a positive number) logical lanes in which data of a frame accommodating a client signal is divided into blocks of m bytes (m is a positive number) and distributed in units of blocks. Is a frame receiving apparatus that receives a frame and reproduces a frame from a logical lane.

The frame receiving apparatus according to an embodiment includes, for each logical lane, an FAS synchronization processing unit that detects a marker for identifying the position of the logical lane to which the frame is distributed, and a marker value detected by the FAS synchronization processing unit. The data rotation unit that changes the position of the logical lane to which the frame is distributed according to the data, and the data of the n logical lanes whose position has been changed by the data rotation unit is input, and the data of the frame distributed to the logical lane is in block units A data array conversion unit for output.

  The data array conversion unit according to an embodiment can hold m × n bytes of data, which is the product of the block size and the number of logical lanes, and is equal to the amount of data input to the data array conversion unit with one processing clock. A data storage unit having a plurality of memories capable of storing data, and the data array conversion unit sequentially stores the data of the input logical lanes in the plurality of memories in synchronization with the processing clock. When the data of the logical lane is held, the data arrangement of the plurality of memories is rearranged so that the data of the frame distributed to the logical lane is output in units of m bytes.

  As described above, according to the present invention, it is possible to provide a frame transmission device and a frame reception device that enable logical lane distribution with less data transfer processing delay (latency).

It is a figure explaining an OTN frame structure. (A) is a figure explaining an OTN frame structure in more detail, (b) is a figure which shows the structure of FAOH in an OTN frame. It is a figure for demonstrating the logical lane distribution of OTU4. FIG. 10 is a diagram illustrating a configuration of an apparatus that distributes and transmits OTUk frames disclosed in Patent Document 1 to logical lanes. It is a figure explaining the structure of the lane allocation part which concerns on this embodiment. It is a figure explaining the structure of the data arrangement conversion part which concerns on this embodiment. It is a figure explaining the structure of the data holding part which concerns on this embodiment. It is a figure explaining the connection state between the shift registers based on the setting of the selector part which concerns on this embodiment. (A) And (b) is a figure explaining the operation | movement which the data arrangement | sequence conversion part which concerns on this embodiment captures data in data capture / output mode. (A) And (b) is a figure explaining the operation | movement which the data arrangement | sequence conversion part which concerns on this embodiment captures data in data capture / output mode. It is a figure explaining the operation | movement which the data arrangement conversion part concerning this embodiment takes in data in data distribution mode. It is a figure explaining the example of a setting of the selector part in the data distribution mode which concerns on this embodiment. It is a figure explaining the operation | movement which the data arrangement | sequence conversion part which concerns on this embodiment takes in data, and the data arrangement | sequence conversion part is 1 processing clock by the data amount which integrated | accumulated the block size which is a division | segmentation unit of an OTU frame, and the number of logical lanes. It is a figure explaining the state which stored the data in memory, when it is equal to the data amount which can be taken in. It is a figure explaining the structure of the lane coupling | bond part which concerns on this embodiment. It is a figure explaining the operation | movement which the data arrangement | sequence conversion part which concerns on this embodiment takes in data in data acquisition / output mode. It is a figure explaining the operation | movement which the data arrangement conversion part concerning this embodiment takes in data in data distribution mode.

  The present invention relates to a technique for distributing an OTUk frame to a plurality of logical lanes and transmitting the OTUk frame in parallel. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 4, the transmission apparatus according to the embodiment of the present invention includes a frame generation unit that accommodates client signals and generates an OTN frame (OTUk frame), and an OTUk frame for every m bytes (m is a positive number). A lane allocation unit that divides the data into a plurality of blocks, distributes them to n logical lanes (n is a positive number), and outputs the logical lane signals. j is a positive number smaller than n) and includes a bit multiplexing unit that generates a signal of the physical lane and outputs the signal to the transmission path. However, in the transmission apparatus according to the embodiment of the present invention, the configuration of the lane allocation unit is different from that shown in FIG.

  In addition, as illustrated in FIG. 4, the receiving device according to the embodiment of the present invention includes a logical lane restoration unit that generates n logical lane signals by bit interleaving received j physical lane signals. A lane combining unit that combines the signals distributed and transmitted to n logical lanes in units of blocks to reproduce an OTUk frame, and a frame processing unit that extracts and restores a client signal from the reproduced OTUk frame. However, the receiving apparatus according to the embodiment of the present invention is different from that shown in FIG. 4 in the configuration of the lane coupling unit.

  In the OTU4 frame parallel transmission technology standard disclosed in Non-Patent Document 1, the division unit block is 16 bytes (m = 16), the number of logical lanes is 20 (n = 20), and the number of physical lanes is 4 ( j = 4). Note that the configuration may be such that the logical lane itself is transmitted as a physical lane without using the bit multiplexing unit 430 in the transmission device 400 and the logical lane restoration unit 610 in the reception device 600 shown in FIG. In that case, naturally, the number of logical lanes n = the number of physical lanes j.

  Hereinafter, configurations and processing methods of a lane allocation unit and a lane combination unit according to an embodiment of the present invention will be described in detail with reference to the drawings.

[Configuration of lane allocation unit provided in transmission device]
FIG. 5 is a diagram illustrating the configuration of the lane allocation unit 520 according to the present embodiment. The lane allocation unit 520 is provided in the transmission device 400 as described in FIG. 4, and includes an LLM adding unit 422, a data array conversion unit 530, and a data rotation unit 560.

  The OLM frame 130 generated by the frame generation unit 410 (FIG. 4) is input to the LLM adding unit 422. The LLM adding unit 422 rewrites the third OA2 byte (six columns in the first row) of the input OTUk frame 130 with the value of the logical lane marker (LLM). The LLM value is set to a value that is sequentially incremented from 0 (“0000 0000” in the bit string) to 239 (same “1110 1111”) for each input OTUk frame. The LLM adding unit 422 outputs the OTUk frame 130 in which the LLM is added to the third OA2 byte of the OTUk frame to the data array conversion unit 530. The LLM adding unit 422 outputs the OTUk frame 130 as a parallel signal. Here, it is assumed that a 320-bit width parallel signal is output. In order to enable the LLM adding unit 422 to output the OTUk frame 130 of the parallel signal, the LLM adding unit 422 or the frame generation unit 410 may be configured to serial-parallel convert the OTUk frame 130, or frame generation A configuration in which signals are parallelized in a stage prior to the unit 410 may be employed.

  The data array conversion unit 530 divides the OTUk frame 130 output from the LLM adding unit 422 into 16-byte blocks as shown in FIG. 3A to generate 1020 blocks. Are distributed to 20 logical lanes in a round-robin manner as shown in FIG. The data array conversion unit 530 outputs the signals distributed to the 20 logical lanes in parallel. Here, it is assumed that a parallel signal having a 16-bit width per logical lane (a total of 20 logical lanes × 16 bits = 320 bits wide) is output. Details of the configuration and processing of the data array conversion unit 530 will be described later.

  The data rotation unit 560 receives the 20 logical lane parallel signal output from the data array conversion unit 530. A frame synchronization signal (Frame alignment signal, FAS) and LLM arranged at the head of each OTUk frame 130 are always assigned to the first logical lane (Lane0) when input to the data rotation unit 560. When the data rotation unit 560 detects FAS in Lane0, the data rotation unit 560 reads the value of the LLM from the position corresponding to the third OA2 byte in the FAS. The data rotation unit 560 calculates a remainder when this LLM value is divided by 20 (this is expressed as “LLM MOD 20”). As shown in FIG. 3B, the data rotation unit 560 rotates the signal between the logical lanes so that the FAS is arranged in the logical lane having the same number as the value of the LLM MOD 20. For example, when LLM MOD 20 = 1, the data rotation unit moves the signal of Lane0 to Lane1, the signal of Lane1 to Lane2, the signal of Lane2 to Lane3,..., And the signal of Lane19 to Lane0. When LLM MOD 20 = 0, the data rotation unit 560 does not need to perform such rotation processing. The data rotation unit 560 rotates the signal of each logical lane between logical lanes according to the value of the LLM, and then outputs the signal to the bit multiplexing unit 430 (FIG. 4).

(Configuration of data array converter)
The data array conversion unit 530 divides the OTUk frame 130 into blocks of m bytes and distributes each block of m × n bytes of data to the n logical lanes in a round robin manner. The operation may be performed so that the data once held, the held m × n bytes of data are rearranged in a desired arrangement, and then output. Hereinafter, a configuration example and an operation example of the data array conversion unit 530 according to the present embodiment will be described with reference to FIGS. 6 to 10 where m = 16 bytes and n = 20 logical lanes. FIG. 6 is a diagram illustrating the configuration of the data array conversion unit 530 according to the present embodiment. FIG. 7 is a diagram illustrating the configuration of the data holding unit according to the present embodiment. FIG. 8 is a diagram for explaining a connection state between shift registers based on the setting of the selector unit according to the present embodiment.

  As shown in FIG. 6, the data array conversion unit 530 has a data holding unit 540 that can hold at least 320 bytes (= 16 bytes × 20 logical lanes) of data, and data that is input to and output from the data holding unit 540. A selector unit 532 for controlling the flow is provided. The data array conversion unit 530 receives the OTUk frame 130 as a parallel signal having a 320-bit width, and outputs the OTUk frame 130 distributed to the logical lane as a parallel signal having a 320-bit width. Accordingly, data of 320 bits (= 40 bytes) per processing clock is input to the data array conversion unit 530. As shown in FIG. 7, the data holding unit 540 includes a plurality of memories A to H each capable of holding an amount of data (= 40 bytes) equal to the amount of data input in one processing clock. In order to be able to hold 320 bytes of data as a whole in the data holding unit 540, it is only necessary to provide eight memories (320 bytes / 40 bytes =) that can hold 40 bytes. Each of the memories A to H includes the same number (= 20) of independent shift registers 548 as the number of logical lanes. Each of the shift registers 548 holds the amount of data that can be held by one memory by an amount that is equally divided. That is, each of the shift registers 548 holds 2 bytes (40 bytes / 20 logical lanes =). Such a shift register 548 may be configured to include, for example, 16 independent flip-flops. Each shift register 548 has a 16-bit wide input terminal, a 16-bit wide output terminal, and a reset signal input terminal (not shown). The input / output terminal of each shift register 548 may be a parallel input / output terminal having a bit width capable of inputting / outputting data (2 bytes) that can be held by the shift register in one processing clock. The input terminal of each shift register 548 is connected to the output terminal of the selector unit 532, and the output terminal is connected to the input terminal of the selector unit 532. As shown in FIG. 6, the selector unit 532 and the data holding unit 540 are connected by parallel signal lines 542 and 544 each having a 2560-bit width (= 16-bit width × 20 × 8). The selector unit 532 has a 320-bit width frame input terminal for inputting the data output from the LLM adding unit 422 via the parallel signal line 534, and the signal data distributed to the 20 logical lanes via the parallel signal line 536. Is provided with a 320-bit wide logic lane output terminal. Since the selector unit 532 controls the flow of data input to and output from the data holding unit 540, either the parallel signal line 534 or the parallel signal line 542 input to the selector unit 532 is output from the selector unit. It may be configured to include a plurality of switches that can arbitrarily connect either the parallel signal line 536 or the parallel signal line 544 in units of 16 bits.

(Processing of the data array converter)
The data array conversion unit 530 has two operation modes. The first operation mode is a data capture / output mode for capturing data of the OTUk frame 130, and the second operation mode is a data distribution mode for rearranging the captured data in a desired arrangement.

  First, the data capture / output mode which is the first operation mode will be described. In the data capture / output mode, the selector unit 532 is shifted so that the data held in the data holding unit 540 is sequentially shifted from memory H → memory G → memory F →... → memory A in synchronization with the processing clock. Is set. FIG. 8 is a diagram illustrating a connection state based on the setting of the selector unit 532 in the data capture / output mode. That is, the selector unit 532 has 1 to 16 bits in the first shift register (first from the top) of the memory H among the 320 bits of data input to the frame input terminal, and 17 to 32 bits in the memory H. In the second shift register (second from the top of the drawing), 33 to 48 bits are in the third shift register of the memory H (third from the top in the drawing),..., 305 to 320 bits are in the memory H. The input state of each shift register of the memory H is set (data path is set) so as to input to the 20 shift registers (20th from the top (first from the bottom)). In addition, the selector unit 532 is provided in each of the memories A to H so that data transitions in the order of the first shift register of the memory H → the first shift register of the memory G →... → the first shift register of the memory A. Sets the input / output state of the first shift register (sets the data path). The selector unit 532 sets the input / output states of the second to twentieth shift registers included in the memories A to H to be the same input / output state as the first shift register (sets a data path). The selector unit 532 sets the output state of the memory A (sets a data path) so that the output of the memory A is output from the logical lane output terminal of the selector unit 532.

  FIGS. 9 (a) and 9 (b) and FIGS. 10 (a) and 10 (b) are diagrams illustrating an operation in which the data array conversion unit 530 captures data in the data capture / output mode that is the first operation mode. . 9 and FIG. 10, each of the 20 squares located below the squares A to H is the 20 shift registers (first to 20th shift registers) provided in each of the memories A to H in FIG. 7. ). Further, the description such as [15: 0] described in the leftmost column of FIGS. 9 and 10 represents the input terminal number of the 320-bit width parallel signal input to the data array conversion unit 530. For example, the notation [15: 0] means 0th to 15th input terminal numbers corresponding to 1 to 16-bit parallel input signals.

  First, the selector unit 532 outputs the first 320 bits of data (40 bytes) of the OTUk frame 130 captured in synchronization with the first processing clock to the memory H. The 320-bit data is synchronized with the first processing clock, as shown in FIG. 9A, 1 to 16 bits are stored in the first shift register of the memory H (“2” in FIG. 9A). This number means that “1-2 bytes” stored from the top of the OTUk frame 130 are stored in the second shift register (same as above). “4”, which means that “3-4 bytes” stored from the top of the OTUk frame 130 is stored in the third shift register of the memory H (same as “6”). , 305 to 320 bits are stored in the 20th shift register of the memory H (same as “40”). Described as “39-40 bytes” stored from the beginning of the OTUk frame. Means). As described above, the data array conversion unit 530 stores the first 40 bytes of data of the OTUk frame in the first to twentieth shift registers of the memory H every two bytes in synchronization with the first processing clock. Here, the same hatched data in FIG. 9A means data corresponding to a “block” obtained by dividing the OTUk frame 130 into a predetermined size (m = 16 bytes).

  Next, the selector unit 532 outputs data of 321 to 640 bits (40 bytes) counted from the beginning of the OTUk frame 130 in synchronization with the second processing clock to the memory H. In synchronization with the second processing clock, the 320-bit data is 321 to 336 bits in the first shift register of the memory H (“42” in FIG. 9B) as shown in FIG. 9B. 337 to 352 bits in the second shift register of the memory H (same as “44”), and 353 to 368 bits in the third shift register of the memory H (same as “46”). , 625 to 640 bits are stored in the 20th shift register of the memory H (denoted as “80”). The data stored in the memory H in synchronization with the first processing clock is shifted to the memory G in synchronization with the second processing clock and stored in the memory G. As described above, the data array conversion unit 530 synchronizes with the second processing clock, and stores 41 to 80 bytes of data counted from the beginning of the OTUk frame 130 into the first to twentieth shift registers of the memory H with 2 bytes. The first 40 bytes of data in the OTUk frame 130 are stored in the first to twentieth shift registers of the memory G every two bytes.

  Next, the selector unit 532 outputs data of 641 to 960 bits (40 bytes) counted from the beginning of the OTUk frame 130 in synchronization with the third processing clock to the memory H. In synchronization with the third processing clock, the 320-bit data is 641 to 656 bits in the first shift register of the memory H (“82” in FIG. 10A) as shown in FIG. 657 to 672 bits in the second shift register of the memory H (same as “84”), and 673 to 688 bits in the third shift register of the memory H (same as “86”). , 945 to 960 bits are stored in the twentieth shift register (denoted as “120”) of the memory H. The data stored in the memory H in synchronization with the second processing clock is shifted to the memory G in synchronization with the third processing clock and stored in the memory G. Data stored in the memory G in synchronization with the second processing clock is shifted to the memory F in synchronization with the third processing clock and stored in the memory F. As described above, the data array conversion unit 530 synchronizes with the third processing clock, and stores 81 to 120 bytes of data counted from the beginning of the OTUk frame 130 into the first to twentieth shift registers of the memory H with 2 bytes. For each byte, 41 to 80 bytes of data counted from the beginning of the OTUk frame 130 are stored every 2 bytes in the first to twentieth shift registers of the memory G, and the first 40 bytes of data of the OTUk frame 130 are stored. The data is stored in the first to twentieth shift registers of the memory F every 2 bytes.

  The data array conversion unit 530 synchronizes with each of the fourth to seventh processing clocks, captures 40 bytes of data of the OTUk frame 130 and stores it in the memory H, and stores it in the memory H as well as the above. The stored data is shifted and held in the adjacent memory. The data array conversion unit 530 holds 280 bytes (40 bytes × 7 clocks) of the OTUk frame 130 in the memories B to H as shown in FIG. 10B in synchronization with the seventh processing clock. To do. That is, the memory B has the first 40 bytes of the OTUk frame 130, the memory C has 41 to 80 bytes counted from the head of the OTUk frame 130,..., And the memory H has 241 to 280 bytes. 1 to 20 shift registers are stored every 2 bytes.

  The data array conversion unit 530 transitions to the data distribution mode, which is the second operation mode, at the timing of holding 320 bytes of data that can be held by itself. Hereinafter, the data distribution mode which is the second operation mode will be described. In the data distribution mode, 280 bytes of data held in the memories B to H of the data holding unit 540 are not shifted to the adjacent memories, but a certain block is the same as that of the memories A to H as shown in FIG. The selector unit 532 is set so as to be held in the sequential shift registers (shift registers arranged in the horizontal direction in the drawing). A block, which is a unit for distributing the OTUk frame 130 to logical lanes, is 16 bytes. On the other hand, the amount of data that can be held in the first shift register of each of the memories A to H is also 16 bytes (= 2 bytes × 8). The same applies to the second to twentieth shift registers. Therefore, the selector unit 532 synchronizes with the eighth processing clock, and the first block (1 to 16 bytes, stored in the memory B) obtained by dividing the OTUk frame 130 is stored in the first shift registers of the memories A to H. The second block (17 to 32 bytes, stored in memory B) is stored in the second shift register of memories A to H, and the third block (33 to 48 bytes, stored in memories B and C) is stored in memories A to H. Set the input / output state of each shift register so that the 17th block (257 to 272 bytes, stored in the memory H) is stored in the 17th shift register of the memories A to H in the third shift register. (Set the data path) The selector unit 532 sets the input / output state of each shift register so that the first 8 bytes (273 to 280 bytes, stored in the memory H) of the 18th block are stored in the 18th shift register of the memories A to D. Set (set the data path). At that time, the selector unit 532 stores each shift register so that data closest to the head of the OTUk frame 130 in the block is stored in the memory A and data farthest from the head of the OTUk frame 130 is stored in the memory H. Set the output status (set the data path). Then, the selector unit 532 receives the 2241 to 2560-bit data (40 bytes) of the OTUk frame 130 captured in synchronization with the eighth processing clock, the 18th shift register of the memories E to H, and the memories A to H. It is set so as to be input to the 19th shift register and the 20th shift register of the memories A to H (a data path is set). By performing such processing in synchronization with the eighth processing clock, the data array conversion unit converts 320 bytes of data of the OTUk frame into the same blocks in the memories A to H as shown in FIG. The data array can be rearranged so that it is held in the ordered shift register.

  FIG. 12 is a diagram for explaining a setting example of the selector unit 532 in the data distribution mode. Two bytes (the first two bytes of the OTUk frame 130) stored in the first shift register of the memory B in synchronization with the seventh processing clock are stored in the first shift register of the memory A in synchronization with the eighth processing clock. Store it. Accordingly, the selector unit 532 sets the input / output states of these shift registers so that the output terminal of the first shift register of the memory B and the input terminal of the first shift register of the memory A are connected (the data path is changed). Set). 2 bytes (3 and 4 bytes counted from the beginning of the OTUk frame 130) stored in the second shift register of the memory B in synchronization with the seventh processing clock are stored in the memory B in synchronization with the eighth processing clock. What is necessary is just to store in a 1st shift register. Accordingly, the selector unit 532 sets the input / output state of these shift registers so that the output terminal of the second shift register of the memory B and the input terminal of the first shift register of the memory B are connected (data path). Set). On the other hand, 2 bytes (17 and 18 bytes counted from the beginning of the OTUk frame 130 and 2 bytes at the beginning of the second block) stored in the ninth shift register of the memory B in synchronization with the seventh processing clock are The second shift register of the memory A may be stored in synchronization with the eighth processing clock. Therefore, the selector unit 532 sets the input / output states of these shift registers so that the output terminal of the ninth shift register of the memory B and the input terminal of the second shift register of the memory A are connected (data path). Set). In addition, the selector unit 532 inputs these shift registers so that the input terminal of the input terminal number [207: 192] and the input terminal of the twentieth shift register of the memory A are connected in synchronization with the eighth processing clock. Set the state, set the input state of these shift registers so that the input terminal of the input terminal number [223: 208] and the input terminal of the 20th shift register of the memory B are connected. [319: 304] The input state of these shift registers is set so that the input terminal of the twentieth shift register of the memory H is connected (the data path is set). By such a change in the operation mode setting of the selector unit 532, the data array conversion unit 530 arranges the 320-byte data of the OTUk frame 130 in the arrangement shown in FIG. 11 in synchronization with the eighth processing clock. Can be sorted.

  When the rearrangement of the acquired 320 bytes of data is completed, the data array conversion unit 530 is again set to the data acquisition / output mode which is the first operation mode. The data array conversion unit 530 outputs the 40-byte (320 bits) data stored in the memory A from the logic lane output terminal of the selector unit 532 having a 320-bit width in synchronization with the ninth processing clock. At the same time, the data stored in the memory B is shifted to the memory A, the data stored in the memory C is shifted to the memory B,..., And the data stored in the memory H is shifted to the memory G and held. At the same time, the data array conversion unit 530 outputs the first 320 bits of data (40 bytes) of the next 320 bytes of the fetched OTUk frame 130 to the memory H in the same manner as the processing with the first processing clock. Hold. The data array conversion unit 530 outputs the 40-byte (320 bits) data stored in the memory A from the logic lane output terminal of the selector unit having a 320-bit width in synchronization with the tenth processing clock. The data stored in the memory B is shifted to the memory A, the data stored in the memory C is shifted to the memory B,..., And the data stored in the memory G is shifted to the memory F and held. At the same time, the data array conversion unit 530 outputs 321 to 640-bit data (40 bytes) of the next 320 bytes of the fetched OTUk frame 130 to the memory H in the same manner as the processing with the second processing clock. And hold. The data array conversion unit outputs the data stored in the memory A in synchronization with the eleventh to fifteenth processing clocks, and shifts and holds the data stored in each memory to the adjacent memory. , 320-bit data (40 bytes) is output to the memory H and held. The data array conversion unit 530 sets the selector unit 532 to the data distribution mode that is the second operation mode in synchronization with the sixteenth processing clock, and stores the data stored in the memory A (this is the eighth processing clock). In the rearrangement of the data performed in synchronization with the clock, the data stored in the memory H) is output from the logical lane output terminal of the selector unit 532, and the data stored in the memories B to H is stored in the memory by a certain block. The data are stored in the shift registers having the same order of A to H, and the data is rearranged for each block.

  By the processing of the data array conversion unit 530 described above, data divided into 16-byte blocks and distributed to the first logical lane are sequentially output from the first shift register of the memory A. Similarly, the data distributed to the second logical lane is sequentially output from the second shift register of the memory A. The data distributed to the xth logical lane is output from the xth (x is an integer of 1 to 20) shift register of the memory A.

  As described above, the data array conversion unit 530 determines that the size of a block, which is a unit for dividing the OTUk frame 130, is m bytes, and the number of logical lanes in which the OTUk frame 130 is distributed in units of blocks is n. The data of the n-byte OTUk frame is taken into the data holding unit, and the arrangement of the data taken into the data holding unit is rearranged so that a certain block is held in the shift register of the same order, so that the LLM adding unit 422 outputs The OTUk frame 130 can be divided into 16-byte blocks, which are division units, and distributed and output to 20 logical lanes in a round robin manner. At this time, the rearrangement of the data arrangement in the data distribution mode, which is the second operation mode, is completed in only one processing clock, so that logical lane distribution with a small data transfer processing delay (latency) is possible.

  As described above, the data array conversion unit 530 according to the present embodiment receives the data of the OTUk frame 130 as a parallel signal (bit width a), and parallelizes the data of the OTUk frame 130 distributed to a plurality of n logical lanes. M × n, which is output as a signal (bit width a) and is the product of the block size (m bytes), which is the division unit of the OTUk frame 130, and the number of logical lanes (n) to which the OTUk frame 130 is distributed A data holding unit 540 capable of holding byte data is provided. The data holding unit 540 includes a plurality of memories 546 each capable of holding data equal to the amount of data (a bit) input to the data array conversion unit 530 with one processing clock. The number of memories 546 is m × n / (a / 8). Then, the data array conversion unit 530 sequentially stores the data of the OTUk frame 130 input in synchronization with the processing clock in the plurality of memories 546, and when the data of m × n bytes is stored, The arrangement of the data held in each memory 546 is rearranged so that the data of the blocks divided in units of m bytes from the beginning is arranged in parallel, and the data arranged in parallel is output.

  Here, each of the plurality of memories 546 may include a number of shift registers 548 equal to the number of logical lanes (n). The data array conversion unit 530 may further include a selector unit 532 in order to control the flow of data input to and output from the data holding unit 540.

  6 and 7 illustrate a specific configuration example of the data array conversion unit 530 according to the present embodiment. Data is input / output with a bit width a = 320, and the capacity of the data holding unit is m. Xn = 320 bytes (block size m = 16 bytes, number of logical lanes n = 20), 8 memory units each having 40 bytes, each of which has a configuration of a data array conversion unit 530 having 20 shift registers Is disclosed. However, the present invention is not limited to this configuration, and can be applied to various configurations without departing from the above concept.

  For example, when the parallel signal input to the data array conversion unit 530 is 160 bits wide, the OTU4 frame parallel transmission technology (block size m = 16 bytes, number of logical lanes n = 20) disclosed in Non-Patent Document 1 is used. In order to implement, the capacity of the data holding unit 540 may be 320 bytes, but the capacity of each memory 546 is 160/8 = 20 bytes, and the capacity of the shift register 548 provided in the memory is 20/20 = 1 byte. And it is sufficient. Then, the number of memories 546 provided in the data holding unit 540 may be 320/20 = 16. Even in this case, the total capacity of the first shift register provided in each of the 16 memories 546 is 16 bytes. Since this is equal to the size of the block, which is the division unit of the OTU4 frame, using the data array conversion unit having such a configuration, “the block of the block divided in units of 16 bytes from the beginning of the input data is used. The arrangement of the data held in each memory can be rearranged so that the data is arranged in parallel.

  The present invention can also be applied to block sizes and logical lane numbers different from those specified in Non-Patent Document 1. When the number of logical lanes is n = 10, the capacity of the data holding unit may be 160 bytes (16 bytes × 10 logical lanes).

(Special case)
As a special example, the data amount (m × n bytes) obtained by integrating the block size (m bytes) and the number of logical lanes (n) can be captured by the data array conversion unit 530 in one processing clock. It may be equal to the amount (that is, the parallel signal input width of the data array conversion unit). In this case, the capacity of the data holding unit 540 is equal to the capacity of the memory 546, that is, the data holding unit 540 is provided with one memory 546. In this case, it is necessary to hold the data in the memory 546 in the first place. There is no.

  For example, if the block size m = 10 bytes, the number of logical lanes n = 4, and the parallel signal input to the data array converter is 320 bits wide, the data array converter 530 performs one process as shown in FIG. Mxn bytes of data are stored with the clock. The data array conversion unit 530 has input terminal numbers 0 to 79 as first logical lanes, input terminal numbers 80 to 159 as second logical lanes, input terminal numbers 160 to 239 as third logical lanes, and input terminal numbers 240. ˜319 as the fourth logical lane, it is possible to “divide the OTUk frame into a plurality of blocks, and distribute and output the blocks in a plurality of logical lanes”. In this case, since it is not necessary to rearrange the arrangement of the data stored in the memory, it is not necessary to hold the OTUk frame data in the memory.

  Therefore, when the data amount obtained by integrating the block size and the number of logical lanes is equal to the data amount that the data array conversion unit 530 can capture in one processing clock, the data of the OTUk frame input to the data array conversion unit 530 May be output as is without being stored in the data holding unit 540. In other words, the selector 532 of the data array conversion unit 530 controls the data flow so that the data of the OTUk frame 130 input to the data array conversion unit 530 is output as it is without being stored in the data holding unit 140. That's fine. With such a configuration or control, when the OTUk frame 130 is distributed and output to a plurality of logical lanes, it is not necessary to perform data buffer processing (that is, temporary storage of data in the data storage unit 540). Therefore, the data transfer processing delay (latency) can be further shortened.

[Configuration of lane coupling unit provided in receiving device]
FIG. 14 is a diagram illustrating the configuration of the lane coupling unit 720 according to the present embodiment. The lane combination unit 720 is provided in the reception device 600 as described in FIG. 4, and includes a FAS synchronization processing unit 722, a data rotation unit 724, a data array conversion unit 726, and a frame reproduction unit 630.

  The FAS synchronization processing unit 722 receives 20 logical lane signals output from the logical lane restoration unit 610 (FIG. 4). The FAS synchronization processing unit 722 detects FAS (FIG. 3B) for each input logical lane. The FAS synchronization processing unit 722 recognizes the LLM value from the third OA2 byte included in the detected FAS, and outputs the LLM value to the data rotation unit 724. In addition, the FAS synchronization processing unit 722 corrects delay time variation (skew) between logical lanes by giving a delay to the signal of each logical lane based on the detected FAS. The FAS synchronization processing unit 722 outputs the skew corrected 20 logical lane signals to the data rotation unit 724 as parallel signals. Here, each logical lane is output as a 16-bit parallel signal (a total of 320 bits).

  The data rotation unit 724 acquires the LLM value output from the FAS synchronization processing unit 722 and calculates a remainder LLM MOD 20 when the LLM value is divided by 20. The value of LLM MOD 20 indicates the logical lane in which the FAS is arranged for a certain OTUk frame 130. Therefore, based on the value of LLM MOD 20, the signal between the logical lanes is rotated so that the FAS is arranged in Lane0. For example, when LLM MOD 20 = 1, as shown in FIG. 3B, since the FAS is arranged in Lane1, the signal of Lane1 is set to Lane0, the signal of Lane2 is set to Lane1, and the signal of Lane3 is set to Lane2 Then, the signal of Lane19 is moved to Lane18, and the signal of Lane0 is moved to Lane19. The data rotation unit 724 rotates the signal of each logical lane between the logical lanes according to the LLM value, and then outputs it to the data array conversion unit. The data rotation unit 724 also outputs a 16-bit parallel signal (a total of 320 bits) for each logical lane.

  The data array conversion unit 726 reassembles the OTUk frame 130 (FIG. 3A) by sequentially combining the blocks distributed to each logical lane. Details of the configuration and processing of the data array conversion unit 726 will be described later.

  The OTUk frame 130 output from the data array conversion unit 726 is input to the frame reproduction unit 630 as a parallel signal (here, 320 bits wide). However, in this OTUk frame 130, the third OA2 byte of FAS is rewritten to the value of LLM. Therefore, the frame reproduction unit 630 rewrites the third OA2 byte of the FAS to the original OA2 value (“0010 1000” bits), and reproduces the OTUk frame 130. The frame playback unit 630 outputs the played OTUk frame 130 to the frame processing unit 630 (FIG. 4).

(Configuration of data array converter)
The data array conversion unit 726 included in the lane combination unit 720 of the reception apparatus has the same configuration as the data array conversion unit 530 included in the lane allocation unit 520 of the transmission apparatus illustrated in FIGS. A data holding unit 540 capable of holding m × n bytes of data, which is the product of the block size (m bytes) as a division unit and the number of logical lanes (n) for distributing the OTUk frame 130, and the data holding unit 540 A selector unit 532 for controlling the flow of data to be input / output is provided. The data holding unit 540 includes a plurality of memories 546 each capable of holding data equal to the amount of data (a bit) input to the data array conversion unit 726 with one processing clock. The number of memories is m × n / (a / 8). Each of the plurality of memories includes a number of shift registers 548 equal to the number of logical lanes (n).

  For example, when the block size m = 16 bytes, the number of logical lanes n = 20, and the parallel signal input to the data array conversion unit 726 is 320 bits wide, the capacity of the data holding unit 540 is at least 320 bytes, and the data holding unit 540 The number of memories 546 included in the memory 546 may be eight, and the number of shift registers 548 included in each of the memories 546 may be twenty.

(Processing of the data array converter)
The data array conversion unit 726 included in the receiving device has two operation modes, similar to the data array conversion unit 530 included in the transmission device. The first operation mode is a data capture / output mode in which data input in synchronization with a processing clock is sequentially held in a plurality of memories, or data held in the memories is sequentially output. Is a data distribution mode for rearranging the arrangement of data held in each memory when m × n bytes of data are held.

  FIGS. 15A and 15B are diagrams illustrating an operation in which the data array conversion unit 726 captures data in the data capture / output mode that is the first operation mode. FIG. 16 is a diagram illustrating an operation in which the data array conversion unit 726 captures data in the data distribution mode that is the second operation mode. 15 (a) and 15 (b) and FIG. 16 indicate the data corresponding to the “block” obtained by dividing the OTUk frame 130 into a predetermined size (m = 16 bytes). (Similar to FIG. 9 to FIG. 11). Note that data in the A column → B column →... → H column in FIG. 11 is sequentially input to the data array conversion unit 726 provided in the receiving device in synchronization with the processing clock. This is the same data that the transmitting device outputs to the logical lane (provided that there is no bit error or the like during transmission).

  The data array conversion unit 726 causes the memory H to hold 320-bit data corresponding to the column A in FIG. 11 captured in synchronization with the first processing clock (FIG. 15A). The data array conversion unit 726 stores 320-bit data corresponding to the B column in FIG. 11 captured in synchronization with the second processing clock in the memory H, and stores the data stored in the memory H into the memory G. Shift to hold. The data array conversion unit 726 stores, in the memory H, 320-bit data corresponding to columns C to G in FIG. 11 captured in synchronization with the third to seventh processing clocks, and is already stored in the memory. The stored data is shifted and held in the adjacent memory (FIG. 15B).

  The data array conversion unit 726 transitions to the data distribution mode at the timing of holding 320 bytes of data that can be held by itself. In the data distribution mode, which is the second operation mode, the 280-byte data held in the memories B to H of the data holding unit 540 is not shifted to the adjacent memories, but as shown in FIG. The arrangement is rearranged so that data closer to the head of 130 is sequentially arranged in the memory A and data farther from the head is arranged in the memory H. The selector unit 532 sets the connection state of the input / output terminals of each shift register included in the memories A to H so that the data in the arrangement of FIG. 15B can be rearranged in FIG. 16 (data path) Set). The data array conversion unit 530 takes in 320-bit data corresponding to the H column in FIG. 11 in synchronization with the eighth processing clock, and rearranges it in the arrangement in FIG. 16 at the same time.

  The data array conversion unit 726 transitions again to the data capture / output mode, which is the first operation mode, and outputs data stored in the memory A in synchronization with the ninth to sixteenth processing clocks. The data stored in .about.H is shifted and held in the adjacent memory, and the input 320-bit data is stored in the memory H.

(Special case)
Similarly to the lane allocation unit 520 provided in the transmission device, the data amount (m × n bytes) obtained by integrating the block size (m bytes) and the number of logical lanes (n) is the data array conversion unit 726 (530). When the amount of data that can be captured by the processing clock (that is, the parallel signal input width of the data array conversion unit) is equal, it is not necessary to hold the data in the data holding unit 540.

  Therefore, when the data amount obtained by integrating the block size and the number of logical lanes is equal to the data amount that the data array conversion unit 726 can capture in one processing clock, the data input to the data array conversion unit 727 is What is necessary is just to output as it is, without storing in the data holding part 540. In other words, the selector unit 532 of the data array conversion unit 726 may control the data flow so that the data input to the data array conversion unit 726 is output as it is without being stored in the data holding unit 540. With this configuration or control, when receiving the OTUk frame 130 distributed and transmitted to a plurality of logical lanes, it is necessary to perform data buffer processing (that is, temporary storage of data in the data storage unit). Therefore, the data reception processing delay (latency) can be further shortened.

  Each of the LLM adding unit 422, the data rotation unit 560, and the FAS synchronization processing unit 722, the data rotation unit 724, and the frame reproduction unit 630 included in the lane allocation unit 520 and the lane combination unit 720 described above are, for example, logic circuits. You may comprise by the integrated circuit or LSI (Large Scale Integrated circuit) which mounted. Or it is good also as a structure which operate | moves by the general-purpose processor or MPU (Micro Processing Unit) processing the command from the program loaded into the main memory.

100 Client signal 110 OPUk frame 112 OPUk payload 114 OPUk overhead 120 ODUk frame 124 ODUk overhead 130 OTUk frame 134 OTUk overhead 136 OTUk FEC
230 Frame synchronization (FA) overhead 232 Frame synchronization signal (FAS)
234 Multi-frame synchronization signal (MFAS)
400 frame transmission apparatus 410 frame generation unit 420 520 lane allocation unit 422 LLM addition unit 424 block division unit 426 block distribution unit 430 bit multiplexing unit 530 data array conversion unit 532 selector unit 534, 536 320-bit width parallel signal line 540 data holding 542, 544 2560-bit width parallel signal line 546 memory 548 shift register 560 data rotation unit 600 frame receiver 610 logical lane restoration unit 620, 720 lane combination unit 622 logical lane identification unit 624 block combination unit 626 frame reproduction unit 630 frame Processing unit 722 FAS synchronization processing unit 724 Data rotation unit 726 Data array conversion unit

Claims (4)

A frame transmitting apparatus that divides data of a frame containing a client signal into blocks of m bytes (m is a positive number), distributes the data to n logical lanes (n is a positive number), and outputs the divided blocks. ,
An LLM adding unit that attaches a marker for identifying the position of the logical lane to which the frame is distributed to the header of the frame, and outputs data of the frame to which the marker is attached as a parallel signal;
A data array conversion unit that inputs the data of the frame output from the LLM adding unit as a parallel signal, distributes the input data of the frame to the logical lanes in units of blocks, and
A data rotation unit that changes the position of the logical lane to which the frame is distributed according to the value of the marker;
Each of the data array conversion units has a storage element M _ij having a capacity of V bytes (where i and j are positive numbers satisfying 1 ≦ i ≦ n and 1 ≦ j ≦ k, and k satisfies V × k = m). comprising a storage element group including a positive number), the memory element M _1k according to (k-1) -th clock from 1, M _2k, ... storage element is sequentially shifted from M _nk M _12, M _22, until ... M _n2 The data of the frame is taken into the storage element group k-1 times in units of V × n bytes, and V × n × (k taken in according to the 1st to k−1th clocks according to the kth clock. -1) The data of the frame of bytes and the data of the frame of V × n bytes captured according to the k-th clock are converted into n × k memory elements M ₁₁ , M ₁₂ ,... M _1k , M _{21, M 22, ... M 2k} , ..., M n1, ... sequentially 1st element M _nk, the second element, - - As a n × k-th element in said storage device within the group, and arrangement conversion as the order of order as the memory element of data of the frame match,
M _1k ,..., M ₁₂ , M ₁₁
M _2k ,..., M ₂₂ , M ₂₁
:
M _nk ,..., M _n2 , M _n1
.., M _n1 is distributed to the logical lane as the block unit and output from the memory elements M ₁₁ , M ₂₁ ,... M _n1 . A frame transmitting apparatus that divides data of a frame containing a client signal into blocks of m bytes (m is a positive number), distributes the data to n logical lanes (n is a positive number), and outputs the divided blocks. ,
An LLM adding unit that attaches a marker for identifying the position of the logical lane to which the frame is distributed to the header of the frame, and outputs data of the frame to which the marker is attached as a parallel signal;
A data array conversion unit that inputs the data of the frame output from the LLM adding unit as a parallel signal, distributes the input data of the frame to the logical lanes in units of blocks, and
A data rotation unit that changes the position of the logical lane to which the frame is distributed according to the value of the marker;
With
The parallel signal input to the data array conversion unit has a signal width of m × n bytes,
The data array conversion unit divides the parallel signal inputted to the n m-byte data, frame transmitting device you characterized by splitting and outputting to the logical lanes. Data of a frame containing a client signal is divided into blocks each having m bytes (m is a positive number), and n logical lanes (n is a positive number) distributed in units of blocks are received. A frame receiving device for reproducing the frame,
For each of the logical lanes, an FAS synchronization processing unit that detects a marker for identifying the position of the logical lane to which the frame is distributed;
A data rotation unit that changes the position of the logical lane to which the frame is distributed according to the value of the marker detected by the FAS synchronization processing unit;
A data array conversion unit that receives data of n logical lanes whose positions have been changed by the data rotation unit , disassembles the block, converts the data of the frame into a series of parallel signals, and outputs the data;
Each of the data array conversion units is a storage element M _ij having a capacity V (where i and j are positive numbers satisfying 1 ≦ i ≦ n and 1 ≦ j ≦ k, and k is a positive number satisfying V × k = m). comprising a storage element group including a number), the memory element M _1k according to (k-1) -th clock from 1, M _2k, ... storage element is sequentially shifted from M _nk M _12, M _22, until said ... M _n2 The output of the data rotation unit is fetched into the storage element group k-1 times in units of V × n bytes, and V × n × ( k-1) The output of the data rotation unit of bytes and the output of the data rotation unit of V × n bytes captured according to the k-th clock are represented by n × k storage elements M ₁₁ , M ₂₁ , _{... M n1, M 12, M} 22, ... M n2, ..., M 1k, ... sequentially 1st element M _nk, the second element, - - As a n × k-th element in said storage device within the group, and arrangement conversion as the order of order as the memory element of data of the frame match,
M _1k ,..., M ₁₂ , M ₁₁
M _2k ,..., M ₂₂ , M ₂₁
:
M _nk ,..., M _n2 , M _n1
A frame receiving apparatus characterized in that k pieces of V × n byte data are respectively output as parallel signals from storage elements M ₁₁ , M ₂₁ ,... M _n1 . Data of a frame containing a client signal is divided into blocks each having m bytes (m is a positive number), and n logical lanes (n is a positive number) distributed in units of blocks are received. A frame receiving device for reproducing the frame,
For each of the logical lanes, an FAS synchronization processing unit that detects a marker for identifying the position of the logical lane to which the frame is distributed;
A data rotation unit that changes the position of the logical lane to which the frame is distributed according to the value of the marker detected by the FAS synchronization processing unit;
A data array conversion unit that receives data of n logical lanes whose positions have been changed by the data rotation unit, disassembles the block, converts the data of the frame into a series of parallel signals, and outputs the data
With
The data array conversion unit integrates n m-byte blocks input from the data rotation unit in order of the data of the frame, converts the data into a parallel signal having a signal width of m × n bytes, and outputs the parallel signal . that frame the receiving device.

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