JP2019114975A - Frame transmission device and frame receiver unit - Google Patents

Abstract

To provide a frame transmission device capable of realizing less data transmission processing delay.SOLUTION: A frame transmission device outputting the data of a frame receiving a client signal while distributing to n logic lanes in units of m bite block includes a data arrangement conversion part for receiving the data of a frame marked for identifying the position of the logic lane to be distributed as a parallel signal, and outputting to the logic lanes while distributing in units of block, and a data rotation part for changing the position of the logic lane to which a frame is distributed according to the value of the mark. The data arrangement conversion part makes multiple memories sequentially hold the data of the inputted frame, in synchronism with a processing clock, and when the data of a frame of m×n bites is held, rearranges the data of the multiple memories so that the data of blocks, divided in units of m bites, are arranged in parallel from the head of data of the inputted frame, before being outputted.SELECTED DRAWING: Figure 5

Description

  The present invention relates to transmission technology of a frame storing digital data, and more particularly to a frame transmission apparatus and a frame reception apparatus which distributes a frame to a plurality of logical lanes and transmits them in parallel.

  In the current backbone communication network, "ITU-T G. 709 / Y. 1331" recommended by "International Telecommunication Union-Telecommunication Standardization Sector" (ITU-T), which is an international standardization organization. The optical transmission standard "is widely used. This optical transmission standard is also called "optical transport network" (OTN), and it is a supervisory control system that considers wavelength division multiplex (WDM) signal management, Ethernet (registered trademark), synchronous digital hierarchy, etc. It defines bit rates and mapping methods for accommodating and transparently transmitting various client signals such as (Synchronous Digital Hierarchy, SDH). (See Non-Patent Document 1)

  FIG. 1 is a diagram for explaining the structure of the OTN frame. At the beginning of various frames making up the OTN frame, overhead for storing address information and various supervisory signals used when transmitting data is added, but in the following, the overhead is abbreviated OH and is stored in OH. Information and signals to be transmitted will be described as OH information. The OPUk frame 110 is composed of a payload area 112 in which a client signal 100 such as Ethernet (registered trademark) or SDH is accommodated, and an OPUk (Optical Channel Payload Unit-k) OH 114 which is OH for providing accommodation information of the client signal. Ru. The OPUk frame 110 is provided with ODUk (Optical Channel Data Unit-k) OH 124 which is OH that provides (stores) signals for end-to-end path monitoring and performance monitoring, and the ODUk frame 120 is configured. Be done. The ODUk frame 120 provides (stores) a signal for maintenance and operation functions necessary for transmission of an optical channel which is a signal transmission between 3R regeneration (re-amplification, reshaping, retiming) OTUk (Optical Channel) A Transport Unit-k) OH 134 and a code 136 for providing a Forward Error Correction (FEC) function are added, and an OTUk frame 130 is constructed.

  FIG. 2A is a diagram for explaining the structure of the OTUk frame described in FIG. 1 in more detail. Frame Alignment (FA) OH 230 is defined in the first to seventh columns of the first line of the OTUk frame, and OTUk OH 134 is defined in the eighth to fourteenth columns of the first line. ODUk OH 124 is defined in the 1st to 14th columns in the 2nd to 4th rows. OPUk OH 114 is defined in the 15th to 16th columns in the 1st to 4th rows, and the payload 112 is defined in the 17th to 3824th columns in the 1st to 4th rows. The OTUk FEC code 136 is defined in the 3825th to 4080th columns in the first to fourth rows.

  FIG. 2B is a view for explaining the specific structure of the FA OH 230 in the OTUk frame. The first six bytes of FA OH (the first row to the first column to the sixth column of the OTUk frame) are defined as a frame alignment signal (FAS) 232. The FAS 232 is used to detect the beginning of the OTUk frame when the transmitted OTUk frame 130 is received. Of the six bytes of the FAS, the first to third bytes are respectively designated as OA1, and in all cases, the “1111 0110” bit is fixedly assigned. The fourth to sixth bytes of FAS are respectively named OA2, and "0010 1000" bits are fixedly assigned to each of them. One byte (the first row and seventh column of the OTUk frame) following the FAS 232 of the FA OH 230 is defined as a multiframe alignment signal (MFAS) 234. MFAS is equivalent to a counter, and the value of MFAS (MFAS value) is incremented and added each time one OTUk frame 130 is generated. The MFAS value is incremented back to 0 (“0000 0000”) again when it reaches 255 (“1111 1111” in the bit string).

  Annex C of ITU-T G. 709 / Y. 1331 discloses a method for dividing an OTUk frame (k = 3, 4) into a plurality of physical lanes and transmitting the same. For example, OTU4 frames are distributed to 20 logical lanes by interleaving in units of 16 bytes. Then, by simply bit-multiplexing 5 logical lanes, 20 logical lanes are multiplexed into 4 physical lanes and transmitted.

  FIG. 3 is a diagram for explaining the logical lane distribution of OTU4. The logical lane distribution of the OTU 4 will be more specifically described with reference to FIG. As shown in FIG. 3A, the OTU4 frame described in FIG. 2A is divided into 1020 groups of 16 bytes each starting from the FAS. The first 16 byte unit divided (denoted as “1:16 (FAS)” in FIG. 3A) contains the FAS. Each 16 byte unit of the OTU4 frame is distributed to the 20 logical lanes of Lane 0 to Lane 19 in a round robin manner as described in FIG. 3 (b). By repeating this distribution 51 times every 320 bytes (= 16 bytes × 20 logical lanes), one entire OTU4 frame is distributed to 20 logical lanes.

  The distribution of the OTU4 frame into 20 logical lanes (also referred to as "lane assignment") is rotated on the boundary of the OTU4 frame. That is, in the lane allocation of the second OTU4 frame, as in the 52nd distribution shown in FIG. 3B, the first 16 byte unit including FAS is Lane 1 and the next 16 byte unit (17th to 32 bytes) are allocated to Lane 2; 19th 16-byte units (289th to 304th bytes) to Lane 19; and 20th 16-byte units (305th to 320th bytes) to Lane 0. The lane allocation of the third OTU4 frame is rotated so that the first 16 byte unit including FAS is allocated to Lane2. The lane allocation of the 20th OTU4 frame is rotated so that the first 16 byte units including the FAS are allocated to Lane19. Then, in lane allocation of the 21st OTU4 frame, the first 16-byte unit is allocated to Lane 0, returning to the original state.

  The third OA2 byte (first row, sixth column) of the OTU4 frame is borrowed as a Logical Lane Marker (LLM) used as a marking mechanism for lane assignment (temporary value as described later) Is rewritten and later written back to “00101000”). The LLM is sequentially incremented from 0 to 239 every OTU4 frame. An OTU4 frame in which the remainder when LLM value is divided by 20 (denoted as "LLM MOD 20") becomes 0 is assigned such that the first 16 byte unit including FAS becomes Lane0. The OTU4 frame in which LLM MOD 20 is 1 is lane-assigned such that the first 16 byte unit including FAS is Lane 1. Similarly, an OTU4 frame in which LLM MOD 20 is m (m is an integer from 0 to 19) is lane-assigned such that the first 16-byte unit including FAS is Lane m. LLM MOD 20 acts as an identifier for lane assignment.

  Thus, in Annex C of ITU-T G. 709 / Y. 1331, when distributing an OTU4 frame to 20 logical lanes by interleaving in units of 16 bytes, the frame is rotated by rotating the lane arrangement according to the LLM value. Since the positions of FAS used for synchronization can be distributed to all the logical lanes Lane0 to Lane19, frame synchronization can be performed on any logical lane, and skew can be removed between the logical lanes.

  As for the OTU3 frame, one OTU3 frame is divided into 16-byte units as shown in FIG. 3A, but the number of logical lanes is 4, and the value of the lower 2 bits of MFAS is used to identify the lane assignment. Used.

  FIG. 4 is a view for explaining the configuration of an apparatus for distributing and transmitting a conventionally known OTUk frame to logical lanes (see, for example, Patent Document 1). The transmission apparatus (frame transmission apparatus) 400 includes a frame generation unit 410, an LLM attachment unit 422, a block division unit 424, a block distribution unit 426, and a bit multiplexing unit 430. The LLM assignment unit 422, the block division unit 424, and the block distribution unit 426 constitute a lane assignment unit 420. The reception apparatus (frame reception apparatus) 600 includes a logical lane restoration unit 610, a logical lane identification unit 622, a block connection unit 624, a frame reproduction unit 626, and a frame processing unit 630. The logical lane identification unit 622, the block connection unit 624, and the frame reproduction unit 626 constitute a lane connection unit 620. The transmitter 400 and the receiver 600 are coupled by a transmission line such as an optical fiber.

  The frame generation unit 410 of the transmission device 400 receives the client signal and generates an OTUk frame 130. The LLM assignment unit 422 assigns a logical lane marker (LLM) to the OH area 230 of the OTUk frame. The block division unit 424 divides the OTUk frame 130 into a plurality of blocks of 16-byte units. The block distribution unit 426 distributes the divided blocks into 20 logical lanes based on LLM. The bit multiplexing unit 430 bit-multiplexes the signal of 20 logical lanes to generate a signal of 4 physical lanes, and outputs the signal to the transmission path.

  The logical lane recovery unit 610 of the reception device 600 performs bit interleaving of the received signals of the four physical lanes to generate signals of 20 logical lanes. The logical lane identification unit 622 detects the LLM from each logical lane and recognizes what number lane the own lane is. The block combining unit 524 eliminates the skew between the logical lanes by using the FAS 232 present in each logical lane, and then arranges and combines the blocks transmitted in the plurality of logical lanes in the original order. The frame reproduction unit 626 removes the LLM from the combined block and rewrites it to the original OA2 value (“0010 1000” bit) to reproduce the OTUk frame 130. The frame processing unit 630 extracts and restores the client signal from the reproduced OTUk frame.

JP, 2011-223454, A

International Telecommunication Union, “Interfaces for the optical transport network,” Recommendation ITU-T G.709 / Y.1331, February 2012

  Although Patent Document 1 discloses that the block distribution unit 426 of the lane allocation unit 420 distributes the divided blocks to 20 logical lanes, the specific processing content is not disclosed. Further, Patent Document 1 discloses that the block combining unit 624 of the lane combining unit 620 arranges and combines blocks transmitted in a plurality of logical lanes in the original order, but the specific processing content is Not disclosed.

  The present invention has been made in view of the above, and it is an object of the present invention to divide an OTUk frame into blocks, which are division units, and to distribute and output a plurality of logical lanes in block units as less data. An object of the present invention is to provide a frame transmission device and a frame reception device capable of realizing transfer processing delay.

  In order to achieve such an object, according to a first aspect of the present invention, data of a frame accommodating a client signal is divided into blocks of m bytes (m is a positive number), and n blocks (n Is a frame transmitting apparatus which distributes and outputs to the logical lanes of positive numbers).

  A frame transmitting apparatus according to an embodiment adds a marker for identifying a position of a logical lane to which the frame is distributed to a header of the frame, and outputs an LLM attaching unit that outputs data of the frame to which the marker is attached as a parallel signal. , Data of the frame output by the LLM attaching unit is input as a parallel signal, and a data array conversion unit that distributes and outputs the data of the input frame to logical lanes in block units, and the frame is distributed according to the value of the marker And a data rotating unit that changes the position of the logical lane.

  The data array conversion unit of one embodiment can hold m × n bytes of data which is the product of the block size and the number of logical lanes, and is equal to the amount of data input to the data array conversion unit in one processing clock. A data holding unit having a plurality of memories capable of holding data is provided. The data array conversion unit causes the input frame data to be sequentially held in a plurality of memories in synchronization with the processing clock, and when the m × n byte frame data is held, the head of the input frame data Data arrangement of a plurality of memories is rearranged and output so that data of blocks divided in units of m bytes are arranged in parallel.

  According to a second aspect of the present invention, there are n (n is positive number) logical lanes in which data of a frame accommodating a client signal is divided into m byte (m is positive number) blocks and distributed in block units. And a frame receiving apparatus that reproduces a frame from a logical lane.

The frame receiving apparatus according to one embodiment includes, for each of the logical lanes, an FAS synchronization processing unit that detects a marker for identifying the position of the logical lane to which the frame is distributed, and a marker value detected by the FAS synchronization processing unit. In response, the data rotation unit changes the position of the logical lane to which the frame is distributed, and the data of n logical lanes whose positions are changed by the data rotation unit are input, and the data of the frame distributed to the logical lane is block united And an output data array conversion unit.

  The data array conversion unit of one embodiment can hold m × n bytes of data which is the product of the block size and the number of logical lanes, and is equal to the amount of data input to the data array conversion unit in one processing clock. A data holding unit having a plurality of memories capable of holding data is provided, and the data array conversion unit sequentially holds input logical lane data in a plurality of memories in synchronization with a processing clock. When the data of the logical lane is held, the data arrangement of the plurality of memories is rearranged so that the data of the frame distributed to the logical lane is output in units of m bytes from the beginning of the data.

  As described above, according to the present invention, it is possible to provide a frame transmission apparatus and a frame reception apparatus that enable logical lane distribution with less data transfer processing delay (latency).

It is a figure explaining OTN frame structure. (A) is a figure which illustrates OTN frame structure in more detail, (b) is a figure which shows the structure of FA OH in an OTN flame | frame. It is a figure for demonstrating logical lane distribution of OTU4. It is a figure explaining the structure of the apparatus which distributes the OTUk flame | frame disclosed by patent document 1 to a logical lane, and transmits. It is a figure explaining the composition of the lane assignment part concerning this embodiment. It is a figure explaining the composition of the data sequence conversion part concerning this embodiment. It is a figure explaining the composition of the data attaching part concerning this embodiment. It is a figure explaining the connection state between shift registers based on the setting of the selector part concerning this embodiment. (A) And (b) is a figure explaining the operation | movement which takes in data in the data taking-in / output mode by the data arrangement | sequence conversion part which concerns on this embodiment. (A) And (b) is a figure explaining the operation | movement which takes in data in the data taking-in / output mode by the data arrangement | sequence conversion part which concerns on this embodiment. It is a figure explaining the operation | movement which a data array conversion part which concerns on this embodiment takes in data in data distribution mode. It is a figure explaining the setting example of the selector part in the data distribution mode which concerns on this embodiment. FIG. 8 is a diagram for explaining the operation of the data array conversion unit according to the present embodiment for capturing data; the data amount obtained by integrating the block size which is the division unit of OTU frame and the number of logical lanes is one processing clock of the data array conversion unit. When it is equal to the amount of data which can be taken in, it is a figure explaining the state where data were stored in memory. It is a figure explaining the composition of the lane connection part concerning this embodiment. It is a figure explaining the operation | movement which takes in data in the data acquisition / output mode by the data array conversion part which concerns on this embodiment. It is a figure explaining the operation | movement which a data array conversion part which concerns on this embodiment takes in data in data distribution mode.

  The present invention relates to a technique for distributing OTUk frames to a plurality of logical lanes and transmitting them in parallel. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  A transmitting apparatus according to an embodiment of the present invention, as shown in FIG. 4, is a frame generating unit that accommodates a client signal and generates an OTN frame (OTUk frame), an OTUk frame for every m bytes (m is a positive number) The lane allocation unit divides the signal into n blocks (n is a positive number) and outputs them in block units, and the signals of n logical lanes are bit-multiplexed and j j is a positive number smaller than n) physical lane signal generation and includes a bit multiplexing unit for output to the transmission path. However, the transmission apparatus according to the embodiment of the present invention is different from that shown in FIG. 4 in the configuration of the lane assignment unit.

  Further, as shown in FIG. 4, the receiving apparatus according to the embodiment of the present invention is a logical lane restoration unit that generates a signal of n logical lanes by bit interleaving the received signals of j physical lanes, The lane combining unit combines signals transmitted and distributed to n logical lanes in block units to reproduce an OTUk frame, and a frame processing unit extracts and restores a client signal from the reproduced OTUk frame. However, in the receiving device according to the embodiment of the present invention, the configuration of the lane coupling unit is different from that shown in FIG.

  According to the OTU 4 frame parallel transmission technology standard disclosed in Non-Patent Document 1, the block as a division unit is 16 bytes (m = 16), the number of logical lanes is 20 (n = 20), and the number of physical lanes is 4 ( j = 4). The configuration may be such that the logical lane itself is transmitted as a physical lane without using the bit multiplexing unit 430 in the transmitting apparatus 400 and the logical lane restoration unit 610 in the receiving apparatus 600 illustrated in FIG. 4. In that case, as a matter of course, the number of logical lanes n = the number of physical lanes j.

  Hereinafter, configurations and processing methods of a lane assignment unit and a lane coupling unit according to an embodiment of the present invention will be described in detail using the drawings.

[Configuration of Lane Allocation Unit Provided to Transmission Device]
FIG. 5 is a diagram for explaining the configuration of the lane assignment unit 520 according to the present embodiment. The lane assignment unit 520 is included in the transmission device 400 as described in FIG. 4, and includes an LLM assignment unit 422, a data array conversion unit 530, and a data rotation unit 560.

  The LTM assignment unit 422 receives the OTUk frame 130 generated by the frame generation unit 410 (FIG. 4). The LLM assignment unit 422 rewrites the third OA2 byte (sixth row of the first row) of the input OTUk frame 130 into the value of the logical lane marker (LLM). The value of LLM is set to a value sequentially incremented from 0 ("0000 0000" in bit string) to 239 ("11 10 1111") in each input OTUk frame. The LLM assignment unit 422 outputs the OTUk frame 130 in which the LLM is assigned to the third OA2 byte of the OTUk frame to the data array conversion unit 530. The LLM assignment unit 422 outputs the OTUk frame 130 as a parallel signal. Here, it is assumed that the signal is output as a 320-bit parallel signal. The LLM attaching unit 422 or the frame generating unit 410 may be configured to perform serial / parallel conversion of the OTUk frame 130 so that the LLM attaching unit 422 can output the OTUk frame 130 of the parallel signal, or The signal may be parallelized in a stage before the unit 410.

  The data array conversion unit 530 divides the OTUk frame 130 output from the LLM attachment unit 422 into 16-byte blocks as shown in FIG. 3A to generate 1020 blocks, and each block of 16-byte units Are distributed to 20 logical lanes in a round robin manner as shown in FIG. 3 (b). The data array conversion unit 530 outputs the signals distributed to the 20 logical lanes in parallel. Here, it is assumed that a 16-bit wide parallel signal (total of 20 logical lanes x 16 bits = 320 bits wide) is output per one logical lane. Details of the configuration and processing of the data array conversion unit 530 will be described later.

  The data rotation unit 560 receives parallel signals of 20 logical lanes output from the data array conversion unit 530. The frame alignment signal (FAS) and LLM placed at the beginning of each OTUk frame 130 are always assigned to the first logical lane (Lane 0) when they are input to the data rotation unit 560. When the data rotation unit 560 detects FAS in Lane 0, the data rotation unit 560 reads the value of LLM from the location corresponding to the third OA2 byte in FAS. The data rotation unit 560 calculates a remainder (denoted as “LLM MOD 20”) obtained by dividing the value of LLM by 20. The data rotation unit 560 rotates the signal between the logical lanes so that the FAS is arranged in the logical lanes having the same number as the value of the LLM MOD 20 as shown in FIG. 3B. For example, when LLM MOD 20 = 1, the data rotating unit moves the signal of Lane 0 to Lane 1, the signal of Lane 1 to Lane 2, the signal of Lane 2 to Lane 3, the signal of Lane 19 to Lane 0. When LLM MOD 20 = 0, the data rotation unit 560 does not have to perform such rotation processing. The data rotation unit 560 rotates the signal of each logical lane between the logical lanes according to the value of LLM, and outputs the result to the bit multiplexing unit 430 (FIG. 4).

(Configuration of data array conversion unit)
The data array conversion unit 530 divides the OTUk frame 130 into m-byte blocks and distributes m × n-byte data, which is the product, to distribute each block to n logical lanes in a round robin manner. Once the m × n bytes of data once held and held are rearranged into a desired arrangement, the data may be output. Hereinafter, a configuration example and an operation example of the data array conversion unit 530 according to the present embodiment will be described using m = 16 bytes and n = 20 logical lane numbers and using FIGS. 6 to 10. FIG. 6 is a diagram for explaining the configuration of the data array conversion unit 530 according to the present embodiment. FIG. 7 is a diagram for explaining the configuration of the data holding unit according to the present embodiment. FIG. 8 is a diagram for explaining the connection state between shift registers based on the setting of the selector unit according to the present embodiment.

  As shown in FIG. 6, data array conversion unit 530 is capable of holding data of at least 320 bytes (= 16 bytes × 20 logical lanes), and data input / output to / from data holding unit 540. A selector unit 532 that controls the flow is provided. The data array conversion unit 530 receives the OTUk frame 130 as a 320-bit parallel signal and outputs the OTUk frame 130 distributed to the logical lane as a 320-bit parallel signal. Therefore, data of 320 bits (= 40 bytes) is input to the data array conversion unit 530 per processing clock. As shown in FIG. 7, the data holding unit 540 is provided with a plurality of memories A to H each capable of holding data (= 40 bytes) of an amount equal to the amount of data input with this one processing clock. In order to be able to hold 320 bytes of data in the entire data holding unit 540, eight (320 bytes / 40 bytes =) memory capable of holding 40 bytes may be provided. Each of the memories A to H includes the same number (= 20) of independent shift registers 548 as the number of logical lanes. Each of the shift registers 548 holds an amount of data that can be held by one memory equally divided. That is, each of the shift registers 548 holds 2 bytes (40 bytes / 20 logical lanes ==). Such a shift register 548 may be configured to include, for example, 16 independent flip flops. Each shift register 548 has a 16-bit wide input terminal, a 16-bit wide output terminal, and a reset signal input terminal (not shown). The input / output terminal of each shift register 548 may be a parallel input / output terminal having a bit width that can input / output an amount (two bytes) of data that can be held by the shift register with one processing clock. The input terminal of each shift register 548 is connected to the output terminal of the selector unit 532, and the output terminal is connected to the input terminal of the selector unit 532. The selector unit 532 and the data holding unit 540 are connected by parallel signal lines 542 and 544 each having a width of 2560 bits (= 16 bits wide × 20 × 8) as shown in FIG. Selector unit 532 is a frame input terminal of 320 bit width for inputting data output from LLM attaching unit 422 via parallel signal line 534, and data of signals distributed to 20 logical lanes via parallel signal line 536. And a 320-bit wide logical lane output terminal. The selector unit 532 outputs data from either the parallel signal line 534 or the parallel signal line 542 input to the selector unit 532 and the selector unit in order to control the flow of data input to or output from the data holding unit 540. A plurality of switches may be provided which can be arbitrarily connected in units of 16 bits to either the parallel signal line 536 or the parallel signal line 544.

(Processing of data array conversion unit)
Data array conversion unit 530 has two operation modes. The first operation mode is a data acquisition / output mode for acquiring the data of the OTUk frame 130, and the second operation mode is a data distribution mode for rearranging the acquired data into a desired arrangement.

  First, the data acquisition / output mode which is the first operation mode will be described. In the data acquisition / output mode, the selector unit 532 is shifted so that the data held in the data holding unit 540 is sequentially shifted to the memory H → memory G → memory F → ... → memory A in synchronization with the processing clock. It is set. FIG. 8 is a diagram for explaining the connection state based on the setting of the selector unit 532 in the data acquisition / output mode. That is, the selector unit 532 sets 1 to 16 bits of the 320 bits of data input to the frame input terminal to the first shift register of the memory H (the first from the top in the drawing) and 17 to 32 bits of the memory H. In the second shift register (second from the top of the drawing), 33 to 48 bits in the third shift register (third from the top of the drawing) of the memory H,. 20. The input state of each shift register of the memory H is set (the data path is set) so as to be input to the 20th shift register (the 20th from the top of the drawing (first from the bottom). In addition, the selector unit 532 is provided in each of the memories A to H so that data transitions in the order of the first shift register of the memory H → the first shift register of the memory G →... → the first shift register of the memory A. Set the input / output state of the first shift register (set the data path). The selector unit 532 also sets the input / output state of the second to twentieth shift registers in each of the memories A to H to be the same as the input / output state of the first shift register (set the data path). The selector unit 532 sets the output state of the memory A so as to output the output of the memory A from the logical lane output terminal of the selector unit 532 (set the data path).

  FIGS. 9A and 9B and FIGS. 10A and 10B are diagrams for explaining the operation of the data array conversion unit 530 for acquiring data in the data acquisition / output mode which is the first operation mode. . Each of the 20 squares located below the squares indicated as A to H in FIGS. 9 and 10 corresponds to 20 shift registers (first to twentieth shift registers provided in each of the memories A to H in FIG. 7). Represents the). The description such as [15: 0] described in the leftmost column of FIGS. 9 and 10 represents the input terminal number of the 320-bit wide parallel signal input to the data array conversion unit 530. For example, the notation [15: 0] means the 0th to 15th input terminal numbers corresponding to 1 to 16 bits of parallel input signals.

  First, the selector unit 532 outputs, to the memory H, data (40 bytes) of the initial 320 bits of the OTUk frame 130 captured in synchronization with the first processing clock. The 320 bits of data are synchronized with the first processing clock, as shown in FIG. 9A, 1 to 16 bits of the first shift register of the memory H (“2” in FIG. 9A). This number means that “1 to 2 bytes” have been stored counting from the beginning of the OTUk frame 130.) 17 to 32 bits of the second shift register of the memory H Described as “4.” It means that “3 to 4 bytes” are stored counting from the beginning of the OTUk frame 130), the third shift register of the memory H (same as “6”, etc.) Note: Counting from the beginning of the OTUk frame 130 means that "5 to 6 bytes" has been stored), ..., 305 to 320 bits of the 20th shift register of the memory H (same as "40" Note: “39 to 40 bytes” have been stored counting from the beginning of the OTUk frame Is stored in Thus, the data array conversion unit 530 stores the first 40 bytes of data of the OTUk frame in the first to twentieth shift registers of the memory H every two bytes in synchronization with the first processing clock. Here, the same hatched data in FIG. 9A means data corresponding to a “block” obtained by dividing the OTUk frame 130 into a predetermined size (m = 16 bytes).

  Next, the selector unit 532 outputs data (for 40 bytes) of 321 to 640 bits counted from the beginning of the OTUk frame 130 to the memory H in synchronization with the second processing clock. The 320-bit data is synchronized with the second processing clock, and as shown in FIG. 9B, the first shift register (“42” in FIG. 9B) of the memory H has 321 to 363 bits. 337-352 bits in the second shift register (denoted as "44" in memory H) and 353-368 bits in the third shift register (same as "46" in memory H). ,..., 625 to 640 bits are stored in the twentieth shift register (denoted as "80" in the memory H). The data stored in the memory H in synchronization with the first processing clock is shifted to the memory G in synchronization with the second processing clock and stored in the memory G. As described above, the data array conversion unit 530 synchronizes the data of 41 to 80 bytes counted from the beginning of the OTUk frame 130 to the first to twentieth shift registers of the memory H in synchronization with the second processing clock. And stores the first 40 bytes of data of the OTUk frame 130 in the first to twentieth shift registers of the memory G every two bytes.

  Next, the selector unit 532 outputs 641 to 960 bits of data (for 40 bytes) counted from the beginning of the OTUk frame 130 to the memory H in synchronization with the third processing clock. The 320 bits of data are synchronized with the third processing clock, and as shown in FIG. 10A, 641 to 656 bits of the first shift register of the memory H (“82” in FIG. In the second shift register (denoted as "84") of the memory H, and 673 to 688 bits in the second shift register of the memory H (denoted as "86" in the same). ,..., 945 to 960 bits are stored in the twentieth shift register (denoted as "120" in the memory H). The data stored in the memory H in synchronization with the second processing clock is shifted to the memory G in synchronization with the third processing clock and stored in the memory G. The data stored in the memory G in synchronization with the second processing clock is shifted to the memory F in synchronization with the third processing clock and stored in the memory F. As described above, the data array conversion unit 530 synchronizes the third processing clock with data of 81 to 120 bytes counted from the beginning of the OTUk frame 130 and transfers 2 bytes to the first to twentieth shift registers of the memory H. And store 41 to 80 bytes of data counted from the beginning of the OTUk frame 130 every 2 bytes in the first to twentieth shift registers of the memory G, and 40 bytes of data at the beginning of the OTUk frame 130, The first to twentieth shift registers of the memory F are stored every two bytes.

  The data array conversion unit 530 takes in 40 bytes of data of the OTUk frame 130 in synchronization with each of the fourth to seventh processing clocks, and stores the data in the memory H, as described above. The stored data is shifted and held in the adjacent memory. The data array conversion unit 530 holds data of 280 bytes (40 bytes × 7 clocks) of the OTUk frame 130 in the memories B to H in synchronization with the seventh processing clock as shown in FIG. Do. That is, the first 40 bytes of the OTUk frame 130 in the memory B, 41 to 80 bytes counting from the beginning of the OTUk frame 130 in the memory C,..., And 241 to 280 bytes in the memory H are provided in each memory. It is stored every 2 bytes in the 1st to 20th shift registers.

  The data array conversion unit 530 transitions to the data distribution mode, which is the second operation mode, at the timing of holding 320 bytes of data that can be held by itself. Hereinafter, the data distribution mode which is the second operation mode will be described. In the data distribution mode, the 280 bytes of data held in the memories B to H of the data holding unit 540 are not shifted to the adjacent memories, respectively, and as shown in FIG. The selector unit 532 is set to be held in the order shift register (shift register aligned in the horizontal direction in the drawing). A block, which is a unit for distributing the OTUk frame 130 to logical lanes, is 16 bytes. On the other hand, the amount of data that can be held in the first shift register of each of the memories A to H is also 16 bytes (= 2 bytes × 8). The same applies to the 2nd to 20th shift registers. Therefore, the selector unit 532 causes the first block (1 to 16 bytes stored in the memory B) obtained by dividing the OTUk frame 130 to the first shift register of the memories A to H in synchronization with the eighth processing clock. The second block (17 to 32 bytes, stored in memory B) is in the second shift register of memory A to H, and the third block (33 to 48 bytes, stored in memory B and C) is on memory A to H Set the input / output status of each shift register so that the 17th block (257 to 272 bytes, stored in the memory H) is stored in the 17th shift register of the memories A to H in the third shift register, ... Do (set the data path). Further, the selector unit 532 sets the input / output state of each shift register so that the first 8 bytes (273 to 280 bytes, stored in the memory H) of the 18th block are stored in the 18th shift register of the memories A to D. Set up (set up the data path). At this time, the selector unit 532 sets each shift register so that data closest to the beginning of the OTUk frame 130 in a certain block is stored in the memory A and data farthest from the beginning of the OTUk frame 130 is stored in the memory H. Set the output state (set the data path). Then, the selector unit 532 causes the 2241-2560-bit data (for 40 bytes) of the OTUk frame 130 captured in synchronization with the eighth processing clock to be stored in the eighteenth shift register in the memories E to H, in the memories A to H. It is set to be input to the 19th shift register and the 20th shift register of the memories A to H, respectively (the data path is set). By performing such processing in synchronization with the eighth processing clock, the data array conversion unit can process 320 bytes of data of the OTUk frame as shown in FIG. It is possible to rearrange the arrangement of data so as to be held in the order shift register.

  FIG. 12 is a diagram for explaining a setting example of the selector unit 532 in the data distribution mode. The two bytes (the first two bytes of the OTUk frame 130) stored in the first shift register of the memory B in synchronization with the seventh processing clock are synchronized with the first shift register of the memory A in synchronization with the eighth processing clock. You just store it. Therefore, selector unit 532 sets the input / output states of these shift registers so that the output terminal of the first shift register of memory B and the input terminal of the first shift register of memory A are connected (data path To set). Two bytes (3 and 4 bytes counted from the beginning of the OTUk frame 130) stored in the second shift register of the memory B in synchronization with the seventh processing clock are synchronized with the eighth processing clock of the memory B. It may be stored in the first shift register. Therefore, selector unit 532 sets the input / output states of these shift registers so that the output terminal of the second shift register of memory B and the input terminal of the first shift register of memory B are connected (data path To set On the other hand, the 2 bytes (17 and 18 bytes counted from the beginning of the OTUk frame 130 and the 2 bytes at the beginning of the second block) stored in the ninth shift register of the memory B in synchronization with the seventh processing clock are , And may be stored in the second shift register of the memory A in synchronization with the eighth processing clock. Therefore, the selector unit 532 sets the input / output states of these shift registers so that the output terminal of the ninth shift register of the memory B and the input terminal of the second shift register of the memory A are connected (data path To set In addition, the selector unit 532 is an input of these shift registers so that the input terminal of the input terminal number [207: 192] and the input terminal of the 20th shift register of the memory A are connected in synchronization with the eighth processing clock. Set the input states of these shift registers so that the input terminal of input terminal number [223: 208] is connected to the input terminal of the 20th shift register of memory B,... The input states of these shift registers are set such that the input terminals of [319: 304] and the input terminals of the 20th shift register of the memory H are connected (the path of data is set). By such setting change of the operation mode of the selector unit 532, the data array conversion unit 530 arranges the 320-byte data of the OTUk frame 130 in the arrangement as shown in FIG. 11 in synchronization with the eighth processing clock. It can be rearranged.

  When rearrangement of the captured 320 bytes of data is completed, data array conversion unit 530 is set to the data acquisition / output mode, which is the first operation mode. Then, the data array conversion unit 530 outputs the 40-byte (320 bits) data stored in the memory A from the logical lane output terminal of the selector unit 532 having a width of 320 bits in synchronization with the ninth processing clock. At the same time, the data stored in the memory B is shifted to the memory A, the data stored in the memory C is shifted to the memory G, and so on. At the same time, the data array conversion unit 530 outputs the first 320 bits of data (for 40 bytes) out of the next 320 bytes of the captured OTUk frame 130 to the memory H, as in the processing with the first processing clock. Hold. The data array conversion unit 530 outputs the 40-byte (320 bits) data stored in the memory A from the logical lane output terminal of the 320-bit wide selector unit in synchronization with the tenth processing clock. The data stored in the memory B is shifted to the memory A, the data stored in the memory C is shifted to the memory F, and so on. At the same time, the data array conversion unit 530 outputs, to the memory H, data (for 40 bytes) of 321 to 640 bits of the next 320 bytes of the captured OTUk frame 130, as in the processing with the second processing clock. And hold. The data array conversion unit outputs the data stored in the memory A in synchronization with the eleventh to fifteenth processing clocks, shifts the data stored in each memory to the adjacent memory, and holds it at the same time. , 320 bits of data (40 bytes) are output to the memory H and held. The data array conversion unit 530 sets the selector unit 532 to the data distribution mode which is the second operation mode in synchronization with the sixteenth processing clock, and the data stored in the memory A (this corresponds to the eighth process). In the rearrangement of data performed in synchronization with the clock, the data stored in the memory H is output from the logical lane output terminal of the selector unit 532 and the data stored in the memories B to H The shift registers of A to H are held in the same order shift register to rearrange data for each block.

  By the processing of the data array conversion unit 530 described above, the first shift register of the memory A sequentially outputs data divided into 16-byte blocks and distributed to the first logical lane. Similarly, the second shift register of the memory A sequentially outputs data distributed to the second logical lane. The xth (x is an integer of 1 to 20) shift register of the memory A outputs the data distributed to the xth logical lane.

  As described above, when the size of a block which is a unit for dividing the OTUk frame 130 is m bytes and the number of logical lanes in which the OTUk frame 130 is distributed in block units is n, the data array conversion unit 530 generates m. Data of OTUk frame of × n bytes is taken into the data holding unit, and the arrangement of the data taken into the data holding unit is rearranged so that a certain block is held in the shift register of the same order, the LLM attaching unit 422 outputs The OTUk frame 130 can be divided into 16-byte blocks as division units, distributed to 20 logical lanes in a round robin manner, and output. At that time, since rearrangement of data arrangement in the data distribution mode which is the second operation mode is completed with only one processing clock, logical lane distribution with less data transfer processing delay (latency) becomes possible.

  As described above, the data array conversion unit 530 according to the present embodiment receives the data of the OTUk frame 130 as a parallel signal (bit width a) and parallelizes the data of the OTUk frame 130 distributed to a plurality of n logical lanes. It is output as a signal (bit width a), and is m × n which is the product of the block size (m bytes) which is a division unit of the OTUk frame 130 and the number of logical lanes (n) distributing the OTUk frame 130 A data holding unit 540 capable of holding byte data is provided. The data holding unit 540 includes a plurality of memories 546 each capable of holding data equal to the amount of data (a bit) input to the data arrangement conversion unit 530 in one processing clock. The number of memories 546 is m × n / (a / 8). Then, the data array conversion unit 530 causes the plurality of memories 546 to sequentially hold the data of the OTUk frame 130 input in synchronization with the processing clock, and when data of m × n bytes is held, the input data The arrangement of data held in each memory 546 is rearranged so that data of blocks divided in units of m bytes from the beginning are arranged in parallel, and data arranged in parallel is output.

  Here, each of the plurality of memories 546 may be configured to include shift registers 548 equal in number to the number of logical lanes (n). The data array conversion unit 530 may further include a selector unit 532 in order to control the flow of data input to and output from the data holding unit 540.

  6 and 7 illustrate a specific configuration example of the data array conversion unit 530 according to the present embodiment. Data is input / output with a bit width a = 320, and the capacity of the data storage unit is m. × n = 320 bytes (block size m = 16 bytes, number of logical lanes n = 20), comprising eight 40-byte memories, each of which comprises twenty shift registers; configuration of data array conversion unit 530 Is disclosed. However, the present invention is not limited to this configuration, and can be applied to various configurations without departing from the concept described above.

  For example, when the parallel signal input to the data array conversion unit 530 is 160 bits wide, the parallel transmission technology (block size m = 16 bytes, number of logical lanes n = 20) of OTU4 frame disclosed in Non-Patent Document 1 For the implementation, the capacity of the data holding unit 540 may be 320 bytes as well, but the capacity of each memory 546 is 160/8 = 20 bytes, and the capacity of the shift register 548 provided in the memory is 20/20 = 1 bytes And it is sufficient. The number of memories 546 provided in the data holding unit 540 may be 320/20 = 16. Even in this case, the capacity of the first shift register provided in each of the 16 memories 546 adds up to 16 bytes. Since this is equal to the size of the block which is the division unit of the OTU4 frame, “a block of divided into 16 byte units from the head of the input data is The arrangement of data held in each memory can be rearranged "so that the data is arranged in parallel.

  The present invention can also be applied to block sizes and logical lane numbers different from those specified in Non-Patent Document 1. When the number of logical lanes is n = 10, the capacity of the data holding unit may be 160 bytes (16 bytes × 10 logical lanes).

(Special case)
As a special example, the amount of data (m × n bytes) obtained by integrating the block size (m bytes) and the number of logical lanes (n) can be acquired by the data array conversion unit 530 in one processing clock. It may be equal to the quantity (ie the parallel signal input width of the data array converter). In this case, the capacity of the data holding unit 540 and the capacity of the memory 546 become equal, that is, the data holding unit 540 is provided with one memory 546. In this case, it is necessary to hold the data in the memory 546 in the first place There is no.

  For example, when the block size m = 10 bytes, the number of logical lanes n = 4, and the parallel signal input to the data array conversion unit is 320 bits wide, as shown in FIG. Data of m × n bytes is stored by the clock. The data array conversion unit 530 has input terminal numbers 0 to 79 as a first logical lane, input terminal numbers 80 to 159 as a second logical lane, input terminal numbers 160 to 239 as a third logical lane, and input terminal number 240. If the 319 to 319 are output as the fourth logical lane, “the OTUk frame can be divided into a plurality of blocks, and can be distributed and output to the plurality of logical lanes in block units”. In this case, since it is not necessary to rearrange the data array stored in the memory, it is not necessary to hold the data of the OTUk frame in the memory in the first place.

  Therefore, when the amount of data obtained by integrating the block size and the number of logical lanes is equal to the amount of data that can be acquired by the data arrangement conversion unit 530 in one processing clock, the data of the OTUk frame input to the data arrangement conversion unit 530 May be output as it is without being stored in the data holding unit 540. In other words, the selector unit 532 of the data array conversion unit 530 controls the flow of data so that the data of the OTUk frame 130 input to the data array conversion unit 530 is output as it is without being stored in the data storage unit 140. Just do it. With such a configuration or control, when the OTUk frame 130 is distributed and output to a plurality of logical lanes, it is not necessary to buffer the data (that is, temporarily hold data in the data holding unit 540). Therefore, the data transfer processing delay (latency) can be further shortened.

[Configuration of Lane Coupling Unit Provided to Receiving Device]
FIG. 14 is a diagram for explaining the configuration of the lane coupling unit 720 according to the present embodiment. The lane combining unit 720 is included in the receiving device 600 as described in FIG. 4 and includes an FAS synchronization processing unit 722, a data rotation unit 724, a data array conversion unit 726, and a frame reproduction unit 630.

  The FAS synchronization processing unit 722 receives the signals of the twenty logical lanes output from the logical lane restoration unit 610 (FIG. 4). The FAS synchronization processing unit 722 detects FAS (FIG. 3B) for each of the input logical lanes. The FAS synchronization processing unit 722 recognizes the value of the LLM from the third OA2 byte included in the detected FAS, and outputs the value of the LLM to the data rotation unit 724. Further, the FAS synchronization processing unit 722 corrects the delay time variation (skew) between the logical lanes by delaying the signal of each logical lane based on the detected FAS. The FAS synchronization processing unit 722 outputs the skew-corrected 20 logical lane signals to the data rotation unit 724 as parallel signals. Here, each logical lane is output as a parallel signal with a width of 16 bits (a total of 320 bits wide).

  The data rotation unit 724 obtains the value of LLM output from the FAS synchronization processing unit 722, and calculates a remainder LLM MOD 20 when the value of LLM is divided by 20. The value of LLM MOD 20 indicates the logical lane in which the FAS is arranged for a certain OTUk frame 130. Therefore, based on the value of LLM MOD 20, the signal between the logical lanes is rotated so that FAS is placed in Lane 0. For example, in the case of LLM MOD 20 = 1, as shown in FIG. 3 (b), FAS is arranged on Lane 1, the signal of Lane 1 is Lane 0, the signal of Lane 2 is Lane 1 and the signal of Lane 3 is Lane 2 ... Move the signal of Lane 19 to Lane 18 and the signal of Lane 0 to Lane 19. The data rotation unit 724 performs rotation processing on the signal of each logical lane between the logical lanes according to the value of LLM, and outputs the result to the data array conversion unit. Also in the data rotation unit 724, each logical lane outputs a 16-bit parallel signal (320 bits in total).

  The data array conversion unit 726 combines the blocks distributed to each logical lane in order to reconstruct the OTUk frame 130 (FIG. 3A). Details of the configuration and processing of the data array conversion unit 726 will be described later.

  The OTUk frame 130 output from the data array conversion unit 726 is input to the frame reproduction unit 630 as a parallel signal (here, 320 bits wide). However, in this OTUk frame 130, the third OA2 byte of FAS is replaced with the value of LLM. Therefore, the frame reproduction unit 630 rewrites the third OA2 byte of FAS to the value of the original OA2 (“0010 1000” bit), and reproduces the OTUk frame 130. The frame reproduction unit 630 outputs the reproduced OTUk frame 130 to the frame processing unit 630 (FIG. 4).

(Configuration of data array conversion unit)
The data array conversion unit 726 included in the lane coupling unit 720 of the receiving device has the same configuration as the data array conversion unit 530 included in the lane allocation unit 520 of the transmitting device illustrated in FIGS. 6 and 7. A data holding unit 540 capable of holding m × n byte data, which is the product of the block size (m bytes), which is a division unit, and the number (n) of logical lanes distributing the OTUk frame 130; A selector unit 532 that controls the flow of input and output data is provided. The data holding unit 540 includes a plurality of memories 546 each capable of holding data equal to the amount of data (a bit) input to the data arrangement conversion unit 726 in one processing clock. The number of memories is m × n / (a / 8). Each of the plurality of memories comprises shift registers 548 equal in number to the number of logical lanes (n).

  For example, when the block size m = 16 bytes, the number of logical lanes n = 20, and the parallel signal input to the data array conversion unit 726 is 320 bits wide, the capacity of the data holding unit 540 is at least 320 bytes, the data holding unit 540 The number of memories 546 provided in the memory may be eight, and the number of shift registers 548 provided in each of the memories 546 may be twenty.

(Processing of data array conversion unit)
The data array conversion unit 726 included in the receiving apparatus has two operation modes, similarly to the data array conversion unit 530 included in the transmitting apparatus. The first operation mode is a data acquisition / output mode in which data input in synchronization with the processing clock is sequentially held in a plurality of memories, or data held in the memory is sequentially output. The second operation mode Is a data distribution mode for rearranging the arrangement of data held in each memory when data of m × n bytes is held.

  FIGS. 15A and 15B are diagrams for explaining the operation of the data array conversion unit 726 for capturing data in the data loading / output mode which is the first operation mode. FIG. 16 is a diagram for explaining an operation of the data array conversion unit 726 to capture data in the data distribution mode which is the second operation mode. The hatched data in FIGS. 15A and 15B and FIG. 16 mean data corresponding to “blocks” obtained by dividing the OTUk frame 130 into a predetermined size (m = 16 bytes). (Similar to FIGS. 9 to 11). Note that data of A column → B column →... → H column of FIG. 11 is sequentially input to the data array conversion unit 726 included in the receiving apparatus in synchronization with the processing clock. This is the same as the data output to the logical lane by the transmitting device (provided that there is no bit error or the like during transmission).

  The data array conversion unit 726 causes the memory H to hold 320-bit data corresponding to the A column of FIG. 11 captured in synchronization with the first processing clock (FIG. 15A). The data array conversion unit 726 stores 320-bit data corresponding to the B column in FIG. 11 captured in synchronization with the second processing clock in the memory H, and also stores the data stored in the memory H in the memory G. Shift to hold. The data array conversion unit 726 stores 320 bits of data corresponding to columns C to G in FIG. 11 taken in synchronization with the third to seventh processing clocks in the memory H and is already stored in the memory. The stored data is shifted and held in the adjacent memory (FIG. 15 (b)).

  The data array conversion unit 726 transitions to the data distribution mode at the timing of holding 320-byte data that it can hold. In the data distribution mode, which is the second operation mode, the 280-byte data held in the memories B to H of the data holding unit 540 are not shifted to the adjacent memories, respectively, but as shown in FIG. The arrangement is rearranged so that data closer to the top of the data 130 is sequentially arranged in the memory A and data farther from the top is sequentially arranged in the memory H. Selector unit 532 sets the connection state of the input / output terminal of each shift register included in memories A to H so that the data of the arrangement of FIG. 15B can be rearranged in FIG. To set The data array conversion unit 530 takes in 320-bit data corresponding to the H column of FIG. 11 in synchronization with the eighth processing clock, and simultaneously rearranges the arrangement of FIG.

  The data array conversion unit 726 again transits to the data acquisition / output mode which is the first operation mode, and outputs the data stored in the memory A in synchronization with the ninth to sixteenth processing clocks. The data stored in ~ H are shifted and held in the adjacent memory, and the input 320-bit data is stored in the memory H.

(Special case)
Similar to the lane assignment unit 520 included in the transmission apparatus, the data amount (m × n bytes) obtained by integrating the block size (m bytes) and the number of logical lanes (n) is 1 for the data array conversion unit 726 (530). If it is equal to the amount of data that can be fetched by the processing clock (that is, the parallel signal input width of the data array conversion unit), it is not necessary to hold the data in the data holding unit 540.

  Therefore, when the amount of data obtained by integrating the block size and the number of logical lanes is equal to the amount of data that can be acquired by the data array conversion unit 726 in one processing clock, the data input to the data array conversion unit 727 is It may be output as it is without storing it in the data holding unit 540. In other words, the selector unit 532 of the data array conversion unit 726 may control the flow of data so as to output the data input to the data array conversion unit 726 as it is without storing the data in the data storage unit 540. With such a configuration or control, when receiving the OTUk frame 130 distributed and transmitted to a plurality of logical lanes, it is necessary to buffer the data (that is, temporarily hold the data in the data holding unit) As a result, the data reception processing delay (latency) can be further shortened.

  Each of the LLM providing unit 422, the data rotation unit 560, and the FAS synchronization processing unit 722, the data rotation unit 724, and the frame reproduction unit 630, which are included in the lane coupling unit 720, included in the lane assignment unit 520 described above, is, for example, a logic circuit. May be implemented by an integrated circuit or a large scale integrated circuit (LSI) on which the Alternatively, the general-purpose processor or MPU (Micro Processing Unit) may be configured to operate by processing an instruction from a program loaded to the main storage device.

100 client signal 110 OPUk frame 112 OPUk payload 114 OPUk overhead 120 ODUk frame 124 ODUk overhead 130 OTUk frame 134 OTUk overhead 136 OTUkFEC
230 Frame Sync (FA) Overhead 232 Frame Sync (FAS)
234 Multi-frame synchronization signal (MFAS)
400 frame transmission apparatus 410 frame generation unit 420 520 lane allocation unit 422 LLM attachment unit 424 block division unit 426 block distribution unit 430 bit multiplexing unit 530 data array conversion unit 532 selector unit 534, 536 320 bit width parallel signal line 540 data holding Section 542, 544 2560-bit parallel signal line 546 Memory 548 Shift register 560 Data rotation section 600 Frame reception device 610 Logical lane restoration section 620, 720 Lane connection section 622 Logical lane identification section 624 Block connection section 626 Frame reproduction section 630 frames Processing unit 722 FAS synchronization processing unit 724 Data rotation unit 726 Data array conversion unit

Claims (8)

A frame transmitting apparatus which divides data of a frame containing a client signal into blocks of m bytes (m is a positive number), distributes n blocks (n is a positive number) to logical lanes in block units, and outputs ,
An LLM attaching unit that attaches a marker for identifying the position of the logical lane to which the frame is distributed to a header of the frame, and outputs data of the frame to which the marker is attached as a parallel signal;
A data array conversion unit that receives the data of the frame output from the LLM assignment unit as a parallel signal, and distributes the input data of the frame to the logical lane in units of blocks, and outputs the data.
And a data rotating unit that changes the position of the logical lane to which the frame is distributed according to the value of the marker.
The data array conversion unit can hold m × n bytes of data, which is the product of the size of the block and the number of logical lanes, and each data amount input to the data array conversion unit in one processing clock A data holding unit having a plurality of memories capable of holding data equal to
The data array conversion unit causes the plurality of memories to sequentially hold the input data of the frame in synchronization with the processing clock, and is input when data of the frame of m × n bytes is stored. A frame transmission apparatus characterized by rearranging and outputting data arrangement of the plurality of memories so that data of blocks divided in units of m bytes from the head of data of the frame are arranged in parallel. The frame transmission apparatus according to claim 1, wherein the data array conversion unit further includes a selector unit that controls a path of data input to and output from the data holding unit. The frame transmission apparatus according to claim 1, wherein each of the plurality of memories comprises shift registers equal in number to the number of logical lanes. When the amount of data input to the data array conversion unit in one processing clock is equal to m × n bytes, which is the product of the size of the block and the number of logical lanes, the selector unit selects the data array conversion unit. The frame transmitting apparatus according to claim 2, wherein the input data of the frame is output without being stored in the data holding unit. The data of the frame containing the client signal is divided into blocks of m bytes (m is a positive number), and n pieces (n is a positive number) of logical lanes distributed in block units are received, and from the logical lane A frame receiving apparatus for reproducing the frame, wherein
An FAS synchronization processing unit that detects a marker for identifying the position of the logical lane to which the frame is distributed for each of the logical lanes;
A data rotation unit that changes the position of the logical lane to which the frame is distributed according to the value of the marker detected by the FAS synchronization processing unit;
A data array conversion unit for receiving data of the n logical lanes whose positions have been changed by the data rotation unit and outputting the data of the frame distributed to the logical lanes in units of blocks;
The data array conversion unit can hold m × n bytes of data, which is the product of the size of the block and the number of logical lanes, and each data amount input to the data array conversion unit in one processing clock A data holding unit having a plurality of memories capable of holding data equal to
The data array conversion unit causes the plurality of memories to sequentially hold the input data of the logical lane in synchronization with the processing clock, and the data of the logical lane of m × n bytes is held, A frame receiving apparatus characterized by rearranging the data arrangement of the plurality of memories so that the data is output in units of m bytes from the beginning of the data of the frame distributed to logical lanes. The frame reception device according to claim 5, wherein the data array conversion unit further includes a selector unit that controls a path of data input to and output from the data holding unit. The frame reception device according to claim 5 or 6, wherein each of the plurality of memories comprises shift registers whose number is equal to the number of the logical lanes. When the amount of data input to the data array conversion unit in one processing clock is equal to m × n bytes, which is the product of the size of the block and the number of logical lanes, the selector unit selects the data array conversion unit. The frame receiving apparatus according to claim 6, wherein the input data of the logical lane is output without being stored in the data holding unit.

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