JP2011222943A - Circuit board, semiconductor device, method of manufacturing circuit board and method of manufacturing semiconductor device - Google Patents

Circuit board, semiconductor device, method of manufacturing circuit board and method of manufacturing semiconductor device Download PDF

Info

Publication number
JP2011222943A
JP2011222943A JP2010238475A JP2010238475A JP2011222943A JP 2011222943 A JP2011222943 A JP 2011222943A JP 2010238475 A JP2010238475 A JP 2010238475A JP 2010238475 A JP2010238475 A JP 2010238475A JP 2011222943 A JP2011222943 A JP 2011222943A
Authority
JP
Japan
Prior art keywords
layer
circuit
insulating layer
resin
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010238475A
Other languages
Japanese (ja)
Inventor
Yoshiki Nishikawa
佳樹 西川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP2010238475A priority Critical patent/JP2011222943A/en
Priority to PCT/JP2011/001461 priority patent/WO2011118146A1/en
Priority to TW100110283A priority patent/TW201203472A/en
Publication of JP2011222943A publication Critical patent/JP2011222943A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3489—Composition of fluxes; Methods of application thereof; Other methods of activating the contact surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81022—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H01L2224/81204—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81411—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81897—Mechanical interlocking, e.g. anchoring, hook and loop-type fastening or the like
    • H01L2224/81898—Press-fitting, i.e. pushing the parts together and fastening by friction, e.g. by compression of one part against the other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81905—Combinations of bonding methods provided for in at least two different groups from H01L2224/818 - H01L2224/81904
    • H01L2224/81906—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81905—Combinations of bonding methods provided for in at least two different groups from H01L2224/818 - H01L2224/81904
    • H01L2224/81907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H01L2224/83204—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01038—Strontium [Sr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01056—Barium [Ba]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a circuit board capable of suppressing occurrence of deflection.SOLUTION: A circuit board 1 includes a first insulator layer 21 through which a conductor penetrates; a first circuit layer 22 which is provided on one side of the first insulator layer 21 and is connected to the conductor; a second insulator layer 23 which covers the first circuit layer 22 and in which an opening for exposing a part of the first circuit layer 22 is formed; and a metal layer 27 which is provided in the opening of a second insulator layer 23 and contacts to the part of the first circuit layer 22 exposed from the opening. The metal layer 27 comprises, starting from the first circuit layer 22 side, a metal layer (a) 271 containing copper and having a thickness of 0-55 μm, a metal layer (b) 272 which contains nickel and has a thickness of 2-15 μm, and a metal layer (c) 273 which contains tin and has a thickness of 3-30 μm.

Description

本発明は、回路基板、半導体装置、回路基板の製造方法および半導体装置の製造方法に関する。   The present invention relates to a circuit board, a semiconductor device, a circuit board manufacturing method, and a semiconductor device manufacturing method.

従来、半導体チップ等を搭載する基板としては、様々なものが提案されている。たとえば、インターポーザ基板等が提案されている（特許文献１参照）。   Conventionally, various substrates have been proposed for mounting semiconductor chips and the like. For example, an interposer substrate has been proposed (see Patent Document 1).

特開平１０−３２１９９０号公報Japanese Patent Laid-Open No. 10-321990

近年、大きな回路基板を形成した後、複数の半導体チップをのせ、その後回路基板をダイシングして、個々の半導体装置を得るという製造方法が実施されている。このような製造方法において、回路基板と半導体チップとの半田接続において、均一に接続することが困難であった。   In recent years, a manufacturing method has been implemented in which a large circuit board is formed, a plurality of semiconductor chips are mounted, and then the circuit board is diced to obtain individual semiconductor devices. In such a manufacturing method, it has been difficult to make a uniform connection in solder connection between the circuit board and the semiconductor chip.

本発明によれば、導電体が貫通する第一絶縁層と、
前記第一絶縁層の一方の側に設けられ、前記導電体に接続された第一回路層と、
この第一回路層を被覆するとともに、第一回路層の一部を露出させるための開口が形成された第二絶縁層と、
前記第一絶縁層の他方の側に設けられ、前記導電体に接続された第二回路層と、
前記第二回路層を被覆する第三絶縁層と、
前記第二絶縁層の開口内に設けられ、前記開口から露出する前記第一回路層の一部と接触する金属層とを備え、
前記金属層は、前記第一回路層側から、銅を含む金属層（ａ）、ニッケルを含む金属層（ｂ）、錫を含む金属層（ｃ）がこの順に構成され、銅を含む金属層（ａ）の厚さは０μｍ以上、５５μｍ以下であり、ニッケルを含む金属層（ｂ）の厚さは２μｍ以上、１５μｍ以下であり、錫を含む金属層（ｃ）の厚さは３μｍ以上、３０μｍ以下である回路基板を提供できる。 According to the present invention, a first insulating layer through which a conductor penetrates;
A first circuit layer provided on one side of the first insulating layer and connected to the conductor;
A second insulating layer covering the first circuit layer and having an opening for exposing a portion of the first circuit layer;
A second circuit layer provided on the other side of the first insulating layer and connected to the conductor;
A third insulating layer covering the second circuit layer;
A metal layer provided in the opening of the second insulating layer and in contact with a part of the first circuit layer exposed from the opening;
The metal layer is composed of a metal layer (a) containing copper, a metal layer (b) containing nickel, and a metal layer (c) containing tin in this order from the first circuit layer side. The thickness of (a) is 0 μm or more and 55 μm or less, the thickness of the metal layer (b) containing nickel is 2 μm or more and 15 μm or less, and the thickness of the metal layer (c) containing tin is 3 μm or more, A circuit board having a thickness of 30 μm or less can be provided.

この発明によれば、前記金属層を、前記第一回路層側から、銅を含む金属層（ａ）、ニッケルを含む金属層（ｂ）、錫を含む金属層（ｃ）がこの順に構成され、銅を含む金属層（ａ）の厚さは０μｍ以上、５５μｍ以下であり、ニッケルを含む金属層（ｂ）の厚さは２μｍ以上、１５μｍ以下であり、錫を含む金属層（ｃ）の厚さは３μｍ以上、３０μｍ以下とすることで、半導体チップに設けられた接続部と確実に接続ができる。   According to this invention, the metal layer (a) including copper, the metal layer (b) including nickel, and the metal layer (c) including tin are configured in this order from the first circuit layer side. The thickness of the metal layer (a) containing copper is 0 μm or more and 55 μm or less, the thickness of the metal layer (b) containing nickel is 2 μm or more and 15 μm or less, and the thickness of the metal layer (c) containing tin By setting the thickness to 3 μm or more and 30 μm or less, it is possible to reliably connect to the connection portion provided in the semiconductor chip.

本発明によれば、半導体チップとの接続が確実にできる回路基板が提供される。   According to the present invention, a circuit board that can be reliably connected to a semiconductor chip is provided.

本発明の一実施形態にかかる回路基板の断面図である。It is sectional drawing of the circuit board concerning one Embodiment of this invention. 回路基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of a circuit board. 回路基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of a circuit board. 回路基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of a circuit board. 回路基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of a circuit board. 回路基板上に半導体チップを搭載する工程を示す図である。It is a figure which shows the process of mounting a semiconductor chip on a circuit board. 半導体装置を示す図である。It is a figure which shows a semiconductor device.

以下、本発明の実施形態を図面に基づいて説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

はじめに、図５を参照して、本実施形態の回路基板１の概要について説明する。   First, the outline of the circuit board 1 of the present embodiment will be described with reference to FIG.

本実施形態の回路基板１は、分割して複数の回路基板部として使用されるものである。   The circuit board 1 of this embodiment is divided and used as a plurality of circuit board portions.

基板２は、導電体２０が貫通する第一絶縁層２１と、第一絶縁層２１の一方の側に設けられ、導電体２０に接続された第一回路層２２と、この第一回路層２２を被覆するとともに、第一回路層２２の一部上に開口が形成された第二絶縁層２３と、第一絶縁層２１の他方側に設けられ、導電体２０に接続された第二回路層２４と、第二回路層２４を被覆する第三絶縁層２５と、第二絶縁層２３の開口内に設けられた金属層２７とを備える。   The substrate 2 includes a first insulating layer 21 through which the conductor 20 passes, a first circuit layer 22 provided on one side of the first insulating layer 21 and connected to the conductor 20, and the first circuit layer 22 A second insulating layer 23 having an opening formed on a part of the first circuit layer 22 and a second circuit layer provided on the other side of the first insulating layer 21 and connected to the conductor 20 24, a third insulating layer 25 covering the second circuit layer 24, and a metal layer 27 provided in the opening of the second insulating layer 23.

また、図１に示すように、フラックス機能を有する化合物を含む樹脂層３が、第二絶縁層２３を被覆するとともに、金属層２７上に設けられていてもよい。   Further, as shown in FIG. 1, a resin layer 3 containing a compound having a flux function may cover the second insulating layer 23 and be provided on the metal layer 27.

金属層２７は、第一回路層２２側から順に、銅を含む金属層（ａ）２７１、ニッケルを含む金属層（ｂ）２７２、錫を含む金属層（ｃ）２７３がこの順に構成されている。   The metal layer 27 includes a metal layer (a) 271 containing copper, a metal layer (b) 272 containing nickel, and a metal layer (c) 273 containing tin in this order from the first circuit layer 22 side. .

銅を含む金属層（ａ）２７１の厚さは０μｍ以上、５５μｍ以下であり、ニッケルを含む金属層（ｂ）２７２の厚さは２μｍ以上、１５μｍ以下であり、錫を含む金属層（ｃ）２７３の厚さは３μｍ以上、３０μｍ以下である。   The thickness of the metal layer (a) 271 containing copper is 0 μm or more and 55 μm or less, the thickness of the metal layer (b) 272 containing nickel is 2 μm or more and 15 μm or less, and the metal layer (c) containing tin The thickness of 273 is 3 μm or more and 30 μm or less.

次に、本実施形態の回路基板１について詳細に説明する。
（第一絶縁層２１）
第一絶縁層２１は、無機繊維基材を含んでいてもよい。無機繊維基材としては、例えばガラス繊布、ガラス不繊布等のガラス繊維基材、あるいはガラス以外の無機化合物を成分とする繊布又は不繊布等の無機繊維基材があげられる。これらのなかでも、プリント配線基板としたときの剛性の面からガラス織布繊維基材が好ましい。 Next, the circuit board 1 of this embodiment will be described in detail.
(First insulating layer 21)
The first insulating layer 21 may include an inorganic fiber base material. As an inorganic fiber base material, inorganic fiber base materials, such as glass fiber base materials, such as a glass fiber cloth and a glass non-woven cloth, or the fiber cloth or non-fiber cloth which contain inorganic compounds other than glass, for example are mention | raise | lifted. Among these, a glass woven fiber base material is preferable from the viewpoint of rigidity when used as a printed wiring board.

第一絶縁層２１の樹脂を構成する材料としては、例えば、熱硬化性樹脂と、硬化剤とを含んでいることが好ましい。熱硬化性樹脂としては、エポキシ樹脂、シアネート樹脂、フェノール樹脂などを単独あるいは複数組合わせて用いることができる。エポキシ樹脂としては、特に限定はされないが、例えば、絶縁基板用として一般に使用されている、例えば、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、ビスフェノールＡＤ型エポキシ樹脂等のビスフェノール型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂等のノボラック型エポキシ樹脂、臭素化ビスフェノールＡ型エポキシ樹脂、臭素化フェノールノボラック型エポキシ樹脂等の臭素化型エポキシ樹脂、トリグリシジルイソシアネートなどの複素環式エポキシ樹脂のほか、脂環式型エポキシ樹脂、ビフェニル型エポキシ樹脂、ナフタレン型エポキシ樹脂、グリシジルエステル型エポキシ樹脂等が挙げられる。これらを単独または２種類以上組み合わせて使用することができる。   As a material which comprises resin of the 1st insulating layer 21, it is preferable that the thermosetting resin and the hardening | curing agent are included, for example. As the thermosetting resin, an epoxy resin, a cyanate resin, a phenol resin, or the like can be used alone or in combination. Although it does not specifically limit as an epoxy resin, For example, bisphenol type epoxy resins, such as bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol AD type epoxy resin, etc. which are generally used for insulating substrates, phenol Novolak-type epoxy resins, cresol novolak-type epoxy resins, etc. novolak-type epoxy resins, brominated bisphenol A-type epoxy resins, brominated phenol novolac-type epoxy resins, etc. brominated epoxy resins, and heterocyclic epoxy resins such as triglycidyl isocyanate In addition, alicyclic epoxy resin, biphenyl type epoxy resin, naphthalene type epoxy resin, glycidyl ester type epoxy resin and the like can be mentioned. These can be used alone or in combination of two or more.

前記シアネート樹脂としては、例えばハロゲン化シアン化合物とフェノール類とを反応させ、必要に応じて加熱等の方法でプレポリマー化することにより得ることができる。具体的には、ノボラック型シアネート樹脂、ビスフェノールＡ型シアネート樹脂、ビスフェノールＥ型シアネート樹脂、テトラメチルビスフェノールＦ型シアネート樹脂等のビスフェノール型シアネート樹脂等を挙げることができる。これらの中でもノボラック型シアネート樹脂が好ましい。これにより、架橋密度増加による耐熱性向上と、樹脂組成物等の難燃性を向上することができる。   The cyanate resin can be obtained by, for example, reacting a halogenated cyanide compound with a phenol and prepolymerizing it by a method such as heating as necessary. Specific examples include bisphenol type cyanate resins such as novolac type cyanate resin, bisphenol A type cyanate resin, bisphenol E type cyanate resin, and tetramethylbisphenol F type cyanate resin. Among these, novolac type cyanate resin is preferable. Thereby, the heat resistance improvement by a crosslinking density increase and flame retardance, such as a resin composition, can be improved.

硬化剤としては、特に限定はされないが、例えば、絶縁基板用として一般に使用されている、アミノ基を有する硬化剤であって、メタフェニレンジアミン、パラフェニレンジアミン、パラキシレンジアミン、４，４’−ジアミノジフェニルメタン、４，４’−ジアミノジフェニルプロパン、４，４’−ジアミノジフェニルエーテル、４，４’−ジアミノジフェニルスルフォン、４，４’−ジアミノジシクロヘキサン、ビス（４−アミノフェニル）フェニルメタン、１，５−ジアミノナフタレン、メタキシリレンジアミン、パラキシレンナフタレン、１，１−ビス（４−アミノフェニル）シクロヘキサン、ジシアンジアミド、ジアミノジエチルジメチルフェニルメタンなどが用いられる。耐熱性、硬化性等の点で、好ましい硬化剤は、４，４’−ジアミノジフェニルメタン、ジシアンジアミド、ジアミノジエチルジメチルフェニルメタンである。これらのうち何種類かを併用しても良い。   Although it does not specifically limit as a hardening | curing agent, For example, it is a hardening | curing agent which has an amino group generally used for insulating substrates, Comprising: Metaphenylenediamine, paraphenylenediamine, paraxylenediamine, 4,4'- Diaminodiphenylmethane, 4,4′-diaminodiphenylpropane, 4,4′-diaminodiphenyl ether, 4,4′-diaminodiphenylsulfone, 4,4′-diaminodicyclohexane, bis (4-aminophenyl) phenylmethane, 1, 5-Diaminonaphthalene, metaxylylenediamine, paraxylene naphthalene, 1,1-bis (4-aminophenyl) cyclohexane, dicyandiamide, diaminodiethyldimethylphenylmethane, and the like are used. In view of heat resistance, curability and the like, preferred curing agents are 4,4'-diaminodiphenylmethane, dicyandiamide, and diaminodiethyldimethylphenylmethane. Some of these may be used in combination.

また、絶縁基板２１には無機充填材を含んでいてもよい。例えばタルク、焼成クレー、未焼成クレー、マイカ、ガラス等のケイ酸塩、酸化チタン、アルミナ、シリカ、溶融シリカ等の酸化物、炭酸カルシウム、炭酸マグネシウム、ハイドロタルサイト等の炭酸塩、水酸化アルミニウム、水酸化マグネシウム、水酸化カルシウム等の水酸化物、硫酸バリウム、硫酸カルシウム、亜硫酸カルシウム等の硫酸塩または亜硫酸塩、ホウ酸亜鉛、メタホウ酸バリウム、ホウ酸アルミニウム、ホウ酸カルシウム、ホウ酸ナトリウム等のホウ酸塩、窒化アルミニウム、窒化ホウ素、窒化ケイ素、窒化炭素等の窒化物、チタン酸ストロンチウム、チタン酸バリウム等のチタン酸塩等を挙げることができる。無機充填材として、これらの中の１種類を単独で用いることもできるし、２種類以上を併用したりすることもできる。これらの中でも特に、水酸化アルミニウム、シリカが好ましく、溶融シリカ（特に球状溶融シリカ）が低熱膨張性に優れる点で好ましい。その形状は破砕状、球状があるが、基材への含浸性を確保するために樹脂組成物の溶融粘度を下げるには球状シリカを使う等、その目的にあわせた使用方法が採用される。無機充填材の含有量は、樹脂成分１００重量部に対して、３０重量部以上、７０重量部以下であることが好ましく、さらに好ましくは４０重量部以上、６０重量部以下である。   The insulating substrate 21 may contain an inorganic filler. For example, silicates such as talc, calcined clay, unfired clay, mica and glass, oxides such as titanium oxide, alumina, silica and fused silica, carbonates such as calcium carbonate, magnesium carbonate and hydrotalcite, aluminum hydroxide , Hydroxides such as magnesium hydroxide, calcium hydroxide, sulfates or sulfites such as barium sulfate, calcium sulfate, calcium sulfite, zinc borate, barium metaborate, aluminum borate, calcium borate, sodium borate, etc. Borate, aluminum nitride, boron nitride, silicon nitride, carbon nitride and other nitrides, strontium titanate, titanates such as barium titanate, and the like. As the inorganic filler, one of these can be used alone, or two or more can be used in combination. Among these, aluminum hydroxide and silica are particularly preferable, and fused silica (particularly spherical fused silica) is preferable in terms of excellent low thermal expansion. The shape is crushed and spherical, but in order to reduce the melt viscosity of the resin composition in order to ensure the impregnation property to the substrate, a usage method suitable for the purpose is used such as using spherical silica. The content of the inorganic filler is preferably 30 to 70 parts by weight, more preferably 40 to 60 parts by weight with respect to 100 parts by weight of the resin component.

無機充填材の平均粒子径は、特に限定されないが、０．０５〜１０μｍが好ましく、特に０．３〜５μｍが好ましい。この平均粒子径は、例えば粒度分布計（ＨＯＲＩＢＡ製、ＬＡ−５００）により測定することができる。   The average particle diameter of the inorganic filler is not particularly limited, but is preferably 0.05 to 10 μm, and particularly preferably 0.3 to 5 μm. This average particle diameter can be measured, for example, by a particle size distribution meter (manufactured by HORIBA, LA-500).

また、前記無機充填材は、特に限定されないが、平均粒子径が単分散の無機充填材を用いることもできるし、平均粒子径が多分散の無機充填材を用いることができる。さらに平均粒子径が単分散及び／または、多分散の無機充填材を１種類または２種類以上併用したりすることもできる。   Further, the inorganic filler is not particularly limited, but an inorganic filler having a monodispersed average particle diameter can be used, and an inorganic filler having a polydispersed average particle diameter can be used. Furthermore, one or two or more inorganic fillers having an average particle size of monodisperse and / or polydisperse can be used in combination.

なお、第一絶縁層２１として、以下のような樹脂フィルムを使用してよい。樹脂フィルムとしては、例えばポリイミド樹脂フィルム、ポリエーテルイミド樹脂フィルム、ポリアミドイミド樹脂フィルム等のポリイミド樹脂系樹脂フィルム、ポリアミド樹脂フィルム等のポリアミド樹脂系フィルム、ポリエステル樹脂フィルム等のポリエステル樹脂系フィルムが挙げられる。これら中でも主としてポリイミド樹脂系フィルムが好ましい。これにより、弾性率と耐熱性を特に向上することができる。   As the first insulating layer 21, the following resin film may be used. Examples of the resin film include polyimide resin films such as polyimide resin films, polyetherimide resin films, polyamideimide resin films, polyamide resin films such as polyamide resin films, and polyester resin films such as polyester resin films. . Among these, a polyimide resin film is mainly preferable. Thereby, especially an elasticity modulus and heat resistance can be improved.

以上のような第一絶縁層２１の厚みは、３０μｍ〜２００μｍが好ましく、より好ましくは４０μｍ〜１２０μｍである。   The thickness of the first insulating layer 21 as described above is preferably 30 μm to 200 μm, more preferably 40 μm to 120 μm.

また、第一絶縁層２１内部を、導電体２０が貫通している。導電体２０は、金属、たとえば、銅のビアであり、第一絶縁層２１の表裏面にそれぞれ設けられた第一回路層２２、第二回路層２４に接続されている。第一回路層２２、第二回路層２４は、ぞれぞれ、金属製の回路、たとえば、銅の回路である。
（第二絶縁層２３，第三絶縁層２５）
第二絶縁層２３は、第一回路層２２を被覆するとともに、第一回路層２２の一部の上方に位置する部分に開口が形成されている。さらにこの開口内には、第一回路層２２に接続された金属層２７が配置されている。 Further, the conductor 20 penetrates through the first insulating layer 21. The conductor 20 is a via made of metal, for example, copper, and is connected to a first circuit layer 22 and a second circuit layer 24 provided on the front and back surfaces of the first insulating layer 21, respectively. The first circuit layer 22 and the second circuit layer 24 are each a metal circuit, for example, a copper circuit.
(Second insulating layer 23, third insulating layer 25)
The second insulating layer 23 covers the first circuit layer 22, and an opening is formed in a portion located above a part of the first circuit layer 22. Further, a metal layer 27 connected to the first circuit layer 22 is disposed in the opening.

金属層２７の厚さは高速信号対応する場合は電気的信頼性の面から８５μｍ以下が好ましい。金属層２７は第一回路層２２側から順に、銅を含む金属層（ａ）２７１、ニッケルを含む金属層（ｂ）２７２、錫を含む金属層（ｃ）２７３がこの順に構成されている。   The thickness of the metal layer 27 is preferably 85 μm or less from the viewpoint of electrical reliability when the high-speed signal is supported. The metal layer 27 includes a metal layer (a) 271 containing copper, a metal layer (b) 272 containing nickel, and a metal layer (c) 273 containing tin in this order from the first circuit layer 22 side.

銅を含む金属層（ａ）２７１の厚さは０μｍ以上、５５μｍ以下であり、ニッケルを含む金属層（ｂ）２７２の厚さは０μｍ以上、１５μｍ以下であり、錫を含む金属層（ｃ）２７３の厚さは３μｍ以上、３０μｍ以下である。
また、錫を含む金属層（ｃ）２７３は、フラックス機能を有する化合物を含む樹脂層３に接触していてもよい。 The thickness of the metal layer (a) 271 containing copper is 0 μm or more and 55 μm or less, the thickness of the metal layer (b) 272 containing nickel is 0 μm or more and 15 μm or less, and the metal layer (c) containing tin The thickness of 273 is 3 μm or more and 30 μm or less.
Moreover, the metal layer (c) 273 containing tin may be in contact with the resin layer 3 containing a compound having a flux function.

錫を含む金属層（ｃ）２７３が３μｍ以上であれば、チップ側の金バンプとの接合時に十分に濡れ広がり、接続面積を確保し、信頼性を維持するために好ましい。また、錫を含む金属層（ｃ）２７３が３０μｍ以下であれば、狭ピッチ回路において絶縁信頼性が低下しないので好ましい。次に、ニッケルを含む金属層（ｂ）２７２の厚さが２μｍ以上であれば、半田接合時、錫を含む金属層（ｃ）２７３への銅の拡散を防ぐことができる。また、生産性の面からニッケルを含む金属層（ｂ）２７２の厚さは１５μｍ以下が好ましい。   If the metal layer (c) 273 containing tin is 3 μm or more, it is preferable in order to sufficiently wet and spread at the time of bonding with the gold bump on the chip side, to secure a connection area, and to maintain reliability. Moreover, it is preferable that the metal layer (c) 273 containing tin is 30 μm or less because the insulation reliability is not lowered in a narrow pitch circuit. Next, if the thickness of the metal layer (b) 272 containing nickel is 2 μm or more, the diffusion of copper to the metal layer (c) 273 containing tin can be prevented at the time of soldering. Further, from the viewpoint of productivity, the thickness of the metal layer (b) 272 containing nickel is preferably 15 μm or less.

銅を含む金属層（ａ）２７１の厚さは、第二絶縁層２３の厚さによって決めることができる。第二絶縁層２３の厚さとは、対応する第一回路層２２の面からの高さをいう。ニッケルを含む金属層（ｂ）２７２と錫を含む金属層（ｃ）２７３の厚さの合計が、第二絶縁層２３の厚さと同等であれば、銅を含む金属層（ａ）２７１は不要となる。一方、ニッケルを含む金属層（ｂ）２７２と錫を含む金属層（ｃ）２７３との厚さの合計よりも第二絶縁層２３の厚さが厚い場合には、上述の三層の金属層の厚さが第二絶縁層２３と略同じか突出するように銅を含む金属層（ａ）２７１を形成する。例えば、第二絶縁層２３の厚さが２０μｍの場合、ニッケルを含む金属層（ｂ）２７２の厚さが１０μｍ、錫を含む金属層（ｃ）２７３の厚さが１０μｍとなり、銅を含む金属層（ａ）２７１は不要となる。一方、第二絶縁層２３の厚さが、６０μｍの場合、ニッケルを含む金属層（ｂ）２７２の厚さを１５μｍ、錫を含む金属層（ｃ）２７３の厚さを１５μｍとしたとき、銅を含む金属層（ａ）２７１の厚さは３０μｍとなる。また、第二絶縁層２３の厚さが１５μｍの場合、ニッケルを含む金属層（ｂ）２７２の厚さを８μｍ、錫を含む金属層（ｃ）２７３の厚さを７μｍとしてもよいし、ニッケルを含む金属層（ｂ）２７２の厚さを３μｍ、錫を含む金属層（ｃ）２７３の厚さを７μｍ、銅を含む金属層（ａ）２７１の厚さを５μｍとしてもよい。以上のように第二絶縁層２３の厚さによって、銅を含む金属層（ａ）２７１の厚さと、ニッケルを含む金属層（ｂ）２７２の厚さを変えることにより、半導体装置の信頼性を向上させることができる。   The thickness of the metal layer (a) 271 containing copper can be determined by the thickness of the second insulating layer 23. The thickness of the second insulating layer 23 refers to the height from the surface of the corresponding first circuit layer 22. If the total thickness of the metal layer (b) 272 containing nickel and the metal layer (c) 273 containing tin is equal to the thickness of the second insulating layer 23, the metal layer (a) 271 containing copper is unnecessary. It becomes. On the other hand, when the thickness of the second insulating layer 23 is larger than the total thickness of the metal layer (b) 272 containing nickel and the metal layer (c) 273 containing tin, the above three metal layers The metal layer (a) 271 containing copper is formed so that the thickness of the metal layer (a) 271 is substantially the same as or protrudes from the second insulating layer 23. For example, when the thickness of the second insulating layer 23 is 20 μm, the thickness of the metal layer (b) 272 containing nickel is 10 μm, the thickness of the metal layer (c) 273 containing tin is 10 μm, and the metal containing copper The layer (a) 271 is not necessary. On the other hand, when the thickness of the second insulating layer 23 is 60 μm, the thickness of the metal layer (b) 272 containing nickel is 15 μm, and the thickness of the metal layer (c) 273 containing tin is 15 μm. The thickness of the metal layer (a) 271 containing 30 μm. When the thickness of the second insulating layer 23 is 15 μm, the thickness of the metal layer (b) 272 containing nickel may be 8 μm, the thickness of the metal layer (c) 273 containing tin may be 7 μm, The thickness of the metal layer (b) 272 containing 3 μm, the thickness of the metal layer (c) 273 containing tin 7 μm, and the thickness of the metal layer (a) 271 containing copper 5 μm may be used. As described above, the reliability of the semiconductor device is improved by changing the thickness of the metal layer (a) 271 containing copper and the thickness of the metal layer (b) 272 containing nickel depending on the thickness of the second insulating layer 23. Can be improved.

第三絶縁層２５は、第二回路層２４を被覆するとともに、第二回路層２４の一部の上方に位置する部分に開口が形成されている。さらにこの開口内には、第二回路層２４に接続された金属層２８が形成されている。金属層２８は、たとえば、金めっき層である。   The third insulating layer 25 covers the second circuit layer 24, and an opening is formed in a portion located above a part of the second circuit layer 24. Further, a metal layer 28 connected to the second circuit layer 24 is formed in the opening. The metal layer 28 is, for example, a gold plating layer.

第二および第三絶縁層２３、２４の線膨張係数を等しくすることで、第二絶縁層２３、第三絶縁層２５が対称に配置され、回路基板１の反りの発生が抑制されることとなる。   By equalizing the linear expansion coefficients of the second and third insulating layers 23 and 24, the second insulating layer 23 and the third insulating layer 25 are arranged symmetrically, and the occurrence of warping of the circuit board 1 is suppressed. Become.

また、第二絶縁層２３の厚み（Ｔ１）は、５μｍ以上、８５μｍ以下であり、第三絶縁層２５の厚み（Ｔ２）は、１０μｍ以上、１００μｍ以下であることが好ましい。   The thickness (T1) of the second insulating layer 23 is preferably 5 μm or more and 85 μm or less, and the thickness (T2) of the third insulating layer 25 is preferably 10 μm or more and 100 μm or less.

ここで、第二絶縁層２３の厚み（Ｔ１）と、第三絶縁層２５との厚み（Ｔ２）は同じであってもよいが、第二絶縁層２３の厚み（Ｔ１）と、第三絶縁層２５との厚み（Ｔ２）とが異なることが好ましい。第二絶縁層２３の厚み（Ｔ１）と、第三絶縁層２５との厚み（Ｔ２）の比であるＴ１／Ｔ２は、１以上であることが好ましい。   Here, the thickness (T1) of the second insulating layer 23 and the thickness (T2) of the third insulating layer 25 may be the same, but the thickness (T1) of the second insulating layer 23 and the third insulating layer 23 are the same. It is preferable that the thickness (T2) with the layer 25 is different. It is preferable that T1 / T2 which is the ratio of the thickness (T1) of the second insulating layer 23 and the thickness (T2) of the third insulating layer 25 is 1 or more.

Ｔ１／Ｔ２を１以上とすることで反り抑制という効果がある。   By setting T1 / T2 to 1 or more, there is an effect of suppressing warpage.

また、第一絶縁層２１の表裏上に設けられた第一回路層２２、第二回路層２４のパターンの違いや、第二絶縁層２３に形成された開口の割合、第三絶縁層２５に形成された開口の割合の違いにより、回路基板１に反りが生じることがある。   Further, the pattern difference between the first circuit layer 22 and the second circuit layer 24 provided on the front and back of the first insulating layer 21, the ratio of the openings formed in the second insulating layer 23, the third insulating layer 25 The circuit board 1 may be warped due to a difference in the ratio of the formed openings.

この反りの発生を抑制するために、第二絶縁層２３、第三絶縁層２５の厚みを異なるもの、特に、Ｔ１／Ｔ２を１以上、特に、異なる厚みとすることで、より、フラットな回路基板１を得ることができる。   In order to suppress the occurrence of the warp, the second insulating layer 23 and the third insulating layer 25 have different thicknesses, in particular, by setting T1 / T2 to 1 or more, particularly different thicknesses, a more flat circuit The substrate 1 can be obtained.

また、第二絶縁層２３、第三絶縁層２５の厚みは、第一絶縁層２１よりも薄く、第一絶縁層２１の厚みの１／１０以上であることが好ましい。このようにすることで、反り抑制という効果がある。   The thicknesses of the second insulating layer 23 and the third insulating layer 25 are preferably thinner than the first insulating layer 21 and 1/10 or more of the thickness of the first insulating layer 21. By doing in this way, there exists an effect of curvature suppression.

以上のような第二絶縁層２３、第三絶縁層２５は、プリプレグではなく、樹脂組成物からなるものであることが好ましい。第二絶縁層２３、第三絶縁層２５は、同じ材料で構成することができ、たとえば、エポキシ樹脂、硬化剤、無機充填材とする樹脂組成物で構成することができる。   The second insulating layer 23 and the third insulating layer 25 as described above are preferably made of a resin composition instead of a prepreg. The 2nd insulating layer 23 and the 3rd insulating layer 25 can be comprised with the same material, for example, can be comprised with the resin composition used as an epoxy resin, a hardening | curing agent, and an inorganic filler.

第二絶縁層２３の樹脂を構成する材料としては、例えば、熱硬化性樹脂と、硬化剤とを含んでいることが好ましい。熱硬化性樹脂としては、エポキシ樹脂、シアネート樹脂、フェノール樹脂などを単独あるいは複数組合わせて用いることができる。エポキシ樹脂としては、特に限定はされないが、例えば、積層板用として一般に使用されている、例えば、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、ビスフェノールＡＤ型エポキシ樹脂等のビスフェノール型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂等のノボラック型エポキシ樹脂、臭素化ビスフェノールＡ型エポキシ樹脂、臭素化フェノールノボラック型エポキシ樹脂等の臭素化型エポキシ樹脂、トリグリシジルイソシアネートなどの複素環式エポキシ樹脂のほか、脂環式型エポキシ樹脂、ビフェニル型エポキシ樹脂、ナフタレン型エポキシ樹脂、グリシジルエステル型エポキシ樹脂等が挙げられる。これらを単独または２種類以上組み合わせて使用することができる。   As a material constituting the resin of the second insulating layer 23, for example, a thermosetting resin and a curing agent are preferably included. As the thermosetting resin, an epoxy resin, a cyanate resin, a phenol resin, or the like can be used alone or in combination. Although it does not specifically limit as an epoxy resin, For example, bisphenol type epoxy resins, such as a bisphenol A type epoxy resin, a bisphenol F type epoxy resin, a bisphenol AD type epoxy resin, etc. which are generally used for laminated boards, for example Novolak epoxy resins, novolak epoxy resins such as cresol novolac epoxy resins, brominated epoxy resins such as brominated bisphenol A epoxy resins, brominated phenol novolac epoxy resins, and heterocyclic epoxy resins such as triglycidyl isocyanate In addition, alicyclic epoxy resin, biphenyl type epoxy resin, naphthalene type epoxy resin, glycidyl ester type epoxy resin and the like can be mentioned. These can be used alone or in combination of two or more.

前記シアネート樹脂としては、例えばハロゲン化シアン化合物とフェノール類とを反応させ、必要に応じて加熱等の方法でプレポリマー化することにより得ることができる。具体的には、ノボラック型シアネート樹脂、ビスフェノールＡ型シアネート樹脂、ビスフェノールＥ型シアネート樹脂、テトラメチルビスフェノールＦ型シアネート樹脂等のビスフェノール型シアネート樹脂等を挙げることができる。これらの中でもノボラック型シアネート樹脂が好ましい。これにより、架橋密度増加による耐熱性向上と、樹脂組成物等の難燃性を向上することができる。   The cyanate resin can be obtained by, for example, reacting a halogenated cyanide compound with a phenol and prepolymerizing it by a method such as heating as necessary. Specific examples include bisphenol type cyanate resins such as novolac type cyanate resin, bisphenol A type cyanate resin, bisphenol E type cyanate resin, and tetramethylbisphenol F type cyanate resin. Among these, novolac type cyanate resin is preferable. Thereby, the heat resistance improvement by a crosslinking density increase and flame retardance, such as a resin composition, can be improved.

硬化剤としては、特に限定はされないが、例えば、積層板用として一般に使用されている、アミノ基を有する硬化剤であって、メタフェニレンジアミン、パラフェニレンジアミン、パラキシレンジアミン、４，４’−ジアミノジフェニルメタン、４，４’−ジアミノジフェニルプロパン、４，４’−ジアミノジフェニルエーテル、４，４’−ジアミノジフェニルスルフォン、４，４’−ジアミノジシクロヘキサン、ビス（４−アミノフェニル）フェニルメタン、１，５−ジアミノナフタレン、メタキシリレンジアミン、パラキシレンナフタレン、１，１−ビス（４−アミノフェニル）シクロヘキサン、ジシアンジアミド、ジアミノジエチルジメチルフェニルメタンなどが用いられる。耐熱性、硬化性等の点で、好ましい硬化剤は、４，４’−ジアミノジフェニルメタン、ジシアンジアミド、ジアミノジエチルジメチルフェニルメタンである。これらのうち何種類かを併用しても良い。   Although it does not specifically limit as a hardening | curing agent, For example, it is a hardening | curing agent which has an amino group generally used for laminated boards, Comprising: Metaphenylenediamine, paraphenylenediamine, paraxylenediamine, 4,4'- Diaminodiphenylmethane, 4,4′-diaminodiphenylpropane, 4,4′-diaminodiphenyl ether, 4,4′-diaminodiphenylsulfone, 4,4′-diaminodicyclohexane, bis (4-aminophenyl) phenylmethane, 1, 5-Diaminonaphthalene, metaxylylenediamine, paraxylene naphthalene, 1,1-bis (4-aminophenyl) cyclohexane, dicyandiamide, diaminodiethyldimethylphenylmethane, and the like are used. In view of heat resistance, curability and the like, preferred curing agents are 4,4'-diaminodiphenylmethane, dicyandiamide, and diaminodiethyldimethylphenylmethane. Some of these may be used in combination.

また、第二絶縁層２３には無機充填材を含んでいてもよい。例えばタルク、焼成クレー、未焼成クレー、マイカ、ガラス等のケイ酸塩、酸化チタン、アルミナ、シリカ、溶融シリカ等の酸化物、炭酸カルシウム、炭酸マグネシウム、ハイドロタルサイト等の炭酸塩、水酸化アルミニウム、水酸化マグネシウム、水酸化カルシウム等の水酸化物、硫酸バリウム、硫酸カルシウム、亜硫酸カルシウム等の硫酸塩または亜硫酸塩、ホウ酸亜鉛、メタホウ酸バリウム、ホウ酸アルミニウム、ホウ酸カルシウム、ホウ酸ナトリウム等のホウ酸塩、窒化アルミニウム、窒化ホウ素、窒化ケイ素、窒化炭素等の窒化物、チタン酸ストロンチウム、チタン酸バリウム等のチタン酸塩等を挙げることができる。無機充填材として、これらの中の１種類を単独で用いることもできるし、２種類以上を併用したりすることもできる。これらの中でも特に、水酸化アルミニウム、シリカが好ましく、溶融シリカ（特に球状溶融シリカ）が低熱膨張性に優れる点で好ましい。その形状は破砕状、球状があるが、基材への含浸性を確保するために樹脂組成物の溶融粘度を下げるには球状シリカを使う等、その目的にあわせた使用方法が採用される。無機充填材の含有量は、樹脂成分１００重量部に対して、３０重量部以上、７０重量部以下であることが好ましく、さらに好ましくは４０重量部以上、６０重量部以下である。   The second insulating layer 23 may contain an inorganic filler. For example, silicates such as talc, calcined clay, unfired clay, mica and glass, oxides such as titanium oxide, alumina, silica and fused silica, carbonates such as calcium carbonate, magnesium carbonate and hydrotalcite, aluminum hydroxide , Hydroxides such as magnesium hydroxide, calcium hydroxide, sulfates or sulfites such as barium sulfate, calcium sulfate, calcium sulfite, zinc borate, barium metaborate, aluminum borate, calcium borate, sodium borate, etc. Borate, aluminum nitride, boron nitride, silicon nitride, carbon nitride and other nitrides, strontium titanate, titanates such as barium titanate, and the like. As the inorganic filler, one of these can be used alone, or two or more can be used in combination. Among these, aluminum hydroxide and silica are particularly preferable, and fused silica (particularly spherical fused silica) is preferable in terms of excellent low thermal expansion. The shape is crushed and spherical, but in order to reduce the melt viscosity of the resin composition in order to ensure the impregnation property to the substrate, a usage method suitable for the purpose is used such as using spherical silica. The content of the inorganic filler is preferably 30 to 70 parts by weight, more preferably 40 to 60 parts by weight with respect to 100 parts by weight of the resin component.

無機充填材の平均粒子径は、特に限定されないが、０．０５〜１０μｍが好ましく、特に０．３〜５μｍが好ましい。この平均粒子径は、例えば粒度分布計（ＨＯＲＩＢＡ製、ＬＡ−５００）により測定することができる。   The average particle diameter of the inorganic filler is not particularly limited, but is preferably 0.05 to 10 μm, and particularly preferably 0.3 to 5 μm. This average particle diameter can be measured, for example, by a particle size distribution meter (manufactured by HORIBA, LA-500).

また、前記無機充填材は、特に限定されないが、平均粒子径が単分散の無機充填材を用いることもできるし、平均粒子径が多分散の無機充填材を用いることができる。さらに平均粒子径が単分散及び／または、多分散の無機充填材を１種類または２種類以上併用したりすることもできる。   Further, the inorganic filler is not particularly limited, but an inorganic filler having a monodispersed average particle diameter can be used, and an inorganic filler having a polydispersed average particle diameter can be used. Furthermore, one or two or more inorganic fillers having an average particle size of monodisperse and / or polydisperse can be used in combination.

第三絶縁層２５としては、上述の第二絶縁層２３に用いた樹脂を構成する材料とすることができる。第二絶縁層２３と第三絶縁層２５は同一の構成であってもよいし異なっていてもよい。さらに、第一絶縁層２１とは、無機繊維基材を含まない以外は同一の樹脂構成であってもよいし異なっていてもよい。ここで、第一絶縁層２１は、無機繊維基材に絶縁性の樹脂を含浸させて得られたものであってもよい。   As the third insulating layer 25, a material constituting the resin used for the second insulating layer 23 described above can be used. The second insulating layer 23 and the third insulating layer 25 may have the same configuration or may be different. Further, the first insulating layer 21 may have the same resin configuration or may be different except that the inorganic fiber base material is not included. Here, the first insulating layer 21 may be obtained by impregnating an inorganic fiber base material with an insulating resin.

また、第二絶縁層２３、第三絶縁層２５は、たとえば、（ｈ）感光性樹脂を必須成分とする樹脂組成物で構成することができる。   Moreover, the 2nd insulating layer 23 and the 3rd insulating layer 25 can be comprised with the resin composition which has (h) photosensitive resin as an essential component, for example.

このような樹脂組成物を使用することで、露光及び現像により、第二絶縁層２３、第三絶縁層２５の開口を容易にパターニングすることが出来る。   By using such a resin composition, the openings of the second insulating layer 23 and the third insulating layer 25 can be easily patterned by exposure and development.

前記（ｈ）感光性樹脂は、特に限定されるものではなく、公知の感光性樹脂組成物を用いて形成することができる。前記（ｈ）感光性樹脂は、ネガ型、ポジ型のどちらであっても良い。   The (h) photosensitive resin is not particularly limited, and can be formed using a known photosensitive resin composition. The (h) photosensitive resin may be either a negative type or a positive type.

前記（ｈ）感光性樹脂は、たとえば、アクリル樹脂などを含み、エポキシ変性アクリル樹脂などを用いることができる。また、アクリル樹脂などの光硬化性樹脂の他に、エポキシ樹脂などの熱硬化性樹脂などを加えても良い。   The (h) photosensitive resin includes, for example, an acrylic resin, and an epoxy-modified acrylic resin can be used. In addition to a photocurable resin such as an acrylic resin, a thermosetting resin such as an epoxy resin may be added.

前記（ｈ）感光性樹脂は、重合開始剤、増感剤、レベリング剤などを含んでも良い。また、シリカなどの充填剤を含んでいても良い。このとき、粒径サイズは、露光時の光の波長よりも小さいものが好ましい。   The (h) photosensitive resin may contain a polymerization initiator, a sensitizer, a leveling agent and the like. Moreover, fillers, such as a silica, may be included. At this time, the particle size is preferably smaller than the wavelength of light at the time of exposure.

また、前記（ｈ）感光性樹脂としては、液状タイプ、または、フィルムタイプなどの形態を用いることができる。第一回路層２２、第二回路層２４への被覆性を考慮した場合、フィルムタイプを用いることが好ましい。   Moreover, as said (h) photosensitive resin, forms, such as a liquid type or a film type, can be used. In consideration of the coverage to the first circuit layer 22 and the second circuit layer 24, it is preferable to use a film type.

液状タイプの場合は、スクリーン印刷法、コータ法など形成することができる。また、両面に回路層（第一回路層２２、第二回路層２４）が形成されている場合は、両面回路基板を液状レジスト中に浸漬することにより、両面同時に第二絶縁層２３および第三絶縁層２５を形成することも可能である。   In the case of the liquid type, a screen printing method, a coater method, or the like can be formed. When circuit layers (first circuit layer 22 and second circuit layer 24) are formed on both surfaces, the second insulating layer 23 and the third surface are simultaneously formed on both surfaces by immersing the double-sided circuit board in a liquid resist. It is also possible to form the insulating layer 25.

フィルムタイプの場合は、真空ラミネータなどを用いて形成することが出来る。
（フラックス機能を有する化合物を含む樹脂層３）
フラックス機能を有する化合物を含む樹脂層３は、第二絶縁層２３を被覆するとともに、金属層２７上に、錫を含む金属層（ｃ）２７３に接触して設けられていてもよい。 In the case of a film type, it can be formed using a vacuum laminator or the like.
(Resin layer 3 containing a compound having a flux function)
The resin layer 3 containing a compound having a flux function may be provided on the metal layer 27 in contact with the metal layer (c) 273 containing tin while covering the second insulating layer 23.

フラックス機能を有する化合物を含む樹脂層３は、硬化後の室温における弾性率が０．５ＧＰａ以上、１５ＧＰａ以下であることが好ましい。なお、弾性率は、以下の方法で測定したものである。   The resin layer 3 containing a compound having a flux function preferably has an elastic modulus at room temperature after curing of 0.5 GPa or more and 15 GPa or less. The elastic modulus is measured by the following method.

幅４ｍｍ×長さ４５ｍｍ×厚み０．１ｍｍのフィルム状の試験片を１８０℃、１時間で硬化させて作製させた後、周波数１０Ｈｚ、３℃／分の昇温速度で０℃〜３００℃の温度範囲で、動的粘弾性測定機（ＤＭＡ）にて引っ張りモードで計測し、２５℃における弾性率を算出した。   A film-shaped test piece having a width of 4 mm, a length of 45 mm and a thickness of 0.1 mm was prepared by curing at 180 ° C. for 1 hour, and then at a frequency of 10 Hz and a temperature increase rate of 3 ° C./min. The elastic modulus at 25 ° C. was calculated by measuring in a tensile mode with a dynamic viscoelasticity measuring device (DMA) in the temperature range.

フラックス機能を有する化合物を含む樹脂層３は、たとえば、１核体から３核体の合計の含有量が、３０〜７０％であるフェノール系ノボラック樹脂と、２５℃で液状であるエポキシ樹脂と、フラックス機能を有する化合物と、成膜性樹脂と、を含むものであることが好ましい。   The resin layer 3 containing the compound having a flux function is, for example, a phenol-based novolak resin having a total content of 30 to 70% of a mononuclear body to a trinuclear body, an epoxy resin that is liquid at 25 ° C., and It is preferable to include a compound having a flux function and a film-forming resin.

前記フェノール系ノボラック樹脂としては、フェノールノボラック樹脂、クレゾールノボラック樹脂、ビスフェノールＡ型ノボラック樹脂、ビスフェノールＦ型ノボラック樹脂、ビスフェノールＡＦ型ノボラック樹脂等が挙げられるが、接着フィルムの硬化物のガラス転移温度を効果的に高めることができ、また、アウトガスとなるフェノール系ノボラック樹脂の量を低減することができる、フェノールノボラッック樹脂、クレゾールノボラック樹脂が好ましい。   Examples of the phenolic novolak resin include phenol novolak resin, cresol novolak resin, bisphenol A type novolak resin, bisphenol F type novolak resin, bisphenol AF type novolak resin, etc., which are effective for the glass transition temperature of the cured adhesive film. Phenol novolac resins and cresol novolac resins, which can increase the amount of phenolic novolac resins that can be increased and reduce the amount of phenolic novolak resins that are outgasses, are preferred.

前記フェノール系ノボラック樹脂の含有量は、特に限定されるわけではないが、樹脂層３中に３〜３０重量％含まれることが好ましく、５〜２５重量％含まれることが特に好ましい。前記フェノール系ノボラック樹脂の含有量を上記範囲とすることで、樹脂層３の硬化物のガラス転移温度を効果的に高めること、さらに、アウトガスとなるフェノール系ノボラック樹脂の量を効果的に低減することを両立することができる。   The content of the phenolic novolak resin is not particularly limited, but is preferably 3 to 30% by weight, and particularly preferably 5 to 25% by weight in the resin layer 3. By making content of the said phenol type novolak resin into the said range, the glass transition temperature of the hardened | cured material of the resin layer 3 is raised effectively, Furthermore, the quantity of the phenol type novolak resin used as an outgas is reduced effectively. Can be compatible.

前記１核体から３核体の合計の含有量が３０％より小さい（４核体以上の合計の含有量が７０％以上）場合、２５℃で液状であるエポキシ樹脂との反応性が低下し、樹脂層３の硬化物中に未反応のフェノール系ノボラック樹脂が残留するため、樹脂層３が脆くなり作業性が低下してしまうといった問題が生じる。また、前記１核体から３核体の合計の含有量が７０％より大きい（４核体以上の合計の含有量が３０％以下）場合、樹脂層３を硬化させる際のアウトガス量が増大する可能性がある。さらに、樹脂層３のタック性が大きくなり過ぎる可能性もある。   When the total content of mononuclear to trinuclear is less than 30% (total content of four or more nuclei is 70% or more), the reactivity with the epoxy resin that is liquid at 25 ° C. decreases. Since the unreacted phenolic novolak resin remains in the cured product of the resin layer 3, there arises a problem that the resin layer 3 becomes brittle and the workability is lowered. In addition, when the total content of the mononuclear body to the trinuclear body is greater than 70% (the total content of the 4-nuclear body or more is 30% or less), the outgas amount when the resin layer 3 is cured increases. there is a possibility. Further, the tackiness of the resin layer 3 may become too large.

前記フェノール系ノボラック樹脂中の２核体と３核体の合計の含有量は、特に限定されるわけではないが、３０〜７０％であることが好ましい。上記下限値以上とすることで、樹脂層３を硬化させる際のアウトガス量が増大してしまうことを抑制できる。また。上記上限値以下とすることで、樹脂層３の柔軟性と屈曲性をより効果的に確保することができる。   The total content of the binuclear body and the trinuclear body in the phenolic novolak resin is not particularly limited, but is preferably 30 to 70%. By setting it as the said lower limit or more, it can suppress that the amount of outgas at the time of hardening the resin layer 3 will increase. Also. By setting the upper limit value or less, the flexibility and flexibility of the resin layer 3 can be more effectively ensured.

前記フェノール系ノボラック樹脂中の１核体の含有量は、特に限定されるわけではないが、樹脂層３中に１％以下であることが好ましく、０．８％以下であることが特に好ましい。前記１核体の含有量を、上記範囲とすることで、樹脂層３を硬化する際のアウトガス量を低減することができる。   The content of the mononuclear substance in the phenolic novolak resin is not particularly limited, but is preferably 1% or less in the resin layer 3 and particularly preferably 0.8% or less. By setting the content of the mononuclear body within the above range, the outgas amount when the resin layer 3 is cured can be reduced.

前記フェノール系ノボラック樹脂の重量平均分子量は、特に限定されるわけではないが、３００〜１，５００であることが好ましく、４００〜１４００であることが特に好ましい。上記下限値以上とすることで、樹脂層３を硬化させる際のアウトガス量を抑制できる。また。上記上限値以下とすることで、樹脂層３の柔軟性と屈曲性をより効果的に確保することができる。   The weight average molecular weight of the phenolic novolak resin is not particularly limited, but is preferably 300 to 1,500, and particularly preferably 400 to 1400. By setting it to the above lower limit or more, the outgas amount when the resin layer 3 is cured can be suppressed. Also. By setting the upper limit value or less, the flexibility and flexibility of the resin layer 3 can be more effectively ensured.

フラックス機能を有する化合物を含む樹脂層３は、２５℃で液状であるエポキシ樹脂を含むことが好ましい。これにより、樹脂層３に柔軟性および屈曲性を付与することができる。   The resin layer 3 containing a compound having a flux function preferably contains an epoxy resin that is liquid at 25 ° C. Thereby, flexibility and flexibility can be imparted to the resin layer 3.

２５℃で液状であるエポキシ樹脂としては、特に限定されるものではないが、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、グリシジルアミン型エポキシ樹脂、グリシジルエステル型エポキシ樹脂等が挙げられる。これらの中でも、接着フィルムの支持体および被着体に対する密着性、さらに、接着フィルム硬化後の機械特性に優れる、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂が好ましい。   The epoxy resin that is liquid at 25 ° C. is not particularly limited, and examples thereof include bisphenol A type epoxy resins, bisphenol F type epoxy resins, glycidyl amine type epoxy resins, and glycidyl ester type epoxy resins. Among these, bisphenol A-type epoxy resins and bisphenol F-type epoxy resins, which are excellent in adhesion of the adhesive film to the support and adherend, and excellent in mechanical properties after the adhesive film is cured, are preferable.

また、前記２５℃で液状であるエポキシ樹脂としては、より好ましくは、２５℃における粘度が、５００〜５０，０００ｍＰａ・ｓであるもの、さらに好ましくは、８００〜４０，０００ｍＰａ・ｓであるものが挙げられる。２５℃における粘度を上記下限値以上とすることで、樹脂層３の柔軟性と屈曲性を確保することができる。また、２５℃における粘度を上記上限値以下とすることで樹脂層３のタック性が強くなり、ハンドリング性が低下することを防止することができる。   The epoxy resin that is liquid at 25 ° C. is more preferably one having a viscosity at 25 ° C. of 500 to 50,000 mPa · s, more preferably 800 to 40,000 mPa · s. Can be mentioned. By setting the viscosity at 25 ° C. to the above lower limit or more, the flexibility and flexibility of the resin layer 3 can be ensured. Moreover, the tack property of the resin layer 3 becomes strong by making the viscosity in 25 degreeC below the said upper limit, and it can prevent that handling property falls.

また、前記２５℃で液状であるエポキシ樹脂の含有量は、特に限定されるものではないが、１０〜８０重量％が好ましく、１５〜７５重量％が特に好ましい。上記下限値以上とすることで、樹脂層３の柔軟性と屈曲性をより効果的に発現させることができる。また、上記上限値以下とすることで、樹脂層３のタック性が強くなり、ハンドリング性が低下することをより効果的に防止することができる。   Further, the content of the epoxy resin that is liquid at 25 ° C. is not particularly limited, but is preferably 10 to 80% by weight, and particularly preferably 15 to 75% by weight. By setting it as the said lower limit or more, the softness | flexibility and flexibility of the resin layer 3 can be expressed more effectively. Moreover, by setting it as the said upper limit or less, the tack property of the resin layer 3 becomes strong and it can prevent more effectively that handling property falls.

フラックス機能を有する化合物としては、半田表面の酸化膜を除去する働きがあれば、特に限定されるものではないが、カルボキシル基又はフェノール性水酸基のいずれか、あるいは、カルボキシル基及びフェノール水酸基の両方を備える化合物が好ましい。   The compound having a flux function is not particularly limited as long as it has a function of removing an oxide film on the solder surface. However, either a carboxyl group or a phenolic hydroxyl group, or both a carboxyl group and a phenol hydroxyl group are used. The compound provided is preferred.

フラックス機能を有する化合物の配合量は、１〜３０重量％が好ましく、３〜２０重量％が特に好ましい。フラックス機能を有する化合物の配合量が、上記範囲であることにより、フラックス活性を向上させることができるとともに、樹脂層３を硬化した際に、未反応の化合物が残存するのを防止することができ、耐マイグレーション性を向上することができる。   The amount of the compound having a flux function is preferably 1 to 30% by weight, particularly preferably 3 to 20% by weight. When the compounding amount of the compound having the flux function is within the above range, the flux activity can be improved and the remaining of the unreacted compound can be prevented when the resin layer 3 is cured. Migration resistance can be improved.

また、エポキシ樹脂の硬化剤として作用する化合物の中には、フラックス機能を有する化合物が存在する（以下、このような化合物を、フラックス活性硬化剤とも記載する。）。例えば、エポキシ樹脂の硬化剤として作用する、脂肪族ジカルボン酸、芳香族ジカルボン酸等は、フラックス作用も有している。このような、フラックスとしても作用し、エポキシ樹脂の硬化剤としても作用するようなフラックス活性硬化剤を、好適に用いることができる。   Further, among the compounds that act as curing agents for epoxy resins, there are compounds having a flux function (hereinafter, such compounds are also referred to as flux active curing agents). For example, aliphatic dicarboxylic acids, aromatic dicarboxylic acids and the like that act as curing agents for epoxy resins also have a flux action. Such a flux active curing agent that acts as a flux and also acts as a curing agent for an epoxy resin can be suitably used.

なお、カルボキシル基を備えるフラックス機能を有する化合物とは、分子中にカルボキシル基が１つ以上存在するものをいい、液状であっても固体であってもよい。また、フェノール性水酸基を備えるフラックス機能を有する化合物とは、分子中にフェノール性水酸基が１つ以上存在するものをいい、液状であっても固体であってもよい。また、カルボキシル基及びフェノール性水酸基を備えるフラックス機能を有する化合物とは、分子中にカルボキシル基及びフェノール性水酸基がそれぞれ１つ以上存在するものをいい、液状であっても固体であってもよい。   In addition, the compound having a flux function having a carboxyl group refers to a compound having one or more carboxyl groups in the molecule, and may be liquid or solid. Further, the compound having a flux function having a phenolic hydroxyl group means a compound having one or more phenolic hydroxyl groups in the molecule, and may be liquid or solid. Further, the compound having a flux function including a carboxyl group and a phenolic hydroxyl group means a compound having one or more carboxyl groups and phenolic hydroxyl groups in the molecule, and may be liquid or solid.

これらのうち、カルボキシル基を備えるフラックス機能を有する化合物としては、脂肪族酸無水物、脂環式酸無水物、芳香族酸無水物、脂肪族カルボン酸、芳香族カルボン酸等が挙げられる。   Among these, examples of the compound having a flux function having a carboxyl group include aliphatic acid anhydrides, alicyclic acid anhydrides, aromatic acid anhydrides, aliphatic carboxylic acids, and aromatic carboxylic acids.

前記カルボキシル基を備えるフラックス機能を有する化合物に係る脂肪族酸無水物としては、無水コハク酸、ポリアジピン酸無水物、ポリアゼライン酸無水物、ポリセバシン酸無水物等が挙げられる。   Examples of the aliphatic acid anhydride related to the compound having a flux function having a carboxyl group include succinic anhydride, polyadipic acid anhydride, polyazeline acid anhydride, and polysebacic acid anhydride.

前記カルボキシル基を備えるフラックス機能を有する化合物に係る脂環式酸無水物としては、メチルテトラヒドロ無水フタル酸、メチルヘキサヒドロ無水フタル酸、無水メチルハイミック酸、ヘキサヒドロ無水フタル酸、テトラヒドロ無水フタル酸、トリアルキルテトラヒドロ無水フタル酸、メチルシクロヘキセンジカルボン酸無水物等が挙げられる。   Examples of the alicyclic acid anhydride related to the compound having a flux function with a carboxyl group include methyltetrahydrophthalic anhydride, methylhexahydrophthalic anhydride, methylhymic anhydride, hexahydrophthalic anhydride, tetrahydrophthalic anhydride, Examples thereof include trialkyltetrahydrophthalic anhydride, methylcyclohexene dicarboxylic acid anhydride and the like.

前記カルボキシル基を備えるフラックス機能を有する化合物に係る芳香族酸無水物としては、無水フタル酸、無水トリメリット酸、無水ピロメリット酸、ベンゾフェノンテトラカルボン酸無水物、エチレングリコールビストリメリテート、グリセロールトリストリメリテート等が挙げられる。   Examples of the aromatic acid anhydride related to the compound having a flux function having a carboxyl group include phthalic anhydride, trimellitic anhydride, pyromellitic anhydride, benzophenonetetracarboxylic anhydride, ethylene glycol bistrimellitate, glycerol tristritriate. Examples include meritate.

前記カルボキシル基を備えるフラックス機能を有する化合物に係る脂肪族カルボン酸としては、下記一般式（１）で示される化合物や、蟻酸、酢酸、プロピオン酸、酪酸、吉草酸、ピバル酸カプロン酸、カプリル酸、ラウリン酸、ミリスチン酸、パルミチン酸、ステアリン酸、アクリル酸、メタクリル酸、クロトン酸、オレイン酸、フマル酸、マレイン酸、シュウ酸、マロン酸、琥珀酸等が挙げられる。   Examples of the aliphatic carboxylic acid related to the compound having a flux function having a carboxyl group include the compound represented by the following general formula (1), formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid pivalate, and caprylic acid. , Lauric acid, myristic acid, palmitic acid, stearic acid, acrylic acid, methacrylic acid, crotonic acid, oleic acid, fumaric acid, maleic acid, oxalic acid, malonic acid, oxalic acid and the like.

ＨＯＯＣ−（ＣＨ２）ｎ−ＣＯＯＨ （１）
（式（１）中、ｎは、１以上２０以下の整数を表す。）
前記カルボキシル基を備えるフラックス機能を有する化合物に係る芳香族カルボン酸としては、安息香酸、フタル酸、イソフタル酸、テレフタル酸、ヘミメリット酸、トリメリット酸、トリメシン酸、メロファン酸、プレーニト酸、ピロメリット酸、メリット酸、トリイル酸、キシリル酸、ヘメリト酸、メシチレン酸、プレーニチル酸、トルイル酸、ケイ皮酸、サリチル酸、２，３−ジヒドロキシ安息香酸、２，４−ジヒドロキシ安息香酸、ゲンチジン酸（２，５−ジヒドロキシ安息香酸）、２，６−ジヒドロキシ安息香酸、３，５−ジヒドロキシ安息香酸、浸食子酸（３，４，５−トリヒドロキシ安息香酸）、１，４−ジヒドロキシ−２−ナフトエ酸、３，５−ジヒドロキシ−２−ナフトエ酸等のナフトエ酸誘導体、フェノールフタリン、ジフェノール酸等が挙げられる。 HOOC- (CH 2) n -COOH ( 1)
(In formula (1), n represents an integer of 1 or more and 20 or less.)
Examples of the aromatic carboxylic acid related to the compound having a flux function having a carboxyl group include benzoic acid, phthalic acid, isophthalic acid, terephthalic acid, hemimellitic acid, trimellitic acid, trimesic acid, merophanic acid, planitic acid, pyromellitic acid. Acid, melicic acid, triylic acid, xylic acid, hemelic acid, mesitylene acid, planicylic acid, toluic acid, cinnamic acid, salicylic acid, 2,3-dihydroxybenzoic acid, 2,4-dihydroxybenzoic acid, gentisic acid (2, 5-dihydroxybenzoic acid), 2,6-dihydroxybenzoic acid, 3,5-dihydroxybenzoic acid, gallic acid (3,4,5-trihydroxybenzoic acid), 1,4-dihydroxy-2-naphthoic acid, Naphthoic acid derivatives such as 3,5-dihydroxy-2-naphthoic acid, phenolphthaline, Such as phenolic acids and the like.

これらの前記カルボキシル基を備えるフラックス機能を有する化合物のうち、フラックス機能を有する化合物が有する活性度、樹脂層３の硬化時におけるアウトガスの発生量、及び硬化後の樹脂層３の弾性率やガラス転移温度等のバランスが良い点で、前記一般式（１）で示される化合物が好ましい。そして、前記一般式（１）で示される化合物のうち、式（１）中のｎが３〜１０である化合物が、硬化後の樹脂層３における弾性率が増加するのを抑制することができるとともに、接着性を向上させることができる点で、特に好ましい。   Among these compounds having a flux function having the carboxyl group, the activity of the compound having the flux function, the amount of outgas generated when the resin layer 3 is cured, and the elastic modulus and glass transition of the resin layer 3 after curing. The compound represented by the general formula (1) is preferable in terms of a good balance of temperature and the like. And among the compounds represented by the general formula (1), the compound in which n in the formula (1) is 3 to 10 can suppress an increase in the elastic modulus in the resin layer 3 after curing. In addition, it is particularly preferable in that the adhesiveness can be improved.

前記一般式（１）で示される化合物のうち、式（１）中のｎが３〜１０である化合物としては、例えば、ｎ＝３のグルタル酸（ＨＯＯＣ−（ＣＨ２）３−ＣＯＯＨ）、ｎ＝４のアジピン酸（ＨＯＯＣ−（ＣＨ２）４−ＣＯＯＨ）、ｎ＝５のピメリン酸（ＨＯＯＣ−（ＣＨ２）５−ＣＯＯＨ）、ｎ＝８のセバシン酸（ＨＯＯＣ−（ＣＨ２）８−ＣＯＯＨ）及びｎ＝１０のＨＯＯＣ−（ＣＨ２）１０−ＣＯＯＨ−等が挙げられる。 Among the compounds represented by the general formula (1), as the compound in which n in the formula (1) is 3 to 10, for example, n = 3 glutaric acid (HOOC— (CH 2 ) 3 —COOH), n = 4 adipic acid (HOOC— (CH 2 ) 4 —COOH), n = 5 pimelic acid (HOOC— (CH 2 ) 5 —COOH), n = 8 sebacic acid (HOOC— (CH 2 ) 8 -COOH) and of n = 10 HOOC- (CH 2) 10 -COOH- , and the like.

前記フェノール性水酸基を備えるフラックス機能を有する化合物としては、フェノール類が挙げられ、具体的には、例えば、フェノール、ｏ−クレゾール、２，６−キシレノール、ｐ−クレゾール、ｍ−クレゾール、ｏ−エチルフェノール、２，４−キシレノール、２，５キシレノール、ｍ−エチルフェノール、２，３−キシレノール、メジトール、３，５−キシレノール、ｐ−ターシャリブチルフェノール、カテコール、ｐ−ターシャリアミルフェノール、レゾルシノール、ｐ−オクチルフェノール、ｐ−フェニルフェノール、ビスフェノールＡ、ビスフェノールＦ、ビスフェノールＡＦ、ビフェノール、ジアリルビスフェノールＦ、ジアリルビスフェノールＡ、トリスフェノール、テトラキスフェノール等のフェノール性水酸基を含有するモノマー類等が挙げられる。   Examples of the compound having a flux function having a phenolic hydroxyl group include phenols, and specifically, for example, phenol, o-cresol, 2,6-xylenol, p-cresol, m-cresol, o-ethyl. Phenol, 2,4-xylenol, 2,5 xylenol, m-ethylphenol, 2,3-xylenol, meditol, 3,5-xylenol, p-tertiarybutylphenol, catechol, p-tertiaryamylphenol, resorcinol, p -Contains phenolic hydroxyl groups such as octylphenol, p-phenylphenol, bisphenol A, bisphenol F, bisphenol AF, biphenol, diallyl bisphenol F, diallyl bisphenol A, trisphenol, tetrakisphenol Monomers, and the like.

上述したようなカルボキシル基又はフェノール水酸基のいずれか、あるいは、カルボキシル基及びフェノール水酸基の両方を備える化合物は、エポキシ樹脂との反応で三次元的に取り込まれる。   A compound having either a carboxyl group or a phenol hydroxyl group as described above, or a compound having both a carboxyl group and a phenol hydroxyl group is incorporated three-dimensionally by reaction with an epoxy resin.

そのため、硬化後のエポキシ樹脂の三次元的なネットワークの形成を向上させるという観点からは、フラックス機能を有する化合物としては、フラックス作用を有し且つエポキシ樹脂の硬化剤として作用するフラックス活性硬化剤が好ましい。フラックス活性硬化剤としては、例えば、１分子中に、エポキシ樹脂に付加することができる２つ以上のフェノール性水酸基と、フラックス作用（還元作用）を示す芳香族に直接結合した１つ以上のカルボキシル基とを備える化合物が挙げられる。このようなフラックス活性硬化剤としては、２，３−ジヒドロキシ安息香酸、２，４−ジヒドロキシ安息香酸、ゲンチジン酸（２，５−ジヒドロキシ安息香酸）、２，６−ジヒドロキシ安息香酸、３，４−ジヒドロキシ安息香酸、没食子酸（３，４，５−トリヒドロキシ安息香酸）等の安息香酸誘導体；１，４−ジヒドロキシ−２−ナフトエ酸、３，５−ジヒドロキシ−２−ナフトエ酸、３，７−ジヒドロキシ−２−ナフトエ酸等のナフトエ酸誘導体；フェノールフタリン；及びジフェノール酸等が挙げられ、これらは１種単独又は２種以上を組み合わせでもよい。   Therefore, from the viewpoint of improving the formation of the three-dimensional network of the epoxy resin after curing, as the compound having a flux function, there is a flux active curing agent that has a flux action and acts as a curing agent for the epoxy resin. preferable. Examples of the flux active curing agent include, in one molecule, two or more phenolic hydroxyl groups that can be added to an epoxy resin, and one or more carboxyls directly bonded to an aromatic group that exhibits a flux action (reduction action). And a compound having a group. Such flux active curing agents include 2,3-dihydroxybenzoic acid, 2,4-dihydroxybenzoic acid, gentisic acid (2,5-dihydroxybenzoic acid), 2,6-dihydroxybenzoic acid, 3,4- Benzoic acid derivatives such as dihydroxybenzoic acid and gallic acid (3,4,5-trihydroxybenzoic acid); 1,4-dihydroxy-2-naphthoic acid, 3,5-dihydroxy-2-naphthoic acid, 3,7- Examples thereof include naphthoic acid derivatives such as dihydroxy-2-naphthoic acid; phenolphthaline; and diphenolic acid. These may be used alone or in combination of two or more.

これらの中でも、半田表面の酸化膜を除去する効果とエポキシ樹脂との反応性に優れる、２，３−ジヒドロキシ安息香酸、ゲンチジン酸、フェノールフタリンが好ましい。   Among these, 2,3-dihydroxybenzoic acid, gentisic acid, and phenolphthaline, which are excellent in the effect of removing the oxide film on the solder surface and the reactivity with the epoxy resin, are preferable.

また、樹脂層３中、フラックス活性硬化剤の配合量は、１〜３０重量％が好ましく、３〜２０重量％が特に好ましい。樹脂層３中のフラックス活性硬化剤の配合量が、上記範囲であることにより、樹脂層３のフラックス活性を向上させることができるとともに、樹脂層３中に、エポキシ樹脂と未反応のフラックス活性硬化剤が残存するのが防止される。   Moreover, 1-30 weight% is preferable and, as for the compounding quantity of a flux active hardening | curing agent in the resin layer 3, 3-20 weight% is especially preferable. When the blending amount of the flux active curing agent in the resin layer 3 is within the above range, the flux activity of the resin layer 3 can be improved, and the epoxy resin and the unreacted flux active curing in the resin layer 3 The agent is prevented from remaining.

樹脂層３は、成膜性を向上するために成膜性樹脂を含むことが好ましい。これにより、フィルム状態にするのが容易となる。また、機械的特性にも優れる。   The resin layer 3 preferably contains a film forming resin in order to improve the film forming property. Thereby, it becomes easy to make a film state. It also has excellent mechanical properties.

前記成膜性樹脂としては、特に限定されるわけではないが、例えば、（メタ）アクリル系樹脂、フェノキシ樹脂、ポリエステル樹脂、ポリウレタン樹脂、ポリイミド樹脂、シロキサン変性ポリイミド樹脂、ポリブタジエン、ポリプロピレン、スチレン−ブタジエン−スチレン共重合体、スチレン−エチレン−ブチレン−スチレン共重合体、ポリアセタール樹脂、ポリビニルブチラール樹脂、ポリビニルアセタール樹脂、ブチルゴム、クロロプレンゴム、ポリアミド樹脂、アクリロニトリル−ブタジエン共重合体、アクリロニトリル−ブタジエン−アクリル酸共重合体、アクリロニトリル−ブタジエン−スチレン共重合体、ポリ酢酸ビニル、ナイロン等を挙げることができる。これらは、１種で用いても、２種以上を併用してもよい。中でも、（メタ）アクリル系樹脂、フェノキシ樹脂及びポリイミド樹脂からなる群から選択される少なくとも１種であることが好ましい。  The film-forming resin is not particularly limited, and examples thereof include (meth) acrylic resins, phenoxy resins, polyester resins, polyurethane resins, polyimide resins, siloxane-modified polyimide resins, polybutadiene, polypropylene, and styrene-butadiene. -Styrene copolymer, styrene-ethylene-butylene-styrene copolymer, polyacetal resin, polyvinyl butyral resin, polyvinyl acetal resin, butyl rubber, chloroprene rubber, polyamide resin, acrylonitrile-butadiene copolymer, acrylonitrile-butadiene-acrylic acid copolymer Examples include polymers, acrylonitrile-butadiene-styrene copolymers, polyvinyl acetate, and nylon. These may be used alone or in combination of two or more. Among these, at least one selected from the group consisting of (meth) acrylic resins, phenoxy resins, and polyimide resins is preferable.

前記成膜性樹脂の含有量は、特に限定されないが、前記樹脂層３中の１０〜５０重量％が好ましく、１５〜４０重量％がより好ましく、特に２０〜３５重量％が好ましい。含有量が前記範囲内であると、樹脂層３の流動性を抑制することができ、樹脂層３の取り扱いが容易になる。   The content of the film-forming resin is not particularly limited, but is preferably 10 to 50% by weight in the resin layer 3, more preferably 15 to 40% by weight, and particularly preferably 20 to 35% by weight. When the content is within the above range, the fluidity of the resin layer 3 can be suppressed, and the handling of the resin layer 3 becomes easy.

また、前記樹脂層３は、硬化促進剤やシランカップリング剤を更に含んでもよい。
（第一の実施形態）
第一の実施形態である回路基板１は、次のようにして製造する。 The resin layer 3 may further include a curing accelerator or a silane coupling agent.
(First embodiment)
The circuit board 1 according to the first embodiment is manufactured as follows.

図２（Ａ）に示すように、はじめに、表裏面に、金属膜４１（たとえば、銅膜）が形成された第一絶縁層２１を用意する。次に、図２（Ｂ）に示すように、一方の金属膜４１および第一絶縁層２１を貫通する孔２１１を形成する。一方の金属膜４１を貫通する孔は、エッチングにより形成し、その後、第一絶縁層２１を貫通する孔をレーザーで形成してもよい。   As shown in FIG. 2A, first, a first insulating layer 21 having a metal film 41 (for example, a copper film) formed on the front and back surfaces is prepared. Next, as shown in FIG. 2B, a hole 211 penetrating one metal film 41 and the first insulating layer 21 is formed. The hole penetrating the one metal film 41 may be formed by etching, and then the hole penetrating the first insulating layer 21 may be formed by laser.

なお、図２（Ｃ）に示すように、他方の金属膜４１をも貫通する貫通孔２１１を形成してもよい。   As shown in FIG. 2C, a through hole 211 that also penetrates the other metal film 41 may be formed.

次に、金属膜４１上および、第一絶縁層２１の孔２１１内部に化学めっきを施す。その後、図３（Ａ）に示すように、マスクＭを配置し、孔２１１内部を充填するとともに、金属膜４１上にめっきを施す。これにより、ビアとなる導電体２０を形成するとともに、金属膜４２を形成する（金属膜４２は、金属膜４１と金属膜４１上のめっき膜を示す）。   Next, chemical plating is performed on the metal film 41 and inside the hole 211 of the first insulating layer 21. Thereafter, as shown in FIG. 3A, a mask M is arranged, the inside of the hole 211 is filled, and the metal film 41 is plated. As a result, the conductor 20 serving as a via is formed, and the metal film 42 is formed (the metal film 42 is a metal film 41 and a plating film on the metal film 41).

次に、マスクＭが形成されていた部分の金属膜４２をフラッシュエッチングにより除去し、図３（Ｂ）に示すように、第一回路層２２、第二回路層２４を形成する。   Next, the metal film 42 in the portion where the mask M has been formed is removed by flash etching, and the first circuit layer 22 and the second circuit layer 24 are formed as shown in FIG.

その後、図４（Ａ）に示すように、第一回路層２２上に、シート状の第二絶縁層２３を貼り付ける。   Thereafter, as shown in FIG. 4A, a sheet-like second insulating layer 23 is attached on the first circuit layer 22.

また、第二回路層２４上に、シート状の第三絶縁層２５を貼り付ける。   A sheet-like third insulating layer 25 is attached on the second circuit layer 24.

その後、シート状の第二絶縁層２３、シート状の第三絶縁層２５を加熱ラミネートして、フォトリソグラフィ工程により、パターニングを行った後、熱により完全硬化させる。   Thereafter, the sheet-like second insulating layer 23 and the sheet-like third insulating layer 25 are heat-laminated, patterned by a photolithography process, and then completely cured by heat.

次に、図４（Ｂ）に示すように、第二絶縁層２３，第三絶縁層２５それぞれに開口を形成する。第二絶縁層２３にたとえば、ＵＶレーザを照射し、第三絶縁層２５に炭酸レーザーを照射して開口を形成することができる。   Next, as shown in FIG. 4B, openings are formed in the second insulating layer 23 and the third insulating layer 25, respectively. For example, the second insulating layer 23 can be irradiated with a UV laser, and the third insulating layer 25 can be irradiated with a carbon dioxide laser to form an opening.

その後、第二絶縁層２３の開口内に、銅を含む金属層２７１、ニッケルを含む金属層２７２、錫を含む金属層２７３をこの順に形成し、第二絶縁層２３の厚さに合わせて、銅を含む金属層２７１の厚さを０μｍ以上、５５μｍ以下に、ニッケルを含む金属層２７２の厚さを２μｍ以上、１５μｍ以下に、錫を含む金属層２７３の厚さを３μｍ以上、１５μｍ以下になるよう、第三絶縁層２５の開口内に金属層２８を形成する。   Thereafter, in the opening of the second insulating layer 23, a metal layer 271 containing copper, a metal layer 272 containing nickel, and a metal layer 273 containing tin are formed in this order, and according to the thickness of the second insulating layer 23, The thickness of the metal layer 271 containing copper is 0 μm or more and 55 μm or less, the thickness of the metal layer 272 containing nickel is 2 μm or more and 15 μm or less, and the thickness of the metal layer 273 containing tin is 3 μm or more and 15 μm or less. The metal layer 28 is formed in the opening of the third insulating layer 25 so as to be.

以上の工程により、回路基板１が完成する。   The circuit board 1 is completed through the above steps.

次に、この回路基板１を使用した半導体装置の製造方法について説明する。
（位置決め仮接着）
まず、第二絶縁層２３上に、フラックス機能を有する化合物を含む樹脂層３を圧着させる。 Next, a method for manufacturing a semiconductor device using the circuit board 1 will be described.
(Positioning temporary bonding)
First, the resin layer 3 containing a compound having a flux function is pressure-bonded onto the second insulating layer 23.

図６に示すように、回路基板１上に複数の半導体素子（半導体チップ）５を設置する。複数の半導体素子５は、回路基板１の面方向に沿って並べられる。半導体素子５の電極５１は、フラックス機能を有する化合物を含む樹脂層３を貫通し、金属層２７と接触する。条件は特に限定されないが、２５〜１７５℃、半導体素子５の１つの当たり０．５〜５ｋｇｆで電極５１と金属層２７の位置を合わせて仮接着する。
（接合）
その後、回路基板１および複数の半導体素子５からなる積層体を加熱して、電極５１と金属層２７とを半田接合させる。条件は特に限定されないが、２００〜３００℃×１〜６０秒間、半導体素子５の１つの当たり０．１〜１５ｋｇｆが好ましい。特に２００〜２３０℃×５〜１８０秒間が好ましい。接合温度は金属層２７の半田種の融点に依存し、荷重は接合する端子数に依存する。ここで、フラックス機能を有する化合物を含む樹脂層３を介して、電極５１と金属層２７を接合するので、金属層２７の表面が酸化されるのを抑制しながら（表面酸化膜を除去しながら）半田を接続することができるようになる。
（硬化）
この積層体をさらに加熱することによりフラックス機能を有する化合物を含む樹脂層３を構成する樹脂を硬化させることが好ましい。 As shown in FIG. 6, a plurality of semiconductor elements (semiconductor chips) 5 are installed on the circuit board 1. The plurality of semiconductor elements 5 are arranged along the surface direction of the circuit board 1. The electrode 51 of the semiconductor element 5 penetrates the resin layer 3 containing a compound having a flux function and contacts the metal layer 27. The conditions are not particularly limited, but the electrodes 51 and the metal layer 27 are temporarily bonded to each other at 25 to 175 ° C. and 0.5 to 5 kgf per one semiconductor element 5.
(Joining)
Thereafter, the laminated body composed of the circuit board 1 and the plurality of semiconductor elements 5 is heated to solder the electrode 51 and the metal layer 27 to each other. Although the conditions are not particularly limited, 0.1 to 15 kgf per one semiconductor element 5 is preferable at 200 to 300 ° C. for 1 to 60 seconds. 200-230 degreeC * 5-180 second is especially preferable. The joining temperature depends on the melting point of the solder type of the metal layer 27, and the load depends on the number of terminals to be joined. Here, since the electrode 51 and the metal layer 27 are joined via the resin layer 3 containing the compound having a flux function, the surface of the metal layer 27 is suppressed from being oxidized (the surface oxide film is removed). ) Solder can be connected.
(Curing)
It is preferable that the resin constituting the resin layer 3 containing the compound having a flux function is cured by further heating the laminate.

この際の加熱条件は特に限定されないが、１２０〜２００℃×３０〜１８０分間が好ましく、これにより、フラックス機能を有する化合物を含む樹脂層３が硬化することにより、電極５１と金属層２７の間を封止し、接続信頼性を向上することができる。
なお、本実施の形態では、積層体を得た後、フラックス機能を有する化合物を含む樹脂層３を硬化させたが、これに限らず、フラックス機能を有する化合物を含む樹脂層３を硬化させた後に積層体を得る方法でも良い。
（樹脂封止）
得られた積層体に半導体素子５側から、エポキシ樹脂組成物を金型を用いて圧縮成形する。その後、取り出して乾燥機で硬化乾燥させる。この際の加熱条件は特に限定されないが、圧縮成形は厚み３０〜３００μｍ、１２０〜２００℃×１〜５分間、硬化は１２０〜２００℃×３〜５時間が好ましく、これにより、積層体を封止し、信頼性を確保することができる。
（半田ボール搭載）
さらに、回路基板１の金属層２８上に半田ボールを形成する。これにより、他の基板等への２次実装が容易となる。
半田ボールを付与する方法としては、例えばメッキ法、ペースト印刷法、ボール搭載法が挙げられる。
（ダイシング）
次に、図７（Ａ）に示すように、回路基板１を分割し、一つの半導体素子５と、分割された一つの回路基板１（以下回路基板部１０ということもある）とで構成される複数の半導体装置６を得る。 The heating conditions at this time are not particularly limited, but are preferably 120 to 200 ° C. × 30 to 180 minutes. Thereby, the resin layer 3 containing a compound having a flux function is cured, so that the electrode 51 and the metal layer 27 are interposed. The connection reliability can be improved.
In this embodiment, after obtaining the laminate, the resin layer 3 containing the compound having the flux function is cured. However, the present invention is not limited to this, and the resin layer 3 containing the compound having the flux function is cured. A method of obtaining a laminate later may also be used.
(Resin sealing)
An epoxy resin composition is compression-molded from the semiconductor element 5 side into the obtained laminate using a mold. Thereafter, it is taken out and cured and dried with a dryer. The heating conditions at this time are not particularly limited, but compression molding is preferably 30 to 300 μm in thickness, 120 to 200 ° C. × 1 to 5 minutes, and curing is preferably 120 to 200 ° C. × 3 to 5 hours, whereby the laminate is sealed. It can be stopped and reliability can be secured.
(With solder balls)
Further, solder balls are formed on the metal layer 28 of the circuit board 1. This facilitates secondary mounting on another board or the like.
Examples of methods for applying solder balls include plating, paste printing, and ball mounting.
(Dicing)
Next, as shown in FIG. 7A, the circuit board 1 is divided into one semiconductor element 5 and one divided circuit board 1 (hereinafter also referred to as a circuit board portion 10). A plurality of semiconductor devices 6 are obtained.

分割する際には、半田ボールが付与されているのと反対側の面にダイシングシートを付与してダイシングを行う。
この半導体装置は、図７（Ｂ）に示すように、回路基板部１０の側面と、半導体素子５の側面とがつらいちとなる。
なお、ダイシングする前に、積層体の半田ボールが付与されている側の面にフラックス機能を有する化合物を含む樹脂層を配置しておくことが好ましい。これにより、２次実装での半田接続が容易となると共に、フラックス処理を省略することができ、生産性や温度サイクル性、落下試験等の２次実装後の信頼性を向上させることができる。
ここで、使用するダイシングシートは市販されているものをそのまま用いることができる。 When dividing, dicing is performed by applying a dicing sheet to the surface opposite to the side where the solder balls are applied.
In this semiconductor device, as shown in FIG. 7B, the side surface of the circuit board portion 10 and the side surface of the semiconductor element 5 become smooth.
In addition, it is preferable to arrange | position the resin layer containing the compound which has a flux function in the surface of the side to which the solder ball of the laminated body is provided before dicing. As a result, solder connection in the secondary mounting is facilitated, the flux process can be omitted, and the reliability after the secondary mounting such as productivity, temperature cycle performance, and drop test can be improved.
Here, a commercially available dicing sheet can be used as it is.

（第二の実施形態）
第二の実施形態は、第二絶縁膜２３、第三絶縁膜２５において感光性樹脂を用いる点を除いて、第１の実施形態と同様である。 (Second embodiment)
The second embodiment is the same as the first embodiment except that a photosensitive resin is used in the second insulating film 23 and the third insulating film 25.

ここで、第一の実施形態と同様にして、図３（Ｂ）に示すように、第一回路層２２、第二回路層２４が、形成されている。   Here, as in the first embodiment, as shown in FIG. 3B, the first circuit layer 22 and the second circuit layer 24 are formed.

その後、真空ラミネータを用い、第一回路層２２が形成された側の回路基板１の全面に、第二絶縁膜２３となるフィルムタイプの感光性樹脂をラミネートする。   Thereafter, using a vacuum laminator, a film type photosensitive resin to be the second insulating film 23 is laminated on the entire surface of the circuit board 1 on the side where the first circuit layer 22 is formed.

次いで、所定の開口を得るようにフォトマスクを位置調整し、露光する。   Next, the position of the photomask is adjusted so as to obtain a predetermined opening, and exposure is performed.

次いで、アルカリ水溶液などの現像液に浸漬し、現像する。これにより、図８（Ａ）に示すように、第二絶縁膜２３に開口を形成する。   Next, it is immersed in a developing solution such as an alkaline aqueous solution and developed. As a result, an opening is formed in the second insulating film 23 as shown in FIG.

次いで、用いた感光性樹脂に応じて、適宜、加熱して、硬化させる。   Subsequently, it is suitably heated and cured according to the photosensitive resin used.

同様にして、図８（Ｂ）に示すように、第二回路層２４が形成された側に、第三絶縁膜２５を形成する。   Similarly, as shown in FIG. 8B, a third insulating film 25 is formed on the side where the second circuit layer 24 is formed.

また、所望する開口の径が感光性樹脂の解像度よりも小さくなる場合においては、加熱して、硬化させた後に第１の実施形態と同じく、第二絶縁層２３にたとえば、ＵＶレーザを照射し、第三絶縁層２５に炭酸レーザーを照射して開口を形成することができる。   In addition, when the desired opening diameter is smaller than the resolution of the photosensitive resin, after heating and curing, the second insulating layer 23 is irradiated with, for example, a UV laser as in the first embodiment. The third insulating layer 25 can be irradiated with a carbon dioxide laser to form an opening.

以下、第一の実施形態と同様の方法により、半導体装置６を得る。   Thereafter, the semiconductor device 6 is obtained by the same method as in the first embodiment.

なお、本発明は前述の実施形態に限定されるものではなく、本発明の目的を達成できる範囲での変形、改良等は本発明に含まれるものである。   It should be noted that the present invention is not limited to the above-described embodiments, and modifications, improvements, and the like within the scope that can achieve the object of the present invention are included in the present invention.

たとえば、前記実施形態では、第二絶縁層、第三絶縁層は、単層であったが、これに限らず、第二絶縁層や第三絶縁層が複数の層で構成されていてもよい。   For example, in the said embodiment, although the 2nd insulating layer and the 3rd insulating layer were single layers, it is not restricted to this, The 2nd insulating layer and the 3rd insulating layer may be comprised by the several layer. .

次に、本発明の実施例について説明する。
（実施例１）
前記実施形態と同様の方法で回路基板を製造した。
（第一絶縁層）
以下のようにして第一絶縁層を作製した。３０μｍのガラス繊維基材にエポキシ樹脂組成物を含浸し硬化させた厚さ４０μｍの第一絶縁層とした。次に、第一絶縁層の両面側に、金属層として厚さ２μｍの銅箔（銅箔は１８μのピーラブル箔付き）を形成して厚みが４４μｍの積層板を作成した。 Next, examples of the present invention will be described.
Example 1
A circuit board was manufactured in the same manner as in the previous embodiment.
(First insulation layer)
A first insulating layer was produced as follows. A 30 μm glass fiber substrate was impregnated with an epoxy resin composition and cured to form a first insulating layer having a thickness of 40 μm. Next, a copper foil having a thickness of 2 μm (a copper foil with 18 μ peelable foil) was formed as a metal layer on both sides of the first insulating layer to prepare a laminate having a thickness of 44 μm.

その後、レーザー加工面にサブトラクティブ法にてコンフォーマルマスクを形成してＣＯ２レーザーにより銅張りの積層板に非貫通穴を形成し、電気銅めっきにて銅張りの積層板の非貫通孔内を銅めっきで充填させるとともに、回路パターン形成を行い、第一回路層および第二回路層を形成した。
（第二絶縁層および第三絶縁層）
前記第一絶縁層上の第一回路及び第二回路に回路粗化・有機皮膜形成処理を行い、熱硬化性樹脂（厚み２５μｍ）をラミネートして完全硬化させて第二絶縁層及び第三絶縁層を形成した（回路上から絶縁樹脂表面の厚みは２０μｍ）。その後、第二絶縁層はＵＶレーザーによりブラインドビアを形成してプラズマデスミア処理を行った。第三絶縁層はＣＯ２レーザーにてブラインドビア形成・プラズマデスミア処理を行い、無電解Ｎｉ、Ａｕめっきを行った。その後、プラズマデスミア後の第二絶縁層の開口部に電気メッキにて銅１２μ、Ｎｉ３μ、半田１０μｍの半田バンプ層を形成した。
（フラックス機能を有する化合物を含む樹脂層）
フェノールノボラック樹脂（住友ベークライト社製、ＰＲ５５６１７）１５．０重量部と、液状ビスフェノールＡ型エポキシ樹脂（大日本インキ化学工業社製、ＥＰＩＣＬＯＮ−８４０Ｓ）４５．０重量部と、フラックス活性化合物であるフェノールフタリン（東京化成工業社製）１５．０重量部と、成膜性樹脂としてビスフェノールＡ型フェノキシ樹脂（東都化成社製、ＹＰ−５０）２４．４重量部と、硬化促進剤として２―フェニルー４−メチルイミダゾール（四国化成工業社製、２Ｐ４ＭＺ）０．１重量部と、シランカップリング剤としてβ−（３，４エポキシシクロヘキシル）エチルトリメトキシシラン（信越化学工業社製、ＫＢＭ−３０３）０．５重量部とを、メチルエチルケトンに溶解し、樹脂濃度５０％の樹脂ワニスを調製した。得られた樹脂ワニスを、基材ポリエステルフィルム（東レ株式会社製、ルミラー）に厚さ５０μｍとなるように塗布して、１００℃、５分間乾燥して、厚さ２５μｍのフラックス活性を有する接着フィルムを得た。
（回路基板）
第二絶縁層を第一回路層側に、第三絶縁層を第二回路層側に真空ラミネータにてラミネートし、硬化させた後、ＵＶレーザーにて第二絶縁層に開口部を形成し、銅、ニッケル、はんだめっきを施し、また、ＣＯ２レーザーにて第三絶縁層に開口部を形成し、ニッケル、金めっきを施した。その後、フラックス機能を有する化合物を含む樹脂層を真空ラミネータにてラミネートした。次に、５０ｍｍ×５０ｍｍの大きさに切断し、プリント配線基板を得た。
（半導体装置の製造）
半導体素子（ＴＥＧチップ、サイズ１５ｍｍ×１５ｍｍ、厚み０．８ｍｍ）は、半田バンプをＳｎ／Ａｇ組成の共晶で形成し、回路保護膜をポジ型感光性樹脂（住友ベークライト社製ＣＲＣ−８３００）で形成したものを使用した。半導体装置の組み立ては、まず、半田バンプにフラックス材を転写法により均一に塗布し、次にフリップチップボンダー装置を用い、上記パッケージ基板上に加熱圧着により搭載した。次に、ＩＲリフロー炉で半田バンプを溶融接合した後、液状封止樹脂（住友ベークライト社製、ＣＲＰ−４１５２Ｓ）を充填し、液状封止樹脂を硬化させることで半導体装置を得た。尚、液状封止樹脂は、温度１５０℃、１２０分の条件で硬化させた。 After that, a conformal mask is formed on the laser machined surface by a subtractive method, a non-through hole is formed in the copper-clad laminate by CO 2 laser, and the copper-clad laminate is filled with a non-through hole by electrolytic copper plating. Was filled with copper plating, and a circuit pattern was formed to form a first circuit layer and a second circuit layer.
(Second insulation layer and third insulation layer)
The first circuit and the second circuit on the first insulating layer are subjected to circuit roughening and organic film forming treatment, laminated with a thermosetting resin (thickness 25 μm), and completely cured to form the second insulating layer and the third insulating layer. A layer was formed (the thickness of the insulating resin surface from the circuit was 20 μm). Thereafter, the second insulating layer was subjected to plasma desmear treatment by forming a blind via with a UV laser. The third insulating layer was subjected to blind via formation and plasma desmear treatment with a CO2 laser, and electroless Ni and Au plating was performed. Thereafter, a solder bump layer of 12 μm copper, 3 μm Ni, and 10 μm solder was formed by electroplating in the opening of the second insulating layer after plasma desmearing.
(Resin layer containing a compound having a flux function)
15.0 parts by weight of a phenol novolac resin (Sumitomo Bakelite, PR55617), 45.0 parts by weight of a liquid bisphenol A type epoxy resin (Dainippon Ink and Chemicals, EPICLON-840S), and a phenol that is a flux active compound 15.0 parts by weight of phthalin (manufactured by Tokyo Chemical Industry Co., Ltd.), 24.4 parts by weight of bisphenol A type phenoxy resin (manufactured by Toto Kasei Co., Ltd., YP-50) as a film-forming resin, and 2-phenyl- as a curing accelerator 0.1 parts by weight of 4-methylimidazole (manufactured by Shikoku Kasei Kogyo Co., Ltd., 2P4MZ) and β- (3,4 epoxy cyclohexyl) ethyltrimethoxysilane (manufactured by Shin-Etsu Chemical Co., Ltd., KBM-303) 0 as a silane coupling agent Dissolve 5 parts by weight in methyl ethyl ketone to prepare a resin varnish with a resin concentration of 50%. . The obtained resin varnish is applied to a base polyester film (manufactured by Toray Industries Inc., Lumirror) to a thickness of 50 μm, dried at 100 ° C. for 5 minutes, and an adhesive film having a flux activity of 25 μm in thickness. Got.
(Circuit board)
After laminating and curing the second insulating layer on the first circuit layer side and the third insulating layer on the second circuit layer side with a vacuum laminator, an opening is formed in the second insulating layer with a UV laser, Copper, nickel, and solder plating were performed, and an opening was formed in the third insulating layer with a CO 2 laser, and nickel and gold were plated. Thereafter, a resin layer containing a compound having a flux function was laminated with a vacuum laminator. Next, it cut | disconnected to the magnitude | size of 50 mm x 50 mm, and obtained the printed wiring board.
(Manufacture of semiconductor devices)
In the semiconductor element (TEG chip, size 15 mm × 15 mm, thickness 0.8 mm), the solder bump is formed of a eutectic of Sn / Ag composition, and the circuit protective film is a positive photosensitive resin (CRC-8300 manufactured by Sumitomo Bakelite Co., Ltd.) What was formed in was used. In assembling the semiconductor device, first, a flux material was uniformly applied to the solder bumps by a transfer method, and then mounted on the package substrate by thermocompression bonding using a flip chip bonder device. Next, after solder bumps were melt-bonded in an IR reflow furnace, a liquid sealing resin (manufactured by Sumitomo Bakelite Co., Ltd., CRP-4152S) was filled and the liquid sealing resin was cured to obtain a semiconductor device. The liquid sealing resin was cured at a temperature of 150 ° C. for 120 minutes.

作成した半導体装置にもちいたプリント配線基板の各構成は表１に示すとおりである。各実施例および比較例により得られた半導体装置について、次の各評価を行った。各評価を、評価方法と共に以下に示す。得られた結果を表１に示す。   Each configuration of the printed wiring board used for the created semiconductor device is as shown in Table 1. Each of the following evaluations was performed on the semiconductor devices obtained in the examples and comparative examples. Each evaluation is shown below together with the evaluation method. The obtained results are shown in Table 1.

なお、実施例５は、第二絶縁層および第三絶縁層として感光性レジスト（厚み２５μｍ）をラミネートして、フォトリソグラフィによるパターニング、熱による完全硬化工程を経て、第二絶縁層及び第三絶縁層を形成した以外は実施例１と同様の方法でプリント配線基板を作成した。   In Example 5, a photosensitive resist (thickness: 25 μm) is laminated as the second insulating layer and the third insulating layer, and the second insulating layer and the third insulating layer are subjected to patterning by photolithography and complete curing by heat. A printed wiring board was prepared in the same manner as in Example 1 except that the layer was formed.

１．評価方法
（１）チップ接合後、温度サイクル試験
試験条件として、温度サイクル（−５５℃〜１２５℃）、保持時間１０分、温度変更時間２０分の条件下で、温度サイクル試験機を用いて、１，０００サイクルを導通抵抗確認した。各水準１０ずつ投入し、試験合格数／投入数で評価した。 1. Evaluation method (1) After chip bonding, temperature cycle test As test conditions, using a temperature cycle tester under the conditions of temperature cycle (-55 ° C to 125 ° C), holding time of 10 minutes, temperature change time of 20 minutes, The conduction resistance was confirmed for 1,000 cycles. Each level was put in 10 and evaluated by the number of test passes / number of inputs.

表１から明らかなように、実施例１〜５、チップ接合後の評価試験にて温度サイクル試験で投入した１０枚すべてが良品であった。それに対して、ニッケルを含む金属層（ｂ）が形成されていない比較例１は、温度サイクル試験１０００サイクル後はすべて不良に、ニッケルを含む金属層（ｂ）の厚さが１μｍと薄い場合には４／１０が不良に、また、錫を含む金属層（ｃ）が１μｍと薄い場合、チップとの接続が不十分であったため８／１０が不良であった。   As is apparent from Table 1, Examples 10 to 5 and all 10 sheets introduced in the temperature cycle test in the evaluation test after chip bonding were all non-defective products. In contrast, Comparative Example 1 in which the nickel-containing metal layer (b) was not formed was defective after 1000 cycles of the temperature cycle test, and the thickness of the nickel-containing metal layer (b) was as thin as 1 μm. When the metal layer (c) containing tin was as thin as 1 μm, the connection with the chip was insufficient and 8/10 was defective.

１ 回路基板
２ 基板
３ 樹脂層
５ 半導体素子
６ 半導体装置
１０ 回路基板部
２０ 導電体
２１ 第一絶縁層
２２ 第一回路層
２３ 第二絶縁層
２４ 第二回路層
２５ 第三絶縁層
２７ 金属層
２８ 金属層
４１ 金属膜
４２ 金属膜
５１ 電極
２１１ 孔
２７１ 銅を含む金属層
２７２ ニッケルを含む金属層
２７３ 錫を含む金属層 DESCRIPTION OF SYMBOLS 1 Circuit board 2 Board | substrate 3 Resin layer 5 Semiconductor element 6 Semiconductor device 10 Circuit board part 20 Conductor 21 1st insulating layer 22 1st circuit layer 23 2nd insulating layer 24 2nd circuit layer 25 3rd insulating layer 27 Metal layer 28 Metal layer 41 Metal film 42 Metal film 51 Electrode 211 Hole 271 Metal layer 272 containing copper Metal layer 273 containing nickel Metal layer containing tin

Claims (8)

導電体が貫通する第一絶縁層と、
前記第一絶縁層の一方の側に設けられ、前記導電体に接続された第一回路層と、
この第一回路層を被覆するとともに、第一回路層の一部を露出させるための開口が形成された第二絶縁層と、
前記第一絶縁層の他方の側に設けられ、前記導電体に接続された第二回路層と、
前記第二回路層を被覆する第三絶縁層と、
前記第二絶縁層の開口内に設けられ、前記開口から露出する前記第一回路層の一部と接触する金属層とを備え、
前記金属層は、前記第一回路層側から、銅を含む金属層（ａ）、ニッケルを含む金属層（ｂ）、錫を含む金属層（ｃ）がこの順に構成され、銅を含む金属層（ａ）の厚さは０以上、５５μｍ以下であり、ニッケルを含む金属層（ｂ）の厚さは２μｍ以上、１５μｍ以下であり、錫を含む金属層（ｃ）の厚さは３μｍ以上、３０μｍ以下であることを特徴とする回路基板。 A first insulating layer through which the conductor penetrates;
A first circuit layer provided on one side of the first insulating layer and connected to the conductor;
A second insulating layer covering the first circuit layer and having an opening for exposing a portion of the first circuit layer;
A second circuit layer provided on the other side of the first insulating layer and connected to the conductor;
A third insulating layer covering the second circuit layer;
A metal layer provided in the opening of the second insulating layer and in contact with a part of the first circuit layer exposed from the opening;
The metal layer is composed of a metal layer (a) containing copper, a metal layer (b) containing nickel, and a metal layer (c) containing tin in this order from the first circuit layer side. The thickness of (a) is 0 or more and 55 μm or less, the thickness of the metal layer (b) containing nickel is 2 μm or more and 15 μm or less, and the thickness of the metal layer (c) containing tin is 3 μm or more, A circuit board having a thickness of 30 μm or less. フラックス活性化合物を含む樹脂層は、前記第二絶縁層を被覆するとともに、前記金属層上に設けられている請求項１に記載の回路基板。   The circuit board according to claim 1, wherein a resin layer containing a flux active compound covers the second insulating layer and is provided on the metal layer. 前記第一回路層面から前記第二絶縁層表面までの厚さが３μｍ以上である請求項１または２に記載の回路基板。   The circuit board according to claim 1 or 2, wherein a thickness from the first circuit layer surface to the second insulating layer surface is 3 µm or more. 請求項１ないし３のいずれかに記載の回路基板を複数備えた基板であり、
当該基板を分割することで、前記回路基板を複数得るための回路基板。 A board comprising a plurality of circuit boards according to any one of claims 1 to 3,
A circuit board for obtaining a plurality of the circuit boards by dividing the board. 請求項１ないし４のいずれかに記載の回路基板において、
前記第二絶縁層および前記第三絶縁層はそれぞれ、感光性樹脂を含む回路基板。 The circuit board according to any one of claims 1 to 4,
Each of the second insulating layer and the third insulating layer is a circuit board containing a photosensitive resin. 請求項１ないし５のいずれかに記載の回路基板と、
この回路基板上に積層され、前記回路基板の基板面側からみて前記回路基板と略同じサイズである半導体チップとを有し、
前記回路基板の側面と、前記半導体チップの側面とがつらいちである半導体装置。 A circuit board according to any one of claims 1 to 5,
Laminated on the circuit board, and having a semiconductor chip having substantially the same size as the circuit board when viewed from the board surface side of the circuit board;
A semiconductor device in which a side surface of the circuit board is flush with a side surface of the semiconductor chip. 内部に導電体が貫通するとともに、一方の面側に前記導電体に接続された第一回路層が設けられ、他方の面側に前記導電体に接続された第二回路層が設けられた第一絶縁層を用意する工程と、
前記第一回路層を被覆する第二絶縁層を設ける工程と、
前記第二回路層を被覆する第三絶縁層を設ける工程と、
前記第二絶縁層に前記第一回路層の一部が露出する開口を形成する工程と、
前記開口内に、前記第一回路層の一部と接触する金属層を設ける工程とを含み、
前記金属層は、前記第一回路層側から、銅を含む金属層（ａ）、ニッケルを含む金属層（ｂ）、錫を含む金属層（ｃ）がこの順に構成され、銅を含む金属層（ａ）の厚さは０以上、５５μｍ以下であり、ニッケルを含む金属層（ｂ）の厚さは２μｍ以上、１５μｍ以下であり、錫を含む金属層（ｃ）の厚さは３μｍ以上、３０μｍ以下であることを特徴とする回路基板の製造方法。 A first circuit layer connected to the conductor is provided on one surface side, and a second circuit layer connected to the conductor is provided on the other surface side. Providing one insulating layer;
Providing a second insulating layer covering the first circuit layer;
Providing a third insulating layer covering the second circuit layer;
Forming an opening in the second insulating layer through which a part of the first circuit layer is exposed;
Providing a metal layer in contact with a part of the first circuit layer in the opening,
The metal layer is composed of a metal layer (a) containing copper, a metal layer (b) containing nickel, and a metal layer (c) containing tin in this order from the first circuit layer side. The thickness of (a) is 0 or more and 55 μm or less, the thickness of the metal layer (b) containing nickel is 2 μm or more and 15 μm or less, and the thickness of the metal layer (c) containing tin is 3 μm or more, A method for producing a circuit board, wherein the circuit board is 30 μm or less. 請求項７に記載の回路基板の製造方法を含み、
フラックス活性化合物を含む樹脂層上に複数の半導体チップを配置する工程と、
前記回路基板を固片化して、半導体チップと、固片化した前記回路基板とを備える半導体装置を得る工程とを含む半導体装置の製造方法。 A method for manufacturing a circuit board according to claim 7,
Arranging a plurality of semiconductor chips on a resin layer containing a flux active compound;
A method of manufacturing a semiconductor device, comprising: solidifying the circuit board to obtain a semiconductor device including a semiconductor chip and the solidified circuit board.
JP2010238475A 2010-03-26 2010-10-25 Circuit board, semiconductor device, method of manufacturing circuit board and method of manufacturing semiconductor device Pending JP2011222943A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2010238475A JP2011222943A (en) 2010-03-26 2010-10-25 Circuit board, semiconductor device, method of manufacturing circuit board and method of manufacturing semiconductor device
PCT/JP2011/001461 WO2011118146A1 (en) 2010-03-26 2011-03-14 Circuit board, semiconductor device, manufacturing method for circuit board, and manufacturing method for semiconductor device
TW100110283A TW201203472A (en) 2010-03-26 2011-03-25 Circuit board, semiconductor device, method for manufacturing circuit board, and method for manufacturing semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2010071395 2010-03-26
JP2010071395 2010-03-26
JP2010238475A JP2011222943A (en) 2010-03-26 2010-10-25 Circuit board, semiconductor device, method of manufacturing circuit board and method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JP2011222943A true JP2011222943A (en) 2011-11-04

Family

ID=44672727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010238475A Pending JP2011222943A (en) 2010-03-26 2010-10-25 Circuit board, semiconductor device, method of manufacturing circuit board and method of manufacturing semiconductor device

Country Status (3)

Country Link
JP (1) JP2011222943A (en)
TW (1) TW201203472A (en)
WO (1) WO2011118146A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013131532A (en) * 2011-12-20 2013-07-04 Sumitomo Bakelite Co Ltd Method of manufacturing semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113423178A (en) * 2021-06-16 2021-09-21 梅州市志浩电子科技有限公司 Plasma degumming method for mixed-voltage circuit board

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4387475B2 (en) * 1998-04-20 2009-12-16 日本特殊陶業株式会社 Wiring board
JP2004071656A (en) * 2002-08-01 2004-03-04 Sumitomo Bakelite Co Ltd Multilayer interconnection board and semiconductor device
JP2009004454A (en) * 2007-06-19 2009-01-08 Shinko Electric Ind Co Ltd Electrode structure, forming method thereof, electronic component, and mounting substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013131532A (en) * 2011-12-20 2013-07-04 Sumitomo Bakelite Co Ltd Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
TW201203472A (en) 2012-01-16
WO2011118146A1 (en) 2011-09-29

Similar Documents

Publication Publication Date Title
JP5228908B2 (en) Semiconductor device
JP7258453B2 (en) Thermosetting resin composition, resin film with carrier, prepreg, printed wiring board and semiconductor device
JP5682308B2 (en) Manufacturing method of semiconductor parts
JP5408131B2 (en) Semiconductor device mounting substrate
WO2011118128A1 (en) Circuit board, semiconductor device, manufacturing method for circuit board, and manufacturing method for semiconductor device
WO2011033743A1 (en) Adhesive film, multilayer circuit board, electronic component, and semiconductor device
WO2011007531A1 (en) Method for manufacturing electronic component and electronic component
TWI549248B (en) Method of manufacturing semiconductor package
JP2010010368A (en) Semiconductor device, and manufacturing method of the same
WO2017038713A1 (en) Method for manufacturing printed wiring board, and method for manufacturing semiconductor device
JP2012227441A (en) Semiconductor device manufacturing method and semiconductor device
JP5569582B2 (en) Flexible substrate and electronic device
JP2012049423A (en) Circuit board, semiconductor device, method of manufacturing circuit board and method of manufacturing semiconductor device
JP2012074636A (en) Joining method, semiconductor device, multilayer circuit board, and electronic component
WO2011118146A1 (en) Circuit board, semiconductor device, manufacturing method for circuit board, and manufacturing method for semiconductor device
JP6217870B2 (en) Structure, wiring board, and method of manufacturing wiring board
JP2012057109A (en) Resin composition, adhesive film, semiconductor device, multilayer circuit board and electronic component
JP6107992B1 (en) Resin sheet
JP5593897B2 (en) Circuit board, semiconductor device, circuit board manufacturing method, and semiconductor device manufacturing method
JP4385555B2 (en) Interposer, semiconductor package and manufacturing method thereof
JP5884301B2 (en) Semiconductor device
JP2018172552A (en) Thermosetting resin composition, resin film with carrier, prepreg, printed wiring board, and semiconductor device